Network data packet processing device
By using indirect addressing method and direct memory access controller to manage buffer addresses in the packet description element, the time-consuming problem of traditional network processors in ring buffer management is solved, and the processing efficiency of packet forwarding is significantly improved.
Patent Information
- Application Number
- CN202311684458.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-12-08
- Publication Date
- 2025-06-10
AI Technical Summary
Traditional network processors consume a lot of time when managing ring buffers, affecting the overall processing efficiency of packet forwarding.
Indirect addressing is used to indicate the buffer address in the packet description element, and the temporary address in the packet buffer is applied through the direct memory access controller, and the address-related information is written to the packet description element.
This greatly reduces the time for network processors to read packet description elements, reduces the time consumption of network processors in ring buffer management, thereby improving the overall processing efficiency of packet forwarding.
Smart Images
Figure CN120128562A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to network packet processing, and particularly to a network packet processing apparatus that uses an indirect addressing method in a packet descriptor to indicate a buffer address and / or applies for an available register address in a packet buffer through a direct memory access (DMA) controller and writes address-related information into the packet descriptor. Background Art
[0002] A network processing unit (NPU) is a high-speed programmable processor specifically applied to network packet processing (such as network packet forwarding), and particularly has some features and architectures to accelerate the processing efficiency of network packets. Generally, when a traditional network processor performs network packet forwarding, it is necessary to read a packet descriptor of a network packet from a ring buffer to obtain a buffer address of the network packet in a packet buffer and a packet length of the network packet. Assuming that the ring buffer is implemented by a static random access memory (SRAM), and a read operation on the static random access memory takes 14 memory clocks. Since the read of the packet descriptor requires two read operations on the static random access memory, it takes 28 memory clocks.
[0003] In addition, the traditional network processor is also responsible for applying for an available buffer address in the packet buffer from the management circuit of the packet buffer, and updating the packet descriptor stored in the ring buffer with this buffer address for the direct memory access controller to write subsequent received network packets into the packet buffer. Applying for an available buffer address in the packet buffer by the traditional network processor through the management circuit of the packet buffer takes at least 20 memory clocks. In addition, a write operation on the static random access memory takes 7 memory clocks. Since the operation of updating the packet descriptor stored in the ring buffer requires two write operations on the static random access memory, it takes 14 memory clocks. Thus, a total of at least 34 memory clocks are consumed.
[0004] Traditional network processors spend a lot of time managing the circular buffer, thus affecting the processing efficiency of overall packet forwarding. Therefore, it is necessary to optimize the management of the circular buffer in order to reduce the time consumed by the network processor in managing the circular buffer, thereby improving the processing efficiency of overall packet forwarding. Summary of the Invention
[0005] One object of the present invention is to provide a network packet processing device that uses an indirect addressing method in a packet descriptor to indicate a buffer address and / or applies for an available register address in a packet buffer through a direct memory access controller and writes address-related information into the packet descriptor.
[0006] In one embodiment of the present invention, a network packet processing device is disclosed. The network packet processing device includes a packet buffer, a circular buffer, and a network processor. The packet buffer is used to store a network packet. The circular buffer is used to store a packet descriptor of the network packet, where the packet descriptor includes a first field, and the first field is used to indirectly indicate a buffer address of the network packet in the packet buffer, and the buffer address is not directly recorded in the packet descriptor. The network processor is used to read the packet descriptor from the circular buffer and perform a predetermined packet processing of the network packet according to the packet descriptor.
[0007] In another embodiment of the present invention, a network packet processing device is disclosed. The network packet processing device includes a packet buffer, a circular buffer, and a direct memory access controller. The packet buffer is used to store a network packet. The circular buffer is used to store a packet descriptor of the network packet, where the packet descriptor includes a first field. The direct memory access controller includes a control circuit, and the control circuit is used to write the network packet into the packet buffer and fill the relevant information of the buffer address of the network packet in the packet buffer into the first field.
[0008] The buffer address of the network packet in the packet buffer is not directly recorded in the packet descriptor of the present invention. Since the number of bits required for indirect addressing (i.e., the address identification code) is much smaller than the number of bits required for direct addressing (i.e., the buffer address), the network processor can significantly reduce the time consumed in reading the packet descriptor, thereby improving the processing efficiency of overall packet forwarding. In addition, the network packet processing device of the present invention offloads the management work of the circular buffer from the network processor to the direct memory access controller. In this way, the time consumed by the network processor in managing the circular buffer can be reduced, and thus the processing efficiency of overall packet forwarding can be further improved. Brief Description of the Drawings
[0009] Figure 1 Schematic diagram of a network data packet processing apparatus according to an embodiment of the present invention.
[0010] Figure 2 Schematic diagram of the mapping relationship between the address identification code and the buffer address according to an embodiment of the present invention.
[0011] Figure 3 Flowchart of network data packet transfer through a direct memory access controller according to an embodiment of the present invention.
[0012] Figure 4 Flowchart of network data packet forwarding through a network processor according to an embodiment of the present invention.
[0013]
Symbol description
[0014] 100: Network data packet processing apparatus
[0015] 102: Network processor
[0016] 104: Static random access memory
[0017] 106: Direct memory access controller
[0018] 108: Dynamic random access memory
[0019] 110: Buffer management circuit
[0020] 112: Network card
[0021] 114: Receive buffer
[0022] 116: Packet buffer
[0023] 117, 117_1, 117_2, 117_3, 117_4, 119: Storage block
[0024] 118: Ring buffer
[0025] 120: Packet descriptor
[0026] 121_1, 121_2, 121_3: Field
[0027] 122: Control circuit
[0028] 124: Buffer address filling circuit
[0029] 126: Buffer address pool
[0030] 128: Register
[0031] src_addr: Source address
[0032] buf_addr: Buffer address
[0033] dst_addr: Destination address
[0034] addr_ofs: Address offset
[0035] o_b: Control code
[0036] buf_id: Address identification code
[0037] pkt_len: Packet length
[0038] PKT: Network packet
[0039] addr_base: Base address
[0040] bk_s: Block size
[0041] S302, S304, S306, S308, S402, S404, S406, S408: Steps Detailed implementation manners
[0042] In the specification and claims, certain terms are used to refer to specific elements. Those skilled in the art should understand that hardware manufacturers may use different terms to refer to the same element. The specification and claims do not use the difference in names as a way to distinguish elements, but use the difference in functions of elements as the criterion for distinction. The terms "comprising" and "include" mentioned throughout the specification and claims are open-ended terms and should be interpreted as "including but not limited to". In addition, the term "coupled" or "coupling" herein includes any direct and indirect electrical connection means. Therefore, if a first device is described as being coupled to a second device in the text, it means that the first device can be directly electrically connected to the second device, or indirectly electrically connected to the second device through other devices and connection means.
[0043] Figure 1 It is a schematic diagram of a network packet processing device according to an embodiment of the present invention. For example, the network packet processing device 100 can be applied to a network device, such as a gateway. As shown in the figure, the network packet processing device 100 may include a network processor 102, a static random access memory 104, a direct memory access controller 106, a dynamic random access memory (DRAM) 108, a buffer management circuit 110, and a network interface card (NIC) 112. Please note,Figure 1 Only the elements related to the present invention are shown. In fact, the network data packet processing apparatus 100 may include other elements to implement the specified functions.
[0044] The network card 112 may be implemented by a network chip and has a receive (RX) buffer 112. For example, the receive buffer 112 may be implemented by a first-in first-out (FIFO) buffer. When the network card 112 receives a network data packet PKT from the network connection port, the network data packet PKT will be temporarily stored in the internal buffer of the network card 112 (i.e., the receive buffer 112), and then each network data packet PKT temporarily stored in the receive buffer 112 will be copied and written by the direct memory access controller 106 into the data packet buffer 116 configured in the dynamic random access memory 108. When the data packet buffer 116 is initialized, it will be divided into multiple storage blocks 117 according to a fixed block size (such as 2K bytes or 4K bytes) to store multiple network data packets PKT respectively. Therefore, the network data packets PKT temporarily stored in the receive buffer 112 can be written into the available storage blocks 117 in the data packet buffer 116 through the direct memory access controller 106.
[0045] In addition, a ring buffer 118 is configured in the static random access memory 104 for receiving network data packets. The ring buffer 118 is divided into multiple storage blocks 119 to store multiple data packet descriptors 120 of multiple network data packets respectively. Each data packet descriptor 120 records some metadata of the corresponding network data packet. In this embodiment, the data packet descriptor 120 includes multiple fields 121_1, 121_2, 121_3. Among them, the field 121_1 (with a length of 14 bits) is used to record the data packet length pkt_len, the field 121_2 (with a length of 17 bits) is used to record address-related information, and the field 121_3 (with a length of 1 bit) is used to record the control code o_b. Compared with the traditional data packet descriptor that uses a 32-bit field to directly record the buffer address where the network data packet PKT is stored in the data packet buffer 116, the data packet descriptor 120 of the present invention records the address identification code buf_id through the 17-bit field 121_2 to indirectly indicate the buffer address where the network data packet PKT is stored in the data packet buffer 116.
[0046] Figure 2Schematic diagram of the mapping relationship between the address identification code buf_id and the buffer address buf_addr in an embodiment of the present invention. The data packet buffer 116 is divided into multiple storage blocks (such as storage blocks 117_1, 117_2, 117_3, 117_4), and the block size bk_s of each storage block is 4K bytes, and the base address addr_base of the data packet buffer 116 is 0x80000000. The multiple storage blocks are respectively mapped to multiple address identification codes buf_id. For example, the mapping relationship between the buffer address (i.e., the starting address) buf_addr of each storage block and the address identification code buf_id can be expressed as: buf_addr = addr_base + buf_id * bk_s. However, this is only for illustrative purposes and not a limitation of the present invention. In fact, any method that can use fewer bits to implement the buffer address of the indirect addressing network data packet in the data packet buffer can be adopted, and these design changes are all within the scope of the present invention.
[0047] In short, the data packet descriptor 120 of the present invention does not directly record the buffer address of the network data packet PKT in the data packet buffer 116. Since the number of bits required for indirect addressing (i.e., the address identification code buf_id) (17 bits) is much smaller than the number of bits required for direct addressing (i.e., the buffer address) (32 bits), the network processor 102 only needs one read operation of the static random access memory 104 to read the data packet descriptor 120. If one read operation of the static random access memory 104 takes 14 memory clocks, then the reading of the data packet descriptor 120 only takes 14 memory clocks. Therefore, the time required for the network processor 102 to read the data packet descriptor can be significantly reduced, thereby improving the overall data packet forwarding processing efficiency.
[0048] In addition, compared with traditional network processors that need to be responsible for the management of circular buffers (including applying for available buffer addresses in the data packet buffer and updating the data packet descriptors stored in the circular buffer with these buffer addresses), the network data packet processing device 100 of the present invention offloads the management of these circular buffers to the direct memory access controller 106. In this way, the time consumed by the network processor 102 in circular buffer management can be reduced, and thus the overall data packet forwarding processing efficiency can be further improved. As Figure 1As shown, the direct memory access controller 106 includes a control circuit 122, a buffer address filling circuit 124, and a buffer address pool 126. In addition to receiving the transfer of network data packets between the receive buffer 114 and the packet buffer 116, the control circuit 122 also fills the field data of the packet descriptor 120. Additionally, the buffer address filling circuit 124 is responsible for filling the available buffer addresses in the packet buffer 116 into the buffer address pool 126.
[0049] Please also refer to Figure 1 and Figure 3 , Figure 3 is a flowchart of network data packet transfer through the direct memory access controller 106 according to an embodiment of the present invention. If the same result can be obtained generally, the steps do not necessarily have to be executed exactly in the Figure 3 shown order. In step S302, after receiving the network data packet PKT, the network card 112 temporarily stores the network data packet PKT in the receive buffer (such as a first-in-first-out buffer) 114. In step S304, the direct memory access controller 106 initializes the transfer of the network data packet PKT in the receive buffer 114. For example, the control circuit 122 sets the storage address of the network data packet PKT in the receive buffer 114 as the source address src_addr, and uses the packet length pkt_len of the network data packet PKT as the data length to be transmitted. Additionally, the control circuit 122 obtains an available buffer address buf_addr in the packet buffer 116 from the buffer address pool 126, and sets the destination address dst_addr based on the obtained buffer address buf_addr. In this embodiment, the control circuit 122 can apply an address offset addr_ofs to the buffer address buf_addr as the destination address dst_addr (i.e., dst_addr = buf_addr + addr_ofs), where the address offset addr_ofs mainly reserves some space for header extensions. In step S306, the control circuit 122 copies the network data packet PKT from the receive buffer 114 of the network card 112 and writes it into the storage block 117 in the packet buffer 116 according to the transfer parameters (src_addr, dst_addr, pkt_len).
[0050] After the transfer of the network data packet PKT is completed, the control circuit 122 updates the corresponding field data of the packet descriptor 120 configured for the network data packet PKT in the circular buffer 118 (step S308). In this embodiment, the control circuit 122 converts the buffer address dst_addr (with a length of 32 bits) of the network data packet PKT in the packet buffer 116 into an address identification code buf_id (with a length of 17 bits). For example, the buffer address dst_addr is first subtracted by the address offset addr_ofs to restore the buffer address buf_addr (corresponding to the starting address of the storage block 117), and then the address identification code buf_id is determined through the mapping relationship shown by Figure 2 . However, this is only for illustrative purposes and not a limitation of the present invention. Any method that can use fewer bits to implement the indirect addressing of the buffer address of the network data packet in the packet buffer can be adopted. The control circuit 122 sets the control code o_b to 1 (i.e., o_b = 1) and writes it into the field 121_3 of the packet descriptor 120 to indicate that this packet descriptor 120 is handed over to the network processor 102 for processing. In addition, the control circuit 122 writes the address identification code buf_id into the field 121_2 of the packet descriptor 120 and writes the packet length pkt_len into the field 121_1 of the packet descriptor 120.
[0051] As described above, the control circuit 122 obtains the available buffer address buf_addr in the packet buffer 116 from the buffer address pool 126. In this embodiment, the buffer address pool 126 is used to store multiple available buffer addresses buf_addr in the packet buffer 116. For example, the capacity of the buffer address pool 126 is M. Therefore, the buffer address pool 126 can store at most M available buffer addresses in the packet buffer 116. In addition, the buffer address filling circuit 124 is responsible for the application of the buffer address and the maintenance of the buffer address pool 126, as Figure 1As shown, the buffer management circuit 110 is hardware responsible for managing the use of the data packet buffer 116. That is, without the intervention of the processor (software), the buffer management circuit 110 can handle the initialization of the data packet buffer 116, the application for storage blocks, the recycling of storage blocks, etc. Therefore, the buffer address filling circuit 124 can apply to the buffer management circuit 110 for multiple available buffer addresses through the register 128 of the buffer management circuit 110. For example, when initializing the buffer address pool 126, the buffer address filling circuit 124 applies to the buffer management circuit 110 for M available buffer addresses and fills the buffer address pool 126 with these M available buffer addresses. Additionally, whenever the control circuit 122 reads a buffer address buf_addr from the buffer address pool 126, this buffer address buf_addr will be marked as "used" in the buffer address pool 126. Therefore, after the control circuit 122 transfers N network data packets PKT in the receive buffer 114 to the data packet buffer 116, the number of buffer addresses available for the control circuit 122 in the buffer address pool 126 will decrease from the original M to (M - N). In this embodiment, the buffer address filling circuit 124 is also used to monitor the usage of the buffer address pool 126, and when the number of available buffer addresses in the buffer address pool 126 that have not been used by the control circuit 122 reaches A (for example ), it applies to the buffer management circuit 110 for (M - A) available buffer addresses through the register 128 and fills the buffer address pool 126 with these (M - A) available buffer addresses.
[0052] The network processor 102 can read the packet descriptor 120 from the circular buffer 118 and perform predetermined packet processing on the network data packet PKT according to the packet descriptor 120. For example, the network processor 102 can assist in the forwarding of the network data packet PKT. Please refer to Figure 1 and Figure 4 , Figure 4 which is a flowchart of network data packet forwarding by the network processor 102 according to an embodiment of the present invention. If the same result can be obtained generally, the steps do not necessarily have to be exactly in accordance with Figure 4Execute in the order shown. In step S402, the network processor 102 reads and parses the field data in the packet descriptor 120. For example, the network processor 102 first reads field 121_3 to obtain the control code o_b. When the value of the control code o_b is 1 (i.e., o_b = 1), it indicates that the packet descriptor 120 has currently been handed over by the direct memory access controller 106 to the network processor 102 for processing. Therefore, the network processor 102 will further read field 121_2 and field 121_1 to obtain the address identification code buf_id and the packet length pkt_len respectively, and convert the address identification code buf_id into the buffer address of the network packet PKT in the packet buffer 116. After the network processor 102 has read and parsed the field data in the packet descriptor 120, the network processor 102 will update the field data in this packet descriptor 120. In this embodiment, the network processor 102 only needs to update the control code o_b of field 121_1, and set the control code o_b to 0 (i.e., o_b = 0) to indicate that this packet descriptor 120 is handed over to the direct memory access controller 106 for processing. Subsequently, the direct memory access controller 106 can reuse this packet descriptor 120 to record the field data (such as buf_id and pkt_len) of other network packets. In step S406, the network processor 102 reads the packet content of the network packet PKT to be forwarded from the packet buffer 116, and performs predetermined processing to write the processed information (such as address and length) into the packet descriptor in the transmit (TX) ring buffer (not shown) of the network card 112. After the network packet PKT is forwarded, the network processor 102 will notify the buffer management circuit 110 through the register 128 to recycle the storage block 117 that originally stored this network packet PKT in the packet buffer 116 (step S408).
[0053] The above are only the preferred embodiments of the present invention. All equivalent changes and modifications made according to the claims of the present invention shall fall within the scope of the present invention.
Claims
1. A network data packet processing device, comprising: A data packet buffer for storing network data packets; A circular buffer for storing data packet descriptors of the network data packets, wherein the data packet descriptor includes a first field for indirectly indicating a buffer address of the network data packet in the data packet buffer, and the buffer address is not directly recorded in the data packet descriptor; and A network processor for reading the data packet descriptor from the circular buffer and performing predetermined data packet processing on the network data packet according to the data packet descriptor.
2. The network data packet processing device according to claim 1, further comprising: A direct memory access controller, comprising: A control circuit for writing the network data packet into the data packet buffer, converting the buffer address of the network data packet in the data packet buffer into an address identification code, and filling the address identification code into the first field.
3. The network data packet processing device according to claim 2, wherein the data packet buffer includes a plurality of storage blocks for respectively storing a plurality of network data packets; and the control circuit maps the plurality of storage blocks to a plurality of address identification codes respectively.
4. The network data packet processing device according to claim 2, wherein the data packet descriptor further includes a second field; when the address identification code is filled into the first field, the direct memory access controller further fills a control code into the second field to indicate that the data packet descriptor is handed over to the network processor for processing.
5. The network data packet processing device according to claim 2, wherein the data packet descriptor further includes a second field; after reading the data packet descriptor from the circular buffer, the network processor further fills a control code into the second field to indicate that the data packet descriptor is handed over to the direct memory access controller for processing.
6. The network data packet processing device according to claim 2, wherein the direct memory access controller further includes: A buffer address pool for storing a plurality of available buffer addresses in the data packet buffer; The control circuit is further configured to read an available buffer address from the buffer address pool and determine the buffer address of the network data packet in the data packet buffer according to the available buffer address.
7. The network data packet processing device according to claim 6, further comprising: A buffer management circuit for managing the use of the data packet buffer; Wherein the direct memory access controller further includes: A buffer address filling circuit, wherein the plurality of available buffer addresses are obtained by applying to the buffer management circuit through the buffer address filling circuit.
8. The network data packet processing device according to claim 7, wherein the capacity of the buffer address pool is M, and when the buffer address pool is initialized, the buffer address filling circuit is configured to apply to the buffer management circuit for M available buffer addresses and fill the M available buffer addresses into the buffer address pool.
9. The network data packet processing apparatus according to claim 7, wherein the capacity of the buffer address pool is M, and the buffer address filling circuit is used to monitor the usage of the buffer address pool, and when the number of available buffer addresses in the buffer address pool that have not been used by the control circuit reaches A, apply for (M - A) available buffer addresses to the buffer management circuit, and fill the (M - A) available buffer addresses into the buffer address pool.
10. A network data packet processing apparatus, comprising: A data packet buffer for storing network data packets; A circular buffer for storing data packet descriptors of the network data packets, wherein the data packet descriptor includes a first field; and A direct memory access controller, comprising: A control circuit for writing the network data packet into the data packet buffer and filling the relevant information of the buffer address of the network data packet in the data packet buffer into the first field.
11. The network data packet processing apparatus according to claim 10, further comprising: A network processor for performing predetermined data packet processing on the network data packet according to the data packet descriptor; Wherein the data packet descriptor further includes a second field; when the relevant information of the buffer address is filled into the first field, the direct memory access controller further fills a control code into the second field to indicate that the data packet descriptor is handed over to the network processor for processing.
12. The network data packet processing apparatus according to claim 10, wherein the direct memory access controller further comprises: A buffer address pool for storing a plurality of available buffer addresses in the data packet buffer; The control circuit is further used to read an available buffer address from the buffer address pool and determine the buffer address of the network data packet in the data packet buffer according to the available buffer address.
13. The network data packet processing apparatus according to claim 10, further comprising: A buffer management circuit for managing the usage of the data packet buffer; Wherein the direct memory access controller further comprises: A buffer address filling circuit, wherein the plurality of available buffer addresses are obtained by applying to the buffer management circuit through the buffer address filling circuit.
14. The network data packet processing apparatus according to claim 13, wherein the capacity of the buffer address pool is M, and when the buffer address pool is initialized, the buffer address filling circuit is used to apply for M available buffer addresses to the buffer management circuit and fill the M available buffer addresses into the buffer address pool.
15. The network data packet processing device according to claim 13, wherein the capacity of the buffer address pool is M, and the buffer address filling circuit is used to monitor the usage of the buffer address pool, and when the number of available buffer addresses in the buffer address pool that have not been used by the control circuit reaches A, apply for (M - A) available buffer addresses to the buffer management circuit, and fill the (M - A) available buffer addresses into the buffer address pool.