Method for switching DP interface to HDMI interface and interface converter

Abstract

The invention discloses a method for switching a DP interface to an HDMI interface and an interface converter. The method comprises the following steps: receiving a main data flow attribute MSA sent by the DP interface; analyzing the MSA to obtain the total amount of horizontal lines occupied by a vertical synchronization Vsync signal and a vertical back shoulder VBP; sending the data stream sent by the DP interface to the HDMI interface in a delayed manner, wherein the number of horizontal lines occupied by the delayed sending in the time domain is the total amount X; and when the data enable DE identifier is monitored in the data stream sent by the DP interface, sending a Vsync signal to the HDMI interface. Therefore, the data flow of the HDMI interface is staggered by X horizontal lines backwards relative to the data flow of the DP interface, and at the moment, the time domain position for sending the Vsync signal is overlapped with the position of the DE identifier. Furthermore, the Vsync signal is sent when the DE identifier is monitored, so that the normalization of the data stream sent to the HDMI interface is ensured, and the compatibility of switching the DP interface to the HDMI interface is improved. Compared with the method of carrying out software and hardware adaptation on the graphics card to enable the graphics card to have the capability of sending the AS-SDP, the resource overhead is relatively low, and the implementation cost is reduced.

Description

Technical Field

[0001] This application relates to the field of display technologies, and particularly to a method for converting a DP interface to an HDMI interface and an interface converter. Background Art

[0002] Currently, with the continuous development of display technologies, the usage experience of display devices is gradually being emphasized. For example, the Adaptive-Sync technology applied to the DisplayPort (DP) interface and the variable refresh rate (VRR) technology applied to the high definition multimedia interface (HDMI) can both dynamically adjust the refresh rate of a display device, enabling the display device to synchronously refresh according to the rendering speed of the graphics card. This effectively solves the problem of picture misalignment and tearing caused by the display device showing multiple frame picture contents within one frame refresh cycle when the refresh rates between the graphics card and the display device are not synchronized.

[0003] See Figure 1 As shown, these are the specific implementation manners of the Adaptive-Sync technology and the VRR technology. Generally, one refresh cycle of a display device includes a period for transmitting valid image data and a vertical blanking interval (VBI). Among them, the VBI is the time period between the last row of valid image data of the previous frame and the first row of valid image data of the next frame. Within the VBI, the graphics card can send a Vsync (vertical synchronization) signal to the display device to indicate that the display device is ready to refresh the next frame. Among them, the time period between the Vsync signal and the last row of valid image data of the previous frame is the vertical front porch (VFP), and the time period between the Vsync signal and the first row of valid image data of the next frame is the vertical back porch (VBP). Based on this, when the total width of the VBP and the Vsync signal (i.e., the number of horizontal lines occupied in the time domain) remains fixed, by adjusting the width of the VFP, the duration of the VBI can be dynamically changed, that is, the refresh cycle of the display device can be dynamically changed.

[0004] However, when a DP interface with Adaptive-Sync technology is used to connect to an HDMI interface with VRR technology, there are often compatibility risks. In the data transmission based on the HDMI interface, the widths of both the VBP and Vsync signals are fixed (the duration is fixed, that is, the number of horizontal lines occupied in the time domain remains unchanged). That is to say, after the dynamically changing VFP, the HDMI transmitter can generate and send a Vsync signal with a fixed width, followed by VBP data with a fixed width. In the data transmission based on the DP interface, the Vsync signal is packed into a data packet for transmission. This transmission method makes it difficult for the interface converter to determine the position of the Vsync signal in the time domain. Furthermore, when the interface converter forwards the data stream from the DP interface to the HDMI interface, due to the lack of position information of the Vsync signal in the time domain, the interface converter cannot accurately send a Vsync signal with a fixed width and VBP data after VFP, resulting in an irregular data stream sent to the HDMI interface and poor compatibility. Summary of the Invention

[0005] Embodiments of the present application provide a method and an interface converter for connecting a DP interface to an HDMI interface to improve the compatibility of the interface connection. In addition, embodiments of the present application also provide corresponding computing devices, computer-readable storage media, and computer program products.

[0006] In a first aspect, an embodiment of the present application provides a method for connecting a DP interface to an HDMI interface, including: receiving a Main Stream Attributes (MSA) sent by the DP interface; parsing the MSA to obtain the total number X of horizontal lines occupied by a Vertical Sync (Vsync) signal and a Vertical Back Porch (VBP), where X is a positive integer; delaying the transmission of the data stream sent by the DP interface to the HDMI interface, and the number of horizontal lines occupied by the delayed transmission in the time domain is X; when a Data Enable (DE) flag is detected in the data stream sent by the DP interface, sending the Vsync signal to the HDMI interface.

[0007] In a possible implementation manner, the method further includes: determining whether the data stream sent by the DP interface includes an Adaptive Vertical Sync Assist Packet (AS-SDP), where the AS-SDP is used to indicate the transmission time of the Vsync signal; the delaying the transmission of the data stream sent by the DP interface to the HDMI interface includes: when the data stream sent by the DP interface does not include the AS-SDP, delaying the transmission of the data stream sent by the DP interface to the HDMI interface; the sending the Vsync signal to the HDMI interface when the DE flag is detected in the data stream sent by the DP interface includes: when the data stream sent by the DP interface does not include the AS-SDP, sending the Vsync signal to the HDMI interface when the DE flag is detected in the data stream sent by the DP interface.

[0008] In a possible implementation manner, the method further includes: when the data stream sent by the DP interface includes the AS-SDP, directly sending the data stream sent by the DP interface to the HDMI interface; sending the Vsync signal to the HDMI interface at the transmission time of the Vsync signal indicated by the AS-SDP.

[0009] In a possible implementation manner, the delaying the transmission of the data stream sent by the DP interface to the HDMI interface includes: caching the data stream sent by the DP interface; when the number of horizontal lines in the cached data stream sent by the DP interface reaches X, sending the cached data stream sent by the DP interface to the HDMI interface.

[0010] In a possible implementation manner, the receiving the MSA sent by the DP interface includes: receiving the MSA within the first Vertical Blanking Interval (VBI) of the data stream transmitted by the DP interface.

[0011] In a second aspect, an interface converter for converting a DP interface to an HDMI interface according to an embodiment of the present application includes: a DP receiver, where the DP receiver is used to receive a Main Stream Attributes (MSA) sent by the DP interface; the DP receiver is further used to parse the MSA to obtain the total number X of horizontal lines occupied by the Vertical Sync (Vsync) signal and the Vertical Back Porch (VBP), where X is a positive integer; an HDMI transmitter, where the HDMI transmitter is used to delay the transmission of the data stream sent by the DP interface received by the DP receiver to the HDMI interface, and the number of horizontal lines occupied by the delayed transmission in the time domain is X; the HDMI transmitter is further used to send the Vsync signal to the HDMI interface when the DP receiver detects a Data Enable (DE) flag in the data stream sent by the DP interface.

[0012] In a possible implementation, the DP receiver is further configured to determine whether the data stream sent by the DP interface includes an Adaptive Vertical Sync Auxiliary Data Packet (AS-SDP), where the AS-SDP is used to indicate the transmission time of the Vsync signal; specifically, the HDMI transmitter is configured to, when the data stream sent by the DP interface does not include the AS-SDP, delay sending the data stream received by the DP receiver from the DP interface to the HDMI interface; when the DP receiver monitors a Data Enable (DE) flag in the data stream sent by the DP interface and the data stream sent by the DP interface does not include the AS-SDP, send the Vsync signal to the HDMI interface.

[0013] In a possible implementation, the HDMI transmitter is further configured to, when the data stream sent by the DP interface includes the AS-SDP, directly send the data stream received by the DP receiver from the DP interface to the HDMI interface; and send the Vsync signal to the HDMI interface at the transmission time of the Vsync signal indicated by the AS-SDP.

[0014] In a possible implementation, the DP receiver is further configured to cache the data stream sent by the DP interface; specifically, the HDMI receiver is configured to, when the number of horizontal lines in the data stream sent by the DP interface cached by the DP receiver reaches X, send the data stream cached by the DP receiver from the DP interface to the HDMI interface.

[0015] In a possible implementation, the DP receiver is specifically configured to receive the MSA within the first Vertical Blanking Interval (VBI) of the data stream transmitted by the DP interface.

[0016] In a third aspect, an embodiment of the present application further provides a computing device, which may include a processor and a memory: the memory is used to store a computer program; the processor is configured to execute the method according to the first aspect and any implementation manner of the first aspect based on the computer program.

[0017] In a fourth aspect, an embodiment of the present application further provides a computer-readable storage medium, which is used to store a computer program, and the computer program is used to execute the method according to the first aspect and any implementation manner of the first aspect.

[0018] Fifth aspect, an embodiment of the present application further provides a computer program product including instructions, which, when running on a computing device, causes the computing device to execute the method described in the above first aspect and any one of the implementation manners in the first aspect.

[0019] In the above implementation manner of the embodiment of the present application, receive the main stream attribute (MSA) sent by the DP interface; parse the MSA to obtain the total number of horizontal lines occupied by the vertical synchronization Vsync signal and VBP; delay sending the data stream sent by the DP interface to the HDMI interface, and the number of horizontal lines occupied in the time domain for the delay sending is the total amount X, where X is a positive integer; when a data enable DE flag is detected in the data stream sent by the DP interface, send the Vsync signal to the HDMI interface.

[0020] Generally, in the data transmission based on the DP interface, since the Vsync signal is packed into a data packet for sending, there is no identification information in the VBI for marking the time domain position of the Vsync signal. However, there is a data enable (DE) flag between the VBI and the first line of valid image data for transmitting a frame of picture, which is used to mark the start of the transmission of the valid image data. Based on this, by receiving the MSA sent by the DP interface, the total amount X of the horizontal lines occupied by the Vsync signal and VBP in the time domain can be parsed. Furthermore, when forwarding the data stream from the DP interface to the HDMI interface, delay sending X horizontal lines, that is to say, the data stream of the HDMI interface is staggered backward by X horizontal lines compared with the data stream of the DP interface. It can be understood that at this time, the time domain position of sending the Vsync signal in the data stream of the HDMI interface overlaps with the position of the DE flag in the DP interface. On this basis, when the DE flag is detected in the data stream sent by the DP interface, send the Vsync signal to the HDMI interface, which realizes the requirement of "accurately sending a Vsync signal and VBP data with a fixed width after VFP" specified in the VRR technology, ensures the standardization of the data stream sent to the HDMI interface, and improves the compatibility of the DP interface to the HDMI interface. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the drawings described below are only some embodiments recorded in the present application. For those of ordinary skill in the art, other drawings can also be obtained according to these drawings.

[0022] Figure 1 It is a schematic diagram of a specific implementation manner of an Adaptive-Sync technology and a VRR technology in an embodiment of the present application; Figure 2 Schematic diagram of a data transmission system in an embodiment of the present application; Figure 3 Schematic architecture diagram of an interface converter in an embodiment of the present application; Figure 4 Schematic flow diagram of a method for converting a DP interface to an HDMI interface in an embodiment of the present application; Figure 5 Schematic timing comparison diagram of converting a DP interface to an HDMI interface in an embodiment of the present application; Figure 6 Schematic hardware structure diagram of a computing device in an embodiment of the present application. Detailed implementation manners

[0023] Refer to Figure 2 , which is a schematic diagram of a data transmission system provided by the present application. As Figure 2 shown, the data transmission system 10 includes a graphics card, an interface converter, and a display device. Figure 1 Taking the interface converter 100, the graphics card 200, and the display device 300 as an example, in the actual application scenario, the data transmission system 10 may include a larger number of graphics cards, interface converters, and display devices.

[0024] Among them, the interface converter 100 refers to a device with the ability to convert and transmit data interfaces. For example, the interface converter 100 may be a docking station, etc., and there is no limitation thereto. In the embodiment of the present application, the interface converter 100 is used to implement the function of converting a DP interface to an HDMI interface. In more other embodiments, the interface converter 100 may also be an interface converter between other display interfaces, and there is no limitation thereto.

[0025] Refer to Figure 3 , which is a schematic architecture diagram of an interface converter provided by the present application. Figure 3 The interface converter shown may be Figure 2 the interface converter 100 in. The interface converter 100 includes a DP receiver 101 and an HDMI transmitter 102. Among them, the DP receiver 101 is used to receive, process, and decode the data stream of the DP interface, and the HDMI transmitter 102 is used to encode, process, and transmit the data stream of the HDMI interface. In addition, a memory (not shown in the figure) may be included in the DP receiver 101 or the HDMI transmitter 102, and the memory may be used to store the data stream. For example, the memory may be a buffer.

[0026] The graphics card 200 refers to a device with graphics processing and output capabilities. In the embodiment of the present application, the graphics card 200 may also specifically refer to the graphics processing unit (GPU) in the graphics card 200 for graphics processing and output.

[0027] The display device 300 refers to a device with specific image display capabilities, such as a liquid crystal display (LCD), an organic light-emitting diode display (OLED), etc.

[0028] The graphics card 200 and the interface converter 100, and the display device 300 and the interface converter 100 are connected by a connecting line. In the embodiments of the present application, the connecting line between the graphics card 200 and the interface converter 100 can be, for example, a DP transmission line, and the connecting line between the display device 300 and the interface converter 100 can be, for example, an HDMI transmission line. It should be noted that there may also be other interface converters or other connection devices between the graphics card 200 and the interface converter 100, and between the display device 300 and the interface converter 100, and this is not limited.

[0029] In an actual application scenario, the Adaptive-Sync technology applied to the DP interface and the VRR technology applied to the HDMI interface can both dynamically adjust the refresh rate of the display device, so that the display device synchronously refreshes according to the rendering speed of the graphics card, effectively solving the problem of screen tearing.

[0030] Generally, a refresh cycle of the display device includes a period for transmitting valid image data and the VBI. Among them, the VBI is the time period between the last row of valid image data of the previous frame and the first row of valid image data of the next frame (as Figure 1 shown). During the VBI, the graphics card can send a Vsync signal to the display device to indicate that the display device is ready to refresh the next frame. And, the time period before the Vsync signal is sent within the VBI is VFP, and the time period after the Vsync signal is sent is VBP. Therefore, in the Adaptive-Sync technology and the VRR technology, by fixing the width of the Vsync signal and the width of the VFP, and dynamically adjusting the width of the VFP, the width of the VBI can be dynamically changed, and then the refresh cycle (refresh rate) of the display device also changes accordingly.

[0031] It should be noted that in the embodiments of the present application, the width of each of the above time periods can be equivalent to the duration of each time period, or can be equivalent to the number of horizontal lines occupied by each time period in the time domain, and this is not limited. For example, in the present application, the width of the Vsync signal can specifically refer to the number of horizontal lines transmitted during the duration of the high-level pulse of the Vsync signal.

[0032] However, when a DP interface with Adaptive-Sync technology is connected to an HDMI interface with VRR technology, there are often compatibility risks. For VRR technology, the widths of the VBP and Vsync signals are fixed. That is to say, the width of the VFP varies dynamically with the refresh rate of the graphics card. After the dynamically changing VFP, the HDMI transmitter generates and sends a Vsync signal with a fixed width, followed by VBP data with a fixed width. It should be noted that in data transmission based on the HDMI interface, the flag bit of the Vsync signal (equivalent to the high or low level of the signal) is usually used as a specific control code and is transmitted in the Transition Minimized Differential Signaling (TMDS) channel 0. However, for Adaptive-Sync technology, even though the same implementation method of dynamically changing the width of VFP and keeping the widths of VBP and Vsync signals fixed is still used within the VBI, in data transmission based on the DP interface, the data stream is packed into data packets for transmission. This makes it difficult for the interface converter to determine the position of the Vsync signal in the time domain. That is to say, it is difficult to distinguish the time periods of VFP, VBP, and the transmission of the Vsync signal through the flag bit within the VBI. Furthermore, when the interface converter forwards the data stream from the DP interface to the HDMI interface, due to the lack of position information of the Vsync signal in the time domain, it is impossible to accurately send a Vsync signal with a fixed width and VBP data after the VFP, resulting in an irregular data stream sent to the HDMI interface and poor compatibility.

[0033] It should be noted that in data transmission based on the DP interface, the Adaptive Sync Secondary Data Packet (AS-SDP) can be used to indicate the position of the Vsync signal in the time domain. However, in practical applications, graphics cards often do not have the ability to send AS-SDP, and the implementation method of enabling the graphics card to send AS-SDP through software and hardware adaptation will incur significant costs and resource overheads.

[0034] Based on this, the interface converter 100 receives the main stream attribute (MSA) sent by the DP interface; the interface converter 100 parses the MSA to obtain the total number of horizontal lines occupied by the vertical sync Vsync signal and VBP; the interface converter 100 delays the transmission of the data stream sent by the DP interface to the HDMI interface, and the number of horizontal lines occupied by the delayed transmission in the time domain is the total amount X, where X is a positive integer; when the data enable DE flag is detected in the data stream sent by the DP interface, the interface converter 100 sends the Vsync signal to the HDMI interface.

[0035] Generally, in data transmission based on the DP interface, since the Vsync signal is packed into data packets for transmission, there is no identification information in the VBI for marking the time domain position of the Vsync signal. However, there is a DE identification between the VBI and the first line of valid image data for transmitting a frame of picture, which is used to mark the start of the transmission of valid image data. Based on this, by receiving the MSA sent by the DP interface, the total number X of horizontal lines occupied by the Vsync signal and the VBP in the time domain can be parsed. Furthermore, when forwarding the data stream from the DP interface to the HDMI interface, X horizontal lines are sent with a delay. That is to say, the data stream of the HDMI interface is staggered backward by X horizontal lines compared with the data stream of the DP interface. It can be understood that at this time, the time domain position for sending the Vsync signal in the data stream of the HDMI interface overlaps with the position of the DE identification in the DP interface. On this basis, when the DE identification is detected in the data stream sent by the DP interface, the Vsync signal is sent to the HDMI interface, realizing the requirement of "accurately sending the Vsync signal and VBP data with a fixed width after the VFP" specified in the VRR technology, ensuring the normativity of the data stream sent to the HDMI interface, and improving the compatibility of the DP interface to the HDMI interface. In addition, compared with the implementation method of making the graphics card have the AS-SDP sending ability through software and hardware adaptation, the resource overhead is often smaller, and the implementation cost of compatibility is effectively reduced.

[0036] To make the above objects, features, and advantages of the present application more obvious and understandable, the following will exemplarily illustrate various non-limiting implementation manners in the embodiments of the present application with reference to the accompanying drawings. Obviously, the described embodiments are part of the embodiments of the present application, rather than all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present application.

[0037] Refer to Figure 4 , Figure 4 shows a schematic flowchart of a method for converting a DP interface to an HDMI interface in an embodiment of the present application. This method can be applied to Figure 1 the data transmission system 10 shown in Figure 1 or can be applied to other applicable data transmission systems. The following takes the application to Figure 4 the data transmission system 10 shown in

[0038] S401: The interface converter 100 receives the MSA sent by the DP interface.

[0039] S402: The interface converter 100 parses the MSA to obtain the Vsync signal and the total number X of horizontal lines occupied by the VBP, where X is a positive integer.

[0040] The interface converter 100 may include a DP receiver 101. When the interface converter 100 receives the MSA sent by the DP interface, specifically, it may be the DP receiver 101 that receives the MSA sent by the DP interface. Similarly, when the interface converter 100 parses the MSA to obtain the above X, specifically, it may be the DP receiver 101 that parses the MSA to obtain the above X.

[0041] Among them, the MSA is used to describe the key information of the main data stream of the DP interface, so that the display device receiving the MSA can correctly parse and display the picture. The MSA may include, for example, information such as the number of horizontal pixels of the picture, the number of vertical pixels of the picture (i.e., the number of horizontal lines occupied by the valid image data), the number of horizontal lines occupied by the fixed Vsync signal and VBP respectively, the color depth, and the pixel format.

[0042] In actual application, the MSA is transmitted within each VBI. Therefore, to enable the interface converter 100 to adapt to and be compatible with the VRR technical specification as soon as possible, the DP receiver 101 can receive and parse the MSA within the first VBI of the DP data stream, so that the interface converter 100 can send a standard data stream to the HDMI interface during subsequent data stream transmission.

[0043] S403: The interface converter 100 delays sending the data stream sent by the DP interface to the HDMI interface, and the number of horizontal lines occupied by the delayed sending in the time domain is X.

[0044] S404: When the DE flag is detected in the data stream sent by the DP interface, the interface converter 100 sends the Vsync signal to the HDMI interface.

[0045] The interface converter 100 may include an HDMI transmitter 102. When the interface converter 100 delays sending the data stream sent by the DP interface to the HDMI interface, specifically, it may be that the HDMI transmitter 102 sends the data stream of the DP interface received by the DP receiver 101 to the HDMI interface. When the interface converter 100 sends the Vsync signal to the HDMI interface when the DE flag is detected in the data stream sent by the DP interface, specifically, when the DP receiver 101 detects the DE flag in the data stream sent by the DP interface, the HDMI transmitter 102 sends the Vsync signal to the HDMI interface.

[0046] The following combines Figure 5 to specifically introduce the delayed sending of the data stream by the interface converter 100.

[0047] Based on the relevant descriptions above, during the data transmission through the DP interface, since the Vsync signal is packed into the data packet for transmission, there is no identification information in the entire VBI that can be used to mark the time-domain position of the Vsync signal. However, there is a DE identification between the first line of valid image data of each frame and the VBI. This DE identification is mainly used to mark the start of the transmission of the valid image data, that is, the DE identification differentiates the VBI and the time period for transmitting the valid image data. Based on this, when the HDMI transmitter 102 forwards the data stream of the DP interface to the HDMI interface, if the data stream of the HDMI interface is delayed by a certain time for transmission, there will be a misalignment of X horizontal lines between the two data streams (that is, the delayed time occupies X horizontal lines in the time domain), as Figure 5 shown. Since the value of X is the number of horizontal lines fixedly occupied by the Vsync signal and the VBP, after the above delay, the DE identification in the DP interface data stream will overlap with the time when the Vsync signal is sent in the HDMI interface data stream. Therefore, once the DP receiver 101 detects the DE identification in the DP interface data stream, the HDMI transmitter 102 sends the Vsync signal to the HDMI interface, thus achieving the requirement of "accurately sending the Vsync signal and VBP data with a fixed width after the VFP" stipulated in the VRR technology, ensuring the normativity of the data stream sent to the HDMI interface and improving the compatibility of the DP interface to the HDMI interface.

[0048] Next, a specific introduction is given to the delay in sending the data stream of the DP interface by the interface converter 100. Exemplarily, there is a buffer in the DP receiver 101, which can be, for example, a line buffer. Based on this, the DP receiver 101 can receive and buffer the data stream sent by the DP interface, and when the data stream of the horizontal lines in the buffered data stream reaches the above-mentioned X, the HDMI transmitter 102 sends the data stream of the DP interface buffered in the buffer to the HDMI interface. In addition, the delay in sending the data stream of the DP interface by the interface converter 100 can also be other implementation forms, which are not limited herein.

[0049] In actual application, the graphics card 200 connected to the interface converter 100 may have the ability to send AS-SDP, where AS-SDP can be used to indicate the transmission time of the Vsync signal. Therefore, before step S403, the interface converter 100 can first determine whether the graphics card 200 has the ability to send AS-SDP. Exemplarily, AS-SDP is usually sent in each VBI. Therefore, if the interface converter 100 (specifically the DP receiver 101 therein) receives AS-SDP in the first VBI of the DP interface data stream, it can be determined that the graphics card 200 has the ability to send AS-SDP; on the contrary, if AS-SDP is not received in the first VBI of the DP interface data stream, it can be determined that the graphics card 200 does not have the ability to send AS-SDP (or even if it has this ability, the graphics card 200 does not send AS-SDP).

[0050] Further, in the case where the data stream sent through the DP interface does not include AS-SDP, the interface converter 100 can refer to S403 and S403 above to delay the transmission of the data stream, and send the Vsync signal to the HDMI interface when the DE flag is detected. Compared with the implementation method of making the graphics card have the ability to send AS-SDP through software and hardware adaptation, the resource overhead is often smaller, and the implementation cost of compatibility is effectively reduced.

[0051] In the case where the data stream sent through the DP interface includes AS-SDP, the interface converter 100 does not need to delay the transmission of the data stream, but can directly send the data stream sent through the DP interface to the HDMI interface. It can be understood that the above direct transmission of the data stream means that the data stream is not delayed by one or more horizontal lines, and the HDMI transmitter 102 directly sends the data stream. Furthermore, at the transmission time of the Vsync signal indicated by AS-SDP, the HDMI transmitter 102 can send the Vsync signal to the HDMI interface. The above implementation method of determining whether the graphics card 200 has the ability to send AS-SDP and adopting different compatibility means improves the flexibility and adaptability of implementing the VRR technology.

[0052] In addition, the embodiment of the present application also provides a computing device. Refer to Figure 6 , Figure 6 shows a schematic diagram of the hardware structure of a computing device in an embodiment of the present application. As Figure 6 shown, the computing device 600 may include a processor 601 and a memory 602.

[0053] Among them, the memory 602 is used to store computer programs; The processor 601 is configured to execute the method of converting a DP interface to an HDMI interface in the above method embodiment according to the computer program.

[0054] In addition, an embodiment of the present application further provides a computer-readable storage medium, which is used to store a computer program, and the computer program is used to execute the method of converting a DP interface to an HDMI interface in the above method embodiment.

[0055] In addition, an embodiment of the present application further provides a computer program product containing instructions, which, when running on a computing device, causes the computing device to execute the method of converting a DP interface to an HDMI interface in the above method embodiment.

[0056] From the description of the above embodiments, those skilled in the art can clearly understand that all or part of the steps in the above embodiment methods can be implemented by means of software plus a general hardware platform. Based on such an understanding, the technical solution of the present application can be embodied in the form of a software product, and the computer software product can be stored in a storage medium, such as a read-only memory (ROM) / RAM, magnetic disk, optical disk, etc., including several instructions for causing a computer device (which can be a personal computer, a server, or a network communication device such as a router) to execute the methods described in various embodiments or some parts of the embodiments of the present application.

[0057] Each embodiment in this specification is described in a progressive manner, and the same or similar parts between each embodiment can be referred to each other. Each embodiment focuses on the differences from other embodiments. In particular, for the device embodiment, since it is basically similar to the method embodiment, it is described relatively simply, and the relevant parts can be referred to the partial description of the method embodiment. The device embodiments described above are only illustrative. The modules described as separate components may or may not be physically separated, and the components shown as modules may or may not be physical modules, that is, they may be located in one place, or may be distributed to multiple network units. Some or all of the modules can be selected according to actual needs to achieve the purpose of the solution of this embodiment. Those of ordinary skill in the art can understand and implement it without creative efforts.

[0058] The above are only exemplary embodiments of the present application and are not used to limit the protection scope of the present application.

Claims

1. A method for converting a DP interface to an HDMI interface, characterized in that: The method comprises: Receiving a main data stream attribute MSA sent by the DP interface; Parse the MSA to obtain the total amount X of horizontal lines occupied by the vertical synchronization Vsync signal and the vertical back porch VBP, where X is a positive integer; Delaying the sending of the data stream sent by the DP interface to the HDMI interface, wherein the number of horizontal lines occupied by the delayed sending in the time domain is X; When a data enable DE flag is detected in the data stream sent by the DP interface, the Vsync signal is sent to the HDMI interface.

2. The method according to claim 1, characterized in that The method further comprises: Determine whether the data stream sent by the DP interface includes an adaptive vertical synchronization auxiliary data packet AS-SDP, where the AS-SDP is used to indicate the sending time of the Vsync signal; The delaying sending the data stream sent by the DP interface to the HDMI interface includes: When the data stream sent by the DP interface does not contain the AS-SDP, delay sending the data stream sent by the DP interface to the HDMI interface; When a DE identifier is detected in the data stream sent by the DP interface, sending the Vsync signal to the HDMI interface includes: In a case where the AS-SDP is not included in the data stream sent by the DP interface, when the DE identifier is detected in the data stream sent by the DP interface, the Vsync signal is sent to the HDMI interface.

3. The method according to claim 2, characterized in that The method further comprises: When the data stream sent by the DP interface includes the AS-SDP, directly sending the data stream sent by the DP interface to the HDMI interface; At the sending time of the Vsync signal indicated by the AS-SDP, the Vsync signal is sent to the HDMI interface.

4. The method according to any one of claims 1 to 3, characterized in that: The delaying sending the data stream sent by the DP interface to the HDMI interface includes: Buffering the data stream sent by the DP interface; When the number of horizontal lines in the buffered data stream sent by the DP interface reaches X, the buffered data stream sent by the DP interface is sent to the HDMI interface.

5. The method according to claim 1, characterized in that The receiving the MSA sent by the DP interface comprises: The MSA is received within the first vertical blanking period VBI of the DP interface transmission data stream.

6. An interface converter for converting a DP interface to an HDMI interface, the interface converter comprising: A DP receiver, the DP receiver is used to receive the main data stream attribute MSA sent by the DP interface; the DP receiver is also used to parse the MSA to obtain the total amount X of horizontal lines occupied by the vertical synchronization Vsync signal and the vertical back porch VBP, where X is a positive integer; An HDMI transmitter, wherein the HDMI transmitter is used to delay sending the data stream sent by the DP interface and received by the DP receiver to the HDMI interface, and the number of horizontal lines occupied by the delayed sending in the time domain is X; the HDMI transmitter is also used to send the Vsync signal to the HDMI interface when the DP receiver detects a data enable DE flag in the data stream sent by the DP interface.

7. The interface converter according to claim 6, characterized in that: The DP receiver is further used to determine whether the data stream sent by the DP interface contains an adaptive vertical synchronization auxiliary data packet AS-SDP, and the AS-SDP is used to indicate the sending time of the Vsync signal; The HDMI transmitter is specifically used to, when the data stream sent by the DP interface does not contain the AS-SDP, delay sending the data stream sent by the DP interface and received by the DP receiver to the HDMI interface; when the data stream sent by the DP interface does not contain the AS-SDP, when the DP receiver detects the data enable DE flag in the data stream sent by the DP interface, send the Vsync signal to the HDMI interface.

8. The interface converter according to claim 7, characterized in that: The HDMI transmitter is also used to, when the data stream sent by the DP interface contains the AS-SDP, directly send the data stream sent by the DP interface and received by the DP receiver to the HDMI interface; and send the Vsync signal to the HDMI interface at the sending time of the Vsync signal indicated by the AS-SDP.

9. The interface converter according to any one of claims 6 to 8, characterized in that: The DP receiver is also used to cache the data stream sent by the DP interface; the HDMI receiver is specifically used to send the data stream sent by the DP interface cached by the DP receiver to the HDMI interface when the number of horizontal lines in the data stream sent by the DP interface cached by the DP receiver reaches X.

10. The interface converter according to claim 6, characterized in that: The DP receiver is specifically used to receive the MSA within the first vertical blanking period VBI of the DP interface transmission data stream.

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