A method for converting a DP interface to an HDMI interface and an interface converter

Abstract

The present application discloses a method for converting a DP interface to an HDMI interface and an interface converter, comprising: receiving the main data stream attribute MSA sent by the DP interface; parsing the MSA to obtain the total number of horizontal lines occupied by the vertical synchronization Vsync signal and the vertical back porch VBP; delaying the sending of the data stream sent by the DP interface to the HDMI interface, and the number of horizontal lines occupied by the delayed sending in the time domain is a total of X; when a data enable DE flag is detected in the data stream sent by the DP interface, sending a Vsync signal to the HDMI interface. In this way, the data stream of the HDMI interface is staggered by X horizontal lines compared to the data stream of the DP interface, and the time domain position of the Vsync signal is overlapped with the position of the DE flag. Furthermore, when the DE flag is detected, the Vsync signal is sent, which ensures the standardization of the data stream sent to the HDMI interface and improves the compatibility of the DP interface to the HDMI interface. Compared with adapting the graphics card's software and hardware to enable it to have the ability to send AS-SDP, the resource overhead of the present application is small, which reduces the implementation cost.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a method for converting a DP interface to an HDMI interface and an interface converter. Background Art

[0002] With the continuous advancement of display technology, the user experience of display devices is becoming increasingly important. For example, Adaptive-Sync technology applied to the DisplayPort (DP) interface and variable refresh rate (VRR) technology applied to the high-definition multimedia interface (HDMI) can dynamically adjust the refresh rate of the display device, ensuring that the display device refreshes in sync with the graphics card's rendering speed. This effectively solves the problem of image distortion and tearing caused by the display device displaying multiple frames within a single refresh cycle when the refresh rates of the graphics card and display device are out of sync.

[0003] See also Figure 1 The figure below illustrates the specific implementation of Adaptive-Sync and VRR technologies. Generally, a display device refresh cycle consists of a period for transmitting active image data and a vertical blanking interval (VBI). The VBI is the time period between the last line of active image data in the previous frame and the first line of active image data in the next frame. Within the VBI, the graphics card can send a Vsync (vertical synchronization) signal to the display device, indicating that it is ready to refresh the next frame. The period between the Vsync signal and the last line of active image data in the previous frame is the vertical front porch (VFP), and the period between the Vsync signal and the first line of active image data in the next frame is the vertical back porch (VBP). By adjusting the width of the VFP, while keeping the total width of the VBP and Vsync signals (the number of horizontal lines occupied in the time domain) fixed, the duration of the VBI, and therefore the refresh cycle of the display device, can be dynamically varied.

[0004] However, when a DisplayPort interface using Adaptive-Sync technology is connected to an HDMI interface using VRR technology, compatibility risks often arise. In data transmission over an HDMI interface, the widths of the VBP and Vsync signals are fixed (the duration is fixed, meaning the number of horizontal lines occupied in the time domain remains constant). This means that after the dynamically changing VFP, the HDMI transmitter can generate and transmit a fixed-width Vsync signal, followed by fixed-width VBP data. In contrast, in data transmission over a DisplayPort interface, the Vsync signal is packaged into data packets for transmission. This transmission method makes it difficult for the interface converter to determine the Vsync signal's position in the time domain. Consequently, when the interface converter forwards the data stream from the DisplayPort interface to the HDMI interface, lacking information about the Vsync signal's position in the time domain, it cannot accurately transmit the fixed-width Vsync signal and VBP data after the VFP. This results in a non-standard data stream sent to the HDMI interface and poor compatibility. Summary of the Invention

[0005] The present invention provides a method for converting a DP interface to an HDMI interface and an interface converter to improve the compatibility of the interface conversion. In addition, the present invention also provides a corresponding computing device, a computer-readable storage medium, and a computer program product.

[0006] In the first aspect, an embodiment of the present application provides a method for converting a DP interface to an HDMI interface, including: receiving a main data stream attribute MSA sent by the DP interface; parsing the MSA to obtain the total number X of horizontal lines occupied by the vertical synchronization Vsync signal and the vertical back shoulder VBP, where X is a positive integer; delaying the sending of the data stream sent by the DP interface to the HDMI interface, and the number of horizontal lines occupied by the delayed sending in the time domain is X; when a data enable DE flag is detected in the data stream sent by the DP interface, sending the Vsync signal to the HDMI interface.

[0007] In a possible embodiment, the method also includes: determining whether the data stream sent by the DP interface contains an adaptive vertical synchronization auxiliary data packet AS-SDP, and the AS-SDP is used to indicate the sending time of the Vsync signal; delaying the sending of the data stream sent by the DP interface to the HDMI interface includes: when the data stream sent by the DP interface does not contain the AS-SDP, delaying the sending of the data stream sent by the DP interface to the HDMI interface; when the DE identifier is detected in the data stream sent by the DP interface, sending the Vsync signal to the HDMI interface includes: when the data stream sent by the DP interface does not contain the AS-SDP, when the DE identifier is detected in the data stream sent by the DP interface, sending the Vsync signal to the HDMI interface.

[0008] In a possible implementation, the method further includes: when the data stream sent by the DP interface includes the AS-SDP, directly sending the data stream sent by the DP interface to the HDMI interface; and sending the Vsync signal to the HDMI interface at the sending time of the Vsync signal indicated by the AS-SDP.

[0009] In one possible embodiment, the delaying sending of the data stream sent by the DP interface to the HDMI interface includes: caching the data stream sent by the DP interface; when the number of horizontal lines in the cached data stream sent by the DP interface reaches X, sending the cached data stream sent by the DP interface to the HDMI interface.

[0010] In a possible implementation manner, the receiving the MSA sent by the DP interface includes: receiving the MSA within the first vertical blanking interval (VBI) of the data stream transmitted by the DP interface.

[0011] In the second aspect, an embodiment of the present application provides an interface converter for converting a DP interface to an HDMI interface, including: a DP receiver, wherein the DP receiver is used to receive the main data stream attribute MSA sent by the DP interface; the DP receiver is also used to parse the MSA to obtain the total number X of horizontal lines occupied by the vertical synchronization Vsync signal and the vertical back shoulder VBP, wherein X is a positive integer; an HDMI transmitter, wherein the HDMI transmitter is used to delay sending the data stream sent by the DP interface received by the DP receiver to the HDMI interface, and the number of horizontal lines occupied by the delayed sending in the time domain is X; the HDMI transmitter is also used to send the Vsync signal to the HDMI interface when the DP receiver detects a data enable DE identifier in the data stream sent by the DP interface.

[0012] In one possible embodiment, the DP receiver is also used to determine whether the data stream sent by the DP interface contains an adaptive vertical synchronization auxiliary data packet AS-SDP, and the AS-SDP is used to indicate the sending time of the Vsync signal; the HDMI transmitter is specifically used to delay sending the data stream sent by the DP interface and received by the DP receiver to the HDMI interface when the data stream sent by the DP interface does not contain the AS-SDP; when the data stream sent by the DP interface does not contain the AS-SDP, when the DP receiver detects a data enable DE identifier in the data stream sent by the DP interface, it sends the Vsync signal to the HDMI interface.

[0013] In one possible embodiment, the HDMI transmitter is also used to, when the data stream sent by the DP interface includes the AS-SDP, directly send the data stream sent by the DP interface and received by the DP receiver to the HDMI interface; and send the Vsync signal to the HDMI interface at the sending time of the Vsync signal indicated by the AS-SDP.

[0014] In one possible embodiment, the DP receiver is also used to cache the data stream sent by the DP interface; the HDMI receiver is specifically used to send the data stream sent by the DP interface cached by the DP receiver to the HDMI interface when the number of horizontal lines in the data stream sent by the DP interface cached by the DP receiver reaches X.

[0015] In a possible implementation manner, the DP receiver is specifically configured to receive the MSA within a first vertical blanking period (VBI) of the DP interface transmission data stream.

[0016] In a third aspect, an embodiment of the present application further provides a computing device, which may include a processor and a memory: the memory is used to store a computer program; the processor is used to execute the method described in the first aspect and any one of the implementation methods of the first aspect according to the computer program.

[0017] In a fourth aspect, an embodiment of the present application further provides a computer-readable storage medium, wherein the computer-readable storage medium is used to store a computer program, and the computer program is used to execute the method described in the first aspect and any one of the implementation methods of the first aspect.

[0018] In a fifth aspect, an embodiment of the present application further provides a computer program product comprising instructions, which, when executed on a computing device, enables the computing device to execute the method described in the first aspect and any one of the implementation methods of the first aspect.

[0019] In the above-mentioned implementation method of the embodiment of the present application, the main stream attribute (MSA) sent by the DP interface is received; the MSA is parsed to obtain the total number of horizontal lines occupied by the vertical synchronization Vsync signal and the VBP; the data stream sent by the DP interface is delayed and sent to the HDMI interface, and the number of horizontal lines occupied by the delayed sending in the time domain is the total number X, where X is a positive integer; when the data enable DE flag is detected in the data stream sent by the DP interface, the Vsync signal is sent to the HDMI interface.

[0020] Generally, in data transmission based on the DP interface, since the Vsync signal is packaged into a data packet for transmission, there is no identification information in the VBI for marking the time domain position of the Vsync signal. However, there is a data enable (DE) identifier between the VBI and the first line of valid image data transmitted in a frame of the picture, which is used to mark the start of the transmission of valid image data. Based on this, by receiving the MSA sent by the DP interface, the total number of horizontal lines X occupied by the Vsync signal and the VBP time domain can be parsed. Furthermore, when forwarding the data stream from the DP interface to the HDMI interface, the transmission of X horizontal lines is delayed, that is, the data stream of the HDMI interface is staggered by X horizontal lines compared to the data stream of the DP interface. It can be understood that at this time, the time domain position of the Vsync signal sent in the data stream of the HDMI interface overlaps with the position of the DE identifier in the DP interface. On this basis, when the DE logo is detected in the data stream sent by the DP interface, the Vsync signal is sent to the HDMI interface, realizing the requirement of "accurately sending Vsync signals and VBP data with a fixed width after VFP" stipulated in the VRR technology, ensuring the standardization of the data stream sent to the HDMI interface, and improving the compatibility of the DP interface to the HDMI interface. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments recorded in the present application. For ordinary technicians in this field, other drawings can also be obtained based on these drawings.

[0022] Figure 1 Schematic diagram of a specific implementation of Adaptive-Sync technology and VRR technology in an embodiment of the present application;

[0023] Figure 2 This is a schematic diagram of a data transmission system in an embodiment of the present application;

[0024] Figure 3 This is a schematic diagram of the architecture of an interface converter according to an embodiment of the present application;

[0025] Figure 4 This is a flow chart of a method for converting a DP interface to an HDMI interface in an embodiment of the present application;

[0026] Figure 5 This is a timing comparison diagram of converting a DP interface to an HDMI interface in an embodiment of the present application;

[0027] Figure 6 This is a schematic diagram of the hardware structure of a computing device in an embodiment of the present application. DETAILED DESCRIPTION

[0028] See also Figure 2 , is a schematic diagram of a data transmission system provided by this application. Figure 2 As shown, the data transmission system 10 includes a graphics card, an interface converter and a display device. Figure 1 The interface converter 100, the graphics card 200 and the display device 300 are taken as an example. In actual application scenarios, the data transmission system 10 may include a larger number of graphics cards, interface converters and display devices.

[0029] The interface converter 100 refers to a device capable of converting and transmitting data interfaces. For example, the interface converter 100 may be a docking station, etc., without limitation. In the embodiment of the present application, the interface converter 100 is used to implement the function of converting a DP interface to an HDMI interface. In other embodiments, the interface converter 100 may also be an interface converter between other display interfaces, without limitation.

[0030] See also Figure 3 , is a schematic diagram of the architecture of an interface converter provided in this application. Figure 3 The interface converter shown can be Figure 2 The interface converter 100 includes a DisplayPort receiver 101 and an HDMI transmitter 102. The DisplayPort receiver 101 is used to receive, process, and decode the data stream of the DisplayPort interface, and the HDMI transmitter 102 is used to encode, process, and transmit the data stream of the HDMI interface. In addition, the DisplayPort receiver 101 or the HDMI transmitter 102 may include a memory (not shown in the figure), which can be used to store the data stream. For example, the memory can be a buffer.

[0031] The graphics card 200 refers to a device with graphics processing and output capabilities. In the embodiment of the present application, the graphics card 200 can also be used to specifically refer to a graphics processing unit (GPU) in the graphics card 200 for graphics processing and output.

[0032] The display device 300 refers to a device with specific image display capabilities, and may be, for example, a liquid crystal display (LCD), an organic light-emitting diode display (OLED), or the like.

[0033] The graphics card 200 and the interface converter 100, and the display device 300 and the interface converter 100 are connected via cables. In the embodiment of the present application, the cable between the graphics card 200 and the interface converter 100 may be, for example, a DP transmission cable, and the cable between the display device 300 and the interface converter 100 may be, for example, an HDMI transmission cable. It should be noted that other interface converters or other connecting devices may be present between the graphics card 200 and the interface converter 100, and between the display device 300 and the interface converter 100, and this is not limited to this.

[0034] In actual application scenarios, the Adaptive-Sync technology applied to the DP interface and the VRR technology applied to the HDMI interface can both dynamically adjust the refresh rate of the display device so that the display device refreshes synchronously according to the rendering speed of the graphics card, effectively solving the screen tearing phenomenon.

[0035] Generally, a refresh cycle of a display device includes a period for transmitting valid image data and VBI, wherein VBI is the time period between the last line of valid image data of the previous frame and the first line of valid image data of the next frame (e.g. Figure 1 As shown in the figure). Within the VBI, the graphics card can send a Vsync signal to the display device, instructing it to prepare to refresh the next frame. The period before the Vsync signal is sent within the VBI is called VFP, and the period after the Vsync signal is sent is called VBP. Therefore, in Adaptive-Sync and VRR technologies, by fixing the width of the Vsync signal and the width of the VFP and dynamically adjusting the width of the VFP, the VBI width can be dynamically changed, and the refresh period (refresh rate) of the display device can also change accordingly.

[0036] It should be noted that, in the embodiments of the present application, the width of each of the above time periods can be equivalent to the duration of each time period, or can be equivalent to the number of horizontal lines occupied by each time period in the time domain, without limitation. For example, in the present application, the width of the Vsync signal can specifically refer to the number of horizontal lines transmitted within the duration of the high-level pulse of the Vsync signal.

[0037] However, when a DP interface using Adaptive-Sync technology is connected to an HDMI interface using VRR technology, compatibility risks often exist. With VRR technology, the widths of the VBP and Vsync signals remain fixed. That is, the width of the VFP changes dynamically with the graphics card's refresh rate. Following the dynamically changing VFP, the HDMI transmitter generates and transmits a fixed-width Vsync signal, followed by fixed-width VBP data. It's worth noting that in data transmission over the HDMI interface, the Vsync signal's flag bit (equivalent to a high or low signal level) is typically transmitted as a specific control code in TMDS (Transition Minimized Differential Signaling) channel 0. However, for Adaptive-Sync technology, even though the same implementation method of dynamically changing the width of the VFP signal and keeping the width of the VBP and Vsync signals fixed is still used within the VBI, in data transmission based on the DP interface, the data stream is packaged into data packets for transmission. This makes it difficult for the interface converter to determine the position of the Vsync signal in the time domain. In other words, it is difficult to distinguish the VFP, VBP, and the time period for transmitting the Vsync signal through the flag bits within the VBI. Furthermore, when the interface converter forwards the data stream from the DP interface to the HDMI interface, due to the lack of information about the position of the Vsync signal in the time domain, it is unable to accurately send the fixed-width Vsync signal and VBP data after the VFP, resulting in an irregular data stream sent to the HDMI interface and poor compatibility.

[0038] It's important to note that in data transmission over the DisplayPort interface, the Adaptive Sync Secondary Data Packet (AS-SDP) can be used to indicate the time domain position of the Vsync signal. However, in real-world applications, graphics cards often lack the ability to send AS-SDP, and implementing software and hardware adaptations to enable AS-SDP incurs significant costs and resource overhead.

[0039] Based on this, the interface converter 100 receives the main stream attribute (MSA) sent by the DP interface; the interface converter 100 parses the MSA to obtain the total number of horizontal lines occupied by the vertical synchronization Vsync signal and VBP; the interface converter 100 delays sending the data stream sent by the DP interface to the HDMI interface, and the number of horizontal lines occupied by the delayed sending in the time domain is the total amount X, where X is a positive integer; when the data enable DE flag is detected in the data stream sent by the DP interface, the interface converter 100 sends the Vsync signal to the HDMI interface.

[0040] Generally, in data transmission over the DisplayPort interface, since the Vsync signal is packaged within a data packet for transmission, the VBI does not contain any identifier to mark the temporal position of the Vsync signal. However, a DE identifier exists between the VBI and the first line of valid image data transmitted within a frame, marking the start of transmission of valid image data. Based on this, by receiving the MSA sent by the DisplayPort interface, the total number of horizontal lines occupied by the Vsync signal and VBP in the temporal domain (X) can be parsed. Furthermore, when forwarding the data stream from the DisplayPort interface to the HDMI interface, the transmission is delayed by X horizontal lines. In other words, the HDMI interface data stream is offset by X horizontal lines relative to the DisplayPort data stream. It can be understood that the temporal position of the Vsync signal in the HDMI interface data stream overlaps with the position of the DE identifier in the DisplayPort interface. Therefore, when the DE identifier is detected in the data stream transmitted by the DisplayPort interface, a Vsync signal is transmitted to the HDMI interface. This fulfills the VRR technology requirement of "accurately transmitting a fixed-width Vsync signal and VBP data after the VFP," ensuring the standardization of the data stream transmitted to the HDMI interface and improving the compatibility of the DisplayPort to HDMI interface. In addition, compared with the implementation method of adapting the graphics card's hardware and software to enable it to send AS-SDP capabilities, the resource overhead is often smaller and the implementation cost of compatibility is effectively reduced.

[0041] To make the above-mentioned purposes, features, and advantages of the present application more clearly understood, various non-limiting embodiments of the embodiments of the present application will be exemplified below with reference to the accompanying drawings. Obviously, the described embodiments are only some of the embodiments of the present application, not all of them. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0042] See Figure 4 , Figure 4 A schematic diagram of a method for converting a DP interface to an HDMI interface in an embodiment of the present application is shown. The method can be applied to Figure 1The data transmission system 10 shown in FIG. 1 may be applied to other applicable data transmission systems. Figure 1 The data transmission system 10 shown in FIG. Figure 4 As shown, the method may specifically include the following steps.

[0043] S401: The interface converter 100 receives the MSA sent by the DP interface.

[0044] S402: The interface converter 100 parses the MSA to obtain the total amount X of horizontal lines occupied by the Vsync signal and the VBP, where X is a positive integer.

[0045] The interface converter 100 may include a DP receiver 101. The interface converter 100 receives the MSA sent by the DP interface, which may specifically be the DP receiver 101 receiving the MSA sent by the DP interface. Similarly, the interface converter 100 parses the MSA to obtain the above X, which may specifically be the DP receiver 101 parses the MSA to obtain the above X.

[0046] The MSA describes key information about the main data stream of the DP interface, enabling a display device receiving the MSA to correctly interpret and display the image. For example, the MSA may include information such as the horizontal pixel count, the vertical pixel count (i.e., the number of horizontal lines occupied by valid image data), the number of horizontal lines occupied by the fixed Vsync signal and VBP, respectively, the color depth, and the pixel format.

[0047] In actual application, the MSA is transmitted within each VBI. Therefore, in order to enable the interface converter 100 to adapt to the VRR technical specifications as quickly as possible, the DP receiver 101 can receive and parse the MSA within the first VBI of the DP data stream, so that in subsequent data stream transmission, the interface converter 100 can send a standardized data stream to the HDMI interface.

[0048] S403: The interface converter 100 delays sending the data stream sent by the DP interface to the HDMI interface, and the number of horizontal lines occupied by the delayed sending in the time domain is X.

[0049] S404: When a DE flag is detected in the data stream sent by the DP interface, the interface converter 100 sends a Vsync signal to the HDMI interface.

[0050] The interface converter 100 may include an HDMI transmitter 102, and the interface converter 100 delays sending the data stream sent by the DP interface to the HDMI interface. Specifically, the HDMI transmitter 102 sends the data stream of the DP interface received by the DP receiver 101 to the HDMI interface. When the DE identifier is detected in the data stream sent by the DP interface, the interface converter 100 sends a Vsync signal to the HDMI interface. Specifically, when the DP receiver 101 detects the DE identifier in the data stream sent by the DP interface, the HDMI transmitter 102 sends a Vsync signal to the HDMI interface.

[0051] The following combination Figure 5 , the interface converter 100 delays sending data streams and is specifically introduced.

[0052] Based on the above description, it can be known that in the process of data transmission through the DP interface, since the Vsync signal is packaged into a data packet for transmission, there is no identification information in the entire VBI that can be used to mark the time domain position of the Vsync signal. However, there will be a DE identifier between the first line of valid image data and the VBI when transmitting each frame of the picture. The DE identifier is mainly used to mark the start of the transmission of valid image data, that is, the DE identifier distinguishes the VBI from the time period for transmitting valid image data. Based on this, when the HDMI transmitter 102 forwards the data stream of the DP interface to the HDMI interface, if the data stream of the HDMI interface is delayed for a certain time before being sent, there will be a misalignment of X horizontal lines between the two data streams (that is, the delayed time occupies X horizontal lines in the time domain), such as Figure 5 As shown. Since the value of X is the number of horizontal lines fixedly occupied by the Vsync signal and VBP, after the above delay, the DE identifier in the DP interface data stream will overlap with the time when the Vsync signal is sent in the HDMI interface data stream. Therefore, once the DP receiver 101 detects the DE identifier in the DP interface data stream, the HDMI transmitter 102 sends the Vsync signal to the HDMI interface, thus achieving the requirement of "accurately sending a fixed-width Vsync signal and VBP data after VFP" stipulated in the VRR technology, ensuring the standardization of the data stream sent to the HDMI interface and improving the compatibility of the DP interface to the HDMI interface.

[0053] The following describes in detail how the interface converter 100 delays the transmission of the DP interface data stream. For example, the DP receiver 101 includes a buffer, such as a line buffer. Based on this, the DP receiver 101 can receive and buffer the data stream transmitted by the DP interface. When the horizontal line of data in the buffered data stream reaches the aforementioned X, the HDMI transmitter 102 transmits the DP interface data stream buffered in the buffer to the HDMI interface. Furthermore, the interface converter 100 can also delay the transmission of the DP interface data stream in other implementations, which are not limited to this.

[0054] In actual practice, the graphics card 200 connected to the interface converter 100 may be capable of sending AS-SDP, where AS-SDP can be used to indicate the transmission time of the Vsync signal. Therefore, before step S403, the interface converter 100 can first determine whether the graphics card 200 is capable of sending AS-SDP. For example, AS-SDP is typically sent in every VBI. Therefore, if the interface converter 100 (specifically, the DP receiver 101 therein) receives AS-SDP in the first VBI of the DP interface data stream, it can be determined that the graphics card 200 is capable of sending AS-SDP. Conversely, if AS-SDP is not received in the first VBI of the DP interface data stream, it can be determined that the graphics card 200 is not capable of sending AS-SDP (or even if it is capable, the graphics card 200 does not send AS-SDP).

[0055] Furthermore, when the data stream sent by the DP interface does not contain AS-SDP, the interface converter 100 can refer to S403 and S404 above to delay the transmission of the data stream and send a Vsync signal to the HDMI interface when the DE flag is detected. Compared with the implementation method of adapting the graphics card's software and hardware to enable it to send AS-SDP, the resource overhead is often small and the cost of implementing compatibility is effectively reduced.

[0056] If the data stream sent by the DP interface includes AS-SDP, the interface converter 100 does not need to delay the data stream, but can directly send the data stream sent by the DP interface to the HDMI interface. It can be understood that the above-mentioned direct transmission of the data stream means that the data stream is not delayed by one or more horizontal lines, and the data stream is directly sent by the HDMI transmitter 102. Furthermore, at the time of sending the Vsync signal indicated by the AS-SDP, the HDMI transmitter 102 can send the Vsync signal to the HDMI interface. The above-mentioned method of determining whether the graphics card 200 has the ability to send AS-SDP and adopting different compatibility measures improves the flexibility and adaptability of implementing VRR technology.

[0057] In addition, the present application also provides a computing device. Figure 6 , Figure 6 FIG. 1 shows a schematic diagram of the hardware structure of a computing device in an embodiment of the present application. Figure 6 As shown, computing device 600 may include a processor 601 and a memory 602 .

[0058] The memory 602 is used to store computer programs;

[0059] The processor 601 is configured to execute the method for converting a DP interface to an HDMI interface described in the above method embodiment according to the computer program.

[0060] In addition, an embodiment of the present application also provides a computer-readable storage medium, which is used to store a computer program, and the computer program is used to execute the method of converting the DP interface to the HDMI interface described in the above method embodiment.

[0061] In addition, an embodiment of the present application also provides a computer program product containing instructions, which, when executed on a computing device, enables the computing device to execute the method of converting the DP interface to the HDMI interface described in the above method embodiment.

[0062] Through the description of the above embodiments, it can be seen that those skilled in the art can clearly understand that all or part of the steps in the above-mentioned embodiment methods can be implemented by means of software plus a general hardware platform. Based on this understanding, the technical solution of the present application can be embodied in the form of a software product. The computer software product can be stored in a storage medium, such as a read-only memory (ROM) / RAM, a magnetic disk, an optical disk, etc., and includes a number of instructions for enabling a computer device (which can be a personal computer, a server, or a network communication device such as a router) to execute the methods described in various embodiments or certain parts of the embodiments of the present application.

[0063] Each embodiment in this specification is described in a progressive manner. The same or similar parts between the embodiments can be referred to each other. Each embodiment focuses on the differences from other embodiments. In particular, for the device embodiment, since it is basically similar to the method embodiment, the description is relatively simple. For the relevant parts, refer to the partial description of the method embodiment. The device embodiment described above is only exemplary. The modules described as separate components may or may not be physically separated, and the components shown as modules may or may not be physical modules, that is, they may be located in one place or distributed on multiple network units. Some or all of the modules can be selected according to actual needs to achieve the purpose of the solution of this embodiment. A person of ordinary skill in the art can understand and implement it without making any creative efforts.

[0064] The above description is merely an exemplary embodiment of the present application and is not intended to limit the scope of protection of the present application.

Claims

1. A method for converting a DP interface to an HDMI interface, characterized in that: The method comprises: Receiving a main data stream attribute MSA sent by the DP interface; Parsing the MSA to obtain a total amount X of horizontal lines occupied by the vertical synchronization Vsync signal and the vertical back porch VBP, where X is a positive integer; Delaying the sending of the data stream sent by the DP interface to the HDMI interface, wherein the number of horizontal lines occupied by the delayed sending in the time domain is X; When a data enable DE flag is detected in the data stream sent by the DP interface, the Vsync signal is sent to the HDMI interface, and the DE flag is used to separate the time period for transmitting the VBP from the time period for transmitting valid image data.

2. The method according to claim 1, characterized in that The method further comprises: Determine whether the data stream sent by the DP interface includes an adaptive vertical synchronization auxiliary data packet AS-SDP, where the AS-SDP is used to indicate the sending time of the Vsync signal; The delaying sending the data stream sent by the DP interface to the HDMI interface includes: When the data stream sent by the DP interface does not include the AS-SDP, delaying the sending of the data stream sent by the DP interface to the HDMI interface; When a DE identifier is detected in the data stream sent by the DP interface, sending the Vsync signal to the HDMI interface includes: In a case where the data stream sent by the DP interface does not contain the AS-SDP, when the DE identifier is detected in the data stream sent by the DP interface, the Vsync signal is sent to the HDMI interface.

3. The method according to claim 2, characterized in that The method further comprises: When the data stream sent by the DP interface includes the AS-SDP, directly sending the data stream sent by the DP interface to the HDMI interface; At the sending time of the Vsync signal indicated by the AS-SDP, the Vsync signal is sent to the HDMI interface.

4. The method according to any one of claims 1 to 3, characterized in that The delaying sending the data stream sent by the DP interface to the HDMI interface includes: Buffering the data stream sent by the DP interface; When the number of horizontal lines in the buffered data stream sent by the DP interface reaches X, the buffered data stream sent by the DP interface is sent to the HDMI interface.

5. The method according to claim 1, wherein The receiving the MSA sent by the DP interface includes: The MSA is received within the first vertical blanking period (VBI) of the DP interface transmission data stream.

6. An interface converter for converting a DP interface to an HDMI interface, the interface converter comprising: A DP receiver, the DP receiver is used to receive the main data stream attribute MSA sent by the DP interface; the DP receiver is further used to parse the MSA to obtain the total amount X of horizontal lines occupied by the vertical synchronization Vsync signal and the vertical back porch VBP, where X is a positive integer; An HDMI transmitter, wherein the HDMI transmitter is used to delay sending the data stream sent by the DP interface and received by the DP receiver to the HDMI interface, and the number of horizontal lines occupied by the delayed sending in the time domain is X; the HDMI transmitter is also used to send the Vsync signal to the HDMI interface when the DP receiver detects a data enable DE identifier in the data stream sent by the DP interface, and the DE identifier is used to separate the time period for transmitting the VBP from the time period for transmitting valid image data.

7. The interface converter according to claim 6, wherein: The DP receiver is further configured to determine whether the data stream sent by the DP interface includes an adaptive vertical synchronization auxiliary data packet AS-SDP, where the AS-SDP is used to indicate a sending time of the Vsync signal; The HDMI transmitter is specifically used to delay sending the data stream sent by the DP interface and received by the DP receiver to the HDMI interface when the data stream sent by the DP interface does not contain the AS-SDP; when the data stream sent by the DP interface does not contain the AS-SDP, when the DP receiver detects the data enable DE flag in the data stream sent by the DP interface, send the Vsync signal to the HDMI interface.

8. The interface converter according to claim 7, wherein: The HDMI transmitter is also used to, when the data stream sent by the DP interface contains the AS-SDP, directly send the data stream sent by the DP interface and received by the DP receiver to the HDMI interface; and send the Vsync signal to the HDMI interface at the sending time of the Vsync signal indicated by the AS-SDP.

9. The interface converter according to any one of claims 6 to 8, characterized in that: The DP receiver is also used to cache the data stream sent by the DP interface; the HDMI receiver is specifically used to send the data stream sent by the DP interface cached by the DP receiver to the HDMI interface when the number of horizontal lines in the data stream sent by the DP interface cached by the DP receiver reaches X.

10. The interface converter according to claim 6, wherein: The DP receiver is specifically configured to receive the MSA within the first vertical blanking period (VBI) of the DP interface transmission data stream.

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