Semiconductor structure and method of manufacturing the same

Abstract

The embodiment of the present disclosure relates to the technical field of semiconductor, and provides a semiconductor structure and a manufacturing method thereof, the manufacturing method comprising: providing a substrate and a first dielectric layer, the substrate comprising a first part, a plurality of second parts arranged at intervals along a first direction on the first part, and a plurality of third parts arranged at intervals along a second direction on a side of the second parts away from the first part, and the first dielectric layer being located at least between adjacent second parts; removing at least part of the first part and part of the thickness of the second part to expose a remaining area of the second part and form a groove between adjacent first dielectric layers; performing a metallization process on the second part exposed by the groove to form a bit line extending along the second direction; and forming at least one bit line contact block in at least part of the groove, and one bit line being in contact with the at least one bit line contact block. The embodiment of the present disclosure is at least beneficial to improving the alignment accuracy between the bit line and the bit line contact block.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and in particular to a semiconductor structure and its manufacturing method. Background Technology

[0002] In two-dimensional or planar semiconductor devices, memory cells are arranged horizontally. Therefore, the integration density of two-dimensional or planar semiconductor devices can be determined by the area occupied by a single memory cell. However, the integration density of two-dimensional or planar semiconductor devices is greatly affected by the technology for forming fine patterns, which limits the continuous increase in the integration density of two-dimensional or planar semiconductor devices. Therefore, the development of semiconductor devices has moved towards three-dimensional semiconductor devices. Three-dimensional semiconductor devices can solve the density limitations of planar memory cells. Three-dimensional semiconductor devices include memory arrays and peripheral circuits to facilitate the operation of the memory array.

[0003] However, as the feature size of a unit memory cell approaches its lower limit, the process and manufacturing technology become challenging and costly, and the shrinking spacing between adjacent unit memory cells places higher demands on the alignment accuracy between unit memory cells and other devices. Summary of the Invention

[0004] This disclosure provides a semiconductor structure and a method for manufacturing the same, which at least helps to improve the alignment accuracy between bit lines and bit line contact blocks.

[0005] According to some embodiments of this disclosure, one aspect of this disclosure provides a method for manufacturing a semiconductor structure, comprising: providing a substrate and a first dielectric layer, the substrate including a first portion, a plurality of second portions located on the first portion and spaced apart along a first direction, and a plurality of third portions located on a side of the second portions away from the first portion and spaced apart along a second direction, the first dielectric layer being located at least between adjacent second portions, the second portions being used to form bit lines, the third portions being used to form semiconductor pillars, the first direction and the second direction intersecting; removing at least a portion of the first portion and a portion of the thickness of the second portions to expose the remaining area of ​​the second portions, and forming a groove between adjacent first dielectric layers; metallizing the second portions exposed by the groove to form the bit lines extending along the second direction; forming at least one bit line contact block in at least a portion of the groove, a bit line being contacted and connected to at least one bit line contact block.

[0006] In some embodiments, the step of removing at least a portion of the first portion and a portion of the second thickness includes: forming a first mask layer having a first opening extending along a first direction, and a plurality of the first openings being spaced apart along a second direction; etching the first portion and a portion of the second thickness exposed by the first opening using the first mask layer as a mask to form a plurality of the grooves spaced apart along the first and second directions; the step of forming at least one bit line contact block in at least a portion of the grooves includes: forming a second dielectric layer filling the grooves; removing a portion of the second dielectric layer in the grooves and forming the bit line contact block.

[0007] In some embodiments, the first direction and the second direction constitute a reference surface, the orthographic projection of the first opening onto the reference surface is a first projection, the orthographic projection of the interval between adjacent third portions along the second direction onto the reference surface is a second projection, and the orthographic projection of the third portion onto the reference surface is a third projection; wherein, the first projection is located within the second projection; or, the first projection and the third projection at least partially overlap.

[0008] In some embodiments, the step of removing at least a portion of the first portion and a portion of the second portion includes: removing the first portion across the entire surface to expose the second portion; continuing to remove a portion of the second portion to form the groove extending along the second direction, the groove and the second portion corresponding one-to-one; the step of forming at least one bit line contact block in at least a portion of the groove includes: forming a second dielectric layer that fills the groove; patterning the second dielectric layer to expose a portion of the groove, and the portion of the groove exposing the bit line; forming the bit line contact block in the portion of the groove.

[0009] In some embodiments, the bit line contact blocks that are in contact with adjacent bit lines are staggered along the first direction, and / or the bit line contact blocks that are in contact with adjacent bit lines are staggered along the second direction.

[0010] In some embodiments, along a direction from the first portion to the second portion, the third portion includes a first sub-portion, a second sub-portion, and a third sub-portion arranged sequentially, the first direction and the second direction forming a reference plane; the substrate further includes: a gate structure and a third dielectric layer, the gate structure surrounding the sidewalls of a plurality of second sub-portions arranged along the first direction, the third dielectric layer being located at least between adjacent gate structures; the manufacturing method further includes: removing the first portion; forming a second mask layer on the side of the first dielectric layer away from the gate structure, the second mask layer having a plurality of second openings, the orthographic projection of one of the second openings on the reference plane at least overlapping the orthographic projection of one of the gate structures on the reference plane; using the third dielectric layer as an etch stop layer, using the second mask layer as a mask to etch the first dielectric layer exposed by the second openings until the gate structure is exposed and a via is formed; forming word line contact blocks in the vias, one of the gate structures being contacted and connected to at least one of the word line contact blocks.

[0011] In some embodiments, the orthographic projection of the second opening on the reference plane overlaps only with the orthographic projection of the gate structure on the reference plane, and the second opening is used only to form a word line contact block.

[0012] In some embodiments, along the second direction, the length of the second opening is greater than the spacing between two adjacent third dielectric layers, and in the step of forming the via, at least a portion of the top surface of the third dielectric layer away from the second portion is also exposed, and along the second direction, the orthographic projection of only one of the adjacent gate structures on the reference plane overlaps with the orthographic projection of the second opening on the reference plane.

[0013] In some embodiments, the third dielectric layer is also located between adjacent bit lines, and the orthographic projection of a second opening on the reference plane overlaps with the orthographic projections of at least two adjacent gate structures on the reference plane. The second opening is used to form at least two word line contact blocks. In the step of etching the first dielectric layer exposed by the second opening using the third dielectric layer as an etch barrier layer and the second mask layer as a mask, at least two vias spaced apart by the third dielectric layer are formed along the second direction.

[0014] In some embodiments, the formed through hole exposes at least one sidewall of the first sub-part; after forming the through hole and before forming the word line contact block, the method further includes: forming a protective layer on the sidewall of the through hole, the protective layer and the bottom surface of the through hole together forming a sub-through hole; forming the word line contact block in the through hole includes: forming the word line contact block that fills the sub-through hole.

[0015] According to some embodiments of this disclosure, another aspect of this disclosure provides a semiconductor structure, comprising: a substrate having a vertical transistor therein, the vertical transistor including a semiconductor pillar extending along a third direction, the semiconductor pillar having a first surface and a second surface opposite to each other in the third direction, the first surface being the back surface of the substrate; a plurality of bit lines spaced apart along a first direction, one of the bit lines contacting a plurality of first surfaces spaced apart along a second direction, the bit lines having a metal semiconductor compound, the first direction, the second direction, and the third direction intersecting each other; a plurality of bit line contact blocks, one of the bit lines contacting at least one bit line contact block on a side of the third direction away from the semiconductor pillar, and the sidewalls of the bit line contact blocks extending along the third direction are all surrounded by a dielectric layer.

[0016] In some embodiments, along the third direction, the semiconductor pillar includes a first sub-section, a second sub-section, and a third sub-section arranged sequentially, the first sub-section being contacted and connected to the bit line; the vertical transistor further includes a gate structure surrounding the sidewalls of a plurality of second sub-sections arranged along the first direction; the semiconductor structure further includes a plurality of word line contact blocks, one of the gate structures being contacted and connected to at least one of the word line contact blocks along the third direction away from the second surface.

[0017] In some embodiments, the semiconductor structure further includes: a protective layer located on two opposite sidewalls of the word line contact block along the first direction, and / or located on two opposite sidewalls of the word line contact block along the second direction.

[0018] In some embodiments, the word line contact blocks that are in contact with adjacent gate structures are staggered along the first direction, and / or the word line contact blocks that are in contact with adjacent gate structures are staggered along the second direction.

[0019] In some embodiments, the bit line contact blocks that are in contact with adjacent bit lines are staggered along the first direction, and / or the bit line contact blocks that are in contact with adjacent bit lines are staggered along the second direction.

[0020] The technical solutions provided in this disclosure have at least the following advantages:

[0021] On the one hand, combining the steps of metallizing a portion of the substrate to form bit lines and forming bit line contact blocks simplifies the process steps for forming bit lines and bit line contact blocks. On the other hand, removing a portion of the substrate to expose the remaining second portion of the substrate and forming a groove between adjacent first dielectric layers allows us to understand that the remaining second portion constitutes the bottom surface of the groove, and at least a portion of the side surfaces of the groove are formed by a second dielectric layer. In other words, a second dielectric layer exists between different grooves corresponding to two adjacent bit lines. Therefore, when at least one bit line contact block is formed in at least a portion of the groove, since the bit line contact block is located in the groove, a second dielectric layer also exists between different bit line contact blocks corresponding to two adjacent bit lines, effectively preventing adjacent bit lines from being short-circuited through the same bit line contact block. This improves the conductivity of the finally formed bit lines while enabling self-alignment between the bit line contact blocks and the bit lines, thereby improving the alignment accuracy between the bit line contact blocks and the bit lines. Attached Figure Description

[0022] One or more embodiments are illustrated by way of example with corresponding pictures in the accompanying drawings. These illustrations do not constitute a limitation on the embodiments. Elements with the same reference numerals in the drawings represent similar elements. Unless otherwise stated, the figures in the drawings do not constitute a limitation on scale. In order to more clearly illustrate the technical solutions in the embodiments of this disclosure or the conventional technology, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0023] Figure 1 A flowchart corresponding to each step in a semiconductor structure manufacturing method provided in an embodiment of this disclosure;

[0024] Figures 2 to 28 This is a schematic diagram of the structure corresponding to each step in a semiconductor structure manufacturing method provided in an embodiment of the present disclosure. Detailed Implementation

[0025] As can be seen from the background technology, the alignment accuracy between a unit memory cell and other devices in a three-dimensional semiconductor device needs to be improved.

[0026] Analysis revealed that in three-dimensional semiconductor devices, the spacing between adjacent bit lines and word lines is limited to increase the integration density per unit memory cell. However, this limitation places higher demands on the alignment accuracy between the conductive structures in the peripheral circuitry that are individually connected to each bit line and the word lines. Currently, in masking and patterning processes, alignment errors between the mask and the memory cell, coupled with the limited spacing between adjacent bit lines and word lines, can easily lead to short circuits between conductive structures in the peripheral circuitry and at least two bit lines, or at least two word lines, or both. This can result in short circuits between adjacent bit lines, adjacent word lines, or bit lines and word lines, thus affecting the electrical performance of the semiconductor device.

[0027] This disclosure provides a semiconductor structure and its manufacturing method. In the manufacturing method, on one hand, the steps of metallizing a portion of a substrate to form bit lines and forming bit line contact blocks are combined, which simplifies the process steps for forming bit lines and bit line contact blocks. On the other hand, a portion of the substrate is removed to expose a second portion of the remaining area in the substrate, and a groove is formed between adjacent first dielectric layers. It is understood that the remaining area of ​​the second portion constitutes the bottom surface of the groove, and at least a portion of the side surfaces of the groove are formed by a second dielectric layer. In other words, a second dielectric layer exists between different grooves corresponding to two adjacent bit lines. Therefore, when at least one bit line contact block is formed in at least a portion of the groove, since the bit line contact block is located in the groove, a second dielectric layer also exists between different bit line contact blocks corresponding to two adjacent bit lines, effectively preventing adjacent bit lines from being short-circuited through the same bit line contact block. This improves the conductivity of the finally formed bit lines while enabling self-alignment between the bit line contact blocks and the bit lines, thereby improving the alignment accuracy between the bit line contact blocks and the bit lines.

[0028] The embodiments of this disclosure will now be described in detail with reference to the accompanying drawings. However, those skilled in the art will understand that many technical details have been provided in the embodiments of this disclosure to facilitate a better understanding of the embodiments. However, the technical solutions claimed in the embodiments of this disclosure can be implemented even without these technical details and various variations and modifications based on the following embodiments.

[0029] This disclosure provides a method for manufacturing a semiconductor structure according to an embodiment. The method for manufacturing a semiconductor structure according to an embodiment of this disclosure will be described in detail below with reference to the accompanying drawings. Figure 1A flowchart corresponding to each step in a semiconductor structure manufacturing method provided in an embodiment of this disclosure; Figures 2 to 28 This is a schematic diagram of the structure corresponding to each step in a semiconductor structure manufacturing method provided in an embodiment of this disclosure. It should be noted that, for ease of description and clear illustration of the steps of the semiconductor structure fabrication method, the following diagrams are provided in an embodiment of this disclosure. Figures 2 to 28 These are partial structural diagrams of semiconductor structures.

[0030] refer to Figures 1 to 28 The manufacturing method of semiconductor structures includes the following steps:

[0031] S101: Reference Figure 2 and Figure 3 The system provides a substrate 100 and a first dielectric layer 111. The substrate 100 includes a first portion 110, a plurality of second portions 120 located on the first portion 110 and spaced apart along a first direction X, and a plurality of third portions 130 located on the side of the second portions 120 away from the first portion 110 and spaced apart along a second direction Y. The first dielectric layer 111 is located at least between adjacent second portions 120. The second portions 120 are used to form bit lines 102, and the third portions 130 are used to form semiconductor pillars. The first direction X and the second direction Y intersect.

[0032] in, Figure 2 A three-dimensional structural diagram of a substrate and a first dielectric layer in a manufacturing method provided in an embodiment of the present disclosure; Figure 3 for Figure 2 The diagram shows a cross-sectional structure along the first cross-section direction AA1.

[0033] It should be noted that in the substrate 100, the first part 110 can be regarded as the bottom of the substrate 100, and the first part 110 is a full-area film layer, that is, the first part 110 has a large extension width along the first direction X and the second direction Y; the second part 120 can be regarded as the initial bit line, that is, the semiconductor material layer that has not yet been doped with metal elements. Subsequently, at least part of the second part 120 is metallized to form a bit line with better conductivity. The second part 120 is a strip structure extending along the second direction Y; the third part 130 is used to form semiconductor pillars. The third part 130 is a pillar structure, and the pillar structure is arranged in an array along the first direction X and the second direction Y.

[0034] In some cases, refer to Figure 1The substrate 100 can be made of either an elemental semiconductor material or a crystalline inorganic compound semiconductor material. Elemental semiconductor materials can be silicon or germanium; crystalline inorganic compound semiconductor materials can be silicon carbide, silicon germanide, gallium arsenide, or indium gallium phosphate, etc. Furthermore, the first portion 110, the second portion 120, and the third portion 130 are all components of the substrate 100, meaning they contain the same semiconductor elements. In practical applications, the first portion 110, the second portion 120, and the third portion 130 can be formed using the same film structure composed of semiconductor elements, making them a single structure. This allows for the mitigation of interface state defects between the bit lines formed subsequently based on the second portion 120 and the semiconductor pillars subsequently formed based on the third portion 130, thereby improving the performance of the semiconductor structure.

[0035] It should be noted that the method of forming the first part 110, the second part 120 and the third part 130 is not limited in one embodiment of this disclosure.

[0036] In some embodiments, the semiconductor element may include at least one of silicon, carbon, germanium, arsenic, gallium, and indium. In one example, the first portion 110, the second portion 120, and the third portion 130 all include silicon.

[0037] Understandably, continue to refer to Figure 1 Multiple second portions 120 extending along the second direction Y are located on the first portion 110, and multiple third portions 130 arranged at intervals along the second direction Y are located on the side of the same second portion 120 away from the first portion 110.

[0038] In some embodiments, the first portion 110 may serve as the bottom of the substrate 100, and the subsequently formed gate structure may be located between the spacing of the plurality of third portions 130. Moreover, the first direction X may be the extension direction of the subsequently formed gate structure, and the second direction Y may be the extension direction of the subsequently formed bit line.

[0039] It should be noted that, Figure 2 The first portion 110, the second portion 120, and the third portion 130 of the substrate 100 are divided by dashed lines; furthermore... Figure 2 The illustration shows four second parts 120 spaced apart along the first direction X, and four third parts 130 spaced apart on each second part 120. In actual applications, there are no restrictions on the number of second parts 120 spaced apart along the first direction X, or the number of third parts 130 spaced apart on each second part 120.

[0040] S102: In conjunction with reference Figures 3 to 6At least a portion of the first portion 110 and a portion of the thickness of the second portion 120 are removed to expose the remaining area of ​​the second portion 120, and a groove 140 is formed between adjacent first dielectric layers 111. Alternatively, in conjunction with reference to... Figure 3 by Figures 7 to 9 At least a portion of the first portion 110 and a portion of the thickness of the second portion 220 are removed to expose the remaining area of ​​the second portion 220, and a groove 240 is formed between adjacent first dielectric layers 211. It is worth noting that in different embodiments, 120 and 220 both represent the second portion, 130 and 230 both represent the third portion, 111 and 211 both represent the first dielectric layer, and 140 and 240 both represent the groove.

[0041] It should be noted that the groove formed in step S102 includes at least the following two situations, therefore step S102 includes at least the following two embodiments:

[0042] In some embodiments, in conjunction with reference Figures 3 to 6 Step S102, which involves removing at least a portion of the first portion 110 and a portion of the thickness of the second portion 120, may include the following steps:

[0043] in, Figure 4 A top view schematic diagram of the first mask layer in a manufacturing method provided in an embodiment of this disclosure; Figure 5 A top view of the structure after a groove is formed in a manufacturing method provided in an embodiment of this disclosure; Figure 6 for Figure 5 The diagram shows a cross-sectional view of the structure along the second section direction BB1 and the third section direction CC1. It should be noted that subsequent descriptions will include one or both of these cross-sectional views, one along the second section direction BB1 and one along the third section direction CC1.

[0044] refer to Figure 4 A first mask layer 104 is formed, the first mask layer 104 having a first opening 114 extending along a first direction X, and a plurality of first openings 114 being arranged at intervals along a second direction Y. It should be noted that, to illustrate the first openings 114 in the first mask layer 104, Figure 4 The first mask layer 104 without the first opening 114 is filled with diagonal lines, and the approximate outline of each first opening 114 is drawn.

[0045] In some cases, in conjunction with references Figure 2 and Figure 4 The first opening 114 and the plurality of third portions 130 arranged along the first direction X each have a facing portion; in other words, the first opening 114 and the gate structure located between the third portions 130 ( Figure 2(Not shown in the diagram) Thus, a first opening 114 and a plurality of second portions 120 spaced apart along the first direction X each have a directly opposite portion. In practical applications, the first opening may also be directly opposite the interval between two adjacent third portions along the second direction. It should be noted that, in the above description, "directly opposite" or "directly aligned" refers to the fact that their orthographic projections on the reference plane formed by the first direction X and the second direction Y coincide or have a significant overlap. Furthermore, any subsequent mentions of "directly opposite" or "directly aligned" will not be further explained.

[0046] In some embodiments, in conjunction with reference Figure 2 and Figure 4 The first direction X and the second direction Y form a reference plane. The orthographic projection of the first opening 114 on the reference plane is the first projection. The orthographic projection of the interval between adjacent third portions 130 along the second direction Y on the reference plane is the second projection. The orthographic projection of the third portion 130 on the reference plane is the third projection.

[0047] In some cases, the first projection is located within the second projection, i.e., the first opening described above is directly opposite the interval between two adjacent third portions along the second direction. Thus, the orthographic projection of the subsequently formed bit line contact block on the reference plane is located between two orthographic projections of adjacent gate structures on the reference plane. In other cases, the first projection and the third projection at least partially overlap, i.e., one of the first openings 114 described above has a directly opposite portion to a plurality of second portions 120 spaced apart along the first direction X. Thus, the orthographic projection of the subsequently formed bit line contact block on the reference plane is located within the orthographic projection of the third portion 130 on the reference plane.

[0048] refer to Figures 3 to 6 Using the first mask layer 104 as a mask, the first portion 110 exposed by the first opening 114 and the second portion 120 of a certain thickness are etched to form a plurality of grooves 140 spaced apart along the first direction X and the second direction Y.

[0049] In some cases, the back side of the substrate 100 includes a first portion 110. In the step of etching the first portion 110 exposed by the first opening 114 and the second portion 120 of a certain thickness using the first mask layer 104 as a mask, the etching process is performed on the first portion 110 and the second portion 120 starting from the back side of the substrate 100.

[0050] It is worth noting that in the step of etching the substrate 100 using the first mask layer 104 as a mask, reference is made to... Figure 6 The cross-sectional structure diagram along the third section direction CC1 shows that not the entire first part 110 of the surface is etched, but rather the first opening 114 (see reference). Figure 4The first portion 110 exposed is etched, in other words, the etched first portion 110 and the first opening 114 are directly opposite each other. Thus, the first portion 110 exposed by any of the first openings 114 can be etched to finally expose a plurality of second portions 120 spaced apart along the first direction X.

[0051] Understandably, this is in conjunction with references. Figure 2 and Figure 4 The first opening 114 not only has a portion directly opposite to each of the plurality of second portions 120 arranged at intervals along the first direction X, but also has a portion directly opposite to each of the plurality of first dielectric layers 111 arranged at intervals along the first direction X. Based on this, due to the difference in material between the substrate 100 and the first dielectric layers 111, in the step of etching the substrate 100 using the first mask layer 104 as a mask, the first portion 110 exposed by the first opening 114 is etched, while the first dielectric layers 111 exposed by the first opening 114 are hardly etched, thus forming a... Figure 5 and Figure 6 The plurality of grooves 140 shown. Thus, a second portion 120 has a plurality of grooves 140.

[0052] The groove 140 has two opposite sidewalls along the first direction X formed by a first dielectric layer 111, and the groove 140 has two opposite sidewalls along the second direction Y formed by the remaining first portion 110.

[0053] In other embodiments, in conjunction with reference to Figure 3 , Figures 7 to 9 Step S102, which involves removing at least a portion of the first portion 110 and a portion of the thickness of the second portion 220, may include the following steps:

[0054] refer to Figure 7 Remove the first part of the entire surface (see reference) Figure 2 This exposes the second portion 220. Thus, each of the second portions 220 is exposed along the third direction Z away from the third portion 230.

[0055] Reference Figures 7 to 9 The second portion 220, with a portion of its thickness removed, is then removed to form a groove 240 extending along the second direction Y, with the groove 240 corresponding one-to-one with the second portion 220. Thus, a groove 240 exposes the entire surface of the second portion 220 along the third direction Z away from the third portion 230.

[0056] It should be noted that, Figure 9 for Figure 8 The diagram shows a cross-sectional structure along the second section direction BB1 and the third section direction CC1. Furthermore... Figure 9 The groove 240 is indicated by a dashed box in the middle right figure.

[0057] S103: The second portion 120 exposed in the groove 140 is metallized to form a bit line 102 extending along the second direction Y.

[0058] It should be noted that step S103 in the two embodiments above is similar, and the following... Figure 6 The groove 140 shown is an example to illustrate step S103 in detail.

[0059] In some embodiments, metallizing the exposed second portion 120 of the groove 140 includes the following steps: referring to reference Figure 6 and Figure 10 A metal layer 132 is formed on the surface of the groove 140 and the exposed surface of the first dielectric layer 111, providing metallic elements for the subsequent formation of bit lines. In some embodiments, the material of the metal layer 132 may include at least one of cobalt, nickel, molybdenum, titanium, tungsten, tantalum, or platinum.

[0060] Reference Figure 10 and Figure 11 Annealing is performed to convert at least a portion of the thickness of the second portion 120 into a metal semiconductor compound 122 and to convert the second portion 120 into a bit line 102; after forming the bit line 102, the remaining metal layer 132 is removed.

[0061] In some embodiments, during the annealing process, the metal layer 132 reacts with the second portion 120, and a portion of the second portion 120 is transformed into a metal semiconductor compound 122. This results in the final bit line 102 containing the metal semiconductor compound 122. In other embodiments, the entire thickness of the second portion can be transformed into a metal semiconductor compound, in which case the bit line is composed of the metal semiconductor compound.

[0062] It is understood that the metal semiconductor compound 122 has a relatively low resistivity compared to the unmetallized semiconductor material. Therefore, the resistivity of the bit line 102 is lower than that of the second part 120, which helps to reduce the resistance of the bit line 102 and the contact resistance between the bit line 102 and the third part 130, thereby further improving the electrical performance of the semiconductor structure.

[0063] In some embodiments, taking silicon as an example of a semiconductor element, the metal semiconductor compound 122 includes at least one of cobalt silicide, nickel silicide, molybdenum silicide, titanium silicide, tungsten silicide, tantalum silicide, or platinum silicide.

[0064] It should be noted that the reference Figure 11After the second portion 120 of the groove 140 is metallized to form a bit line 102 extending along the second direction Y, the groove 140 will be further deepened in the third direction Z due to the process of removing the remaining metal layer 132. The third direction Z is the direction from the third portion 130 to the first portion 110.

[0065] In one example, the first direction X, the second direction Y, and the third direction Z intersect each other.

[0066] S104: At least one bit line contact block 112 is formed in at least a portion of the groove 140, and a bit line 102 is in contact with at least one bit line contact block 112.

[0067] It should be noted that, since the groove formed in step S102 includes at least two scenarios, the bit line contact block 112 formed based on the groove formed in step S102, i.e., step S104 includes at least the following two embodiments:

[0068] In some embodiments, to form Figure 6 or Figure 11 Based on the groove 140 shown, step S104: forming at least one bit line contact block 112 in at least a portion of the groove 140 may include the following steps:

[0069] Reference Figures 11 to 13 This forms a second dielectric layer 121 that fills the groove 140. Figure 13 for Figure 12 The diagram shows a cross-sectional view of the structure along the second section direction BB1.

[0070] In some embodiments, the step of forming the second dielectric layer 121 may include: forming an initial second dielectric layer (not shown) that fills the surface of the groove 140 and the surface of the first dielectric layer 111, and performing a chemical mechanical planarization process on the initial second dielectric layer until the surface of the first dielectric layer 111 is exposed away from the third portion 130.

[0071] It should be noted that in some cases, during the aforementioned step of removing the remaining metal layer 132, the remaining metal layer is also removed. Figure 6 The remaining first portion 110 shown is therefore no longer present in the steps of forming the initial second dielectric layer and performing chemical mechanical planarization on the initial second dielectric layer; in other cases, it is not removed in the aforementioned steps. Figure 6The remaining first portion 110 shown, therefore, in the step of forming the initial second dielectric layer, the initial second dielectric layer may also be located on at least a portion of the surface of the remaining first portion 110. In the step of performing a chemical mechanical planarization process on the initial second dielectric layer, both the remaining first portion 110 and the initial second dielectric layer protruding from the surface of the first dielectric layer 111 away from the third portion 130 are removed.

[0072] Thus, for reference Figure 12 The second dielectric layer 121 and the groove 140 (reference) are finally formed. Figure 11 One-to-one correspondence.

[0073] Reference Figure 12 and Figure 14 The second dielectric layer 121 in part of the groove 140 is removed and bit line contact block 112 is formed.

[0074] Understandably, in practical applications, the number of bit line contact blocks 112 that need to be designed on the same bit line 102 can be selected according to requirements. Based on the number of bit line contact blocks 112 that need to be designed, the same number of second dielectric layers 121 corresponding to the bit line 102 are removed, and the bit line contact blocks 112 are formed in the groove 140 formed after removing the second dielectric layers 121. The correspondence between the bit line 102 and the bit line contact blocks 112 will be explained in detail later.

[0075] It should be noted that the step of removing part of the second dielectric layer 121 in the groove 140 requires the use of a mask layer with openings. To form the bit line contact block 112, selective removal is necessary. Figure 12 The second dielectric layer 121 in the structure shown can be adjusted according to the actual situation, so that the opening in the mask layer only exposes the second dielectric layer 121 that needs to be removed. Due to the differences in the materials of the second dielectric layer 121, the bit line 102, and the first dielectric layer 111, in the step of removing the second dielectric layer 121 in part of the groove 140, even if the alignment accuracy between the opening in the mask layer and the second dielectric layer 121 that needs to be removed is not high, the removal process will only remove the second dielectric layer 121 exposed by the opening in the mask layer. Based on this, the bit line contact block 112 will only be formed in the groove formed after the removal of the second dielectric layer 121, thereby realizing the self-aligned formation process of the bit line contact block 112. This is beneficial to improving the alignment accuracy between the bit line contact block 112 and the bit line 102, and effectively avoiding the situation where the same bit line contact block 112 is in contact with two adjacent bit lines 102, causing the two adjacent bit lines 102 to short-circuit.

[0076] Furthermore, combining the steps of metallizing a portion of the substrate 100 to form the bit line 102 with the step of forming the bit line contact block 112 simplifies the process steps for forming the bit line 102 and the bit line contact block 112. Moreover, it allows for a second dielectric layer 121 between the different recesses 140 corresponding to adjacent bit lines 102. This improves the conductivity of the finally formed bit line 102 while enabling self-alignment between the bit line contact block 112 and the bit line 102, thereby improving the alignment accuracy between the bit line contact block 112 and the bit line 102.

[0077] It should be noted that the low alignment accuracy between the opening in the mask layer and the second dielectric layer 121 to be removed includes the following situations: In some cases, the opening in the mask layer exposes a portion of the second dielectric layer 121 while also exposing the adjacent first dielectric layer 111 or bit line 102; in other cases, the opening in the mask layer simultaneously exposes portions of two adjacent second dielectric layers 121. It is understandable that due to the differences in materials between the second dielectric layer 121, the bit line 102, and the first dielectric layer 11, the process for removing the second dielectric layer 121 will only have a higher etching rate on the second dielectric layer 121.

[0078] In other embodiments, to form Figure 9 Based on the groove 240 shown, step S104: forming at least one bit line contact block 212 in at least a portion of the groove 240 may include the following steps:

[0079] It should be noted that the reference Figure 9 and Figure 15 The step of forming bit line 202 in step S103 is similar to the step of forming bit line 102 in the previous embodiment, and will not be described in detail here.

[0080] refer to Figure 15 This forms a second dielectric layer 221 that fills the groove 240. The second dielectric layer 221 corresponds one-to-one with the bit line 202, meaning that the second dielectric layer 221 is also a long strip structure extending along the second direction Y.

[0081] In some embodiments, the step of forming the second dielectric layer 221 may include: forming an initial second dielectric layer (not shown in the figure) that fills the surface of the groove 240 and the surface of the first dielectric layer 211, and performing a chemical mechanical planarization process on the initial second dielectric layer until the surface of the first dielectric layer 211 away from the third portion 230 is exposed. It should be noted that in the aforementioned step S102, in conjunction with reference to... Figure 2 and Figure 9 Since the first part has been completely removed, it is not necessary to remove the first part in the step of forming the second dielectric layer 221.

[0082] It should be noted that, Figure 7 , Figure 9 and Figure 15 The first sub-part 250, the second sub-part 260 and the third sub-part 270 shown in the figure are the same as those in the previous embodiments, and will not be described again here.

[0083] Reference Figure 15 and Figure 16 The second dielectric layer 221 is patterned to expose a portion of the groove 240, and the bit line 202 is exposed in a portion of the groove 240. It can be understood that only a portion of the groove 240 is exposed, that is, only a portion of the second dielectric layer 221 is etched.

[0084] Reference Figure 16 and Figure 17 Bit line contact block 212 is formed in a portion of the groove 240.

[0085] It should be noted that a mask layer with openings is required in the step of patterning the second dielectric layer 221. To form the bit line contact block 212, selective removal is necessary. Figure 15 In the structure shown, a portion of the second dielectric layer 221 can be exposed. Therefore, the position of the opening in the mask layer can be adjusted according to the actual situation, so that the opening only exposes a portion of the second dielectric layer 221 that needs to be removed. Due to the differences in materials between the second dielectric layer 221, the bit line 202, and the first dielectric layer 211, even if the alignment accuracy between the opening in the mask layer and the portion of the second dielectric layer 221 to be removed is not high during the patterning process of the second dielectric layer 221, the removal process will only remove the second dielectric layer 221 exposed by the opening in the mask layer. Based on this, the bit line contact block 212 will only be formed in the groove formed after removing a portion of the second dielectric layer 221, thereby achieving a self-aligned forming process for the bit line contact block 212. This helps improve the alignment accuracy between the bit line contact block 212 and the bit line 202, and effectively avoids the situation where the same bit line contact block 212 is in contact with two adjacent bit lines 202, causing short circuits between the two adjacent bit lines 202.

[0086] Furthermore, combining the steps of metallizing a portion of the substrate to form the bit line 202 with the step of forming the bit line contact block 212 simplifies the process steps for forming the bit line 202 and the bit line contact block 212. Moreover, it ensures that a second dielectric layer 221 is present between the different recesses 240 corresponding to adjacent bit lines 202. This improves the conductivity of the finally formed bit line 202 while enabling self-alignment between the bit line contact block 212 and the bit line 202, thereby improving the alignment accuracy between them.

[0087] It should be noted that the low alignment accuracy between the opening in the mask layer and the portion of the second dielectric layer 221 to be removed includes the following situations: In some cases, the opening in the mask layer exposes a portion of one second dielectric layer 221 while also exposing the adjacent first dielectric layer 211 or bit line 202; in other cases, the opening in the mask layer simultaneously exposes portions of two adjacent second dielectric layers 221. It is understandable that due to the differences in materials between the second dielectric layer 221, the bit line 202, and the first dielectric layer 211, the process for removing the second dielectric layer 221 will only have a higher etching rate on the second dielectric layer 221.

[0088] It is worth noting that, Figure 14 The diagram illustrates the correspondence between bit line contact block 112 and bit line 102, and... Figure 17 The correspondence between bit line contact blocks 212 and bit lines 202 shown in the diagram is a specific example. In practical applications, there is no limit to the number of bit line contact blocks 112 that are connected to the same bit line 102, nor is there a limit to the spacing between adjacent bit line contact blocks 112 connected to the same bit line 102 in the second direction Y, nor is there a limit to the number of bit lines 102 included in the semiconductor structure. Therefore, the correspondence between bit line contact blocks 112 and bit lines 102 can be designed in various ways according to actual conditions, and it is impossible to list them all here. Therefore, the correspondence between bit line contact blocks 112 and bit lines 102 is summarized to a certain extent below. It is worth noting that in different embodiments, 112 and 212 both represent bit line contact blocks, 102 and 202 both represent bit lines, and 121 and 221 both represent the second dielectric layer.

[0089] In some embodiments, with Figure 17 The semiconductor structure shown is an example. The bit line contact blocks 212 that are in contact with adjacent bit lines 202 can be staggered along the first direction X. In other words, the different bit line contact blocks 212 that are in contact with adjacent bit lines 202 are not directly opposite each other along the first direction X, that is, the orthographic projections of the different bit line contact blocks 212 that are in contact with adjacent bit lines 202 do not coincide on the projection plane formed by the first direction X and the third direction Z; or, the different bit line contact blocks 212 that are in contact with adjacent bit lines 202 are only partially opposite each other along the first direction X, that is, the orthographic projections of the different bit line contact blocks 212 that are in contact with adjacent bit lines 202 only partially overlap on the projection plane formed by the first direction X and the third direction Z. In this way, it is beneficial to increase the spacing between the different bit line contact blocks 212 located on adjacent bit lines 202, reduce the electrical interference between the different bit line contact blocks 212, and thus improve the electrical performance of the semiconductor structure.

[0090] Still with Figure 17 The semiconductor structure shown is an example, and the bit line contact blocks 212 connected to adjacent bit lines 202 can be staggered along the second direction Y. It is worth noting that... Figure 17 In the example shown, each bit line 202 has at least one bit line contact block 212 connected to it. The bit line contact blocks 212 connected to adjacent bit lines 202 are not only staggered along the first direction X, but also staggered along the second direction Y. This facilitates increasing the spacing between any two adjacent bit line contact blocks 212, further reducing electrical interference between different bit line contact blocks 212, thereby further improving the electrical performance of the semiconductor structure.

[0091] It should be noted that, Figure 14 The portion of the bit line contact block 112 shown that is connected to the adjacent bit line 102 is, for example, located in Figure 14 The four bit line contact blocks 112 at the top, which are respectively connected to the four bit lines 102, are also arranged in a staggered manner along the first direction X; moreover, Figure 14 The portion of the bit line contact block 112 shown that is connected to the adjacent bit line 102 is, for example, located in Figure 14 The four bit line contact blocks 112 on the left, which are connected to the two bit lines 102 respectively, are also arranged in a staggered manner along the second direction Y.

[0092] In other embodiments, reference is made to... Figure 18 In section 18a, two adjacent bit lines 102 are considered as a pair of bit lines. For a pair of bit lines, the different bit line contact blocks 112 that are in contact with them can be staggered along the second direction Y. From the layout of the entire bit line 102 and bit line contact blocks 112, although not all different parts of the bit line contact blocks 112 located on any adjacent bit line 102 are staggered along the first direction X, the different bit line contact blocks 112 that are in contact with a pair of bit lines are staggered along the first direction X.

[0093] In some other embodiments, reference is made to Figure 18 In section 18b, when a bit line contact block 112 is connected to a part of the bit line 102, the bit line contact block 112 connected to the adjacent bit line 102 can be staggered only along the first direction X.

[0094] It should be noted that in practical applications, the arrangement of different bit line contact blocks on adjacent bit lines can be adjusted according to actual needs. For example, different bit line contact blocks on adjacent bit lines can be directly opposite each other along the first direction; or, some of the different bit line contact blocks on adjacent bit lines can be directly opposite each other along the first direction, while other parts of the different bit line contact blocks on adjacent bit lines can be staggered along the first direction.

[0095] in, Figure 18 This is a schematic top view of two embodiments of the bit line, gate structure, and bit line contact block according to this disclosure. It should be noted that, to clearly illustrate the positional relationship between the bit line, gate structure, and bit line contact block, Figure 18 The center alignment line 102 is drawn using a perspective drawing method.

[0096] In the various embodiments described above, with Figures 13 to 14 The example shown is for reference only, along section 110 (reference). Figure 2 In the direction pointing to the second part 120, the third part 130 includes a first sub-part 150, a second sub-part 160 and a third sub-part 170 arranged in sequence, and the first direction X and the second direction Y constitute a reference plane.

[0097] refer to Figure 19 and Figure 20 The substrate 100 may further include a gate structure 105 and a third dielectric layer 131, wherein the gate structure 105 surrounds the sidewalls of a plurality of second sub-parts 160 arranged along a first direction X, and the third dielectric layer 131 is located at least between adjacent gate structures 105.

[0098] It is understood that the gate structure 105 as a whole can be regarded as a signal line extending along the first direction X, which surrounds the sidewalls of a plurality of second sub-sections 160 arranged along the first direction X. In other words, a second sub-section 160 and a portion of the gate structure 105 surrounding its sidewalls together constitute a vertical transistor. The second sub-section 160 can serve as the channel region in the vertical transistor, and a gate structure 105 can control the on or off state of the plurality of second sub-sections 160 arranged along the first direction X.

[0099] In some embodiments, the gate structure 105 may include: a gate dielectric layer (not shown) covering the sidewall surface of the second sub-part 160; and a gate conductive layer (not shown) covering the sidewall surface of the gate dielectric layer away from the second sub-part 160, with a gap between adjacent gate conductive layers. Based on this, the third dielectric layer 131 at least fills the gap between adjacent gate conductive layers.

[0100] In some embodiments, reference Figure 19 and Figure 20 The substrate 100 may further include a fourth dielectric layer 141, which fills the gap between the third portion 130, the gate structure 105, and the third dielectric layer 131. It should be noted that the fourth dielectric layer 141 may be a multi-layer structure.

[0101] It should be noted that, Figures 1 to 15 The diagram showing the cross-sectional structure does not depict the gate structure, the third dielectric layer, or the fourth dielectric layer.

[0102] The manufacturing method provided in one embodiment of this disclosure may further include the following steps:

[0103] Remove the first part 110 (reference) Figure 2 It should be noted that in the foregoing embodiments, the remaining first part 110 can be removed in step S103 or step S104. In practical applications, if the remaining first part 110 is not removed in step S103 or step S104, it can be removed in this step.

[0104] refer to Figures 21 to 23 A second mask layer 106 is formed on the side of the first dielectric layer 111 away from the gate structure 105. The second mask layer 106 has a plurality of second openings 116, and the orthographic projection of one second opening 116 onto the reference plane at least overlaps with the orthographic projection of one gate structure 105 onto the reference plane. It should be noted that, to illustrate the second openings 116 in the second mask layer 106, Figure 21 Only for those layers that do not have a second opening 116, the second mask layer 106 is filled with diagonal lines, and the approximate outline of each second opening 116 is drawn.

[0105] in, Figure 22 for Figure 21 A schematic diagram of a cross-sectional structure along the second section direction BB1 shown; Figure 22 for Figure 21 The diagram shows a cross-sectional view of the structure along the fourth section direction DD1.

[0106] In some embodiments, the manufacturing method further includes: forming a spin-coated dielectric layer between the second mask layer 106 and the first dielectric layer 111 to alleviate the contact stress between the second mask layer 106 and the first dielectric layer 111, and to improve the accuracy of pattern transfer from the second opening 116 in the second mask layer 106 to the first dielectric layer 111 and other dielectric layers opposite it.

[0107] It is worth noting that in the second mask layer 106, the orthographic projection of any second opening 116 on the reference plane not only overlaps with the orthographic projection of a gate structure 105 on the reference plane, but also the orthographic projection of any second opening 116 on the reference plane is located in the orthographic projection of the first dielectric layer 111 on the reference plane. In other words, the orthographic projection of any second opening 116 on the reference plane is located in the orthographic projection of the interval between two adjacent bit lines 102 on the reference plane.

[0108] Reference Figure 22 and Figure 24 ,as well as Figure 23 as well as Figure 25Using the third dielectric layer 131 as an etching barrier layer and the second mask layer 106 as a mask, the first dielectric layer 111 exposed by the second opening 116 is etched until the gate structure 105 is exposed and a via 107 is formed.

[0109] It should be noted that, in conjunction with references Figure 22 and Figure 23 A fourth dielectric layer 141 is provided between adjacent first sub-parts 150; in other words, the fourth dielectric layer 141 surrounds the sidewall of each first sub-part 150. Based on this, during the etching of the first dielectric layer 111 exposed by the second opening 116 using the second mask layer 106 as a mask, the fourth dielectric layer 141, which is directly opposite the second opening 116 along the third direction Z, will also be exposed. The fourth dielectric layer 141 will be patterned based on the second opening 116 to form a via 107 that exposes the gate structure 105.

[0110] It is worth noting that the materials of the first dielectric layer 111 and the fourth dielectric layer 141 can be the same, and the materials of the first dielectric layer 111 and the third dielectric layer 131 can be significantly different; or, although the materials of the first dielectric layer 111 and the fourth dielectric layer 141 are different, both of their materials are significantly different from the material of the third dielectric layer 131. In this way, the etching process in the step of forming the via 107 will only have a high etching rate on the first dielectric layer 111 and the fourth dielectric layer 141, and will hardly etch the third dielectric layer 131, thus allowing the third dielectric layer 131 to act as an etching barrier layer.

[0111] In one example, the materials of the first dielectric layer 111 and the fourth dielectric layer 141 can both be silicon oxide, and the material of the third dielectric layer 131 can be silicon nitride.

[0112] Reference Figure 24 and Figure 26 or refer to Figure 25 and Figure 27 A word line contact block 115 is formed in the through hole 107, and a gate structure 105 is in contact with at least one word line contact block 115.

[0113] In some embodiments, the orthographic projection of a second opening 116 on the reference plane overlaps only with the orthographic projection of a gate structure 105 on the reference plane, and the second opening 116 is only used to form a word line contact block 115.

[0114] It is worth noting that, Figures 21 to 23 The correspondence between the second opening 116 and the gate structure 105 shown in the diagram is only an example. Since one second opening 116 corresponds to one word line contact block 115, Figures 21 to 23 The text line contact block 115 is also implicitly shown in the diagram (reference). Figure 26The correspondence between word line contact blocks 115 and gate structure 105 is explained below. In practical applications, there is no limit to the number of word line contact blocks 115 that are connected to the same gate structure 105, nor is there a limit to the spacing between adjacent word line contact blocks 115 connected to the same gate structure 105 in the first direction X, nor is there a limit to the number of gate structures 105 included in the semiconductor structure. Therefore, the correspondence between word line contact blocks 115 and gate structure 105 can be designed in various ways according to actual conditions, and it is impossible to list them all here. Therefore, the correspondence between word line contact blocks 115 and gate structure 105 is summarized to a certain extent below.

[0115] In some embodiments, reference Figure 28 In section 28a, word line contact blocks 115 connected to adjacent gate structures 105 are staggered along the first direction X. In other words, different word line contact blocks 115 connected to adjacent gate structures 105 are not directly opposite each other along the first direction X, that is, the orthographic projections of different word line contact blocks 115 connected to adjacent gate structures 105 on the projection plane formed by the first direction X and the third direction Z do not coincide; or, different word line contact blocks 115 connected to adjacent gate structures 105 are only partially directly opposite each other along the first direction X, that is, the orthographic projections of different word line contact blocks 115 connected to adjacent gate structures 105 on the projection plane formed by the first direction X and the third direction Z only partially overlap. This is beneficial for increasing the spacing between different word line contact blocks 115 located on adjacent gate structures 105, reducing electrical interference between these different word line contact blocks 115, and thus improving the electrical performance of the semiconductor structure.

[0116] In other embodiments, reference continues. Figure 28 In section 28a, word line contact blocks 115, which are connected to adjacent gate structures 105, are arranged in a staggered manner along the second direction Y. It is worth noting that... Figure 28 In the example shown in Figure 28a, a portion of the gate structure 105 has at least one word line contact block 115 connected to it. The word line contact blocks 115 connected to adjacent gate structures 105 are not only staggered along the first direction X, but also staggered along the second direction Y. This facilitates increasing the spacing between any two adjacent word line contact blocks 115, further reducing electrical interference between these different word line contact blocks 115, thereby further improving the electrical performance of the semiconductor structure.

[0117] In other embodiments, reference is made to... Figure 28 In section 28b, when a word line contact block 115 is connected to multiple adjacent gate structures 105, the word line contact block 115 connected to the adjacent gate structure 105 can be staggered only along the second direction Y.

[0118] In other embodiments, word line contact blocks that are connected to adjacent gate structures may be staggered only along a first direction.

[0119] It should be noted that in practical applications, the arrangement of different word line contact blocks on adjacent gate structures can be adjusted according to actual needs. For example, different word line contact blocks on adjacent gate structures can be directly opposite each other along the first direction; or, some of the different word line contact blocks on adjacent gate structures can be directly opposite each other along the first direction, while other parts of the different word line contact blocks on adjacent gate structures can be staggered along the first direction.

[0120] in, Figure 28 This is a schematic top view of two embodiments of the bit line, gate structure, bit line contact block, and word line contact block according to this disclosure. It should be noted that, to clearly illustrate the positional relationship between the bit line, gate structure, bit line contact block, and word line contact block, Figure 28 The center alignment line 102 is drawn using a perspective method. In addition, different shapes are used to represent the bit line contact block 112 and the word line contact block 115.

[0121] In some embodiments, reference Figure 23 Along the second direction Y, the length L1 of the second opening 116 is greater than the spacing L2 between two adjacent third dielectric layers 131; in conjunction with reference Figure 23 and Figure 25 In the step of forming the through-hole 107, the third dielectric layer 131 is also exposed away from the second portion 120 (see reference). Figure 2 At least a portion of the top surface of the gate structure 105, and, along the second direction Y, the orthographic projection of only one of the adjacent gate structures 105 on the reference plane overlaps with the orthographic projection of the second opening 116 on the reference plane.

[0122] It should be noted that the second mask layer 106 has a plurality of second openings 116, and the lengths of the plurality of second openings 116 in the second direction Y may be different. It is possible that the length L1 of some of the second openings 116 is greater than the spacing L2 between two adjacent third dielectric layers 131.

[0123] Therefore, even if the alignment accuracy between the second opening 116 in the second mask layer 106 and the gate structure 105 to be exposed is not high, in other words, such as Figure 23As shown, the second opening 116 is also directly opposite a portion of the third dielectric layer 131. However, the etching process will only remove the first dielectric layer 111 exposed by the second opening 116 and the fourth dielectric layer 141 directly opposite the second opening 116. The third dielectric layer 131 located between adjacent gate structures 105 will block the progress of the etching process, so that only one gate structure 105 is exposed on the bottom surface of a via 107. This enables the self-alignment formation process of the word line contact block 115, which is beneficial to improve the alignment accuracy between the word line contact block 115 and the gate structure 105, and effectively avoids the situation where the same word line contact block 115 is in contact with two adjacent gate structures 105, causing the two adjacent gate structures 105 to short-circuit, thereby improving the electrical performance of the semiconductor structure.

[0124] In addition, refer to Figure 23 When the length L1 of the second opening 116 along the second direction Y is greater than the spacing L2 between two adjacent third dielectric layers 131, the reference... Figure 25 Along the second direction Y, the length of the portion of the through hole 107 that is directly opposite the first dielectric layer 111 is greater than the length of the portion of the through hole 107 that is directly opposite the third dielectric layer 131. This results in the word line contact block 115 formed based on the through hole 107 having a double damask structure, i.e., the word line contact block 115 is wider at the top and narrower at the bottom. This is beneficial to ensure that a word line contact block 115 will only contact and connect with one gate structure 105, while increasing the size of the word line contact block 115 to improve its own conductivity.

[0125] Moreover, along the second direction Y, reference Figure 21 and Figure 23 Only one of the adjacent gate structures 105 has its orthographic projection on the reference plane overlapping with the orthographic projection of the second opening 116 on the reference plane. In other words, among the plurality of gate structures 105 spaced apart along the second direction Y, there is a complete gate structure 105 between two adjacent second openings 116 along the fourth cross-sectional direction DD1, and this gate structure 105 is separated by a via 107 (reference). Figure 25 The exposed area will not be located in the fourth section direction DD1, for example, Figure 21 The second opening 116 corresponding to the gate structure 105 is located in the central region. This ensures that the second openings 116 corresponding to two adjacent gate structures 105 are not adjacent along the second direction Y, preventing communication with the vias 107 corresponding to the two adjacent gate structures 105 during the subsequent step of forming vias 107 based on the second openings 116. This further helps to prevent contact and connection between the word line contact blocks 115 corresponding to the two adjacent gate structures 105 in the second direction Y, thereby further preventing short circuits between adjacent gate structures 105 via the word line contact blocks 115.

[0126] In practical applications, the third dielectric layer can also be located on an adjacent bit line, with the aid of a reference. Figure 23 The third dielectric layer can be embedded within the first dielectric layer, and the top surface of the third dielectric layer is flush with the top surface of the first dielectric layer; that is, the third dielectric layer is also located in the interval between adjacent bit lines. It can be understood that, along the second direction Y, the first dielectric layer located between any two bit lines is also divided into two parts by the third dielectric layer.

[0127] Based on this, the orthographic projection of a second opening on the reference plane can overlap with the orthographic projections of at least two adjacent gate structures on the reference plane. That is, a second opening can simultaneously expose a first dielectric layer divided into two parts by a third dielectric layer, allowing the second opening to be used to form at least two word line contacts. It is understood that, since a second opening can simultaneously expose a first dielectric layer divided into two parts by a third dielectric layer, in the step of etching the first dielectric layer exposed by the second opening using the third dielectric layer as an etch stop layer and the second mask layer as a mask, each of the two parts of the first dielectric layer divided by the third dielectric layer forms a via, so that at least two vias spaced apart by the third dielectric layer can be formed along the second direction.

[0128] In some embodiments, in conjunction with reference Figure 22 and Figure 24 The formed through-hole 107 exposes at least one sidewall of the first sub-part 150. It should be noted that the dimensions of the plurality of second openings 116 in the second mask layer 106 may differ in both the first direction X and the second direction Y. In practical applications, the dimensions of the plurality of second openings 116 in the second mask layer 106 can be approximately similar to the dimensions of one of the various second openings 116 mentioned in the above embodiments. Figures 21 to 23 The purpose of illustrating the different dimensions of the multiple second openings 116 is to provide corresponding illustrations for various sizes of the second openings 116 so that they can be explained in detail.

[0129] refer to Figure 22 Since the size of a portion of the second opening 116 in the first direction X is equal to the spacing of adjacent bit lines 102 in the first direction X, in practical applications, the size of a portion of the second opening in the first direction may be slightly larger than the spacing of adjacent bit lines in the first direction. (Reference) Figure 24 Based on this type of second opening 116, the through hole 107 formed exposes at least one sidewall of the first sub-part 150.

[0130] It should be noted that, Figure 24Taking a through hole 107 that exposes the sidewalls of two first sub-parts 150 as an example, in actual use, due to the alignment deviation between the second opening and the first dielectric layer, for example, the second opening exposes a part of the first dielectric layer 111 and a small part of the second dielectric layer, the through hole formed based on the second opening will only expose the sidewall of one first sub-part 150.

[0131] Provided that at least one sidewall of the first sub-part 150 is exposed in the through hole 107 formed based on the second opening 116, the manufacturing method may further include, after forming the through hole 107 and before forming the word line contact block 115, referring to... Figure 24 and Figure 26 A protective layer 108 is formed on the sidewall of the via 107, and the protective layer 108 and the bottom surface of the via 107 together form a sub-via. A word line contact block 115 is formed in the via 107, including forming a word line contact block 115 that fills the sub-via. In this way, when the alignment deviation between the second opening 116 and the first dielectric layer 111 causes at least one sidewall of the first sub-part 150 to be exposed in the formed via 107, the protective layer 108 is formed on the sidewall of the via 107 to avoid contact connection between the formed word line contact block 115 and the bit line 102 and the third part 130, thereby effectively avoiding the problem of short circuit between the bit line 102 and the gate structure 105 through the word line contact block 115, so as to improve the electrical performance of the semiconductor structure.

[0132] It should be noted that the formation of a protective layer 108 on the sidewall of the through hole 107 includes the following two scenarios: In some cases, refer to Figure 26 A protective layer 108 is formed on all sidewalls of the through hole 107 extending along the third direction Z. The sub-through hole is formed by the protective layer 108 and the bottom surface of the through hole 107. Thus, the protective layer 108 is formed on the sidewalls of the through hole 107, whether along the first direction X or the second direction Y.

[0133] In other cases, refer to Figure 27 The protective layer 108 is formed only on the two opposite sidewalls of the through hole 107 along the first direction X, and not on the two opposite sidewalls of the through hole 107 along the second direction Y. In this way, the protective layer 108 can be formed between the bit line 102, the first sub-part 150 and the word line contact block 115, and the size of the word line contact block 115 in the second direction Y can be increased to ensure that the word line contact block 115 has good conductivity.

[0134] In other embodiments, reference continues. Figure 22 The size of the second opening 116 in the first direction X can also be smaller than the spacing between adjacent bit lines 102 in the first direction X, see reference. Figure 24The through-hole 107 formed by the second opening 116 of this type will not expose the sidewall of the first sub-part 150, and the sidewall of the through-hole 107 is jointly surrounded by the remaining first dielectric layer 111 and the remaining fourth dielectric layer 11. It is understood that in this case, there is no need to form a protective layer.

[0135] It should be noted that the above method for forming word line contact blocks is applicable to the above two methods for forming bit lines.

[0136] In summary, on the one hand, combining the steps of metallizing a portion of the substrate 100 to form the bit line 102 and forming the bit line contact block 112 simplifies the process steps for forming the bit line 102 and the bit line contact block 112. On the other hand, removing a portion of the substrate 100 to expose the remaining area of ​​the second portion 120 in the substrate 100, and forming a groove 140 between adjacent first dielectric layers 111, it can be understood that the remaining area of ​​the second portion 120 constitutes the bottom surface of the groove 140, and at least a portion of the side surface of the groove 140 is formed by the second dielectric layer 121. In other words, the second dielectric layer 121 is present between different grooves 140 corresponding to two adjacent bit lines 12. Therefore, when at least one bit line contact block 112 is formed in at least a portion of the groove 140, since the bit line contact block 112 is located in the groove 140, a second dielectric layer 121 is also present between different bit line contact blocks 112 corresponding to two adjacent bit lines 102, effectively preventing two adjacent bit lines 102 from being short-circuited through the same bit line contact block 112. This is beneficial for improving the conductivity of the finally formed bit line 102 while enabling self-alignment between the bit line contact block 112 and the bit line 102, thereby improving the alignment accuracy between the bit line contact block 112 and the bit line 102.

[0137] Another embodiment of this disclosure provides a semiconductor structure formed by the manufacturing method provided in the foregoing embodiments. The semiconductor structure provided in another embodiment of this disclosure will be described in detail below with reference to the accompanying drawings. It should be noted that parts that are the same as or corresponding to those in the foregoing embodiments will not be repeated here.

[0138] refer to Figure 26 and Figure 27The semiconductor structure includes: a substrate 100, in which a vertical transistor is present, the vertical transistor including a semiconductor pillar extending along a third direction Z, the semiconductor pillar having a first surface and a second surface opposite to each other in the third direction Z, the first surface being the back surface of the substrate 100; a plurality of bit lines 102 spaced apart along a first direction X, each bit line 102 contacting a plurality of first surfaces spaced apart along a second direction Y, the bit lines 102 having a metal semiconductor compound 122, the first direction X, the second direction Y and the third direction intersecting each other; a plurality of bit line contact blocks 112, one side of a bit line 102 away from the semiconductor pillar being in contact with at least one bit line contact block 112, and the sidewalls of the bit line contact blocks 112 extending along the third direction being surrounded by a dielectric layer.

[0139] Understandably, the bit line contact block 112 extends from the back side of the substrate 100 into the substrate to make contact with the bit line 102. Specifically, the side of a bit line 102 away from the semiconductor pillar is in contact with at least one bit line contact block 112, that is, the bit line contact block 112 is formed in the semiconductor structure based on the back side of the substrate 100.

[0140] It should be noted that the vertical transistor includes a semiconductor pillar extending Z-direction, which is... Figure 26 and Figure 27 The third part 130 shown. Figure 26 and Figure 27 The substrate 100 shown is the substrate 100 after the bit line contact block 112 is formed.

[0141] Furthermore, the sidewalls of the bit line contact block 112 extending in the third direction Z are all surrounded by a dielectric layer, referring to the reference... Figure 19 and Figure 20 The sidewalls of the bit line contact block 112 extending in the third direction Z are either covered by the first dielectric layer 111 or by the second dielectric layer 121.

[0142] In some embodiments, continue to refer to Figure 26 and Figure 27 Along the third direction Z, the semiconductor pillar includes a third sub-section 170, a first sub-section 150 and a second sub-section 160 arranged in sequence, the first sub-section 150 being contacted and connected to the bit line 102; the vertical transistor also includes a gate structure 105, the gate structure 105 surrounding the sidewalls of the plurality of second sub-sections 160 arranged along the first direction X; the semiconductor structure may also include: a plurality of word line contact blocks 115, one side of the gate structure 105 away from the second surface being contacted and connected to at least one word line contact block 115.

[0143] In some embodiments, continue to refer to Figure 26 and Figure 27The semiconductor structure may further include: a protective layer 108 located on two opposite sidewalls of the word line contact block 115 along the first direction X, and / or located on two opposite sidewalls of the word line contact block 115 along the second direction Y.

[0144] In some embodiments, reference Figure 28 Word line contact blocks 115 that are in contact with adjacent gate structures 105 are arranged in a staggered manner along the first direction X, and / or word line contact blocks 115 that are in contact with adjacent gate structures 105 are arranged in a staggered manner along the second direction Y.

[0145] In some embodiments, reference Figure 14 , Figure 17 and Figure 18 The bit line contact blocks 112 that are in contact with adjacent bit lines 102 are staggered along the first direction X, and / or the bit line contact blocks 112 that are in contact with adjacent bit lines 102 are staggered along the second direction Y.

[0146] Those skilled in the art will understand that the above embodiments are specific examples of implementing this disclosure, and in practical applications, various changes in form and detail may be made without departing from the spirit and scope of the embodiments of this disclosure. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the embodiments of this disclosure; therefore, the scope of protection of the embodiments of this disclosure should be determined by the scope defined in the claims.

Claims

1. A method for manufacturing a semiconductor structure, comprising: providing a substrate and a first dielectric layer, the substrate comprising a first portion, a plurality of second portions arranged along a first direction on the first portion, and a plurality of third portions arranged along a second direction on a side of the second portions away from the first portion, the first dielectric layer being at least between adjacent second portions, the second portions being configured to form bit lines, and the third portions being configured to form semiconductor pillars, the first direction and the second direction being intersected; removing at least part of the first portion and part of the thickness of the second portions to form recesses, the recesses exposing remaining regions of the second portions and being between adjacent first dielectric layers; and performing a metallization process on the second portions exposed by the recesses to form the bit lines extending along the second direction; and forming at least one bit line contact in at least part of the recesses, one of the bit lines being in contact with at least one of the bit line contacts. 2.The method of claim 1, wherein the step of removing at least part of the first portion and part of the thickness of the second portions comprises: forming a first mask layer having first openings extending along the first direction, the first openings being arranged along the second direction; etching the first portion and part of the thickness of the second portions exposed by the first openings using the first mask layer as a mask to form a plurality of the recesses arranged along the first direction and the second direction; and wherein the step of forming at least one bit line contact in at least part of the recesses comprises: forming a second dielectric layer filling the recesses; and removing part of the second dielectric layer in the recesses to form the bit line contact. 3.The method of claim 2, wherein the first direction and the second direction form a reference plane, a normal projection of the first openings on the reference plane is a first projection, a normal projection of intervals between adjacent third portions along the second direction on the reference plane is a second projection, and a normal projection of the third portions on the reference plane is a third projection; and wherein the first projection is located in the second projection, or the first projection at least partially overlaps the third projection. 4.The method of claim 1, wherein the step of removing at least part of the first portion and part of the thickness of the second portions comprises: removing the first portion to expose the second portions; and continuing to remove part of the thickness of the second portions to form the recesses extending along the second direction, the recesses and the second portions corresponding to each other; and wherein the step of forming at least one bit line contact in at least part of the recesses comprises: forming a second dielectric layer filling the recesses; performing a patterning process on the second dielectric layer to expose part of the recesses, the part of the recesses exposing the bit lines; and forming the bit line contact in the part of the recesses. ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ 5. The manufacturing method of any one of claims 1-4, wherein the bit line contact blocks connected to adjacent bit line contacts are staggered along the first direction, and / or the bit line contact blocks connected to adjacent bit line contacts are staggered along the second direction.

6. The manufacturing method of any one of claims 1-4, wherein the third portion comprises a first sub-portion, a second sub-portion, and a third sub-portion arranged in sequence along a direction from the first portion to the second portion, the first direction and the second direction constituting a reference plane; and the substrate further comprises gate structures surrounding sidewalls of the second sub-portions arranged along the first direction, and a third dielectric layer located at least between adjacent gate structures.

7. The manufacturing method of claim 6, wherein a second opening has a footprint on the reference plane that overlaps only a footprint of one gate structure on the reference plane, and the second opening is used to form only one word line contact block.

8. The manufacturing method of claim 7, wherein along the second direction, a length of the second opening is greater than a spacing between two adjacent third dielectric layers, and in the step of forming the via, at least a portion of a top surface of the third dielectric layer away from the second portion is exposed, and along the second direction, only one of the adjacent gate structures has a footprint on the reference plane that overlaps a footprint of the second opening on the reference plane.

9. The manufacturing method of claim 6, wherein the third dielectric layer is also located between adjacent bit lines, a second opening has a footprint on the reference plane that overlaps footprints of at least two adjacent gate structures on the reference plane, and the second opening is used to form at least two word line contact blocks; and in the step of etching the first dielectric layer exposed by the second opening using the third dielectric layer as an etching stop layer and the second mask layer as a mask, at least two vias are formed along the second direction and separated by the third dielectric layer.

10. The manufacturing method of claim 6, wherein ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ The formed via exposes at least a sidewall of one of the first subparts; after forming the via, before forming the word line contact block, further comprising: forming a protection layer on the sidewall of the via, the protection layer and a bottom surface of the via together enclose a sub-via; Forming the word line contact block in the via comprises: forming the word line contact block to fill the sub-via. 11.A semiconductor structure, comprising: a substrate having a vertical transistor therein, the vertical transistor comprising a semiconductor pillar extending along a third direction, the semiconductor pillar having a first face and a second face opposite in the third direction, the first face being a back face of the substrate; a plurality of bit lines spaced apart along a first direction, one of the bit lines having a metal semiconductor compound and being in contact with a plurality of first face contacts spaced apart along a second direction, the first direction, the second direction and the third direction being mutually perpendicular; a plurality of bit line contact blocks, one of the bit lines being in contact with at least one of the bit line contact blocks away from a side of the semiconductor pillar along the third direction, and a sidewall of each of the bit line contact blocks extending along the third direction being surrounded by a dielectric layer. 12.The semiconductor structure of claim 11, wherein in the third direction, the semiconductor pillar comprises a first subpart, a second subpart and a third subpart arranged in sequence, the first subpart being in contact with the bit line, and the vertical transistor further comprises a gate structure surrounding sidewalls of a plurality of the second subparts arranged along the first direction; and the semiconductor structure further comprises a plurality of word line contact blocks, one of the gate structures being in contact with at least one of the word line contact blocks away from a side of the second face along the third direction. 13.The semiconductor structure of claim 12, further comprising: a protection layer on two sidewalls of the word line contact block opposite in the first direction and / or on two sidewalls of the word line contact block opposite in the second direction. 14.The semiconductor structure of claim 12, wherein the word line contact blocks in contact with adjacent gate structures are misaligned along the first direction and / or the word line contact blocks in contact with adjacent gate structures are misaligned along the second direction. 15.The semiconductor structure of claim 11, wherein the bit line contact blocks in contact with adjacent bit lines are misaligned along the first direction and / or the bit line contact blocks in contact with adjacent bit lines are misaligned along the second direction. ​ ​

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