Method for manufacturing a semiconductor structure and semiconductor structure

Abstract

The embodiment of the present disclosure provides a semiconductor structure manufacturing method and a semiconductor structure. The semiconductor structure manufacturing method comprises the following steps: providing a substrate, wherein the substrate comprises first active structures, second active structures and isolation structures located between adjacent first active structures and second active structures; etching the substrate to form a plurality of spaced grooves, wherein the grooves expose the top surface of the second active structures; forming a first isolation layer, wherein the first isolation layer covers the surface of the grooves; forming a first semiconductor layer, wherein the first semiconductor layer covers the surface of the first isolation layer; etching the first semiconductor layer to expose the first isolation layer covering the top surface of the second active structures; etching the first isolation layer to expose the top surface of the second active structures; and forming a bit line contact structure, wherein the bit line contact structure is at least in contact with the top surface of the second active structures.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the field of semiconductor, and in particular, to a method for manufacturing a semiconductor structure and the semiconductor structure. BACKGROUND

[0002] Dynamic Random Access Memory (DRAM) is a kind of semiconductor memory which can write and read data at high speed and randomly, and is widely applied to data storage devices or apparatuses.

[0003] DRAM includes a plurality of memory cells, each of which usually includes a transistor and a capacitor. The gate of the transistor is electrically connected with a word line (WL), the source is electrically connected with a bit line (BL) through a bit line contact (BLC), and the drain is electrically connected with the capacitor through a storage node contact (SNC). The transistor can be controlled to be turned on or off by a voltage signal on the word line, and data information stored in the capacitor can be read through the bit line or written into the capacitor for storage.

[0004] With the rapid development of semiconductor manufacturing technology, semiconductor devices are developing towards higher component density and higher integration, and the semiconductor process node is continuously decreasing in accordance with the development trend of Moore's law. It is necessary to improve the reliability of the semiconductor structure. SUMMARY

[0005] The present disclosure provides a method for manufacturing a semiconductor structure and the semiconductor structure, which can at least improve the reliability of the formed semiconductor structure.

[0006] According to some embodiments of the present disclosure, the present disclosure provides a method for manufacturing a semiconductor structure, which includes: providing a substrate, the substrate including a first active structure, a second active structure, and an isolation structure located between adjacent first active structures and second active structures; etching the substrate to form a plurality of spaced grooves, the grooves exposing the top surface of the second active structure; forming a first isolation layer covering the surface of the grooves; forming a first semiconductor layer covering the surface of the first isolation layer; etching the first semiconductor layer to expose the first isolation layer covering the top surface of the second active structure; etching the first isolation layer to expose the top surface of the second active structure; and forming a bit line contact structure, the bit line contact structure being at least in contact with the top surface of the second active structure.

[0007] In some embodiments, the method of forming the bit line contact structure comprises: forming an initial bit line contact structure, the initial bit line contact structure filling the recess and covering the top surface of the substrate; etching the initial bit line contact structure to form the spaced bit line contact structures.

[0008] In some embodiments, the aspect ratio of the initial bit line contact structure formed corresponding to the portion of the recess is 2-3.

[0009] In some embodiments, the method of forming the initial bit line contact structure comprises: forming a first initial bit line contact structure, the first initial bit line contact structure filling the recess and covering the top surface of the substrate; removing part of the first initial bit line contact structure, leaving the first initial bit line contact structure flush with the top surface of the recess; forming a second initial bit line contact structure on the top surface of the initial bit line contact structure, the first initial bit line contact structure and the second initial bit line contact structure constituting the initial bit line contact structure.

[0010] In some embodiments, before etching the substrate, the method further comprises: forming a second isolation layer, the second isolation layer covering the top surface of the substrate, the first isolation layer formed also covering the surface of the second isolation layer, and in the process of etching the first semiconductor layer and the first isolation layer, the first semiconductor layer and the first isolation layer on the top surface of the second isolation layer are also etched.

[0011] In some embodiments, the method of etching the first semiconductor layer comprises: etching the first semiconductor layer by dry etching, the dry etching being a gas containing halogen elements.

[0012] In some embodiments, in the process of etching the first isolation layer, the method further comprises: etching the isolation structure to expose part of the sidewall of the second active structure.

[0013] In some embodiments, the method of etching the first isolation layer and the isolation structure comprises: using wet etching.

[0014] According to some embodiments of the present disclosure, another aspect of the present disclosure further provides a semiconductor structure, comprising: a substrate, the substrate comprising first active structures, second active structures and isolation structures located between adjacent first active structures and second active structures, the substrate being provided with a plurality of spaced recesses, the recesses exposing the top surface of the second active structures; a first isolation layer, the first isolation layer covering the sidewall of the recess; and a bit line contact structure, the bit line contact structure being in contact with at least the top surface of the second active structure, the bit line contact structure located in the recess being spaced apart from the first isolation layer.

[0015] In some embodiments, the bit line contact structure further covers the sidewall of the second active structure.

[0016] The technical solution provided by the embodiments of this disclosure has at least the following advantages: During the formation of the groove, since the etching process cannot be precisely controlled, the surface of the first active structure may be exposed during the formation of the groove. As a result, the first active structure and the second active structure may be electrically connected during the subsequent formation of the bit line contact structure, and the first active structure may also be damaged during the formation of the bit line contact structure. Therefore, a first isolation layer and a first semiconductor layer are formed before forming the bit line contact structure, thereby forming an isolation on the sidewall of the groove using the first isolation layer and the first semiconductor layer, and using the first isolation layer and the first semiconductor layer as the second isolation layer of the first active structure. This avoids damage to the first active structure during the formation of the bit line contact structure, and also prevents the bit line contact structure from electrically connecting adjacent first and second active structures, thereby improving the reliability of the semiconductor structure. Attached Figure Description

[0017] One or more embodiments are illustrated by way of example with corresponding pictures in the accompanying drawings. These illustrations do not constitute a limitation on the embodiments. Unless otherwise stated, the pictures in the accompanying drawings do not constitute a limitation on scale. In order to more clearly illustrate the technical solutions in the embodiments of this disclosure or the conventional technology, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0018] Figure 1 A flowchart illustrating a method for fabricating a semiconductor structure according to an embodiment of this disclosure;

[0019] Figure 2 A three-dimensional structural diagram of a semiconductor structure provided in an embodiment of this disclosure;

[0020] Figure 3 Provided for an embodiment of this disclosure Figure 2 A cross-sectional view of the semiconductor structure along the M-M1 direction;

[0021] Figure 4 Provided for an embodiment of this disclosure Figure 3 A schematic diagram of the structure forming the groove based on the above;

[0022] Figure 5 Provided for an embodiment of this disclosure Figure 4 A schematic diagram of the structure in which the first isolation layer and the first semiconductor layer are formed based on the above.

[0023] Figure 6 Provided for an embodiment of this disclosure Figure 5 A schematic diagram of the structure on which the first semiconductor layer and the first isolation layer are etched;

[0024] Figure 7 Provided for an embodiment of this disclosure Figure 6 A schematic diagram of the structure forming the first initial bit line contact structure based on the above;

[0025] Figure 8 Provided for an embodiment of this disclosure Figure 7 A structural diagram showing the removal of part of the first initial bit line contact structure based on the above.

[0026] Figure 9 Provided for an embodiment of this disclosure Figure 8 A schematic diagram of the second initial bit line contact structure formed on the basis of this;

[0027] Figure 10 Provided for an embodiment of this disclosure Figure 9 Based on this, a bit line contact structure is formed. Detailed Implementation

[0028] Currently, during the process of forming the groove, the etching process cannot be precisely controlled. Therefore, the surface of the first active structure may be exposed during the formation of the groove. This may lead to electrical connection between the first and second active structures during the subsequent formation of the bit line contact structure, and may also cause damage to the first active structure during the formation of the bit line contact structure. Therefore, it is necessary to provide a method for fabricating a semiconductor structure to improve the reliability of the formed semiconductor structure.

[0029] This embodiment of the present disclosure forms a first isolation layer and a first semiconductor layer before forming the bit line contact structure, thereby utilizing the first isolation layer and the first semiconductor layer to form isolation on the sidewall of the groove, and using the first isolation layer and the first semiconductor layer as the second isolation layer of the first active structure. This avoids damage to the first active structure during the formation of the bit line contact structure, and also prevents the bit line contact structure from electrically connecting adjacent first and second active structures, thereby improving the reliability of the semiconductor structure.

[0030] The embodiments of this disclosure will now be described in detail with reference to the accompanying drawings. However, those skilled in the art will understand that many technical details have been provided in the embodiments of this disclosure to facilitate a better understanding of the disclosure. However, the technical solutions claimed in this disclosure can be implemented even without these technical details and various variations and modifications based on the following embodiments.

[0031] refer to Figure 1and Figures 2 to 10 , Figure 1 A flow chart of a method for manufacturing a semiconductor structure according to an embodiment of the present disclosure is provided. Figures 2 to 10 A structure diagram corresponding to each step of a method for manufacturing a semiconductor structure according to an embodiment of the present disclosure is provided, Figures 3 to 10 A structure diagram corresponding to each step of a method for manufacturing a semiconductor structure according to an embodiment of the present disclosure is provided in Figure 2 A cross-sectional view in the MM1 direction.

[0032] Referring to Figures 1 to 3 , a substrate is provided, wherein, Figure 1 A flow chart of a method for manufacturing a semiconductor structure according to an embodiment of the present disclosure is provided, Figure 2 A three-dimensional structure diagram of a semiconductor structure according to an embodiment of the present disclosure is provided, Figure 3 A cross-sectional view in the MM1 direction. Figure 2

[0033] S100: A substrate 100 is provided, which includes first active structures 101, second active structures 102, and isolation structures 103 arranged at intervals.

[0034] In some embodiments, the substrate 100 can include a base 110, first active structures 101, second active structures 102, and isolation structures 103 on the surface of the base 110, wherein the base 110 and the first active structures 101 and the second active structures 102 can be an integrated structure, and the isolation structures 103 can be STI (Shallow Trench Isolation). The material of the base 110 can be monocrystalline silicon (Si), monocrystalline germanium (Ge), or silicon-germanium (GeSi), silicon carbide (SiC); it can also be silicon-on-insulator (SOI), germanium-on-insulator (GOI); or it can also be other materials, such as gallium arsenide and other Group III-V compounds.

[0035] The first active structures 101 and the second active structures 102 can be active pillars formed on the base 110, and the material of the first active structures 101 and the material of the second active structures 102 can be the same as the material of the base, such as monocrystalline silicon, monocrystalline germanium, or germanium-silicon, etc.

[0036] The material of the isolation structures 103 can be silicon oxide, silicon nitride, or silicon oxynitride, etc.

[0037] Referring to Figure 1 , Figure 2 and Figure 4 , Figure 4 A groove is formed on the basis of Figure 3 .​

[0038] S200: etching the substrate 100 to form a plurality of spaced grooves 130, the grooves 130 exposing the top surface of the second active structure 102.

[0039] In some embodiments, the method of forming the grooves 130 can include forming by mask etching, that is, first forming a mask layer (not shown) on the top surface of the substrate 100, then etching the substrate 100 with the mask layer as a mask to form the grooves 130, and then removing the mask layer after forming the grooves 130.

[0040] Before forming the mask layer, a second isolation layer 120 is also formed on the surface of the substrate 100, and the mask layer can be formed on the surface of the second isolation layer 120. During etching, part of the second isolation layer 120 is also etched, and during removal of the mask layer, the second isolation layer 120 can also act as an etching stop layer to protect the substrate 100.

[0041] It can be understood that during mask etching, as etching proceeds, the width of the part of the groove 130 extending towards the base 110 will become smaller, and due to lateral etching during etching, the groove 130 can also expose part of the sidewall of the first active structure 101.

[0042] In some embodiments, part of the second active structure 102 is also etched during the formation of the grooves 130, so that the top surface of the first active structure 101 is higher than the top surface of the second active structure 102.

[0043] In some embodiments, before forming the grooves 130, a word line structure 140 can also be formed in the substrate 100, which can include a word line conductive layer 141, a word line isolation structure 142 on the top surface of the word line conductive layer 141, and a word line dielectric layer 143 wrapping the surfaces of the word line conductive layer 141 and the word line isolation structure 142. The word line dielectric layer 143 is used to isolate the first active structure 101 or the second active structure 102 from the word line conductive layer 141, so as to avoid direct contact between the first active structure 101 or the second active structure 102 and the word line conductive layer 141, and to avoid the flow of carriers in the first active structure 101 or the second active structure 102 directly to the word line conductive layer 141.

[0044] In some embodiments, the word line conductive layer 141 can include a first conductive sub-layer 144 and a second conductive sub-layer 145, wherein the second conductive sub-layer 145 covers the top surface of the first conductive sub-layer 144. The material of the first conductive sub-layer 144 can be a metal material, such as tungsten, and the material of the second conductive sub-layer 145 can be a semiconductor material, such as polysilicon. The second conductive sub-layer 145 can be made of a low work function material to reduce the difference in material between the second conductive sub-layer 145 and the first active structure 101 or the second active structure 102, thereby reducing the leakage of the word line conductive layer 141. The first conductive sub-layer 144 can be made of a metal material to reduce the resistance and increase the signal transmission rate of the first conductive sub-layer 144.

[0045] It should be noted that the low work function material herein refers to a material with a lower work function than silicon.

[0046] In some embodiments, before etching the substrate 100, a second isolation layer 120 is formed to cover the top surface of the substrate 100, and the first isolation layer 104 is formed to cover the surface of the second isolation layer 120. The second isolation layer 120 can protect the part that does not need to be etched, and can be used as an etching stop layer for etching the first semiconductor layer 105 and the first isolation layer 104.

[0047] In some embodiments, the material of the second isolation layer 120 can include silicon nitride, silicon oxide, silicon oxynitride, or the like.

[0048] Reference Figure 5 , Figure 5 to form the first isolation layer and the first semiconductor layer based on the substrate. Figure 4

[0049] S300: Form a first isolation layer 104 covering the surface of the recess 130.

[0050] In some embodiments, the material of the first isolation layer 104 can be the same as that of the isolation structure 103, such as silicon oxide, silicon nitride, silicon oxynitride, or the like. It can be understood that part of the isolation structure 103 can be etched during the formation of the recess 130, but part of the isolation structure 103 will still remain. Therefore, using the same material as the isolation structure 103 during the formation of the first isolation layer 104 can facilitate the growth of the first isolation layer 104.

[0051] S400: Form a first semiconductor layer 105 covering the surface of the first isolation layer 104.

[0052] ​The first isolation layer 104 covers the surface of the groove 130, and the first isolation layer 104 can also cover the surface of the second isolation layer 120; the first semiconductor layer 105 covers the surface of the first isolation layer 104.

[0053] The material of the first semiconductor layer 105 can be the same as the material of the bit line contact structure, for example, a semiconductor material such as silicon, germanium, or germanium silicon, and similarly, the material of the first semiconductor layer 105 is the same as the material of the bit line contact structure, which can facilitate the subsequent formation of the bit line contact structure.

[0054] Reference Figure 6 , Figure 6 is etched on the basis of Figure 5 The first semiconductor layer and the first isolation layer are etched.

[0055] S500: Etching the first semiconductor layer 105 to expose the first isolation layer 104 covering the top surface of the second active structure 102.

[0056] In some embodiments, the method of etching the first semiconductor layer 105 includes using dry etching to etch the first semiconductor layer 105, and the dry etching is a gas containing halogen elements. In the process of etching the first semiconductor layer 105, it is necessary to avoid etching the first isolation layer 104 as much as possible, so it is necessary to select an etching mode with a large etching selectivity between the first semiconductor layer 105 and the first isolation layer 104 to etch the first semiconductor layer 105. Using dry etching and the dry etching being a gas containing halogen elements can avoid affecting the first isolation layer 104 as much as possible in the process of etching the first semiconductor layer 105, thereby improving the reliability of the entire semiconductor structure manufacturing method.

[0057] For the first semiconductor layer 105, the same material as the bit line contact structure 106 is usually selected, so that the formation of the first semiconductor layer 105 will not affect the bit line contact structure 106, and for the bit line contact structure 106, in order to improve the contact performance with the second active structure 102, a semiconductor material such as polysilicon is usually selected. Based on this, the first semiconductor layer 105 also selects polysilicon material, and the first isolation layer 104 usually selects the same material as the isolation structure 103, for example, silicon dioxide. In the process of dry etching using a gas containing halogen elements, the ratio range of the etching selectivity between polysilicon and silicon dioxide can be 100-500, that is, dry etching is easier to etch polysilicon, so that excessive damage to the first isolation layer 104 can be avoided in the process of etching the first semiconductor layer 105.

[0058] S600: Etching the first isolation layer 104 to expose the top surface of the second active structure 102.

[0059] In some embodiments, the method of etching the first isolation layer 104 can include wet etching. In order to avoid damaging the second active structure 102 as much as possible during the etching of the first isolation layer 104, a wet etching method is used to etch the first isolation layer 104, so as to avoid damaging the second active structure 102 during the etching of the first isolation layer 104.

[0060] For the first isolation layer 104, the first isolation layer 104 is usually made of the same material as the isolation structure 103, such as silicon dioxide, and the material of the second active structure 102 is usually silicon. In the wet etching process, the ratio of the etching selectivity of silicon dioxide to the etching selectivity of silicon is 50-500, that is, the wet etching is easier to etch silicon dioxide, so as to avoid damaging the second active structure 102 during the etching of the first isolation layer 104.

[0061] The reagent used in the wet etching can include hydrofluoric acid or nitric acid, etc.

[0062] In some embodiments, the method of etching the first isolation layer 104 further includes etching the isolation structure 103 to expose part of the sidewall of the second active structure 102. By etching part of the isolation structure 103 during the etching of the first isolation layer 104, the sidewall of the second active structure 102 is exposed, and in the subsequent process of forming the bit line contact structure 106, the bit line contact structure 106 can be controlled to contact the sidewall of the second active structure 102, so as to improve the contact reliability between the bit line contact structure 106 and the second active structure 102 and reduce the contact resistance between the bit line contact structure 106 and the second active structure 102.

[0063] In some embodiments, the method of etching the first semiconductor layer 105 and the first isolation layer 104 also etches the first semiconductor layer 105 and the first isolation layer 104 on the top surface of the second isolation layer 120.

[0064] Reference Figures 7 to 10 , forming a bit line contact structure.

[0065] S700: forming a bit line contact structure 106, the bit line contact structure 106 at least contacts and connects with the top surface of the second active structure 102.

[0066] In some embodiments, the method of forming the bit line contact structure 106 includes: forming an initial bit line contact structure 116, the initial bit line contact structure 116 filling the recess 130 and covering the top surface of the substrate 100; etching the initial bit line contact structure 116 to form the spaced bit line contact structures 106. By forming the initial bit line contact structure 116 first and then etching, the profile of the formed bit line contact structure 106 can be improved, and the reliability of the formed bit line contact structure 106 can be improved.

[0067] In some embodiments, the aspect ratio of the portion of the initial bit line contact structure 116 corresponding to the recess 130 can range from 2 to 3. The portion of the initial bit line contact structure 116 corresponding to the recess 130 actually refers to the portion of the initial bit line contact structure 116 whose orthogonal projection on the surface of the substrate 100 is located in the recess 130. By controlling the aspect ratio of the portion of the initial bit line contact structure 116 corresponding to the recess 130 to range from 2 to 3, the formation of holes in the initial bit line contact structure 116 due to an excessively high aspect ratio of the initial bit line contact structure 116 can be avoided, and the reliability of the formed bit line contact structure 106 can be improved.

[0068] It can be understood that if the aspect ratio of the portion of the initial bit line contact structure 116 corresponding to the recess 130 is too large, for example, greater than 3, it is easy to form a hole in the initial bit line contact structure 116 during the formation of the initial bit line contact structure 116, which can result in the presence of a hole in the subsequently formed bit line contact structure 106, thereby reducing the reliability of the bit line contact structure 106 and degrading the electrical signal transmission performance of the bit line contact structure 106.

[0069] The material of the initial bit line contact structure 116 can be silicon, germanium, or germanium-silicon, etc.

[0070] Reference Figures 7 to 9 , forming an initial bit line contact structure.

[0071] In some embodiments, the method of forming the initial bit line contact structure 116 can further include: forming a first initial bit line contact structure 126, the first initial bit line contact structure 126 filling the recess 130 and covering the top surface of the substrate 100; removing part of the first initial bit line contact structure 126, and the remaining first initial bit line contact structure 126 being flush with the top surface of the recess 130; forming a second initial bit line contact structure 136, the second initial bit line contact structure 136 being located on the top surface of the initial bit line contact structure 116, and the first initial bit line contact structure 126 and the second initial bit line contact structure 136 constituting the initial bit line contact structure 116.

[0072] The first initial bit line contact structure 126 is used to fill the recess 130, and then part of the first initial bit line contact structure 126 is removed, so that the recess can be exposed when part of the first initial bit line contact structure 126 is removed, and then the recess is filled by the second initial bit line contact structure 136, so as to further improve the reliability of the bit line contact structure 106 formed subsequently.

[0073] In some embodiments, the thickness of the first initial bit line contact structure 126 is greater than the thickness of the initial bit line contact structure 116 formed, in other words, the thickness of the first initial bit line contact structure 126 is greater than the sum of the thickness of the initial bit line contact structure 116 and the thickness of the second initial bit line contact structure 136. For the first initial bit line contact structure 126, the first initial bit line contact structure 126 is formed first to fill the recess 130, so as to facilitate the subsequent patterning of the bit line contact structure 106, and therefore the first initial bit line contact structure 126 formed is thicker. For the second initial bit line contact structure 136, it needs to fill the recess that may exist, and form a bit line contact structure 106 with a suitable thickness, and therefore the second initial bit line contact structure 136 formed is thinner.

[0074] In some embodiments, the material of the first initial bit line contact structure 126 can be the same as the material of the second initial bit line contact structure 136, such as silicon, germanium or germanium silicon, etc. The material of the first initial bit line contact structure 126 can be the same as the material of the second initial bit line contact structure 136, which can facilitate the growth of the second initial bit line contact structure 136, thereby improving the reliability of the initial bit line contact structure 116 formed.

[0075] Reference Figure 10 The bit line contact structure is formed.

[0076] The initial bit line contact structure 116 can be etched by a mask etching method to form the bit line contact structure 106.

[0077] It can be understood that, if the first isolation layer 104 and the first semiconductor layer 105 are not formed in advance in the process of forming the initial bit line contact structure 116, the first active structure 101 will inevitably be damaged when the initial bit line contact structure 116 is etched, resulting in a decrease in the reliability of the semiconductor structure formed.

[0078] If only the first isolation layer 104 is formed without forming the first semiconductor layer 105, the entire first isolation layer 104 can be etched in the process of etching the first isolation layer 104, and the isolation structure 103 can be etched too much. Therefore, the first semiconductor layer 105 can be used as a mask layer in the process of etching the first isolation layer 104, which can avoid the first isolation layer 104 from being etched too much and can also avoid the isolation structure 103 from being affected too much.

[0079] If only the first semiconductor layer 105 is formed without forming the first isolation layer 104, the first active structure 101 can be exposed in the previous etching process. Therefore, part of the first active structure 101 can be etched in the process of etching the bit line contact structure 106. Therefore, the first isolation layer 104 can be used as a protective layer in the process of etching the bit line contact structure 106, which can avoid the first active structure 101 from being etched, and the first isolation layer 104 can further improve the insulation of the film layer formed on the first active structure 101 and the second active structure 102, thereby improving the reliability of the semiconductor structure.

[0080] In the process of etching the bit line contact structure 106, the first semiconductor layer 105 is also etched and removed. Similarly, the first isolation layer 104 can be used as a protective layer in the process of etching the bit line contact structure 106, which can avoid damaging the first active structure 101 in the process of forming the bit line contact structure 106, thereby improving the reliability of the semiconductor structure.

[0081] In some embodiments, the bit line structure 107 can be formed after the bit line contact structure 106 is formed. The bit line structure 107 can include a bit line conductive layer 117 and a bit line cover layer 127. The bit line conductive layer 117 is located on the top surface of the bit line contact structure 106. The bit line cover layer 127 is located on the top surface of the bit line conductive layer 117. The bit line cover layer 127 can cover the top surface of the bit line conductive layer 117, which can avoid affecting the bit line conductive layer 117 in the subsequent process, thereby improving the reliability of the semiconductor structure.

[0082] The bit line conductive layer 117 can include a bit line metal semiconductor layer 137 and a bit line metal layer 147. The bit line metal semiconductor layer 137 covers the top surface of the bit line contact structure 106, and the bit line metal layer 147 covers the top surface of the bit line metal semiconductor layer 137. The bit line metal semiconductor layer 137 can reduce the difference in material between the bit line metal layer 147 and the bit line contact structure 106, thereby improving the stability of the carrier transmission between the bit line structure 107 and the bit line contact structure 106.

[0083] The first isolation layer 104 and the first semiconductor layer 105 are formed before the bit line contact structure 106 is formed, so that the first isolation layer 104 and the first semiconductor layer 105 are used to form isolation on the sidewall of the groove 130, and the first isolation layer 104 and the first semiconductor layer 105 are used as the second isolation layer 120 of the first active structure 101, so that the first active structure 101 is not damaged in the process of forming the bit line contact structure 106, and the bit line contact structure 106 can avoid electrically connecting the adjacent first active structure 101 and the second active structure 102, and the reliability of the semiconductor structure can be improved.

[0084] Another embodiment of the present disclosure also provides a semiconductor structure, which can be formed by the method for manufacturing the semiconductor structure in some or all of the above embodiments. The semiconductor structure provided by another embodiment of the present disclosure will be described below with reference to the accompanying drawings. It should be noted that the same or corresponding parts of the above embodiments can refer to the corresponding description of the above embodiments, which will not be described here.

[0085] Reference Figure 10 , Figure 10 A cross-sectional view of a semiconductor structure provided by an embodiment of the present disclosure.

[0086] In some embodiments, the semiconductor structure can include a substrate 100 including first active structures 101, second active structures 102, and isolation structures 103 arranged at intervals, and a plurality of grooves 130 arranged at intervals in the substrate 100, the grooves 130 exposing the top surface of the second active structure 102.

[0087] The semiconductor structure can include a first isolation layer 104 covering the sidewall of the groove 130.

[0088] The semiconductor structure can include a bit line contact structure 106 at least in contact with the top surface of the second active structure 102, and the bit line contact structure 106 in the groove 130 is spaced apart from the first isolation layer 104.

[0089] By forming the first isolation layer 104 on the sidewall of the groove 130, the bit line contact structure 106 can be prevented from contacting the first active structure 101, thereby improving the reliability of the semiconductor structure.

[0090] In some embodiments, the bit line contact structure 106 also covers the sidewall of the second active structure 102. Covering the sidewall of the second active structure 102 by the bit line contact structure 106 can increase the contact area between the bit line contact structure 106 and the second active structure 102, thereby reducing the contact resistance of the second active structure 102 and the bit line contact structure 106, and can improve the reliability of the semiconductor structure.

[0091] Those skilled in the art can understand that the above-mentioned embodiments are specific embodiments for implementing the present disclosure, and in actual application, various changes can be made in form and details without departing from the spirit and scope of the embodiments of the present disclosure. Any person skilled in the art can make various modifications and modifications without departing from the spirit and scope of the embodiments of the present disclosure, and therefore the protection scope of the embodiments of the present disclosure should be subject to the scope defined by the claims.

Claims

1. A method of fabricating a semiconductor structure, the method comprising: The method comprises: providing a substrate, the substrate comprising a first active structure, a second active structure and an isolation structure located between the first active structure and the second active structure; etching the substrate to form a plurality of spaced recesses, the recesses exposing a top surface of the second active structure; forming a first isolation layer, the first isolation layer covering a surface of the recesses; forming a first semiconductor layer, the first semiconductor layer covering a surface of the first isolation layer; etching the first semiconductor layer to expose the first isolation layer covering the top surface of the second active structure; etching the first isolation layer to expose the top surface of the second active structure; forming a bit line contact structure, the bit line contact structure being in contact with at least the top surface of the second active structure; The method of etching the first semiconductor layer comprises: etching the first semiconductor layer by dry etching, the dry etching being a gas containing halogen elements.

2. The method of fabricating a semiconductor structure of claim 1, wherein, The method of etching the first isolation layer further comprises: etching the isolation structure to expose a part of the sidewall of the second active structure. The method of etching the first isolation layer and the isolation structure comprises: wet etching. The method comprises:

3. The method of fabricating a semiconductor structure of claim 2, wherein, providing a substrate, the substrate comprising a first active structure, a second active structure and an isolation structure located between the first active structure and the second active structure, the substrate being provided with a plurality of spaced recesses, the recesses exposing a top surface of the second active structure; 4. The method of fabricating a semiconductor structure of claim 2, wherein, a first isolation layer, the first isolation layer covering a sidewall of the recesses; a bit line contact structure, the bit line contact structure being in contact with at least the top surface of the second active structure, the bit line contact structure located in the recesses being spaced apart from the first isolation layer. The bit line contact structure further covers a sidewall of the second active structure. ​ 5. The method of fabricating a semiconductor structure of claim 1, wherein, ​ 6. The method of fabricating a semiconductor structure of claim 1, wherein, ​ 7. The method of fabricating a semiconductor structure of claim 6, wherein, ​ 8. A semiconductor structure formed using the method of any one of claims 1 to 7. ​ ​ ​ ​ 9. The semiconductor structure of claim 8, wherein, ​

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