Sidewall forming method of SONOS memory

Abstract

The invention provides a method for forming a side wall of an SONOS (Silicon Oxide Nitride Oxide Semiconductor) memory, which comprises the following steps of: providing a substrate, forming a first oxide layer on the logic region of the substrate, forming an ONO layer on the storage region, depositing a polycrystalline silicon layer, and forming a second oxide layer, a nitride layer and a third oxide layer which are sequentially stacked from bottom to top on the first oxide layer, the nitride layer and the third oxide layer, patterning the polycrystalline silicon layer by utilizing a photoetching and etching method to form a gate polycrystalline silicon layer on the logic region and the storage region; removing the exposed third oxide layer to expose the nitride layer below the third oxide layer; oxidizing the exposed nitride layer and the surface of the grid polycrystalline silicon layer to form a fourth oxide layer, wherein the fourth oxide layer is used as a first side wall material layer; and forming a subsequent side wall structure by using a deposition and back etching method. On the basis that the substrate is not damaged, the ONO layer of the SONOS region and the first oxide layer of the logic region are completely etched, and an effective protection side wall is formed.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and particularly to a method for forming sidewalls of a SONOS memory. Background Art

[0002] In the process development of embedded SONOS memories, the formation of sidewalls needs to take into account both MOS transistors in the logic region and SONOS transistors in the memory region, which poses some challenges. After gate etching and before sidewall formation, the remaining dielectric layer of the SONOS transistor is the ONO layer, while the remaining dielectric of the MOS transistor is SiO2. The sidewall process of the prior art is difficult to balance the SONOS transistor region and the MOS transistor region during etching:

[0003] 1. If over-etching in the logic region is ensured, SIN residue in the ONO layer will occur in the SONOS region, preventing the formation of metal silicide in the source / drain region, which will further lead to poor contact and inability to etch through the contact holes.

[0004] 2. If the ONO layer in the SONOS region is etched cleanly, excessive loss of the silicon substrate will occur in the logic region, resulting in poor source / drain junctions and poor leakage in logic devices.

[0005] To solve the above problems, a new method for forming sidewalls of a SONOS memory needs to be proposed. Summary of the Invention

[0006] In view of the above-mentioned disadvantages of the prior art, the purpose of the present invention is to provide a method for forming sidewalls of a SONOS memory, which is used to solve the problem that it is difficult to balance the SONOS transistor region and the MOS transistor region during etching in the prior art.

[0007] To achieve the above object and other related objects, the present invention provides a method for forming sidewalls of a SONOS memory, including:

[0008] Step 1: Provide a substrate, on which a logic region and a memory region are provided. A first oxide layer is formed in the logic region on the substrate, and an ONO layer is formed on the memory region. The ONO layer is composed of a second oxide layer, a nitride layer, and a third oxide layer stacked from bottom to top. Deposit a polysilicon layer, and then pattern the polysilicon layer by photolithography and etching to form gate polysilicon layers on the logic region and the memory region;

[0009] Step 2: Remove the exposed third oxide layer to expose the nitride layer below it;

[0010] Step 3: Oxidize the exposed nitride layer and the surface of the gate polysilicon layer to form a fourth oxide layer, and the fourth oxide layer serves as a first sidewall material layer;

[0011] Step 4: Use deposition and etch-back methods to form the subsequent sidewall structure.

[0012] Preferably, the method of patterning the polysilicon layer in Step 1 includes: forming a photoresist layer on the polysilicon layer; lithographically opening the photoresist layer to define the formation position of the gate polysilicon layer; using etching to pattern the polysilicon layer to form the gate polysilicon layer; and removing the remaining photoresist layer.

[0013] Preferably, the etching method in Step 1 is dry etching.

[0014] Preferably, in Step 2, the exposed third oxide layer is removed using wet etching.

[0015] Preferably, in Step 3, the exposed nitride layer and the surface of the gate polysilicon layer are oxidized to form the fourth oxide layer using in-situ steam oxidation.

[0016] Preferably, the method of forming the subsequent sidewall structure in Step 4 includes: sequentially depositing the second and third sidewall material layers, where the second sidewall material layer is a nitride and the third sidewall material layer is an oxide layer; etching the second and third sidewall material layers, and the etching stops on the fourth oxide layer, leaving it on the sidewalls of the gate polysilicon layer to form a sidewall structure; and continuing to etch to remove the exposed fourth oxide layer and the first and second oxide layers.

[0017] Preferably, in Step 4, the second and third sidewall material layers are etched using dry etching.

[0018] Preferably, in Step 4, the exposed fourth oxide layer and the first and second oxide layers are etched away using wet etching.

[0019] Preferably, the thickness of the second sidewall material layer in Step 4 is 150 to 300 angstroms.

[0020] Preferably, the thickness of the third sidewall material layer in Step 4 is 200 to 700 angstroms.

[0021] As described above, the sidewall formation method of the SONOS memory of the present invention has the following beneficial effects:

[0022] The present invention can, without damaging the substrate, simultaneously etch the ONO layer in the SONOS region and the first oxide layer in the logic region completely, forming effective protective sidewalls for the SONOS and MOS transistors. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 Schematic diagram of depositing the ONO sidewall shown as the prior art;

[0024] Figure 2 Schematic diagram of the structure after etching the ONO sidewall shown as the prior art;

[0025] Figure 3 Schematic diagram of the process flow of the present invention;

[0026] Figure 4 Schematic diagram of forming the gate polysilicon layer of the present invention;

[0027] Figure 5 Schematic diagram of removing the exposed third oxide layer of the present invention;

[0028] Figure 6 Schematic diagram of oxidizing the exposed nitride layer and the surface of the gate polysilicon layer to form the fourth oxide layer of the present invention;

[0029] Figure 7 Schematic diagram of depositing the second and third sidewall material layers of the present invention;

[0030] Figure 8 Schematic diagram of the sidewall structure of the present invention. Detailed implementation manners

[0031] The following uses specific specific examples to illustrate the implementation manners of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific implementation manners, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0032] Please refer to Figure 3 , the present invention provides a method for forming a sidewall of a SONOS memory, including:

[0033] Step 1: Provide a substrate 1, on which there are a logic region and a storage region. A first oxide layer 2 is formed in the logic region on the substrate 1, and an ONO layer 3 is formed on the storage region. The ONO layer 3 is composed of a second oxide layer, a nitride layer, and a third oxide layer stacked in sequence from bottom to top. Deposit a polysilicon layer, and then use photolithography and etching methods to pattern the polysilicon layer to form a gate polysilicon layer 4 on the logic region and the storage region, forming a structure as Figure 4 shown; in various embodiments of the present invention, the material of the oxide layer can be silicon dioxide, and the material of the nitride layer can be silicon nitride;

[0034] In some embodiments, the method of patterning the polysilicon layer in Step 1 includes: forming a photoresist layer on the polysilicon layer; opening the photoresist layer by photolithography to define the formation position of the gate polysilicon layer 4; using etching to pattern the polysilicon layer to form the gate polysilicon layer 4; removing the remaining photoresist layer, and the photoresist layer can be removed by ashing process, wet cleaning and other methods.

[0035] In some embodiments, the etching method in Step 1 is dry etching.

[0036] Step 2: Remove the exposed third oxide layer to expose the nitride layer below, forming a structure as Figure 5 shown;

[0037] In some embodiments, the exposed third oxide layer is removed by wet etching in Step 2.

[0038] Step 3: Oxidize the exposed nitride layer and the surface of the gate polysilicon layer 4 to form a fourth oxide layer 5. The fourth oxide layer 5 serves as the first sidewall material layer, and the thickness of the fourth oxide layer 5 can be about 100 angstroms, forming a structure as Figure 6 shown;

[0039] In some embodiments, the exposed nitride layer and the surface of the gate polysilicon layer are oxidized to form the fourth oxide layer 5 by in-situ steam oxidation in Step 3.

[0040] Step 4: Form the subsequent sidewall structure by deposition and re-etching.

[0041] In some embodiments, the method for forming the subsequent sidewall structure in Step 4 includes: The method for forming the subsequent sidewall structure in Step 4 includes: sequentially depositing the second and third sidewall material layers. The second sidewall 6 material layer is a nitride, and the third sidewall 7 material layer is an oxide, forming a structure as Figure 7 shown; Etch the second and third sidewall material layers, and stop etching on the fourth oxide layer 5 in the logic region, so that it remains at the sidewalls of the gate polysilicon layer 4 to form a sidewall structure; Continue to etch to remove the exposed fourth oxide layer 5 and the first and second oxide layers, forming a structure as Figure 8 shown.

[0042] In some embodiments, the second and third sidewall material layers are etched by dry etching in Step 4.

[0043] In some embodiments, the exposed fourth oxide layer 5 and the first and second oxide layers are etched away by wet etching in Step 4.

[0044] In some embodiments, the thickness of the second sidewall 6 material layer in Step 4 is 150 to 300 angstroms.

[0045] In some embodiments, the thickness of the third sidewall 7 material layer in Step 4 is 200 to 700 angstroms.

[0046] It should be noted that the illustrations provided in this embodiment only schematically illustrate the basic concept of the present invention. Therefore, only the components related to the present invention are shown in the drawings, rather than being drawn according to the number, shape, and size of the components in actual implementation. The types, quantities, and proportions of the components in actual implementation can be arbitrarily changed, and the component layout type may also be more complex.

[0047] In summary, the present invention can completely etch the ONO layer in the SONOS region and the first oxide layer in the logic region without damaging the substrate, while forming effective protective sidewalls for the SONOS and MOS transistors. Therefore, the present invention effectively overcomes various disadvantages in the prior art and has high industrial utilization value.

[0048] The above embodiments are only illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Any person familiar with this technology can modify or change the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or changes made by those with ordinary knowledge in the technical field without departing from the spirit and technical ideas disclosed by the present invention should still be covered by the claims of the present invention.

Claims

1. A method for forming a sidewall of a SONOS memory, characterized in that: At least: Step 1, providing a substrate, the substrate having a logic area and a storage area, a first oxide layer formed in the logic area of ​​the substrate, an ONO layer formed in the storage area, the ONO layer consisting of a second oxide layer, a nitride layer, and a third oxide layer stacked in sequence from bottom to top, depositing a polysilicon layer, and then patterning the polysilicon layer by photolithography and etching to form a gate polysilicon layer on the logic area and the storage area; Step 2, removing the exposed third oxide layer to expose the nitride layer thereunder; Step 3: oxidizing the exposed surface of the nitride layer and the gate polysilicon layer to form a fourth oxide layer, wherein the fourth oxide layer serves as a first spacer material layer; Step 4: Form a subsequent sidewall structure by using a deposition and back etching method.

2. The method for forming a sidewall of a SONOS memory according to claim 1, wherein: The method for patterning the polysilicon layer in step 1 comprises: forming a photoresist layer on the polysilicon layer; opening the photoresist layer by photolithography to define the formation position of the gate polysilicon layer; patterning the polysilicon layer by etching to form the gate polysilicon layer; The remaining photoresist layer is removed.

3. The method for forming a sidewall of a SONOS memory according to claim 2, wherein: The etching method in step one is dry etching.

4. The method for forming a sidewall of a SONOS memory according to claim 1, wherein: In step 2, the exposed third oxide layer is removed by wet etching.

5. The method for forming a sidewall of a SONOS memory according to claim 1, wherein: In step three, the exposed surfaces of the nitride layer and the gate polysilicon layer are oxidized by in-situ water vapor oxidation to form the fourth oxide layer.

6. The method for forming a sidewall of a SONOS memory according to claim 1, wherein: The method for forming the subsequent sidewall structure in step four includes: depositing the second and third sidewall material layers in sequence, wherein the second sidewall material layer is a nitride and the third sidewall material layer is an oxide layer; etching the second and third sidewall material layers, wherein the etching stops on the fourth oxide layer so that it remains at the sidewall of the gate polysilicon layer to form a sidewall structure; and continuing to etch to remove the exposed fourth oxide layer and the first and second oxide layers.

7. The method for forming a sidewall of a SONOS memory according to claim 6, wherein: In step 4, the second and third sidewall material layers are etched using a dry etching method.

8. The method for forming a sidewall of a SONOS memory according to claim 6, wherein: In step 4, the exposed fourth oxide layer and the first and second oxide layers are etched away by wet etching.

9. The method for forming a sidewall of a SONOS memory according to claim 6, wherein: The thickness of the second spacer material layer in step 4 is 150 to 300 angstroms.

10. The method for forming a sidewall of a SONOS memory according to claim 6, wherein: The thickness of the third spacer material layer in step 4 is 200 to 700 angstroms.

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