Magnetic memory device

Abstract

A magnetic memory device includes a substrate having a top surface and a bottom surface; a first active region on the top surface of the substrate, the first active region including a lower channel pattern and a lower source / drain pattern; a second active region stacked on the first active region, the second active region including an upper channel pattern and an upper source / drain pattern; a gate electrode on the lower channel pattern and the upper channel pattern and extending in a first direction; a lower interconnect layer on the bottom surface of the substrate; a magnetic tunnel junction pattern and a spin-orbit torque line in the lower interconnect layer; a first lower contact electrically connecting the lower source / drain pattern to the magnetic tunnel junction pattern; and a second lower contact electrically connecting the upper source / drain pattern to the spin-orbit torque line.

Description

[0001] Cross - reference to related applications

[0002] This application claims the priority of Korean Patent Application No. 10 - 2023 - 0177073, filed with the Korean Intellectual Property Office on December 7, 2023, the entire contents of which are incorporated herein by reference. Technical field

[0003] The present disclosure generally relates to a magnetic memory device, and more particularly, to a spin - orbit - torque - based magnetic memory device. Background art

[0004] As the demand for electronic devices with increased speed and / or reduced power consumption increases, the demand for semiconductor memory devices with faster operation speed and / or lower operation voltage also increases. To meet this demand, a magnetic memory device has been proposed.

[0005] Due to its high - speed operation and / or non - volatility, the magnetic memory device is emerging as a promising alternative to conventional semiconductor memory devices.

[0006] Generally, a magnetic memory device includes a magnetic tunnel junction (MTJ) pattern. The MTJ pattern includes two magnetic layers and an insulating layer interposed therebetween. The resistance of the MTJ pattern can vary according to the magnetization directions of the magnetic layers relative to each other. For example, the resistance of the MTJ pattern is higher when the magnetization directions of the magnetic layers are antiparallel to each other than when they are parallel to each other. This resistance difference can be detected and used for data storage / reading operations of the magnetic memory device. With the development of the electronics industry, the demand for magnetic memory devices with higher integration density and lower power consumption properties is continuously growing. Therefore, more research is still needed to meet this demand. Summary of the invention

[0007] Embodiments of the inventive concept provide a spin - orbit - torque - based magnetic memory device that can be easily integrated.

[0008] According to an embodiment of the inventive concept, a magnetic memory device may include: a substrate having a top surface and a bottom surface facing each other; a first active region on the top surface of the substrate, the first active region including a lower channel pattern and a lower source / drain pattern connected to the lower channel pattern; a second active region stacked on the first active region, the second active region including an upper channel pattern and an upper source / drain pattern connected to the upper channel pattern; a gate electrode disposed on the lower channel pattern and the upper channel pattern and extending in a first direction; a lower interconnection layer on the bottom surface of the substrate; a magnetic tunnel junction pattern and a spin orbit torque (SOT) line in the lower interconnection layer; a first lower contact configured to penetrate a part of the lower interconnection layer and the substrate (i.e., at least partially extend into a part of the lower interconnection layer and the substrate) and connect the lower source / drain pattern to the magnetic tunnel junction pattern; and a second lower contact configured to penetrate a part of the lower interconnection layer, the substrate, and the lower source / drain pattern and connect the upper source / drain pattern to the spin orbit torque line.

[0009] According to an embodiment of the inventive concept, a magnetic memory device may include: a substrate having a top surface and a bottom surface facing each other; a lower source / drain pattern on the top surface of the substrate; an upper source / drain pattern stacked on the lower source / drain pattern and vertically spaced apart from the lower source / drain pattern, the lower source / drain pattern and the upper source / drain pattern being at least partially vertically overlapped with each other; an interlayer insulating layer covering the lower source / drain pattern and the upper source / drain pattern (i.e., on or above the lower source / drain pattern and the upper source / drain pattern); a source line on the interlayer insulating layer; a lower interconnection layer on the bottom surface of the substrate; a magnetic tunnel junction pattern and a spin orbit torque line disposed in the lower interconnection layer; and a bit line disposed in the lower interconnection layer and spaced apart from the bottom surface of the substrate, the magnetic tunnel junction pattern and the spin orbit torque line being inserted between the bottom surface of the substrate and the bit line. When observed in a plan view, the source line and the bit line may be spaced apart from each other in a first direction and may extend in a second direction crossing the first direction. The spin orbit torque line may extend in the second direction and may be at least partially vertically overlapped with the bit line.

[0010] According to an embodiment of the inventive concept, a magnetic memory device may include: a substrate having a top surface and a bottom surface opposite to each other and including an active pattern; a first active region on the active pattern, the first active region including a lower channel pattern and a lower source / drain pattern connected to the lower channel pattern; a second active region stacked on the first active region, the second active region including an upper channel pattern and an upper source / drain pattern connected to the upper channel pattern; a gate electrode disposed on the lower channel pattern and the upper channel pattern and extending in a first direction; a lower interconnection layer including a first lower insulating layer, a second lower insulating layer, and a third lower insulating layer sequentially stacked on the bottom surface of the substrate; a bit line in the third lower insulating layer; a first lower contact extending at least partially into the first lower insulating layer and the substrate; a second lower contact extending at least partially into the first lower insulating layer, the second lower insulating layer, the substrate, and the lower source / drain pattern; a magnetic tunnel junction pattern in the second lower insulating layer and connected to the first lower contact; and a spin-orbit torque line in the third lower insulating layer and connected to the second lower contact and the magnetic tunnel junction pattern. The magnetic tunnel junction pattern and the spin-orbit torque line may be between the bottom surface of the substrate and the bit line. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Embodiments will be more clearly understood from the following detailed description in conjunction with the accompanying drawings, in which, throughout the several views, like reference numerals (when used) indicate corresponding elements, and

[0012] in the drawings:

[0013] Figure 1A is a circuit diagram showing a cell array of a magnetic memory device according to an embodiment of the inventive concept;

[0014] Figure 1B is a circuit diagram schematically showing a memory cell of a magnetic memory device according to an embodiment of the inventive concept;

[0015] Figure 2A and Figure 2B is an exemplary cross-sectional view showing a magnetic tunnel junction pattern constituting Figure 1B the memory cell;

[0016] Figure 3 is a plan view showing a magnetic memory device according to an embodiment of the inventive concept;

[0017] Figures 4A to 4E are cross-sectional views taken along lines A-A', B-B', C-C', D-D', and E-E' of Figure 3 respectively;

[0018] taken;

[0019] Figures 5A to 19Bis a cross-sectional view showing an intermediate process in an exemplary method of manufacturing a magnetic memory device according to an embodiment of the inventive concept;

[0020] Figure 20A is a schematic circuit diagram showing a cell array of a magnetic memory device according to an embodiment of the inventive concept;

[0021] Figure 20B is a plan view showing a magnetic memory device according to an embodiment of the inventive concept;

[0022] Figure 21A and Figure 21B are cross-sectional views taken along lines C-C' and B-B' of Figure 20B respectively;

[0023] Figure 22 is a plan view showing a magnetic memory device according to an embodiment of the inventive concept;

[0024] Figure 23A and Figure 23B are cross-sectional views taken along lines A-A' and B-B' of Figure 22 respectively;

[0025] Figure 24A is a plan view showing a magnetic memory device according to an embodiment of the inventive concept;

[0026] Figure 24B shows Figure 24A a plan view of the spin-orbit torque lines of the magnetic memory device shown;

[0027] Figure 25A and Figure 25B are cross-sectional views taken along lines A-A' and B-B' of Figure 24A respectively;

[0028] Figure 26 is a plan view showing a magnetic memory device according to an embodiment of the inventive concept;

[0029] Figure 27A and Figure 27B are cross-sectional views taken along lines A-A' and B-B' of Figure 26 respectively;

[0030] Figure 28A is a circuit diagram schematically showing a memory cell of a magnetic memory device according to an embodiment of the inventive concept;

[0031] Figure 28B shows Figure 28A a plan view of the magnetic memory device of; and Figure 29A and Figure 29B are cross-sectional views taken along lines A-A' and B-B' of Figure 28BCross-sectional views taken along lines A-A' and B-B'. Detailed implementation manners

[0032] Example embodiments of the inventive concept will now be described more fully with reference to the accompanying drawings, in which example embodiments are shown.

[0033] Figure 1A is a schematic circuit diagram showing at least a part of an example cell array of a magnetic memory device according to an embodiment of the inventive concept. Figure 1B is a circuit diagram schematically showing a memory cell of a magnetic memory device according to an embodiment of the inventive concept.

[0034] Referring to Figure 1A and Figure 1B , the cell array may include a plurality of word lines WL, a plurality of bit lines BL, a plurality of source lines SL, and a plurality of memory cells MC. Each of the memory cells MC may be connected at the intersection of a corresponding word line WL and a bit line BL.

[0035] Each of the memory cells MC may include a magnetic tunnel junction pattern MTJ, a spin-orbit torque line SOT, an upper transistor TRa, and a lower transistor TRb.

[0036] The magnetic tunnel junction pattern MTJ may include a pinned magnetic pattern PL, a free magnetic pattern FL, and a tunnel barrier pattern TBL therebetween. The free magnetic pattern FL may be disposed between the spin-orbit torque line SOT and the tunnel barrier pattern TBL, the pinned magnetic pattern PL may be spaced apart from the free magnetic pattern FL, and the tunnel barrier pattern TBL may be inserted between the pinned magnetic pattern PL and the free magnetic pattern FL. The free magnetic pattern FL may be in contact with the surface of the spin-orbit torque line SOT. As used herein, the term "contact" (or "be in contact with" or similar terms, such as "be connected to" or "connected to") is broadly intended to include electrical connection and / or physical connection, and may include other intervening elements unless otherwise stated. When there is an in-plane current flowing through the spin-orbit torque line SOT, a spin-orbit torque caused by the spin Hall effect or the Rashba effect may be applied to the free magnetic pattern FL, and as a result, the magnetization direction of the free magnetic pattern FL may be switched.

[0037] The memory cells MC may be arranged to form a plurality of rows and a plurality of columns. The memory cells MC in each row may be commonly connected to a pair of source lines SL and a bit line BL. The memory cells MC in each column may be commonly connected to one of the word lines WL.

[0038] The upper transistor TRa and the lower transistor TRb in each memory cell MC may be commonly connected to a corresponding one of the word lines WL. The spin-orbit torque lines SOT of the memory cells MC in each row may be commonly connected to one of the bit lines BL.

[0039] In a write operation to a selected memory cell, the upper transistor TRa and the lower transistor TRb can be turned on and off by a selected word line WL, respectively. Accordingly, a write current can flow through the spin-orbit torque line SOT. The current direction of the write current can be changed according to the voltages applied to a selected bit line BL and a corresponding source line SL.

[0040] The write current can be an in-plane current that applies a spin-orbit torque to a free magnetic pattern FL of a magnetic tunnel junction pattern MTJ. The write current can flow through a region adjacent to an interface between the spin-orbit torque line SOT and the free magnetic pattern FL in a direction parallel to the interface. In the presence of the write current, a spin current caused by the spin Hall effect and the Rashba effect can flow in a direction perpendicular to the interface between the spin-orbit torque line SOT and the free magnetic pattern FL. As a result, a spin-orbit torque can be applied to the magnetic tunnel junction pattern MTJ. Accordingly, the magnetization direction of the free magnetic pattern FL can be switched to be parallel or antiparallel to the magnetization direction of a pinned magnetic pattern PL.

[0041] In a read operation to a selected memory cell, the lower transistor TRb and the upper transistor TRa can be turned on and off by a selected word line WL, respectively. Accordingly, a read current can flow from the selected bit line BL to the corresponding source line SL. The read current can flow through the magnetic tunnel junction pattern MTJ and the spin-orbit torque line SOT. The read current can pass through the magnetic tunnel junction pattern MTJ in a direction perpendicular to an interface between the spin-orbit torque line SOT and the magnetic tunnel junction pattern MTJ.

[0042] Figure 2A and Figure 2B schematically show a cross-sectional view of a magnetic tunnel junction pattern that constitutes Figure 1B the memory cell.

[0043] Referring to Figure 2A and Figure 2B , the magnetic tunnel junction pattern MTJ can include a free magnetic pattern FL, a tunnel barrier pattern TBL, and a pinned magnetic pattern PL, which are sequentially stacked on the spin-orbit torque line SOT in a direction perpendicular to an upper surface of the spin-orbit torque line SOT. The pinned magnetic pattern PL can have a magnetization direction MDp fixed to a specific direction, and the free magnetic pattern FL can have a magnetization direction MDf that can be changed to be parallel or antiparallel to the magnetization direction MDp of the pinned magnetic pattern PL. As referred to Figure 1A and Figure 1BAs described above, the write current Iw can flow through the spin-orbit torque line SOT in a direction parallel to the interface INF between the spin-orbit torque line SOT and the free magnetic pattern FL, and can flow through the region adjacent to the interface INF. The spin-orbit torque caused by the write current Iw can be applied to the magnetic tunnel junction pattern MTJ, and thus, the magnetization direction of the free magnetic pattern FL can be switched to be parallel or anti-parallel to the magnetization direction of the pinned magnetic pattern PL.

[0044] Referring to Figure 2A , the magnetization direction MDf of the free magnetic pattern FL and the magnetization direction MDp of the pinned magnetic pattern PL can be perpendicular to the interface INF between the spin-orbit torque line SOT and the free magnetic pattern FL, respectively. The free magnetic pattern FL and the pinned magnetic pattern PL can exhibit perpendicular magnetic anisotropy. In this case, each of the free magnetic pattern FL and the pinned magnetic pattern PL can be formed of or include at least one of an intrinsic perpendicular magnetic material and a non-intrinsic perpendicular magnetic material. The intrinsic perpendicular magnetic material can include a material that exhibits perpendicular magnetization properties even without an external cause (e.g., an electromagnetic field). The intrinsic perpendicular magnetic material can include at least one of the following: i) perpendicular magnetic materials (e.g., CoFeTb, CoFeGd, and CoFeDy), ii) perpendicular magnetic materials having an L1 0 structure, iii) CoPt-based materials having a hexagonal close-packed structure, and iv) perpendicular magnetic structures. The perpendicular magnetic material having an L1 0 structure can include at least one of L1 0 FePt, L1 0 FePd, L1 0 CoPd, and L1 0 CoPt. The perpendicular magnetic structure can include alternately and repeatedly stacked magnetic layers and non-magnetic layers. For example, the perpendicular magnetic structure can include (Co / Pt) n , (CoFe / Pt) n , (CoFe / Pd) n , (Co / Pd) n , (Co / Ni) n , (CoNi / Pt) n , (CoCr / Pt) n , and (CoCr / Pd) nat least one of, where n is the number of pairs of the stack. The non-intrinsic perpendicular magnetic material may include a material that exhibits an intrinsic in-plane magnetization property in the absence of an external cause but exhibits a perpendicular magnetization property due to an external cause. For example, the non-intrinsic perpendicular magnetic material may have a perpendicular magnetization property caused by magnetic anisotropy resulting from when the free magnetic pattern FL (or the pinned magnetic pattern PL) contacts the tunnel barrier pattern TBL. The non-intrinsic perpendicular magnetic material may be formed of, for example, CoFeB or may include, for example, CoFeB.

[0045] Referring to Figure 2B , the magnetization direction MDf of the free magnetic pattern FL and the magnetization direction MDp of the pinned magnetic pattern PL may be parallel to the interface INF between the spin-orbit torque line SOT and the free magnetic pattern FL. The free magnetic pattern FL and the pinned magnetic pattern PL may exhibit in-plane magnetic anisotropy. In this case, each of the free magnetic pattern FL and the pinned magnetic pattern PL may be formed of a ferromagnetic material or may include a ferromagnetic material. The pinned magnetic pattern PL may further include an antiferromagnetic material that fixes the magnetization direction of the ferromagnetic material in the pinned magnetic pattern PL.

[0046] In an embodiment, each of the free magnetic pattern FL and the pinned magnetic pattern PL may include a Co-based Heusler alloy. The tunnel barrier pattern TBL may be formed of at least one of magnesium oxide, titanium oxide, aluminum oxide, magnesium zinc oxide, and magnesium boron oxide, or may include at least one of magnesium oxide, titanium oxide, aluminum oxide, magnesium zinc oxide, and magnesium boron oxide.

[0047] The spin-orbit torque line SOT can be formed of or include at least one of heavy metals or a material doped with at least one of heavy metals. In an embodiment, the spin-orbit torque line SOT can include a material (M) doped with at least one of dopants (A) and (B). Dopant (A) can include yttrium (Y), zirconium (Zr), niobium (Nb), molybdenum (Mo), technetium (Tc), ruthenium (Ru), rhodium (Rh), palladium (Pd), cadmium (Cd), indium (In), antimony (Sb), tellurium (Te), hafnium (Hf), tantalum (Ta) (including high-resistance amorphous β-Ta), tungsten (W), rhenium (Re), osmium (Os), iridium (Ir), platinum (Pt), gold (Au), mercury (Hg), thallium (Tl), lead (Pb), bismuth (Bi), polonium (Po), astatine (At), and / or a combination thereof. Dopant (B) can include at least one of vanadium (V), chromium (Cr), manganese (Mn), iron (Fe), cobalt (Co), nickel (Ni), phosphorus (P), sulfur (S), zinc (Zn), gallium (Ga), germanium (Ge), arsenic (As), selenium (Se), yttrium (Y), zirconium (Zr), niobium (Nb), molybdenum (Mo), technetium (Tc), ruthenium (Ru), rhodium (Rh), palladium (Pd), silver (Ag), cadmium (Cd), indium (In), antimony (Sb), tellurium (Te), iodine (I), lutetium (Lu), hafnium (Hf), tantalum (Ta), tungsten (W), rhenium (Re), osmium (Os), iridium (Ir), platinum (Pt), gold (Au), mercury (Hg), thallium (Tl), lead (Pb), bismuth (Bi), polonium (Po), astatine (At), lanthanum (La), cerium (Ce), praseodymium (Pr), neodymium (Nd), promethium (Pm), samarium (Sm), europium (Eu), gadolinium (Gd), terbium (Tb), dysprosium (Dy), holmium (Ho), erbium (Er), thulium (Tm), and / or ytterbium (Yb). The material (M) can include at least one of aluminum (Al), titanium (Ti), vanadium (V), chromium (Cr), manganese (Mn), copper (Cu), zinc (Zn), silver (Ag), hafnium (Hf), tantalum (Ta), tungsten (W), rhenium (Re), platinum (Pt), gold (Au), mercury (Hg), lead (Pb), silicon (Si), gallium (Ga), gallium manganese (GaMn), and / or gallium arsenide (GaAs).

[0048] The spin-orbit torque line SOT may include a chalcogen-based phase insulator (e.g., a topological insulator). The spin-orbit torque line SOT may be formed of or include a compound that contains at least one of chalcogen elements (e.g., tellurium (Te) and selenium (Se)) and at least one of silicon (Si), germanium (Ge), bismuth (Bi), and antimony (Sb). In an embodiment, the spin-orbit torque line SOT may be formed of or include at least one of GeSe, BiSe, BiSbTe, GeTe, GeTeSe, GeSbTe, SiTe, and SiGeTe.

[0049] Figure 3 is a plan view showing a magnetic memory device according to an embodiment of the inventive concept. Figures 4A to 4E are respectively Figure 3 cross-sectional views taken along lines A-A', B-B', C-C', D-D', and E-E' of

[0050] Referring to Figure 3 and Figures 4A to 4E , a substrate 100 having a top surface 100a and a bottom surface 100b that face each other in a third direction D3 may be provided. In the present specification, a first direction D1 and a second direction D2 may be parallel to the top surface 100a of the substrate 100 and may not be parallel to each other. The third direction D3 may be perpendicular to the top surface 100a of the substrate 100. As an example, the first direction D1, the second direction D2, and the third direction D3 may be orthogonal to each other. The substrate 100 may be a semiconductor substrate (e.g., a silicon substrate, a germanium substrate, and / or a silicon-germanium substrate).

[0051] A first active region AR1 and a second active region AR2 may be sequentially stacked on the substrate 100 along the third direction D3. One of the first active region AR1 and the second active region AR2 may be a p-channel metal-oxide-semiconductor field-effect transistor (PMOSFET) region, and the other of the first active region AR1 and the second active region AR2 may be an n-channel metal-oxide-semiconductor field-effect transistor (NMOSFET) region. The NMOS-FETs and PMOS-FETs of the first active region AR1 and the second active region AR2 may be vertically stacked to form a three-dimensional stacked transistor.

[0052] The active pattern AP may be defined in the upper portion of the substrate 100 by the device isolation layer ST. The active pattern AP may be a vertically protruding portion of the substrate 100. The first active region AR1 and the second active region AR2 may be sequentially stacked on the active pattern AP. The device isolation layer ST may include a silicon oxide layer. The top surface of the device isolation layer ST may be coplanar with or lower than the top surface of the active pattern AP. The device isolation layer ST may not cover the lower channel pattern CH1 and the upper channel pattern CH2 to be described below. As used herein, the term "cover" (or "covered by" or a similar term) is intended to broadly mean that a material, layer, or structure is on or above another material, layer, or structure, but does not require that the material, layer, or structure completely cover the other material, layer, or structure, unless specifically stated otherwise.

[0053] The first active region AR1 may include a lower channel pattern CH1 and lower source / drain patterns SD1. The lower channel pattern CH1 may be inserted between the lower source / drain patterns SD1. The lower source / drain patterns SD1 may be disposed on both sides of the lower channel pattern CH1 and may be spaced apart from each other in the second direction D2. The lower channel pattern CH1 may be configured to connect the lower source / drain patterns SD1 to each other.

[0054] The lower channel pattern CH1 may include a first semiconductor pattern to a third semiconductor pattern SP1, SP2, and SP3 stacked in sequence. The first semiconductor pattern to the third semiconductor pattern SP1, SP2, and SP3 may be spaced apart from each other in the vertical direction (i.e., the third direction D3). Each of the first semiconductor pattern to the third semiconductor pattern SP1, SP2, and SP3 may be formed of or include silicon (Si), germanium (Ge), or silicon germanium (SiGe), but the embodiments are not limited thereto. In an embodiment, each of the first semiconductor pattern to the third semiconductor pattern SP1, SP2, and SP3 may be formed of or include crystalline silicon.

[0055] The lower source / drain pattern SD1 may be disposed on the top surface of the active pattern AP. The lower source / drain pattern SD1 may be an epitaxial pattern formed by a selective epitaxial growth (SEG) process. In an embodiment, the top surface of the lower source / drain pattern SD1 may be higher than the top surface of the third semiconductor pattern SP3 of the lower channel pattern CH1 with respect to the top surface 100a of the substrate 100 as a reference layer.

[0056] The lower source / drain pattern SD1 may be doped to have a first conductivity type. The first conductivity type may be an n-type or a p-type. The lower source / drain pattern SD1 may be formed of or include at least one of silicon germanium (SiGe), silicon (Si), and silicon carbide (SiC). The lower source / drain pattern SD1 may be configured to apply tensile strain or compressive strain to the lower channel pattern CH1.

[0057] The first interlayer insulating layer 110 may be disposed on the lower source / drain pattern SD1. The first interlayer insulating layer 110 may cover the lower source / drain pattern SD1. The second interlayer insulating layer 120 and the second active region AR2 may be disposed on the first interlayer insulating layer 110.

[0058] The second active region AR2 may include an upper channel pattern CH2 and upper source / drain patterns SD2. The upper channel pattern CH2 may vertically overlap the lower channel pattern CH1. As used herein, the term "overlap" (or "is overlapped" or similar terms) is intended to broadly mean that a first element intersects at least a portion of a second element in the vertical direction (i.e., the third direction D3), but does not require the first element and the second element to be completely aligned with each other in the horizontal plane (i.e., in the first direction D1 and / or the second direction D2). The upper source / drain patterns SD2 may vertically overlap the lower source / drain pattern SD1. The upper channel pattern CH2 may be inserted between the upper source / drain patterns SD2. The upper source / drain patterns SD2 may be disposed on both sides of the upper channel pattern CH2 and may be spaced apart from each other in the second direction D2. The upper channel pattern CH2 may connect the upper source / drain patterns SD2 to each other.

[0059] The upper channel pattern CH2 may include a fourth semiconductor pattern to a sixth semiconductor pattern SP4, SP5, and SP6 stacked in sequence. The fourth semiconductor pattern to the sixth semiconductor pattern SP4, SP5, and SP6 may be spaced apart from each other in the third direction D3. The fourth semiconductor pattern to the sixth semiconductor pattern SP4, SP5, and SP6 of the upper channel pattern CH2 may be formed of or include the same semiconductor material as the first semiconductor pattern to the third semiconductor pattern SP1, SP2, and SP3 of the lower channel pattern CH1 described above.

[0060] At least one pseudo-channel pattern DSP may be inserted between the lower channel pattern CH1 and the upper channel pattern CH2 in the third direction D3. The pseudo-channel pattern DSP may be spaced apart from the lower source / drain pattern SD1. The pseudo-channel pattern DSP may be spaced apart from the upper source / drain pattern SD2. In other words, the pseudo-channel pattern DSP may not be connected to any source / drain pattern. The pseudo-channel pattern DSP may be formed of or include a semiconductor material (e.g., silicon (Si), germanium (Ge), or silicon germanium (SiGe)) or a silicon-based insulating material (e.g., silicon oxide or silicon nitride), but the embodiments are not limited thereto. In an embodiment, the pseudo-channel pattern DSP may be formed of or include a silicon-based insulating material.

[0061] The upper source / drain pattern SD2 may be disposed on the top surface of the first interlayer insulating layer 110. Each of the upper source / drain patterns SD2 may be an epitaxial pattern formed by a selective epitaxial growth (SEG) process. In an embodiment, the top surface of the upper source / drain pattern SD2 may be higher than the top surface of the sixth semiconductor pattern SP6 of the upper channel pattern CH2.

[0062] The upper source / drain pattern SD2 may be doped to have a second conductivity type. The second conductivity type may be different from the first conductivity type of the lower source / drain pattern SD1. The upper source / drain pattern SD2 may be formed of or include at least one of silicon germanium (SiGe), silicon (Si), and silicon carbide (SiC). The upper source / drain pattern SD2 may be configured to apply tensile strain or compressive strain to the upper channel pattern CH2.

[0063] The second interlayer insulating layer 120 may cover the upper source / drain pattern SD2. The top surface of the second interlayer insulating layer 120 may be coplanar with the top surface of each of the first upper contact 121 and the second upper contact 122 to be described below in the third direction D3 with respect to the top surface 100a of the substrate 100.

[0064] The gate electrode GE may be disposed on the lower channel pattern CH1 and the upper channel pattern CH2. The gate electrode GE may be used as Figure 3 the word line WL. When observed in a plan view, the gate electrode GE may be a bar-shaped pattern extending in the first direction D1. The gate electrode GE may vertically overlap the stacked lower channel pattern CH1 and upper channel pattern CH2.

[0065] The gate electrode GE may be disposed on the top surface, bottom surface, and opposite side surfaces of each of the first semiconductor pattern SP1 to the sixth semiconductor pattern. That is, the transistor according to the present embodiment may include a three-dimensional field effect transistor (e.g., a multi-bridge trench field effect transistor (MBCFET) or a gate-all-around field effect transistor (GAAFET)), in which the gate electrode GE is disposed to surround the channel pattern three-dimensionally. As used herein, the term "surround" (or "enclose" or similar terms) is intended to broadly mean that an element, structure, or layer surrounds, encapsulates, encircles, or encloses another element, structure, or layer on all sides, but there may also be breaks or gaps. Thus, for example, a material layer having voids or gaps therein may still "surround" another layer that it encircles.

[0066] The gate electrode GE may include a lower gate electrode LGE disposed in the first active region AR1 and an upper gate electrode UGE disposed in the second active region AR2. The lower gate electrode LGE and the upper gate electrode UGE may vertically overlap each other. The lower gate electrode LGE and the upper gate electrode UGE may be connected to each other. In other words, the gate electrode GE according to the present embodiment may be a common gate electrode composed of the lower gate electrode LGE and the upper gate electrode UGE respectively disposed on the lower channel pattern CH1 and the upper channel pattern CH2 and connected to each other.

[0067] The lower gate electrode LGE may include a first portion PO1 inserted between the active pattern AP and the first semiconductor pattern SP1, a second portion PO2 inserted between the first semiconductor pattern SP1 and the second semiconductor pattern SP2, a third portion PO3 inserted between the second semiconductor pattern SP2 and the third semiconductor pattern SP3, and a fourth portion PO4 inserted between the third semiconductor pattern SP3 and the pseudo-channel pattern DSP.

[0068] The upper gate electrode UGE may include a fifth portion PO5 inserted between the pseudo-channel pattern DSP and the fourth semiconductor pattern SP4, a sixth portion PO6 inserted between the fourth semiconductor pattern SP4 and the fifth semiconductor pattern SP5, a seventh portion PO7 inserted between the fifth semiconductor pattern SP5 and the sixth semiconductor pattern SP6, and an eighth portion PO8 on the sixth semiconductor pattern SP6.

[0069] The gate spacer GS may be respectively disposed on the opposite side surfaces of the gate electrode GE. Refer to Figure 4A, the gate spacers GS can be respectively disposed on opposite side surfaces of the eighth portion PO8 of the upper gate electrode UGE. The gate spacers GS can extend along the gate electrode GE or in the first direction D1. With respect to the top surface 100a of the substrate 100, the top surface of the gate spacers GS can be higher than the top surface of the gate electrode GE in the third direction D3. The top surface of the gate spacers GS can be coplanar with the top surface of the second interlayer insulating layer 120 in the third direction D3. The gate spacers GS can be formed of or include at least one of SiCN, SiCON, and SiN. In an embodiment, the gate spacers GS can be a multi-layer structure including at least two different materials selected from SiCN, SiCON, and SiN, but the embodiment is not limited thereto. A pair of liner layers LIN can be respectively disposed on opposite side surfaces of each of the fourth portion PO4 and the fifth portion PO5 of the gate electrode GE.

[0070] The gate capping pattern GP can be disposed on the top surface of the gate electrode GE. The gate capping pattern GP can extend along the gate electrode GE or in the first direction D1. In an embodiment, the gate capping pattern GP can be formed of or include at least one of SiON, SiCN, SiCON, and SiN.

[0071] The gate insulating layer GI can be inserted between the gate electrode GE and the first to sixth semiconductor patterns SP1 to SP6. The gate insulating layer GI can be formed of or include at least one of silicon oxide, silicon oxynitride, and / or a high-k dielectric material. In an embodiment, the gate insulating layer GI can include a silicon oxide layer and a high dielectric constant (high-k) dielectric layer, the silicon oxide layer being disposed to directly cover the surface of each of the semiconductor patterns SP1 to SP6, and the high dielectric constant dielectric layer being disposed on the silicon oxide layer. In other words, the gate insulating layer GI can be a multi-layer structure including a silicon oxide layer and a high-k dielectric layer.

[0072] The high-k dielectric layer can be formed of or include at least one of high-k dielectric materials having a dielectric constant higher than that of silicon oxide. The high-k dielectric materials can include, for example, at least one of hafnium oxide, hafnium silicon oxide, hafnium zirconium oxide, hafnium tantalum oxide, lanthanum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanate, barium titanate, strontium titanate, lithium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate.

[0073] The lower gate electrode LGE and the lower source / drain pattern SD1 disposed in the first active region AR1 can constitute Figure 1A and Figure 1Bthe lower transistor TRb. The upper gate electrode UGE and the upper source / drain pattern SD2 disposed in the second active region AR2 may constitute Figure 1A and Figure 1B the upper transistor TRa.

[0074] The third interlayer insulating layer 130 may be disposed on the second interlayer insulating layer 120. The third interlayer insulating layer 130 may cover the gate spacer GS and the gate capping pattern GP.

[0075] The gate contact GC may be configured to penetrate the third interlayer insulating layer 130 and the gate capping pattern GP (i.e., at least partially extend into the third interlayer insulating layer 130 and the gate capping pattern GP), and may be electrically connected to the gate electrode GE. The gate contact GC may be formed of at least one metal material selected from the group consisting of copper (Cu), aluminum (Al), ruthenium (Ru), cobalt (Co), tungsten (W), and molybdenum (Mo) or include at least one metal material selected from the group consisting of copper (Cu), aluminum (Al), ruthenium (Ru), cobalt (Co), tungsten (W), and molybdenum (Mo).

[0076] The source line SL may be disposed on the third interlayer insulating layer 130. When observed in a plan view, the source line SL may extend in the second direction D2. The source line SL may not vertically overlap with the gate contact GC.

[0077] The first upper contact 121 and the second upper contact 122 may be electrically connected to the lower source / drain pattern SD1 and the upper source / drain pattern SD2, respectively. Referring to Figure 3 , the first upper contact 121 and the second upper contact 122 may be disposed on both sides of the gate electrode GE. The first upper contact 121 and the second upper contact 122 may be spaced apart from each other in the second direction D2. When observed in a plan view, the first upper contact 121 and the second upper contact 122 may vertically overlap with the source line SL. In an embodiment, the first upper contact 121 and the second upper contact 122 may be formed of a doped semiconductor material and / or a metal material or include a doped semiconductor material and / or a metal material. For example, the metal material may be selected from the group consisting of copper (Cu), aluminum (Al), ruthenium (Ru), cobalt (Co), tungsten (W), and molybdenum (Mo).

[0078] The first upper contact 121 may extend from the top surface of the second interlayer insulating layer 120 to penetrate the second interlayer insulating layer 120, the upper source / drain pattern SD2, and a part of the first interlayer insulating layer 110, and may be connected to the lower source / drain pattern SD1. The bottom surface of the first upper contact 121 may be in the lower source / drain pattern SD1.

[0079] The first upper isolation structure 121s can surround the first upper contact 121 (i.e., extend around the first upper contact 121). The first upper isolation structure 121s can be inserted between the first upper contact 121 and the upper source / drain pattern SD2 and can extend in the third direction D3. In other words, the first upper isolation structure 121s can be inserted between the first upper contact 121 and the second interlayer insulating layer 120, between the first upper contact 121 and the upper source / drain pattern SD2, and between the first upper contact 121 and the first interlayer insulating layer 110. The first upper isolation structure 121s can extend into the region between the lower source / drain pattern SD1 and the first upper contact 121. The first upper isolation structure 121s can be arranged to expose the bottom surface of the first upper contact 121. The term "exposed" (or "is exposed" or a similar term) can be used to describe the relationship between elements and / or with reference to an intermediate process in manufacturing a semiconductor device, but it may not be necessary for a specific element to be exposed in the completed device. Similarly, the term "not exposed" can be used to describe the relationship between elements and / or with reference to an intermediate process in manufacturing a semiconductor device, but it may not be necessary for a specific element to be not exposed in the completed device. Due to the first upper isolation structure 121s, the first upper contact 121 can be separated from the upper source / drain pattern SD2 and can be electrically disconnected or electrically isolated from the upper source / drain pattern SD2. That is, the first upper contact 121 can be selectively electrically connected to the lower source / drain pattern SD1.

[0080] The second upper contact 122 can extend from the top surface of the second interlayer insulating layer 120 to penetrate a part of the second interlayer insulating layer 120 and can be connected to the upper source / drain pattern SD2. The bottom surface of the second upper contact 122 can be in the upper source / drain pattern SD2.

[0081] The second upper isolation structure 122s can extend around the second upper contact 122. However, in an embodiment, different from the shown structure, the second upper isolation structure 122s may not be provided. The second upper contact 122 can be selectively electrically connected to the upper source / drain pattern SD2.

[0082] The first upper isolation structure 121s and the second upper isolation structure 122s can be formed of a silicon-based insulating material (e.g., silicon oxide or silicon nitride) or include a silicon-based insulating material (e.g., silicon oxide or silicon nitride).

[0083] The source contact 135 can be provided in the third interlayer insulating layer 130. The source contact 135 can electrically connect the source line SL to the first upper contact 121 and the second upper contact 122, respectively.

[0084] The lower interconnect layer BSI may be disposed on the bottom surface 100b of the substrate 100. The lower interconnect layer BSI may include a first lower insulating layer 10, a second lower insulating layer 20, and a third lower insulating layer 30, which are sequentially stacked on the bottom surface 100b of the substrate 100 along the third direction D3. The bit line BL may be disposed in the third lower insulating layer 30. The bit line BL may extend in the second direction D2. When observed in a plan view, the bit line BL may be spaced apart from the source line SL in the first direction D1. The power delivery network layer PDN or an additional interconnect layer may be disposed on the lower interconnect layer BSI.

[0085] A first lower contact 11 and a second lower contact 12 that are respectively electrically connected to the lower source / drain pattern SD1 and the upper source / drain pattern SD2 may be provided. Referring to Figure 3 , the first lower contact 11 and the second lower contact 12 may be provided on both sides of the gate electrode GE. The first lower contact 11 and the second lower contact 12 may be spaced apart from each other in the second direction D2. When observed in a plan view, the first lower contact 11 and the second lower contact 12 may at least partially vertically overlap the bit line BL. In an embodiment, the first lower contact 11 and the second lower contact 12 may include a doped semiconductor material and / or a metal material. The metal material may be selected from the group consisting of copper (Cu), aluminum (Al), ruthenium (Ru), cobalt (Co), tungsten (W), and molybdenum (Mo).

[0086] The first lower contact 11 may be provided to penetrate a part of the lower interconnect layer BSI and may be connected to the lower source / drain pattern SD1. Specifically, the first lower contact 11 may extend from the bottom surface of the first lower insulating layer 10 to penetrate the first lower insulating layer 10 and the substrate 100 and may be connected to the lower source / drain pattern SD1. The top surface of the first lower contact 11 may be in the lower source / drain pattern SD1. The first lower isolation structure 11s may be provided to extend around the first lower contact 11. However, in an embodiment, different from the shown structure, the first lower isolation structure 11s may be omitted. The first lower contact 11 may selectively electrically connect to the lower source / drain pattern SD1.

[0087] The second lower contact 12 may be configured to penetrate a part of the lower interconnection layer BSI and may be connected to the upper source / drain pattern SD2. Specifically, the second lower contact 12 may extend from the bottom surface of the second lower insulating layer 20 to penetrate the second lower insulating layer 20, the first lower insulating layer 10, the substrate 100, the lower source / drain pattern SD1, and the first interlayer insulating layer 110, and may be connected to the upper source / drain pattern SD2. The top surface of the second lower contact 12 may be located in the upper source / drain pattern SD2. The second lower isolation structure 12s may be configured to extend around the second lower contact 12. The second lower isolation structure 12s may be inserted between the second lower contact 12 and the lower source / drain pattern SD1 and may extend in the third direction D3. In other words, the second lower isolation structure 12s may be inserted between the second lower contact 12 and the first interlayer insulating layer 110, the lower source / drain pattern SD1, the substrate 100, the first lower insulating layer 10, and the second lower insulating layer 20. The second lower isolation structure 12s may extend into the region between the upper source / drain pattern SD2 and the second lower contact 12. The second lower isolation structure 12s may be configured to expose the top surface of the second lower contact 12. Due to the second lower isolation structure 12s, the second lower contact 12 may be separated from the lower source / drain pattern SD1 and may be electrically disconnected or isolated from the lower source / drain pattern SD1. That is, the second lower contact 12 may be selectively electrically connected to the upper source / drain pattern SD2.

[0088] Each of the first lower isolation structure 11s and the second lower isolation structure 12s may be formed of a silicon-based insulating material (e.g., silicon oxide or silicon nitride) or may include a silicon-based insulating material (e.g., silicon oxide or silicon nitride).

[0089] The magnetic tunnel junction pattern MTJ may be in the lower interconnection layer BSI. Specifically, the magnetic tunnel junction pattern MTJ may be disposed in the second lower insulating layer 20. The magnetic tunnel junction pattern MTJ may contact and be connected to the first lower contact 11. When observed in a plan view, the magnetic tunnel junction pattern MTJ may at least partially vertically overlap with the first lower contact 11. The magnetic tunnel junction pattern MTJ may include a free magnetic pattern FL, a pinned magnetic pattern PL, and a tunnel barrier pattern TBL therebetween. The pinned magnetic pattern PL may be disposed between the tunnel barrier pattern TBL and the first lower contact 11, the free magnetic pattern FL may be spaced apart from the pinned magnetic pattern PL, and the tunnel barrier pattern TBL may be inserted between the free magnetic pattern FL and the pinned magnetic pattern PL. The magnetic tunnel junction pattern MTJ may be configured to have substantially the same characteristics as the magnetic tunnel junction pattern MTJ described with reference to Figure 2A and Figure 2B described. The magnetic tunnel junction pattern MTJ may be electrically connected to the lower source / drain pattern SD1 through the first lower contact 11. In other words, the magnetic tunnel junction pattern MTJ may be electrically connected to the referenceFigure 1A and Figure 1B the source / drain terminals of the lower transistor described in Figure 1B .

[0090] The spin-orbit torque line SOT may be provided in the lower interconnect layer BSI. Specifically, the spin-orbit torque line SOT may be on the second lower insulating layer 20. The spin-orbit torque line SOT may be a bar pattern extending in the second direction D2. When observed in a plan view, the spin-orbit torque line SOT may at least partially vertically overlap with the bit line BL.

[0091] The spin-orbit torque line SOT may contact and be connected to the magnetic tunnel junction pattern MTJ and the second lower contact 12. The spin-orbit torque line SOT may be electrically connected to the upper source / drain pattern SD2 through the second lower contact 12.

[0092] The magnetic tunnel junction pattern MTJ and the spin-orbit torque line SOT may be between the bottom surface 100b of the substrate 100 and the bit line BL. That is, the bit line BL may be spaced apart from the bottom surface 100b of the substrate 100, and the magnetic tunnel junction pattern MTJ and the spin-orbit torque line SOT are inserted between the bit line BL and the bottom surface 100b of the substrate 100.

[0093] The bit line contact BC may be provided in the lower interconnect layer BSI. Specifically, the bit line contact BC may be provided in the third lower insulating layer 30. The bit line contact BC may electrically connect the spin-orbit torque line SOT to the bit line BL.

[0094] Compared with a spin-transfer torque magnetic memory device (e.g., an STT-MRAM device), a spin-orbit torque magnetic memory device (e.g., an SOT-MRAM device) may have a high operation speed, and since the current paths in the read operation and the write operation are different from each other, data may be stably stored in the cell. However, for an SOT-MRAM device, when the number of terminals and transistors increases, the area of the cell may undesirably increase.

[0095] According to an embodiment of the inventive concept, by using two vertically stacked transistors and by forming a contact from the back surface of the substrate, the integration density of the magnetic memory device can be increased and the complexity of the interconnect structure can be reduced. That is, as referred to in Figure 3 and Figures 4A to 4EAs described above, by vertically stacking the lower source / drain pattern SD1 and the upper source / drain pattern SD2, the integration density of the magnetic memory device can be increased. Additionally, by forming the lower interconnect layer BSI on the bottom surface 100b of the substrate 100 and disposing the magnetic tunnel junction pattern MTJ and the spin-orbit torque line SOT in the lower interconnect layer BSI, the complexity of the interconnect structure can be reduced. In this case, the integration density of the SOT-MRAM device can be easily increased.

[0096] Figures 5A to 19B is a cross-sectional view showing an intermediate process in an exemplary method of manufacturing a magnetic memory device according to an embodiment of the inventive concept. Specifically, Figure 5A 、 Figure 6A 、 Figure 7A 、 Figure 8A 、 Figure 9A 、 Figure 10A 、 Figure 11A 、 Figure 12A 、 Figure 13A and Figure 14A is a cross-sectional view taken along line A-A' of Figure 3 . Figure 15A 、 Figure 16A 、 Figure 17A 、 Figure 18A and Figure 19A is a cross-sectional view taken along line B-B' of Figure 3 . Figure 7B 、 Figure 8B 、 Figure 9B 、 Figure 12B 、 Figure 13B 、 Figure 14B 、 Figure 15B 、 Figure 16B and Figure 17B is a cross-sectional view taken along line C-C' of Figure 3 . Figure 5B 、 Figure 6B 、 Figure 10B and Figure 11B is a cross-sectional view taken along line D-D' of Figure 3 . Figure 18B and Figure 19B is a cross-sectional view taken along line E-E' of Figure 3 .

[0097] Refer to Figure 5A and Figure 5B, the first sacrificial layer SAL1 and the first active layer ACL1 can be alternately stacked on the substrate 100 in a third direction D3. The first sacrificial layer SAL1 and the first active layer ACL1 can be formed of or include at least one of silicon (Si), germanium (Ge), and silicon germanium (SiGe), and can be formed of different materials from each other. For example, the first sacrificial layer SAL1 can be formed of or include silicon germanium (SiGe), and the first active layer ACL1 can be formed of or include silicon (Si).

[0098] A separation layer DSL can be formed on the uppermost one of the first sacrificial layers SAL1 in the first sacrificial layer SAL1. In an embodiment, the cross-sectional thickness of the separation layer DSL (i.e., the cross-sectional thickness in the third direction D3) can be substantially equal to the cross-sectional thickness of the first sacrificial layer SAL1.

[0099] The second sacrificial layer SAL2 and the second active layer ACL2 can be alternately stacked on the separation layer DSL in the third direction D3. Each of the second sacrificial layers SAL2 can be formed of or include the same material as the first sacrificial layer SAL1, and each of the second active layers ACL2 can be formed of or include the same material as the first active layer ACL1. The separation layer DSL can be inserted between the first sacrificial layer SAL1 and the second sacrificial layer SAL2.

[0100] A stacked pattern STP can be formed by patterning the stacked first sacrificial layer SAL1 and second sacrificial layer SAL2, first active layer ACL1 and second active layer ACL2, and separation layer DSL. The formation of the stacked pattern STP can include forming a hard mask pattern on the uppermost one of the second active layers ACL2, and using the hard mask pattern as an etching mask to sequentially etch the layers stacked on the substrate 100 (e.g., SAL1, SAL2, ACL1, ACL2, and DSL). During the formation of the stacked pattern STP, the upper part of the substrate 100 can be patterned to form a trench defining the active pattern AP. The stacked pattern STP can be a bar pattern extending in a second direction D2.

[0101] The stacked pattern STP can include a lower stacked pattern STP1 on the active pattern AP, an upper stacked pattern STP2 on the lower stacked pattern STP1, and a separation layer DSL between the lower stacked pattern STP1 and the upper stacked pattern STP2. The lower stacked pattern STP1 can include alternately stacked first sacrificial layers SAL1 and first active layers ACL1. The upper stacked pattern STP2 can include alternately stacked second sacrificial layers SAL2 and second active layers ACL2.

[0102] A device isolation layer ST can be formed on the substrate 100 to fill the trench. As used herein, the term "fill" (or a similar term) is intended to broadly refer to completely filling a defined space (e.g., a trench) or partially filling a defined space; that is, the defined space does not need to be completely filled, but can be, for example, partially filled or have voids or other spaces throughout the space. In an embodiment, the formation of the device isolation layer ST can include forming an insulating layer (not shown) on the substrate 100 to cover the active pattern AP and the stacked pattern STP, and recessing the insulating layer to expose the stacked pattern STP.

[0103] Referring Figure 6A and Figure 6B , a sacrificial pattern PP can be formed to cross the stacked pattern STP. The sacrificial pattern PP can be formed to have a linear shape extending along the first direction D1. In an embodiment, the formation of the sacrificial pattern PP can include forming a sacrificial layer (not shown) on the substrate 100, forming a hard mask pattern MP on the sacrificial layer, and etching the sacrificial layer using the hard mask pattern MP as an etching mask. The sacrificial layer can be formed of or include amorphous silicon and / or polysilicon.

[0104] Gate spacers GS can be formed on opposite side surfaces of the sacrificial pattern PP, respectively. In an embodiment, the formation of the gate spacers GS can include conformally forming a spacer layer (not shown) on the substrate 100 and performing an anisotropic etching process on the spacer layer. As used herein in the context of a material layer or a coating, the term "conformally" (or "conformal" or a similar term) is intended to broadly refer to a material layer or a coating having a substantially uniform cross-sectional thickness with respect to the profile of the surface on which the material layer is applied. The spacer layer can be formed of or include at least one of SiCN, SiCON, and SiN.

[0105] Referring Figure 7A and Figure 7B , recesses RS can be formed on opposite sides of the sacrificial pattern PP. In an embodiment, the recesses RS can be formed by performing an etching process on the stacked pattern STP using the gate spacers GS and the hard mask pattern MP as etching masks.

[0106] Liner layers LIN can be formed on opposite side surfaces of the upper stacked pattern STP2, respectively. In some embodiments, the liner layers LIN can be formed on the side surfaces of the separation layer DSL. The liner layers LIN can prevent the upper stacked pattern STP2 from being exposed to the recesses RS. The liner layers LIN can be formed to expose the lower stacked pattern STP1. In an embodiment, the liner layers LIN can be formed of or include silicon nitride.

[0107] ReferringFigure 8A and Figure 8B , lower source / drain patterns SD1 may be respectively formed in the recesses RS. Specifically, the exposed side surfaces of the lower stack pattern STP1 may be used as a seed layer to form the lower source / drain patterns SD1 through a first selective epitaxial growth (SEG) process. The first active layer ACL1 and the active pattern AP exposed through the recesses RS may be used as a seed layer to grow the lower source / drain patterns SD1. In an embodiment, the first SEG process may include a chemical vapor deposition (CVD) process or a molecular beam epitaxy (MBE) process.

[0108] In an embodiment, during the first SEG process, impurities may be in-situ implanted into the lower source / drain patterns SD1. In another embodiment, impurities may be implanted into the lower source / drain patterns SD1 after the lower source / drain patterns SD1 are formed. The lower source / drain patterns SD1 may be doped to have a first conductivity type.

[0109] The first active layer ACL1 inserted between the lower source / drain patterns SD1 may constitute the lower channel pattern CH1. That is, the first semiconductor pattern to the third semiconductor pattern SP1, SP2, and SP3 of the lower channel pattern CH1 may be formed by the first active layer ACL1. The lower channel pattern CH1 and the lower source / drain patterns SD1 may constitute the first active region AR1.

[0110] The side surfaces of the upper stack pattern STP2 may be covered with a liner layer LIN. That is, due to the liner layer LIN, during the first SEG process, the second active layer ACL2 of the upper stack pattern STP2 may not be exposed to the outside. Therefore, during the first SEG process, no additional semiconductor layer may be grown on the upper stack pattern STP2.

[0111] Referring to Figure 9A and Figure 9B , a first interlayer insulating layer 110 may be formed to cover the lower source / drain patterns SD1. With respect to the top surface of the substrate 100 as a reference layer, the top surface of the first interlayer insulating layer 110 may be recessed in the third direction D3 to a level lower than the bottom surface of the lowermost one of the second active layers ACL2 in the second active layer ACL2.

[0112] A part of the liner layer LIN exposed by the recesses RS may be removed. The remaining part of the liner layer LIN covered by the first interlayer insulating layer 110 may cover the side surfaces of the isolation layer DSL. Since the liner layer LIN is removed, the second active layer ACL2 may be exposed through the recesses RS.

[0113] Upper source / drain patterns SD2 may be respectively formed on opposite side surfaces of the upper stacked pattern STP2. Specifically, the side surfaces of the upper stacked pattern STP2 may be used as a seed layer to form the upper source / drain patterns SD2 through a second SEG process. The second active layer ACL2 exposed through the recess RS may be used as a seed layer to grow the upper source / drain patterns SD2. The upper source / drain patterns SD2 may be doped to have a second conductivity type different from the first conductivity type.

[0114] The second active layer ACL2 inserted between the upper source / drain patterns SD2 may constitute the upper channel pattern CH2. That is, the fourth to sixth semiconductor patterns SP4, SP5, and SP6 of the upper channel pattern CH2 may be respectively formed by the second active layer ACL2. The upper channel pattern CH2 and the upper source / drain patterns SD2 may constitute the second active region AR2.

[0115] A second interlayer insulating layer 120 may be formed on the first interlayer insulating layer 110 to cover the hard mask pattern MP, the gate spacer GS, and the upper source / drain patterns SD2.

[0116] The second interlayer insulating layer 120 may be planarized to expose the top surface of the sacrificial pattern PP. The planarization of the second interlayer insulating layer 120 may be performed using an etch-back process or a chemical mechanical polishing (CMP) process. During the planarization process, the hard mask pattern MP may be completely removed. As a result, the top surface of the second interlayer insulating layer 120 may be coplanar with the top surface of the sacrificial pattern PP and the top surface of the gate spacer GS.

[0117] Refer to Figure 10A and Figure 10B , the sacrificial pattern PP may be selectively removed. As a result of removing the sacrificial pattern PP, an external region ORG (e.g., a recess) may be formed to expose the lower channel pattern CH1 and the upper channel pattern CH2. In an embodiment, the formation of the external region ORG may be performed through a wet etching process using an etch solution capable of selectively etching the sacrificial pattern PP.

[0118] In an embodiment, the isolation layer DSL exposed through the external region ORG may be replaced with a pseudo-channel pattern DSP. In another embodiment, the isolation layer DSL may be left as it is, thereby forming the pseudo-channel pattern DSP.

[0119] The first to seventh internal regions IRG1 to IRG7 may be respectively formed by selectively removing the first sacrificial layer SAL1 and the second sacrificial layer SAL2 exposed through the external region ORG. Specifically, an etching process may be performed to leave the first to sixth semiconductor patterns SP1 to SP6 and the pseudo-channel pattern DSP, and selectively remove only the first sacrificial layer SAL1 and the second sacrificial layer SAL2.

[0120] Due to the selective removal of the first sacrificial layer SAL1 and the second sacrificial layer SAL2, the first semiconductor pattern to the third semiconductor patterns SP1, SP2, and SP3 can remain on the first active region AR1, and the fourth semiconductor pattern to the sixth semiconductor patterns SP4, SP5, and SP6 can remain on the second active region AR2. The pseudo-channel pattern DSP can remain between the third semiconductor pattern SP3 and the fourth semiconductor pattern SP4.

[0121] The empty space between the active pattern AP and the first semiconductor pattern SP1 can be defined as the first internal region IRG1, the empty space between the first semiconductor pattern SP1 and the second semiconductor pattern SP2 can be defined as the second internal region IRG2, the empty space between the second semiconductor pattern SP2 and the third semiconductor pattern SP3 can be defined as the third internal region IRG3, the empty space between the third semiconductor pattern SP3 and the pseudo-channel pattern DSP can be defined as the fourth internal region IRG4, the empty space between the pseudo-channel pattern DSP and the fourth semiconductor pattern SP4 can be defined as the fifth internal region IRG5, the empty space between the fourth semiconductor pattern SP4 and the fifth semiconductor pattern SP5 can be defined as the sixth internal region IRG6, and the empty space between the fifth semiconductor pattern SP5 and the sixth semiconductor pattern SP6 can be defined as the seventh internal region IRG7.

[0122] Referring to Figure 11A and Figure 11B ,, a gate insulating layer GI can be conformally formed on the exposed surfaces of the first semiconductor pattern to the sixth semiconductor patterns SP1 to SP6. A gate electrode GE can be formed on the gate insulating layer GI. The formation of the gate electrode GE can include forming a first portion PO1 to a seventh portion PO7 in the first internal region IRG1 to the seventh internal region IRG7, respectively, and forming an eighth portion PO8 in the external region ORG.

[0123] The gate electrode GE can be vertically recessed to have a reduced height. A gate capping pattern GP can be formed on the recessed gate electrode GE. A planarization process can be performed on the gate capping pattern GP such that the top surface of the gate capping pattern GP is coplanar with the top surface of the second interlayer insulating layer 120.

[0124] Referring to Figure 12A and Figure 12B ,, a first upper hole (i.e., an opening) UH1 and a second upper hole UH2 can be formed on opposite sides of the gate electrode GE. The first upper hole UH1 and the second upper hole UH2 can be spaced apart from each other in the second direction D2, and the gate electrode GE is inserted between the first upper hole UH1 and the second upper hole UH2.

[0125] The first upper hole UH1 may extend along a third direction D3 from the top surface of the second interlayer insulating layer 120 to the lower source / drain pattern SD1. The first upper hole UH1 may be formed to penetrate (i.e., extend into) a part of the second interlayer insulating layer 120, the upper source / drain pattern SD2, the first interlayer insulating layer 110, and the lower source / drain pattern SD1. The bottom surface of the first upper hole UH1 may be in the lower source / drain pattern SD1.

[0126] The second upper hole UH2 may extend from the top surface of the second interlayer insulating layer 120 to the upper source / drain pattern SD2. The second upper hole UH2 may be formed to penetrate a part of the second interlayer insulating layer 120 and the upper source / drain pattern SD2. The bottom surface of the second upper hole UH2 may be in the upper source / drain pattern SD2.

[0127] Referring to Figure 13A and Figure 13B and, a first upper contact 121, a first upper isolation structure 121s, a second upper contact 122, and a second upper isolation structure 122s may be formed.

[0128] In an embodiment, the formation of the first upper isolation structure 121s may include forming a first upper isolation layer (not shown) to conformally cover the inner surface and the bottom surface of the first upper hole UH1, and performing an anisotropic etching process to remove the portion of the first upper isolation layer covering the bottom surface of the first upper hole UH1. The first upper isolation structure 121s may conformally cover the inner surface of the first upper hole UH1. The first upper isolation structure 121s may not cover the bottom surface of the first upper hole UH1 and may expose the lower source / drain pattern SD1.

[0129] The first upper contact 121 may be formed in the remaining portion of the first upper hole UH1. In an embodiment, the formation of the first upper contact 121 may include forming a first upper layer (not shown) to fill the remaining portion of the first upper hole UH1 and recessing the first upper layer to expose the top surface of the second interlayer insulating layer 120. The bottom surface of the first upper contact 121 may contact the lower source / drain pattern SD1.

[0130] The second upper isolation structure 122s and the second upper contact 122 may be formed by a method substantially the same as that of the first upper isolation structure 121s and the first upper contact 121. However, in an embodiment, the second upper isolation structure 122s may not be formed. In this case, the second upper contact 122 may be formed to fill the entire second upper hole UH2. The bottom surface of the second upper contact 122 may contact the upper source / drain pattern SD2.

[0131] Referring to Figure 14A and Figure 14B, a third interlayer insulating layer 130 may be formed on the second interlayer insulating layer 120. Although not shown, a gate contact GC coupled to the gate electrode GE may be formed to penetrate the third interlayer insulating layer 130 and the gate capping pattern GP. Source contacts 135 respectively electrically connected to the first upper contact 121 and the second upper contact 122 may be formed in the third interlayer insulating layer 130.

[0132] A source line SL may be formed on the third interlayer insulating layer 130. In an embodiment, the formation of the source line SL may include forming a source line layer (not shown) and patterning the source line layer. The source line SL may extend in the second direction D2 to cross the gate electrode GE. The bottom surface of the source line SL may be in electrical contact with the top surface of the source contact 135.

[0133] Referring to Figure 15A and Figure 15B , a first lower insulating layer 10 may be formed on the bottom surface 100b of the substrate 100.

[0134] After forming the first lower insulating layer 10, a first lower hole (i.e., an opening) LH1 may be formed. The first lower hole LH1 may be formed on one side of the gate electrode GE. The first lower hole LH1 may extend in the third direction D3 from the bottom surface of the first lower insulating layer 10 to the lower source / drain pattern SD1. The first lower hole LH1 may be formed to penetrate (i.e., extend into) the first lower insulating layer 10, the substrate 100, and a part of the lower source / drain pattern SD1. The top surface of the first lower hole LH1 may be in the lower source / drain pattern SD1.

[0135] Referring to Figure 16A and Figure 16B , a first lower isolation structure 11s and a first lower contact 11 may be formed in the first lower hole LH1. In an embodiment, the formation of the first lower isolation structure 11s may include forming a first lower isolation layer (not shown) to conformally cover the inner surface and the top surface of the first lower hole LH1, and performing an anisotropic etching process to remove the portion of the first lower isolation layer covering the top surface of the first lower hole LH1. The first lower isolation structure 11s may be formed to conformally cover the inner surface of the first lower hole LH1. The first lower isolation structure 11s may not cover the top surface of the first lower hole LH1 and may expose the lower source / drain pattern SD1. However, in an embodiment, the formation of the first lower isolation structure 11s may be omitted.

[0136] A first lower contact 11 may be formed in a remaining portion of the first lower hole LH1. In an embodiment, the formation of the first lower contact 11 may include forming a first lower layer (not shown) to fill the remaining portion of the first lower hole LH1, and recessing the first lower layer to expose a bottom surface of the first lower insulating layer 10. A top surface of the first lower contact 11 may be in contact with the lower source / drain pattern SD1. However, according to an embodiment of the inventive concept, the first lower isolation structure 11s may not be formed, and in such a case, the first lower contact 11 may be formed to fill the entire first lower hole LH1.

[0137] Referring to Figure 17A and Figure 17B , a magnetic tunnel junction pattern MTJ may be formed. The magnetic tunnel junction pattern MTJ may be formed in a region vertically overlapping with the first lower contact 11 and may be in direct contact with a bottom surface of the first lower contact 11. In an embodiment, the formation of the magnetic tunnel junction pattern MTJ may include sequentially stacking a pinned magnetic layer (not shown), a tunnel barrier layer (not shown), and a free magnetic layer (not shown) on the first lower insulating layer 10, forming a mask pattern on the free magnetic layer, and anisotropically etching the free magnetic layer, the tunnel barrier layer, and the pinned magnetic layer sequentially using the mask pattern as an etch mask to expose the bottom surface of the first lower insulating layer 10 and removing the mask pattern.

[0138] A second lower insulating layer 20 may be formed to cover the first lower insulating layer 10 and the magnetic tunnel junction pattern MTJ. In an embodiment, the formation of the second lower insulating layer 20 may include forming an insulating layer (not shown) on the first lower insulating layer 10 and the magnetic tunnel junction pattern MTJ and planarizing the insulating layer to expose the magnetic tunnel junction pattern MTJ.

[0139] Referring to Figure 18A and Figure 18B , a second lower hole LH2 may be formed. The second lower hole LH2 may be spaced apart from the first lower contact 11 in a second direction D2, and a gate electrode GE may be inserted between the second lower hole LH2 and the first lower contact 11. The second lower hole LH2 may extend from the second lower insulating layer 20 to the upper source / drain pattern SD2 in a third direction D3. The second lower hole LH2 may be formed to penetrate (i.e., extend into) the second lower insulating layer 20, the first lower insulating layer 10, the substrate 100, the lower source / drain pattern SD1, the first interlayer insulating layer 110, and a part of the upper source / drain pattern SD2. A top surface of the second lower hole LH2 may be in the upper source / drain pattern SD2.

[0140] Referring to Figure 19A and Figure 19B, a second lower separation structure 12s and a second lower contact 12 can be formed. In an embodiment, the formation of the second lower separation structure 12s may include forming a second lower separation layer (not shown) to conformally cover the inner surface and the top surface of the second lower hole LH2, and performing an anisotropic etching process to remove a portion of the second lower separation layer covering the top surface of the second lower hole LH2. The second lower separation structure 12s may conformally cover the inner surface of the second lower hole LH2. The second lower separation structure 12s may not cover the top surface of the second lower hole LH2 and may expose the upper source / drain pattern SD2.

[0141] The second lower contact 12 can be formed in the remaining portion of the second lower hole LH2. In an embodiment, the formation of the second lower contact 12 may include forming a second lower layer (not shown) to fill the remaining portion of the second lower hole LH2, and recessing the second lower layer to expose the bottom surface of the second lower insulating layer 20. The top surface of the second lower contact 12 may contact the upper source / drain pattern SD2.

[0142] Returning to the reference Figure 3 and Figures 4A to 4E , a spin-orbit torque line SOT can be formed on the second lower insulating layer 20. The spin-orbit torque line SOT may contact the bottom surface of the magnetic tunnel junction pattern MTJ and the bottom surface of the second lower contact 12. In an embodiment, the formation of the spin-orbit torque line SOT may include forming a spin-orbit torque line layer (not shown) and patterning the spin-orbit torque line layer.

[0143] A third lower insulating layer 30 can be formed on the bottom surface of the second lower insulating layer 20 to cover the spin-orbit torque line SOT. A bit line contact BC and a bit line BL can be formed in the third lower insulating layer 30. A power delivery network layer PDN or an additional interconnect layer can be formed on the bottom surface of the bit line BL.

[0144] Figure 20A is a schematic circuit diagram showing a cell array of a magnetic memory device according to an embodiment of the inventive concept. Figure 20B is a plan view showing a magnetic memory device according to an embodiment of the inventive concept. Figure 21A and Figure 21B are cross-sectional views taken along lines C-C' and B-B' of Figure 20B , respectively. For simplicity of description, the previously described elements may be identified by the same reference numerals without repeating their overlapping descriptions.

[0145] Referring to Figure 20A and Figure 20B , the cell array may include a plurality of word lines WL, a plurality of bit lines BL, a plurality of source lines SL, and a plurality of memory cells MC.

[0146] Each of the memory cells MC may include a magnetic tunnel junction pattern MTJ, a spin orbit torque line SOT, an upper transistor TRa, and a lower transistor TRb. In Figure 20A and Figure 20B embodiments, the memory cells MCa of the even-numbered rows and the memory cells MCb of the odd-numbered rows may be arranged symmetrically when compared with the structures of Figure 1A and Figure 1B . In an embodiment, referring to Figure 20A and Figure 20B , the lower transistor TRb of the memory cells MCa of the even-numbered rows and the upper transistor TRa of the memory cells MCb of the odd-numbered rows may be commonly connected to the source line SL.

[0147] Referring to Figure 20B , Figure 21A and Figure 21B , the third active region AR3 may be spaced apart from the first active region AR1 in the first direction D1. The third active region AR3 may include a lower channel pattern CH1 and a lower source / drain pattern SD1. The lower channel pattern CH1 and the lower source / drain pattern SD1 of the third active region AR3 may have substantially the same characteristics as the lower channel pattern CH1 and the lower source / drain pattern SD1 of the first active region AR1.

[0148] The fourth active region AR4 may be stacked on the third active region AR3 in the third direction D3 and may be spaced apart from the second active region AR2 in the first direction D1. The fourth active region AR4 may include an upper channel pattern CH2 and an upper source / drain pattern SD2. The upper channel pattern CH2 and the upper source / drain pattern SD2 of the fourth active region AR4 may have substantially the same characteristics as the upper channel pattern CH2 and the upper source / drain pattern SD2 of the second active region AR2.

[0149] The gate electrode GE may be disposed on the lower channel pattern CH1 of the third active region AR3 and the upper channel pattern CH2 of the fourth active region AR4. The gate electrode GE may be the same as the gate electrode GE disposed on the lower channel pattern CH1 of the first active region AR1 and the upper channel pattern CH2 of the second active region AR2. The gate electrode GE may correspond to Figure 20B the word line WL. The gate electrode GE may extend in the first direction D1 to cross the vertically stacked first active region AR1 and second active region AR2 and the vertically stacked third active region AR3 and fourth active region AR4.

[0150] The first interlayer insulating layer 110 may be disposed on the substrate 100. The first interlayer insulating layer 110 may cover the lower source / drain pattern SD1 of the first active region AR1 and the third active region AR3.

[0151] The second interlayer insulating layer 120 may be disposed on the first interlayer insulating layer 110. The second interlayer insulating layer 120 may cover the upper source / drain patterns SD2 of the second active region AR2 and the fourth active region AR4.

[0152] Although not shown, a first upper contact 121 and a first upper isolation structure 121s, which are respectively connected to the lower source / drain pattern SD1 of the first active region AR1 and the third active region AR3, may extend in a third direction D3 into the second interlayer insulating layer 120, the upper source / drain patterns SD2 of the second active region AR2 and the fourth active region AR4, and a part of the first interlayer insulating layer 110.

[0153] A second upper contact 122 and a second upper isolation structure 122s, which are respectively electrically connected to the upper source / drain patterns SD2 of the second active region AR2 and the fourth active region AR4, may extend in the third direction D3 into a part of the second interlayer insulating layer 120. However, in an embodiment, the second upper isolation structure 122s may not be provided.

[0154] The first upper contact 121 and the second upper contact 122, and the first upper isolation structure 121s and the second upper isolation structure 122s may be configured to have substantially the same features as those in the Figure 3 and Figures 4A to 4E embodiment.

[0155] The third interlayer insulating layer 130 may be disposed on the second interlayer insulating layer 120. Source contacts 135, which are respectively connected to the first upper contact 121 and the second upper contact 122, may be disposed in the third interlayer insulating layer 130.

[0156] A source line SL extending in a second direction D2 may be disposed on the third interlayer insulating layer 130. The source line SL may extend in the second direction D2 and may be commonly connected to the source contacts 135. When observed in a plan view, the source line SL may vertically overlap with a part of the first active region AR1 and a part of the second active region AR2, and may vertically overlap with a part of the third active region AR3 and a part of the fourth active region AR4.

[0157] The first lower insulating layer 10 may be disposed on the bottom surface 100b of the substrate 100. The first lower contacts 11 of the lower source / drain pattern SD1 electrically connected to the first active region AR1 and the third active region AR3, respectively, may extend into the first lower insulating layer 10 and the substrate 100 in the third direction D3. Each of the first lower contacts 11 may extend from the bottom surface of the first lower insulating layer 10 in the third direction D3 to penetrate the first lower insulating layer 10, the substrate 100, and a part of the lower source / drain pattern SD1. The top surfaces of the first lower contacts 11 may be in the lower source / drain pattern SD1, respectively. The first lower isolation structure 11s may extend around the first lower contacts 11. However, in an embodiment, different from the illustrated structure, the first lower isolation structure 11s may not exist. The first lower contacts 11 may selectively electrically connect to the lower source / drain pattern SD1 of the first active region AR1 and the third active region AR3, respectively.

[0158] The second lower insulating layer 20 may be disposed on the first lower insulating layer 10. The magnetic tunnel junction pattern MTJ may be disposed in the second lower insulating layer 20. The magnetic tunnel junction pattern MTJ may contact and connect to the first lower contacts 11, which are connected to the first active region AR1 and the third active region AR3, respectively. When observed in a plan view, the magnetic tunnel junction pattern MTJ may vertically overlap with the first lower contacts 11, respectively. The magnetic tunnel junction pattern MTJ may be configured to have substantially the same characteristics as the magnetic tunnel junction pattern MTJ described with reference to Figure 3 and Figures 4A to 4E . The magnetic tunnel junction pattern MTJ may be electrically connected to the lower source / drain pattern SD1 of the first active region AR1 and the third active region AR3, respectively, through the first lower contacts 11.

[0159] Although not shown, the second lower contacts 12 of the upper source / drain pattern SD2 connected to the second active region AR2 and the fourth active region AR4, respectively, may extend into the second lower insulating layer 20 in the third direction D3. The second lower contacts 12 may be configured to have substantially the same characteristics as the second lower contacts 12 described with reference to Figure 3 and Figures 4A to 4E .

[0160] The spin-orbit torque line SOT may be disposed on the second lower insulating layer 20. The spin-orbit torque line SOT may contact and connect to the magnetic tunnel junction pattern MTJ and the second lower contacts 12, which are connected to the second active region AR2 and the fourth active region AR4, respectively. The spin-orbit torque line SOT may be electrically connected to the upper source / drain pattern SD2 of the second active region AR2 and the fourth active region AR4, respectively, through the second lower contacts 12.

[0161] The third lower insulating layer 30 may be disposed on the second lower insulating layer 20. The bit line BL may be disposed in the third lower insulating layer 30. The power delivery network layer PDN or an additional interconnect layer may be disposed on the third lower insulating layer 30. The third lower insulating layer 30, the bit line BL, and the power delivery network layer PDN (or the additional interconnect layer) may be configured to have substantially the same features as those in the embodiments Figure 3 and Figures 4A to 4E described.

[0162] In Figure 20A , Figure 20B , Figure 21A and Figure 21B embodiments, the source line SL may be commonly connected to adjacent memory cells in the memory cell MC. That is, by increasing the area of the source line SL, the resistance of the source line SL can be reduced. Figure 22 is a plan view showing a magnetic memory device according to an embodiment of the inventive concept. Figure 23A and Figure 23B are cross-sectional views taken along lines A-A' and B-B' of Figure 22 , respectively. For simplicity of description, the previously described elements may be identified by the same reference numerals without repeating their overlapping descriptions.

[0163] Referring to Figure 22 , Figure 23A and Figure 23B , an interlayer interconnect layer including the interlayer interconnect line 101 and the interlayer interconnect contact 102 may be disposed in the first lower insulating layer 10. Specifically, the interlayer interconnect line 101 and the interlayer interconnect contact 102 may be disposed between the first lower contact 11 and the magnetic tunnel junction pattern MTJ. The first lower contact 11 and the interlayer interconnect line 101 may be in contact with each other and connected to each other. The interlayer interconnect line 101 and the interlayer interconnect contact 102 may be in contact with each other and connected to each other. The interlayer interconnect contact 102 and the magnetic tunnel junction pattern MTJ may be in contact with each other and connected to each other. That is, the magnetic tunnel junction pattern MTJ may be connected to the first lower contact 11 through the interlayer interconnect contact 102 and the interlayer interconnect line 101.

[0164] The magnetic tunnel junction pattern MTJ may not vertically overlap with the first lower contact 11. That is, the magnetic tunnel junction pattern MTJ may not be directly connected to or in direct contact with the first lower contact 11. This is because the magnetic tunnel junction pattern MTJ is connected to the first lower contact 11 through the interlayer interconnect contact 102 and the interlayer interconnect line 101. Therefore, the magnetic tunnel junction pattern MTJ may be present in a region where the spin orbit torque line SOT and the interlayer interconnect layer vertically overlap each other.

[0165] The interlayer interconnect line 101 and the interlayer interconnect contact 102 may be formed of at least one of a metallic material (e.g., tungsten, titanium, tantalum, and cobalt) and / or a conductive metal nitride (e.g., titanium nitride, tantalum nitride, and tungsten nitride), or include at least one of a metallic material (e.g., tungsten, titanium, tantalum, and cobalt) and / or a conductive metal nitride (e.g., titanium nitride, tantalum nitride, and tungsten nitride), but embodiments are not limited thereto.

[0166] In Figure 22 , Figure 23A and Figure 23B embodiments, since the interlayer interconnect layer includes the interlayer interconnect line 101 and the interlayer interconnect contact 102, the degree of freedom in the position of the magnetic tunnel junction pattern MTJ can be increased. That is, different from the embodiments of Figure 3 and Figures 4A to 4E , the magnetic tunnel junction pattern MTJ may exist in a region that does not vertically overlap with the first lower contact 11.

[0167] Figure 24A is a plan view showing a magnetic memory device according to an embodiment of the inventive concept. Figure 24B is a plan view showing Figure 24A a part of the spin-orbit torque line. Figure 25A and Figure 25B are cross-sectional views taken along lines A-A' and B-B' of Figure 24A , respectively. For simplicity of description, previously described elements may be identified by the same reference numerals without repeating their overlapping descriptions.

[0168] Referring to Figure 24A and Figure 24B , the spin-orbit torque line SOT may extend to a region that vertically overlaps with the source line SL. Specifically, the spin-orbit torque line SOT may include a first portion SOTa extending in a first direction D1 and a second direction D2 (i.e., parallel to the upper surface of the substrate 100). The first portion SOTa of the spin-orbit torque line SOT may have a first surface s1 and a second surface s2 that face each other in the first direction D1. The spin-orbit torque line SOT may include a second portion SOTb extending from opposite ends of the second surface s2 in the first direction D1. When observed in a plan view, the first portion SOTa of the spin-orbit torque line SOT may vertically overlap with a part of the source line SL, and the second portion SOTb may vertically overlap with a part of the bit line BL.

[0169] Referring to Figure 24A , Figure 25A and Figure 25B, an interlayer interconnect layer including an interlayer interconnect line 101 and an interlayer interconnect contact 102 may be disposed in the first lower insulating layer 10. The interlayer interconnect contact 102 may be disposed in a region not vertically overlapping with the first lower contact 11. The interlayer interconnect line 101 may contact both the interlayer interconnect contact 102 and the first lower contact 11. Here, the interlayer interconnect line 101 may extend in a first direction D1 and a second direction D2 to contact both the interlayer interconnect contact 102 and the first lower contact 11. In an embodiment, when observed in a plan view, the interlayer interconnect line 101 may have a rectangular shape or the shape of the letter "L".

[0170] The magnetic tunnel junction pattern MTJ may not be vertically overlapped with the first lower contact 11. The magnetic tunnel junction pattern MJT may contact the spin-orbit torque line SOT. The magnetic tunnel junction pattern MTJ may contact and connect to the interlayer interconnect contact 102. In an embodiment, the magnetic tunnel junction pattern MTJ may be disposed in a region contacting both the spin-orbit torque line SOT and the interlayer interconnect contact 102.

[0171] The second part SOTb of the spin-orbit torque line SOT may contact and connect to the bit line contact BC and the second lower contact 12, respectively. In an embodiment, although not shown, the spin-orbit torque line SOT may have a rectangular shape extending in the first direction D1 and the second direction D2.

[0172] In Figure 24A , Figure 25A and Figure 25B 's embodiments, due to the structures of the lower interconnect layer BSI and the spin-orbit torque line SOT, the degree of freedom in arranging the magnetic tunnel junction pattern MTJ can be increased. That is, the magnetic tunnel junction pattern MTJ may not be directly connected to or in direct contact with the first lower contact 11. This is because the magnetic tunnel junction pattern MTJ is connected to the first lower contact 11 through the interlayer interconnect contact 102 and the interlayer interconnect line 101. In addition, due to the shape of the spin-orbit torque line SOT, the degree of freedom in arranging the magnetic tunnel junction pattern MTJ can be increased. Therefore, a magnetic memory device can be easily manufactured.

[0173] Figure 26 is a plan view showing a magnetic memory device according to an embodiment of the inventive concept. Figure 27A and Figure 27B are cross-sectional views taken along lines A-A' and B-B' of Figure 26 respectively. For simplicity of description, the previously described elements may be identified by the same reference numerals without repeating their overlapping descriptions.

[0174] Referring to Figure 26 , Figure 27A and Figure 27B, the third active region AR3 may be spaced apart from the first active region AR1 in the second direction D2. The third active region AR3 may include a lower channel pattern CH1 and a lower source / drain pattern SD1. The lower channel pattern CH1 and the lower source / drain pattern SD1 of the third active region AR3 may have substantially the same characteristics as the lower channel pattern CH1 and the lower source / drain pattern SD1 of the first active region AR1.

[0175] The fourth active region AR4 may be stacked on the third active region AR3 in the third direction D3 and may be spaced apart from the second active region AR2 in the second direction D2. The fourth active region AR4 may include an upper channel pattern CH2 and an upper source / drain pattern SD2. The upper channel pattern CH2 and the upper source / drain pattern SD2 of the fourth active region AR4 may have substantially the same characteristics as the upper channel pattern CH2 and the upper source / drain pattern SD2 of the second active region AR2.

[0176] The first gate electrode GE1 may be disposed on the lower channel pattern CH1 of the first active region AR1 and the upper channel pattern CH2 of the second active region AR2. The second gate electrode GE2 may be disposed on the lower channel pattern CH1 of the third active region AR3 and the upper channel pattern CH2 of the fourth active region AR4. The first gate electrode GE1 and the second gate electrode GE2 may have substantially the same characteristics as the gate electrode GE described with reference to Figure 3 and Figures 4A to 4E . The first gate electrode GE1 may correspond to Figure 26 's first word line WL1. The second gate electrode GE2 may correspond to Figure 26 's second word line WL2. The first gate electrode GE1 and the second gate electrode GE2 may extend in the first direction D1 to cross the bit line BL and the source line SL.

[0177] The first interlayer insulating layer 110 may be disposed on the substrate 100. The first interlayer insulating layer 110 may cover the lower source / drain pattern SD1 of the first active region AR1 and the third active region AR3.

[0178] The second interlayer insulating layer 120 may be disposed on the first interlayer insulating layer 110. The second interlayer insulating layer 120 may cover the upper source / drain pattern SD2 of the second active region AR2 and the fourth active region AR4.

[0179] The third interlayer insulating layer 130 may be disposed on the second interlayer insulating layer 120. The fourth interlayer insulating layer 140 may be disposed on the third interlayer insulating layer 130. The fifth interlayer insulating layer 150 may be disposed on the fourth interlayer insulating layer 140. The upper source line SLt and the upper bit line BLt may be disposed on the fifth interlayer insulating layer 150. The upper source line SLt and the upper bit line BLt may be spaced apart from each other in the first direction D1 and may be bar-shaped patterns extending in the second direction D2.

[0180] The first upper active contact 142 may be disposed in the fourth interlayer insulating layer 140 and may be connected to the upper source / drain pattern SD2 of the second active region AR2. Refer to Figure 26 , the first upper active contact 142 may be disposed on one side of the first word line WL1. Specifically, the first upper active contact 142 may extend from the top surface of the fourth interlayer insulating layer 140 in the third direction D3 into a part of the fourth interlayer insulating layer 140, the third interlayer insulating layer 130, the second interlayer insulating layer 120, and the upper source / drain pattern SD2 of the second active region AR2. The bottom surface of the first upper active contact 142 may be in the upper source / drain pattern SD2 of the second active region AR2.

[0181] The first upper active isolation structure 142s may extend around the first upper active contact 142. However, in an embodiment, different from the structure shown, the first upper active isolation structure 142s may be omitted. The first upper active contact 142 may be selectively electrically connected to the upper source / drain pattern SD2 of the second active region AR2.

[0182] The second upper active contact 152 may be disposed in the fifth interlayer insulating layer 150 and may be electrically connected to the upper source / drain pattern SD2 of the second active region AR2. Refer to Figure 26 , the second upper active contact 152 may be disposed on the opposite side of the first word line WL1 where the first upper active contact 142 is not disposed. When observed in a plan view, the first word line WL1 may extend in the first direction D1 between the first upper active contact 142 and the second upper active contact 152. Specifically, the second upper active contact 152 may extend from the top surface of the fifth interlayer insulating layer 150 in the third direction D3 into a part of the fifth interlayer insulating layer 150, the fourth interlayer insulating layer 140, the third interlayer insulating layer 130, the second interlayer insulating layer 120, and the upper source / drain pattern SD2 of the second active region AR2. The bottom surface of the second upper active contact 152 may be in the upper source / drain pattern SD2 of the second active region AR2.

[0183] The second upper active isolation structure 152s may extend around the second upper active contact 152. However, in an embodiment, different from the structure shown, the second upper active isolation structure 152s may be omitted. The second upper active contact 152 may be selectively electrically connected to the upper source / drain pattern SD2 of the second active region AR2.

[0184] The third upper active contact 162 may be disposed in the third interlayer insulating layer 130 and may be electrically connected to the upper source / drain pattern SD2 of the fourth active region AR4. The third upper active contact 162 may be disposed on one side of the second word line WL2. Specifically, the third upper active contact 162 may extend in the third direction D3 from the top surface of the third interlayer insulating layer 130 into a part of the third interlayer insulating layer 130, the second interlayer insulating layer 120, and the upper source / drain pattern SD2 of the fourth active region AR4. The bottom surface of the third upper active contact 162 may be in the upper source / drain pattern SD2 of the fourth active region AR4.

[0185] The third upper active isolation structure 162s may extend around the third upper active contact 162. However, in an embodiment, different from the structure shown, the third upper active isolation structure 162s may be omitted. The third upper active contact 162 may be selectively electrically connected to the upper source / drain pattern SD2 of the fourth active region AR4.

[0186] The fourth upper active contact 172 may be disposed in the fifth interlayer insulating layer 150 and may be electrically connected to the upper source / drain pattern SD2 of the fourth active region AR4. The fourth upper active contact 172 may be disposed on the opposite side of the second word line WL2 where the third upper active contact 162 is not disposed. When observed in a plan view, the second word line WL2 may extend in the first direction D1 between the third upper active contact 162 and the fourth upper active contact 172. Specifically, the fourth upper active contact 172 may extend in the third direction D3 from the top surface of the fifth interlayer insulating layer 150 into a part of the fifth interlayer insulating layer 150, the fourth interlayer insulating layer 140, the third interlayer insulating layer 130, the second interlayer insulating layer 120, and the upper source / drain pattern SD2 of the fourth active region AR4. The bottom surface of the fourth upper active contact 172 may be in the upper source / drain pattern SD2 of the fourth active region AR4.

[0187] The fourth upper active isolation structure 172s may extend around the fourth upper active contact 172. However, in an embodiment, different from the structure shown, the fourth upper active isolation structure 172s may be omitted. The fourth upper active contact 172 may be selectively electrically connected to the upper source / drain pattern SD2 of the fourth active region AR4.

[0188] The first through fourth upper active contacts 142, 152, 162, and 172 may include a doped semiconductor material and / or a metal material. The metal material may be selected from the group consisting of copper (Cu), aluminum (Al), ruthenium (Ru), cobalt (Co), tungsten (W), and molybdenum (Mo), but embodiments are not limited thereto. The first through fourth upper active isolation structures 142s, 152s, 162s, and 172s may be formed of or include at least one of a silicon-based insulating material (e.g., silicon oxide and silicon nitride).

[0189] The magnetic tunnel junction pattern MTJ may be disposed in the fourth interlayer insulating layer 140. The magnetic tunnel junction pattern MTJ may be configured to have substantially the same characteristics as the magnetic tunnel junction pattern MTJ described with reference to Figure 3 and Figures 4A to 4E The magnetic tunnel junction pattern MTJ may not vertically overlap the third upper active contact 162.

[0190] The upper interconnect line 131t and the upper interconnect contact 132t may be disposed in the fourth interlayer insulating layer 140. Specifically, the upper interconnect line 131t and the upper interconnect contact 132t may be disposed between the magnetic tunnel junction pattern MTJ and the third upper active contact 162. The upper interconnect line 131t may contact the third upper active contact 162 and the upper interconnect contact 132t. The upper interconnect contact 132t may contact the magnetic tunnel junction pattern MTJ. In an embodiment, the magnetic tunnel junction pattern MTJ may be connected to the upper source / drain pattern SD2 of the fourth active region AR4 through the upper interconnect contact 132t, the upper interconnect line 131t, and the third upper active contact 162. When viewed in a plan view, the upper interconnect line 131t may have a rectangular shape or the shape of the letter "L".

[0191] The spin orbit torque line SOT may be disposed on the fourth interlayer insulating layer 140. The spin orbit torque line SOT may contact the magnetic tunnel junction pattern MTJ and the first upper active contact 142. The spin orbit torque line SOT may be a bar pattern extending in the second direction D2.

[0192] The bit line contact BC may be disposed in the fifth interlayer insulating layer 150 to electrically connect the spin orbit torque line SOT to the upper bit line BLt. The second upper active contact 152 and the fourth upper active contact 172 may contact the upper source line SLt.

[0193] The lower interconnect layer BSI can be disposed on the bottom surface 100b of the substrate 100. In an embodiment, the lower interconnect layer BSI can include a first lower insulating layer 10, a second lower insulating layer 20, and a third lower insulating layer 30 sequentially stacked on the bottom surface 100b of the substrate 100. The lower bit line BLd and the lower source line SLd can be disposed on the bottom surface of the third lower insulating layer 30. The lower bit line BLd and the lower source line SLd can be spaced apart from each other in a first direction D1 and can be strip-shaped patterns extending in a second direction D2. The power delivery network layer PDN or an additional interconnect layer can be disposed on the bottom surface of the lower interconnect layer BSI.

[0194] The first lower active contact 21 can be disposed in the second lower insulating layer 20 and can be connected to the lower source / drain pattern SD1 of the first active region AR1. The first lower active contact 21 can be disposed on one side of the first word line WL1. Specifically, the first lower active contact 21 can extend from the bottom surface of the second lower insulating layer 20 in a third direction D3 into a portion of the second lower insulating layer 20, the first lower insulating layer 10, the substrate 100, and the lower source / drain pattern SD1 of the first active region AR1. The top surface of the first lower active contact 21 can be in the lower source / drain pattern SD1 of the first active region AR1.

[0195] The first lower active isolation structure 21s can extend around the first lower active contact 21. However, in an embodiment, different from the illustrated structure, the first lower active isolation structure 21s can be omitted. The first lower active contact 21 can be selectively electrically connected to the lower source / drain pattern SD1 of the first active region AR1.

[0196] The second lower active contact 31 can be disposed in the third lower insulating layer 30 and can be electrically connected to the lower source / drain pattern SD1 of the first active region AR1. The second lower active contact 31 can be disposed on the opposite side of the first word line WL1 where the first lower active contact 21 is not disposed. Specifically, the second lower active contact 31 can extend from the bottom surface of the third lower insulating layer 30 in a third direction D3 into a portion of the third lower insulating layer 30, the second lower insulating layer 20, the first lower insulating layer 10, the substrate 100, and the lower source / drain pattern SD1 of the first active region AR1. The top surface of the second lower active contact 31 can be in the lower source / drain pattern SD1 of the first active region AR1.

[0197] The second lower active isolation structure 31s can extend around the second lower active contact 31. However, different from the illustrated structure, the second lower active isolation structure 31s can be omitted. The second lower active contact 31 can be selectively electrically connected to the lower source / drain pattern SD1 of the first active region AR1.

[0198] The third lower active contact 41 may extend from the bottom surface 100b of the substrate 100 in a third direction D3 and may be connected to the lower source / drain pattern SD1 of the third active region AR3. The third lower active contact 41 may be disposed on one side of the second word line WL2. Specifically, the third lower active contact 41 may extend from the bottom surface 100b of the substrate 100 in the third direction D3 into a part of the substrate 100 and the lower source / drain pattern SD1 of the third active region AR3. The top surface of the third lower active contact 41 may be in the lower source / drain pattern SD1 of the third active region AR3.

[0199] The third lower active isolation structure 41s may extend around the third lower active contact 41. However, in an embodiment, the third lower active isolation structure 41s may be omitted, different from the shown structure. The third lower active contact 41 may be selectively electrically connected to the lower source / drain pattern SD1 of the third active region AR3.

[0200] The fourth lower active contact 51 may be disposed in the third lower insulating layer 30 and may be electrically connected to the lower source / drain pattern SD1 of the third active region AR3. The fourth lower active contact 51 may be disposed on the opposite side of the second word line WL2 where the third lower active contact 41 is not disposed. Specifically, the fourth lower active contact 51 may extend in the third direction D3 from the bottom surface of the third lower insulating layer 30 into a part of the third lower insulating layer 30, the second lower insulating layer 20, the first lower insulating layer 10, the substrate 100, and the lower source / drain pattern SD1 of the third active region AR3. The top surface of the fourth lower active contact 51 may be in the lower source / drain pattern SD1 of the third active region AR3.

[0201] The fourth lower active isolation structure 51s may extend around the fourth lower active contact 51. However, in an embodiment, the fourth lower active isolation structure 51s may be omitted, different from the shown structure. The fourth lower active contact 51 may be selectively electrically connected to the lower source / drain pattern SD1 of the third active region AR3.

[0202] The first lower active contact to the fourth lower active contact 21, 31, 41, and 51 may be formed of or include a doped semiconductor material and / or a metal material. The metal material may be selected from the group consisting of copper (Cu), aluminum (Al), ruthenium (Ru), cobalt (Co), tungsten (W), and molybdenum (Mo). The first lower active isolation structure to the fourth lower active isolation structure 21s, 31s, 41s, and 51s may be formed of or include at least one silicon-based insulating material (e.g., silicon oxide and silicon nitride).

[0203] The magnetic tunnel junction pattern MTJ may be disposed in the second lower insulating layer 20. The magnetic tunnel junction pattern MTJ may be configured to have substantially the same characteristics as the magnetic tunnel junction pattern MTJ described with reference to Figure 3 and Figures 4A to 4E The magnetic tunnel junction pattern MTJ may not vertically overlap with the third lower active contact 41.

[0204] The lower interconnect line 131d and the lower interconnect contact 132d may be disposed in the first lower insulating layer 10. Specifically, the lower interconnect line 131d and the lower interconnect contact 132d may be disposed between the magnetic tunnel junction pattern MTJ and the third lower active contact 41. The lower interconnect line 131d may contact the third lower active contact 41 and the lower interconnect contact 132d. The lower interconnect contact 132d may contact the magnetic tunnel junction pattern MTJ. For example, the magnetic tunnel junction pattern MTJ may be connected to the lower source / drain pattern SD1 of the third active region AR3 through the lower interconnect contact 132d, the lower interconnect line 131d, and the third lower active contact 41. When observed in a plan view, the lower interconnect line 131d may have a rectangular shape or the shape of the letter "L".

[0205] The spin-orbit torque line SOT may be disposed in the third lower insulating layer 30. The spin-orbit torque line SOT may contact the magnetic tunnel junction pattern MTJ and the first lower active contact 21. The spin-orbit torque line SOT may be a bar pattern extending in the second direction D2.

[0206] The bit line contact BC may be disposed in the third lower insulating layer 30 to electrically connect the spin-orbit torque line SOT to the lower bit line BLd. The second lower active contact 31 and the fourth lower active contact 51 may be in electrical contact with the lower source line SLd.

[0207] In the embodiments of Figure 26 , Figure 27A and Figure 27B , the first upper active contact to the fourth upper active contacts 142, 152, 162, and 172 may be electrically connected to the upper source / drain pattern SD2 of the second active region AR2 and the fourth active region AR4 serving as upper transistors. In addition, the first lower active contact to the fourth lower active contacts 21, 31, 41, and 51 may be electrically connected to the lower source / drain pattern SD1 of the first active region AR1 and the third active region AR3 serving as lower transistors. Therefore, the degree of freedom of the interconnect structure may be increased. In addition, with the upper interconnect line 131t and the lower interconnect line 131d and the upper interconnect contact 132t and the lower interconnect contact 132d, the degree of freedom of placing the magnetic tunnel junction pattern MTJ may be increased.

[0208] Figure 28A is a circuit diagram schematically showing a memory cell of a magnetic memory device according to an embodiment of the inventive concept.Figure 28B is a plan view showing Figure 28A a magnetic memory device. Figure 29A and Figure 29B are cross-sectional views taken along Figure 28B lines A-A' and B-B' respectively. For simplicity of description, previously described elements may be identified by the same reference numerals without repeating their overlapping description.

[0209] Referring to Figure 28A , the upper transistor TRa of the memory cell MC may be electrically connected to the upper word line WLa (e.g., the gate terminal of the upper transistor TRa may be connected to the upper word line WLa). The lower transistor TRb of the memory cell MC may be electrically connected to the lower word line WLb. For example, different from the above embodiment, the gate may be provided with a separated structure.

[0210] The lower gate electrode LGE may extend into the substrate 100 in the third direction D3. Specifically, the lower gate electrode LGE may be disposed on the lower channel pattern CH1 of the first active region AR1. The lower gate electrode LGE may include a first portion PO1 inserted between the active pattern AP and the first semiconductor pattern SP1, a second portion PO2 inserted between the first semiconductor pattern SP1 and the second semiconductor pattern SP2, a third portion PO3 inserted between the second semiconductor pattern SP2 and the third semiconductor pattern SP3, and a fourth portion PO4 inserted between the third semiconductor pattern SP3 and the pseudo-channel pattern DSP, and may further include a buried portion PO0 extending into the substrate 100.

[0211] The upper gate electrode UGE may be disposed on the upper channel pattern CH2. The upper gate electrode UGE may be configured to have substantially the same features as the upper gate electrode UGE described with reference to Figure 3 and Figures 4A to 4E .

[0212] The upper gate electrode UGE may correspond to Figure 28A the upper word line WLa. The lower gate electrode LGE may correspond to Figure 28A the lower word line WLb.

[0213] In the embodiments of Figure 28A , Figure 28B , Figure 29A and Figure 29B , since the upper transistor and the lower transistor are separated from each other, the degree of freedom of the method of the operation unit can be increased. In addition, both the lower transistor and the upper transistor may be NMOSFETs, and in this case, the unit may be operated at an increased operation speed.

[0214] According to an embodiment of the inventive concept, a lower source / drain pattern and an upper source / drain pattern may be vertically stacked to respectively form a lower transistor and an upper transistor. Accordingly, an integration density of a magnetic memory device may be increased.

[0215] In addition, by placing a magnetic tunnel junction pattern and a spin orbit torque line on a rear surface of a substrate, complexity of an interconnection structure may be reduced.

[0216] Furthermore, an interlayer interconnection layer may be used to increase a degree of freedom in setting a magnetic tunnel junction pattern.

[0217] Although example embodiments of the inventive concept have been specifically shown and described, those of ordinary skill in the art will understand that changes in form and detail may be made therein without departing from the spirit and scope of the appended claims.

Claims

1. A magnetic memory device, comprising: a substrate having a top surface and a bottom surface opposite to each other; a first active region on a top surface of the substrate, the first active region comprising a lower channel pattern and a lower source / drain pattern connected to the lower channel pattern; a second active region stacked on the first active region in a third direction perpendicular to the top surface of the substrate, the second active region comprising an upper channel pattern and an upper source / drain pattern connected to the upper channel pattern; a gate electrode disposed on the lower channel pattern and the upper channel pattern and extending in a first direction parallel to a top surface of the substrate; a lower interconnect layer on the bottom surface of the substrate; a magnetic tunnel junction pattern and a spin-orbit torque line, the magnetic tunnel junction pattern and the spin-orbit torque line being located in the lower interconnect layer; a first lower contact extending into a portion of the lower interconnect layer and the substrate and connecting the lower source / drain pattern to the magnetic tunnel junction pattern; as well as A second lower contact extends into a portion of the lower interconnect layer, the substrate, and the lower source / drain pattern, and connects the upper source / drain pattern to the spin-orbit torque line.

2. The magnetic memory device according to claim 1, further comprising a lower separation structure extending around a side surface of the second lower contact; in, The second lower contact is electrically separated from the lower source / drain pattern by the lower separation structure.

3. The magnetic memory device according to claim 1, wherein: The spin-orbit torque lines have a stripe pattern extending in a second direction parallel to the top surface of the substrate and crossing the first direction, Wherein, the magnetic storage device further comprises: a bit line in the lower interconnect layer and extending in the second direction; and A bit line contact electrically connects the bit line to the spin-orbit torque line.

4. The magnetic memory device according to claim 1, further comprising: a first interlayer insulating layer on the lower source / drain pattern; a second interlayer insulating layer on the first interlayer insulating layer and the upper source / drain pattern; a first upper contact extending into the second interlayer insulating layer, the upper source / drain pattern, and a portion of the first interlayer insulating layer and electrically connected to the lower source / drain pattern; as well as A second upper contact extends into a portion of the second interlayer insulating layer and is electrically connected to the upper source / drain pattern.

5. The magnetic memory device according to claim 4, further comprising: a third interlayer insulating layer, which is on the second interlayer insulating layer; a source line on the third interlayer insulating layer and extending in the second direction; as well as Source contacts electrically connect the source line to the first upper contact and the second upper contact, respectively.

6. The magnetic memory device according to claim 4, further comprising an upper separation structure extending around a side surface of the first upper contact, in, The first upper contact is electrically separated from the upper source / drain pattern by the upper separation structure.

7. The magnetic memory device according to claim 1, wherein: The magnetic tunnel junction pattern contacts the spin-orbit torque line and at least partially overlaps the first lower contact in the third direction. 8 . The magnetic memory device of claim 1 , further comprising an interlayer interconnection line and an interlayer interconnection contact between the magnetic tunnel junction pattern and the first lower contact.

9. The magnetic memory device according to claim 8, wherein: The magnetic tunnel junction pattern does not overlap the first lower contact in the third direction.

10. The magnetic memory device according to claim 9, wherein: The spin-orbit torque line comprises: a first portion extending in the second direction and having a first surface and a second surface opposite to each other in the first direction; and A second portion extends from a second surface of the first portion in the first direction.

11. The magnetic memory device according to claim 1 , further comprising: a third active region spaced apart from the first active region in the first direction, the third active region including the lower channel pattern and the lower source / drain pattern; a fourth active region stacked on the third active region along the third direction and spaced apart from the second active region in the first direction, the fourth active region comprising the upper channel pattern and the upper source / drain pattern; a first interlayer insulating layer on the lower source / drain patterns of the first active region and the third active region; a second interlayer insulating layer on the first interlayer insulating layer and on upper source / drain patterns of the second active region and the fourth active region; a third interlayer insulating layer, which is on the second interlayer insulating layer; a first upper contact extending into the second interlayer insulating layer, the upper source / drain patterns of the second active region and the fourth active region, and a portion of the first interlayer insulating layer, and electrically connected to the lower source / drain patterns of the first active region and the third active region, respectively; a second upper contact extending into a portion of the second interlayer insulating layer and electrically connected to upper source / drain patterns of the second active region and the fourth active region, respectively; a source contact electrically connected to the first upper contact and the second upper contact, respectively; as well as a source line on the third interlayer insulating layer and extending in the second direction, The source lines extend in the first direction and are electrically connected to the source contacts.

12. The magnetic memory device according to claim 1, wherein: Each of the lower channel pattern and the upper channel pattern includes a plurality of semiconductor patterns stacked to be spaced apart from each other in the third direction, and The gate electrode extends around each of the plurality of semiconductor patterns.

13. The magnetic memory device according to claim 1, further comprising a dummy channel pattern between the lower channel pattern and the upper channel pattern, in, The dummy channel pattern includes a semiconductor material or a silicon-based insulating material.

14. A magnetic memory device comprising: a substrate having a top surface and a bottom surface opposite to each other; a lower source / drain pattern on a top surface of the substrate; an upper source / drain pattern stacked on and vertically spaced apart from the lower source / drain pattern, the lower source / drain pattern and the upper source / drain pattern at least partially vertically overlapping each other; an interlayer insulating layer on the lower source / drain pattern and the upper source / drain pattern; a source line on the interlayer insulating layer; a lower interconnect layer on the bottom surface of the substrate; a magnetic tunnel junction pattern and a spin-orbit torque line, the magnetic tunnel junction pattern and the spin-orbit torque line being located in the lower interconnect layer; and a bit line in the lower interconnect layer and spaced apart from a bottom surface of the substrate, the magnetic tunnel junction pattern and the spin-orbit torque line between the bit line and the bottom surface of the substrate, wherein, when viewed in a plan view, the source line and the bit line are spaced apart from each other in a first direction parallel to the top surface of the substrate, and extend in a second direction parallel to the top surface of the substrate and intersecting the first direction, and The spin-orbit torque line extends in the second direction and vertically overlaps at least partially with the bit line.

15. The magnetic memory device according to claim 14, further comprising: a first lower contact extending into a portion of the lower interconnect layer and the substrate and electrically connecting the lower source / drain pattern to the magnetic tunnel junction pattern; a second lower contact extending into a portion of the lower interconnect layer, the substrate, and the lower source / drain pattern and electrically connecting the upper source / drain pattern to the spin-orbit torque wire; as well as a lower separation structure extending around a side surface of the second lower contact, Wherein, the second lower contact is electrically separated from the lower source / drain pattern by the lower separation structure.

16. The magnetic memory device according to claim 15, wherein: The magnetic tunnel junction pattern contacts the spin-orbit torque line and vertically overlaps at least partially with the first lower contact. 17 . The magnetic memory device of claim 15 , further comprising an interlayer interconnection line and an interlayer interconnection contact, the interlayer interconnection line and the interlayer interconnection contact being located between the magnetic tunnel junction pattern and the first lower contact.

18. A magnetic memory device comprising: a substrate having a top surface and a bottom surface opposite to each other and including an active pattern; a first active region on the active pattern, the first active region comprising a lower channel pattern and a lower source / drain pattern connected to the lower channel pattern; a second active region stacked on the first active region in a third direction perpendicular to the top surface of the substrate, the second active region comprising an upper channel pattern and an upper source / drain pattern connected to the upper channel pattern; a gate electrode on the lower channel pattern and the upper channel pattern and extending in a first direction parallel to a top surface of the substrate; a lower interconnection layer including a first lower insulating layer, a second lower insulating layer, and a third lower insulating layer sequentially stacked along the third direction on the bottom surface of the substrate; a bit line in the third lower insulating layer; a first lower contact extending into the first lower insulating layer and the substrate; a second lower contact extending into the first and second lower insulating layers, the substrate, and the lower source / drain pattern; a magnetic tunnel junction pattern in the second lower insulating layer and electrically connected to the first lower contact; as well as a spin-orbit torque line in the third lower insulating layer and electrically connected to the second lower contact and the magnetic tunnel junction pattern, The magnetic tunnel junction pattern and the spin-orbit torque line are between the bottom surface of the substrate and the bit line.

19. The magnetic memory device according to claim 18, further comprising a lower separation structure extending around a side surface of the second lower contact; in, The second lower contact is electrically separated from the lower source / drain pattern by the lower separation structure.

20. The magnetic memory device according to claim 18, further comprising: a first interlayer insulating layer on the lower source / drain pattern; a second interlayer insulating layer on the first interlayer insulating layer and the upper source / drain pattern; a first upper contact extending into the second interlayer insulating layer, the upper source / drain pattern, and a portion of the first interlayer insulating layer and electrically connected to the lower source / drain pattern; a second upper contact extending into a portion of the second interlayer insulating layer and electrically connected to the upper source / drain pattern; as well as an upper separation structure extending around a side surface of the first upper contact, Wherein, the first upper contact is electrically separated from the upper source / drain pattern by the upper separation structure.

Images