Memory module and electronic device assembly including the same

Abstract

Disclosed is a memory module including a module printed circuit board including a chip region and a pad region, and a memory chip provided on the module printed circuit board in the chip region. The modular printed circuit board includes a board including a first surface and a second surface disposed opposite each other, a first pad provided on the first surface in a pad region, and a second pad provided on the second surface in the pad region. The first pad is disposed farther away from the chip region than the second pad.

Description

Technical Field

[0001] The present disclosure generally relates to memory modules and electronic device components. Background Art

[0002] A computing system includes a memory module that includes storage elements such as DRAM and SRAM. The memory module is mounted on a motherboard or main board and is connected to other components within the computing system. A socket into which the memory module is inserted is provided between the memory module and the motherboard or main board.

[0003] Memory modules are manufactured according to various standards. For example, there are various types of memory modules such as small outline dual in-line memory modules (SODIMMs) and compact attached memory modules. Since various types of memory modules have different ways of connecting to the socket, memory modules suitable for each method are required. Summary of the Invention

[0004] One or more example embodiments provide memory modules and electronic device components having improved characteristics.

[0005] According to an embodiment, a memory module includes: a module printed circuit board including a chip area and a pad area; and memory chips provided on the module printed circuit board in the chip area. The module printed circuit board includes: a board including a first surface and a second surface disposed opposite to each other; a first pad provided in the pad area on the first surface; and a second pad provided in the pad area on the second surface. The first pad is disposed farther from the chip area than the second pad.

[0006] According to an embodiment, an electronic device component includes: a main printed circuit board; a memory module; and a connector provided between the main printed circuit board and the memory module. The memory module includes a module printed circuit board and memory chips, the module printed circuit board including a chip area and a pad area, and the memory chips being provided on the module printed circuit board in the chip area. The module printed circuit board includes a first surface provided on one side of the main printed circuit board, a second surface opposite to and facing the main printed circuit board, a plurality of first pads provided in the pad area on the first surface, and a plurality of second pads provided in the pad area on the second surface. The plurality of first pads are disposed farther from the chip area than the plurality of second pads.

[0007] According to an embodiment, a memory module includes: a board having a first surface and a second surface disposed opposite to each other; memory chips provided on the first surface; and a plurality of first pads provided on the second surface and overlapping the memory chips along the arrangement direction of the first surface and the second surface. Some of the plurality of first pads have an area smaller than the area of other ones of the plurality of first pads.

[0008] Other aspects will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the presented embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] The above and other aspects, features and advantages of certain embodiments of the present disclosure will become more apparent from the following description taken in conjunction with the drawings, in which:

[0010] Figure 1 is a block diagram showing a computing system according to an example embodiment.

[0011] Figure 2 is a top view of a memory module according to an example embodiment.

[0012] Figure 3 is Figure 2 a bottom view of the memory module of

[0013] Figure 4 is a cross-sectional view taken along line A-A' in Figure 2 above.

[0014] Figure 5A is a cross-sectional view showing an electronic device assembly including the memory module of Figure 2 above.

[0015] Figure 5B and 5C are cross-sectional views showing the process of mounting the memory module of Figure 5A above on a first connector.

[0016] Figure 6 is a top view of a memory module according to an example embodiment.

[0017] Figure 7 is Figure 6 a bottom view of the memory module of

[0018] Figure 8 is a top view of a memory module according to an example embodiment.

[0019] Figure 9 is Figure 8 a bottom view of the memory module of

[0020] Figure 10 is a top view of a memory module according to an example embodiment.

[0021] Figure 11 is Figure 10 a bottom view of the memory module of

[0022] Figure 12 is Figure 11An enlarged view of portion AA.

[0023] Figure 13 is a cross-sectional view taken along Figure 10 line B-B' in

[0024] Figure 14 is a cross-sectional view of an electronic device for showing a memory module including Figure 10 .

[0025] Figure 15 is a cross-sectional view of an electronic device according to an exemplary embodiment.

[0026] Figure 16 is Figure 15 an enlarged view of portion BB in DETAILED DESCRIPTION

[0027] Hereinafter, exemplary embodiments will be described in detail with reference to the accompanying drawings. Throughout the specification, like components are denoted by like reference numerals, and redundant descriptions thereof are omitted. It should be understood that when an element or layer is referred to as being "on," "connected to," or "coupled to" another element or layer, it can be directly on, directly connected to, or directly coupled to the other element or layer, or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on," "directly connected to," or "directly coupled to" another element or layer, or as being "in contact with" or "contacting" another element (or using any form of the word "contact"), no intervening elements or layers are present.

[0028] The embodiments described herein are exemplary embodiments, and thus, the present disclosure is not limited thereto and can be implemented in various other forms. Each exemplary embodiment provided in the following description does not exclude being associated with one or more features of another example or another exemplary embodiment provided herein or not provided herein but consistent with the present disclosure. It should also be understood that even if a certain step or operation of manufacturing a device or structure is described later than another step or operation, that step or operation can be performed later than other steps or operations, unless other steps or operations are described as being performed after that step or operation.

[0029] When referring to an orientation, layout, position, shape, size, quantity, or other measurement, terms such as "same", "equal", "planar", or "coplanar" as used herein do not necessarily mean exactly the same orientation, layout, position, shape, size, quantity, or other measurement, but are intended to cover nearly the same orientation, layout, position, shape, size, quantity, or other measurement within acceptable variations that may occur, for example, due to manufacturing processes. Unless the context or other statements indicate otherwise, the term "substantially" may be used herein to emphasize this meaning. For example, an item described as "substantially the same", "substantially equal", or "substantially planar" may be exactly the same, equal, or planar, or may be the same, equal, or planar within acceptable variations that may occur, for example, due to manufacturing processes.

[0030] Figure 1 is a block diagram showing a computing system according to an example embodiment.

[0031] Referring Figure 1 , a computing system 10 may be provided. For example, the computing system 10 may include a user device, a computer, a personal computer (PC), a desktop computer, a laptop computer, a notebook computer, a netbook computer, a tablet computer, a smart phone, an embedded electronic device, a game console, a server array or server farm, a web server, a network server, an Internet server, a workstation, a minicomputer, a mainframe computer, a supercomputer, a network device, a web device, a distributed computing system, a multiprocessor system, a processor-based system, or a combination thereof. The computing system 10 may include a main printed circuit board on which components may be mounted. The computing system 10 may include a processor 13. The processor 13 may include a central processing unit (CPU). The central processing unit may include a plurality of general-purpose processing cores. The processor 13 may include a graphics processing unit (GPU) or other processing unit. The processor 13 may include memory management logic (e.g., a memory controller) and I / O control logic.

[0032] The computing system 10 may include a memory 11 (e.g., system memory). The system memory may be in the same package as the processor 13 or may be separate from the processor 13. In an example embodiment, the memory 11 may include static random access memory (SRAM), dynamic random access memory (DRAM), or a combination thereof. In an example embodiment, the memory 11 may include byte-addressable non-volatile memory, such as single-level or multi-level phase change memory (PCM) or phase change memory with a switch (PCMS), non-volatile memory using chalcogenide phase change materials, resistive memory including metal-oxide-based materials, resistive memory based on oxygen vacancy materials, and conductive bridge random access memory (CB-RAM), nanowire memory, ferroelectric random access memory (FeRAM, FRAM), magnetoresistive random access memory (MRAM) with memristor technology, spin-transfer torque (STT)-MRAM, devices based on spin magnetic junction memory, devices based on magnetic tunnel junctions (MTJs), devices based on domain walls (DW) and spin-orbit transfer (SOT), thyristor-based storage devices, or a combination thereof.

[0033] The computing system 10 may include a communication interface 14, a display (e.g., touch screen, tablet) 16, and other components 15. The computing system 10 may include logic and / or features to support the communication interface 14. In an example embodiment, the communication interface may include one or more input / output (I / O) interfaces that operate according to various communication protocols or standards to communicate directly or via a network communication link or channel. Direct communication may occur by using communication protocols or standards described in one or more industry standards, including successor standards and variants. For example, the I / O interface may be a Serial Advanced Technology Attachment (SATA) interface for coupling elements of a node to a storage device, a Serial Attached SCSI (SAS) interface for coupling other elements of the node (e.g., a controller or other elements of the node) to a storage device, a Peripheral Component Interconnect Express (PCIe) or Non-Volatile Memory Express (NVMe) interface. The communication interface may include a local wired point-to-point link (e.g., USB) interface, a wireless local area network (e.g., WiFi) interface, a wireless point-to-point link (e.g., Bluetooth) interface, a Global Positioning System interface, and / or other interfaces. Although not shown, other components may include, for example, a power source (e.g., a battery or / and other power sources), sensors, power management logic, or other components.

[0034] The computing system 10 may include a non-volatile memory 12. In an example embodiment, the non-volatile memory 12 may be a mass storage component. The non-volatile memory 12 may include byte- or block-addressable non-volatile memory. For example, the non-volatile memory 12 may include NAND flash memory (e.g., multi-threshold level NAND), NOR flash memory, single-level or multi-level phase change memory (PCM), resistive memory, nanowire memory, ferroelectric transistor random access memory (FeTRAM), magnetoresistive random access memory (MRAM) with memristor technology, spin transfer torque MRAM (STT-MRAM), a memory structure including chalcogenide materials and / or phase change materials, or a combination thereof. In an example embodiment, the non-volatile memory 12 may be arranged or configured as a solid state drive (SSD). Data may be read and written in blocks. The mapping or location information of the blocks may be maintained in the memory 11.

[0035] In an example embodiment, the computing system 10 may include one or more accelerators or other computing devices. For example, the computing system 10 may include an artificial intelligence (AI) or machine learning accelerator optimized to perform operations on machine learning algorithms, a graphics accelerator (e.g., GPU), or other types of accelerators. The accelerator may include processing circuitry (analog, digital, or both). The accelerator may include memory within the same package as the accelerator. The accelerator may be mounted on a card to be inserted into a connector (such as the connector described herein).

[0036] Figure 2 is a top view of a memory module according to an example embodiment. Figure 3 is Figure 2 a bottom view of the memory module of. Figure 4 is a cross-sectional view taken along line A-A' in Figure 2 therein.

[0037] Reference Figures 2 to 4, a memory module 100a can be provided. In an exemplary embodiment, the memory module 100a can be used in a compact computing system, such as a laptop computer. The memory module 100a can include a small outline dual in-line memory module (SODIMM). The memory module 100a can include a module printed circuit board 110 and memory chips 104. The memory chips 104 can be semiconductor memory chips 104. The memory chips 104 can be disposed on the module printed circuit board 110. The memory chips 104 can include, for example, DRAM, SRAM, or NAND flash memory. Some of the memory chips 104 can be mounted on the front surface of the module printed circuit board 110. The front surface of the module printed circuit board 110 can be the first surface 112a of the board 112 described below. Other memory chips 104 can be mounted on the back surface of the module printed circuit board 110. The back surface of the module printed circuit board 110 can be the second surface 112b of the board 112. For example, the memory chips 104 can be mounted on the module printed circuit board 110 using surface mount technology (SMT) or through-hole technology (THT).

[0038] The module printed circuit board 110 can include a board 112, conductive lines 114, vias 116, a first pad 122, and a second pad 124. The module printed circuit board 110 can include a chip region 110a and a pad region 110b. The chip region 110a can be a region that provides the memory chips 104. The pad region 110b can be a region that provides the first pad 122 and the second pad 124.

[0039] The board 112 can extend along a first direction DR1 and a second direction DR2. The chip region 110a and the pad region 110b can be sequentially arranged along the first direction DR1. The second direction DR2 can intersect the first direction DR1. The board 112 can include a first surface 112a and a second surface 112b that are spaced apart from each other along a third direction DR3 that intersects the first direction DR1 and the second direction DR2. For example, the first direction DR1, the second direction DR2, and the third direction DR3 can be perpendicular to each other. In an exemplary embodiment, the board 112 can include a plurality of insulating layers 113 stacked along the third direction DR3. The board 112 can be formed of or include at least one of insulating materials having a desired mechanical strength and thermal stability. For example, the board 112 can be formed of FR4, FR2, CEM1, CEM3, polytetrafluoroethylene (PTFE), or polyimide, or include FR4, FR2, CEM1, CEM3, polytetrafluoroethylene (PTFE), or polyimide.

[0040] The conductive wire 114 may be provided within the board 112 or on the surface of the board 112. For example, the conductive wire 114 may also be provided between multiple insulating layers 113. The conductive wire 114 may extend in a direction parallel to the first surface 112a. For example, the conductive wire 114 may extend in the first direction DR1, the second direction DR2, or a combined direction of the first direction DR1 and the second direction DR2. The conductive wire 114 may include at least one of conductive materials. For example, the conductive wire 114 may be formed of or include copper (Cu) or aluminum (Al). The conductive wire 114 may have a specific impedance value. The conductive wire 114 may have desired morphological characteristics (e.g., length, width, and thickness). For example, the morphological characteristics of the conductive wire 114 may be determined to prevent loss or distortion of transmitted signals. In an exemplary embodiment, the conductive wire 114 and the board 112 adjacent to each other may constitute a signal transmission line. The signal transmission line may be configured to transmit signals. For example, the signal transmission line may transmit an input signal provided from outside the memory module 100a to the memory chip 104 and transmit an output signal provided from the memory chip 104. In an exemplary embodiment, one conductive wire 114 and the board 112 adjacent to each other may constitute one signal transmission line. In an exemplary embodiment, multiple conductive wires 114 and the board 112 adjacent to each other may constitute one signal transmission line. For example, the signal transmission line may include a microstrip line, a stripline, or a coplanar waveguide. In an exemplary embodiment, the conductive wire 114 may be a power transmission line that delivers a driving voltage or a ground voltage to the memory chip 104.

[0041] The via 116 can be provided within the board 112. The via 116 can extend along a third direction DR3. The via 116 can be configured to provide electrical connections between different components. The via 116 can electrically connect conductive lines 114 provided at different heights. The conductive lines 114 connected by the via 116 can overlap along the third direction DR3. For example, both ends of the via 116 can respectively contact the conductive lines 114 provided at different heights. The via 116 can electrically connect the conductive line 114 and the memory chip 104. The conductive line 114 and the memory chip 104 connected by the via 116 can overlap along the third direction DR3. For example, both ends of the via 116 can respectively contact the conductive line 114 and the memory chip 104. The via 116 can electrically connect the conductive line 114 and the first pad 122. The conductive line 114 and the first pad 122 connected by the via 116 can overlap along the third direction DR3. For example, both ends of the via 116 can respectively contact the conductive line 114 and the first pad 122. The via 116 can electrically connect the conductive line 114 and the second pad 124. The conductive line 114 and the second pad 124 connected by the via 116 can overlap along the third direction DR3. For example, both ends of the via 116 can respectively contact the conductive line 114 and the second pad 124. The via 116 can include a conductive material. For example, the via 116 can be formed of or include copper (Cu).

[0042] The first pad 122 may be provided on the first surface 112a of the board 112. The first pad 122 may be disposed in the pad region 110b of the module printed circuit board 110. The first pad 122 may include at least one of conductive materials. For example, the first pad 122 may be formed of or include copper (Cu). The first pad 122 may be a signal pad, a power pad, or a ground pad. The first pad 122 as a signal pad may be referred to as the first signal pad. The signal pad may be configured to receive an input signal provided from outside the memory module 100a to the memory chip 104 mounted on the first surface 112a of the board 112, or to send an output signal provided from the memory chip 104 mounted on the first surface 112a of the board 112 to the outside of the memory module 100a. The first pad 122 as a power pad may be referred to as the first power pad. The power pad may be configured to be electrically connected to a terminal outside the memory module 100a that supplies power to the memory chip 104 mounted on the first surface 112a of the board 112. For example, a driving voltage for the memory chip 104 may be applied to the power pad. The first pad 122 as a ground pad may be referred to as the first ground pad. The ground pad may be configured to be electrically connected to a terminal outside the memory module 100a that provides a ground voltage to the memory chip 104 mounted on the first surface 112a of the board 112. In an exemplary embodiment, the first pad 122 may be electrically connected to the via 116. For example, the first pad 122 may be electrically connected to the conductive line 114 provided in the board 112 through the via 116. The first pad 122 and the conductive line 114 connected through the via 116 may overlap along the third direction DR3. In an exemplary embodiment, the first pad 122 may be electrically connected to the conductive line 114 provided on the first surface 112a. The first pad 122 and the conductive line 114 provided on the first surface 112a that are electrically connected to each other may overlap along the first direction DR1, the second direction DR2, or a combination of the first direction DR1 and the second direction DR2.

[0043] The second pad 124 may be provided on the second surface 112b of the board 112. The second pad 124 may be disposed in the pad region 110b of the module printed circuit board 110. The second pad 124 may include at least one of conductive materials. For example, the second pad 124 may be formed of or include copper (Cu). The second pad 124 may be a signal pad, a power pad, or a ground pad. The second pad 124 as a signal pad may be referred to as a second signal pad. The signal pad may be configured to receive an input signal provided from outside the memory module 100a to the memory chip 104 mounted on the second surface 112b of the board 112, or to transmit an output signal provided from the memory chip 104 mounted on the second surface 112b of the board 112 to the outside of the memory module 100a. The second pad 124 as a power pad may be referred to as a second power pad. The power pad may be configured to be electrically connected to a terminal outside the memory module 100a that supplies power to the memory chip 104 mounted on the second surface 112b of the board 112. For example, a driving voltage for the memory chip 104 may be applied to the power pad. The second pad 124 as a ground pad may be referred to as a second ground pad. The ground pad may be configured to be electrically connected to a terminal outside the memory module 100a that supplies a ground voltage to the memory chip 104 mounted on the second surface 112b of the board 112. In an exemplary embodiment, the second pad 124 may be electrically connected to the via 116. For example, the second pad 124 may be electrically connected to the conductive line 114 provided in the board 112 through the via 116. The second pad 124 and the conductive line 114 connected through the via 116 may overlap along the third direction DR3. In an exemplary embodiment, the second pad 124 may be electrically connected to the conductive line 114 provided on the second surface 112b. The second pad 124 and the conductive line 114 provided on the second surface 112b that are electrically connected to each other may overlap along the first direction DR1, the second direction DR2, or a combination of the first direction DR1 and the second direction DR2.

[0044] Each first pad 122 may be a square or rectangular pad that includes a pair of first length sides LS1 extending along the first direction DR1 and a pair of first width sides WS1 extending along the second direction DR2. The first pad 122 may have a first length L1, a first width W1, and a first center line CL1. The first length L1 may be the dimension of the first pad 122 along the first direction DR1. The first length L1 may be the extension distance of the first length side LS1. The first width W1 may be the dimension of the first pad 122 along the second direction DR2. The first width W1 may be the extension distance of the first width side WS1. The first center line CL1 may be an imaginary line that passes through the center of the first length side LS1 and extends along the second direction DR2.

[0045] Each second pad 124 may be a square or rectangular pad that includes a pair of second length sides LS2 extending along a first direction DR1 and a pair of second width sides WS2 extending along a second direction DR2. The second pad 124 may have a second length L2, a second width W2, and a second center line CL2. The second length L2 may be the dimension of the second pad 124 along the first direction DR1. The second length L2 may be the extension distance of the second length side LS2. The second width W2 may be the dimension of the second pad 124 along the second direction DR2. The second width W2 may be the extension distance of the second width side WS2. The second center line CL2 may be an imaginary line passing through the center of the second length side LS2 and extending along the second direction DR2.

[0046] The first pad 122 and the second pad 124 may have substantially the same shape and size. The first length L1 and the second length L2 may be substantially equal to each other. The first width W1 and the second width W2 may be substantially equal to each other. The first center line CL1 may be spaced apart from the second center line CL2 along the first direction DR1. The first center line CL1 may be closer to the side RS of the board 112 facing the first connector described below than the second center line CL2. Hereinafter, the side RS of the board 112 facing the first connector is referred to as the reference side RS. The distance D11 between the first center line CL1 and the reference side RS may be less than the distance D21 between the second center line CL2 and the reference side RS.

[0047] The distance D12 between the first pad 122 and the reference side RS may be less than the distance D22 between the second pad 124 and the reference side RS. In an exemplary embodiment, the sum of the distance D12 between the first pad 122 and the reference side RS and the first length L1 may be greater than the distance D22 between the second pad 124 and the reference side RS. In an exemplary embodiment, the sum of the distance D12 between the first pad 122 and the reference side RS and the first length L1 may be substantially the same as the distance D22 between the second pad 124 and the reference side RS. In an exemplary embodiment, the sum of the distance D12 between the first pad 122 and the reference side RS and the first length L1 may be less than the distance D22 between the second pad 124 and the reference side RS.

[0048] The third direction DR3 is used to explain the positional relationship between the first width side WS1 and the second width side WS2. One of the pair of first width sides WS1 that is set away from the chip area 110a can be spaced apart from one of the pair of second width sides WS2 that is set away from the chip area 110a along the first direction DR1. In an exemplary embodiment, one of the pair of second width sides WS2 that is set further away from the chip area 110a can be spaced apart from one of the pair of first width sides WS1 that is set closer to the chip area 110a along the first direction DR1. In an exemplary embodiment, one of the pair of second width sides WS2 that is set away from the chip area 110a can overlap with one of the pair of first width sides WS1 that is set closer to the chip area 110a. In an exemplary embodiment, one of the pair of first width sides WS1 that is set closer to the chip area 110a can be spaced apart from one of the pair of second width sides WS2 that is set further away from the chip area 110a along the first direction DR1.

[0049] The distance D12 between the reference side RS and one of the pair of first width sides WS1 that is set away from the chip area 110a can be less than the distance D22 between one of the pair of second width sides WS2 that is set away from the chip area 110a and the reference side RS. In an exemplary embodiment, the distance D13 between one of the pair of first width sides WS1 that is set closer to the chip area 110a and the reference side RS can be greater than the distance D22 between one of the pair of first width sides WS1 that is set further away from the chip area 110a and the reference side RS. In an exemplary embodiment, the distance D13 between one of the pair of first width sides WS1 that is set closer to the chip area 110a and the reference side RS can be substantially equal to the distance D22 between one of the pair of second width sides WS2 that is set away from the chip area 110a and the reference side RS. In an exemplary embodiment, the distance D13 between the reference side RS and one of the pair of first width sides WS1 that is set closer to the chip area 110a can be less than the distance D22 between one of the pair of second width sides WS2 that is set away from the chip area 110a and the reference side RS.

[0050] In another exemplary embodiment, the first pad 122 may be configured as a first signal pad. The first pad 122 may not include a first power pad and a first ground pad. The second pad 124 may be configured as a second power pad and a second ground pad. Some of the second pads 124 may be second power pads, and other pads may be second ground pads. The second pad 124 may not include a second signal pad. One of the second power pads or one of the second ground pads may be electrically connected to a plurality of memory chips 104. Before the memory module 100a is connected to the first connector 200 described below, static electricity may accumulate in the first connector 200 and the main printed circuit board 300. When the memory module 100a is connected to the first connector 200, the static electricity accumulated in the first connector 200 and the main printed circuit board 300 may flow into the memory module 100a. As will be referenced later Figures 5A to 5C described, the second power pad and the second ground pad may be electrically connected to the first connector 200 before the first signal pad. Since the second power pad and the second ground pad are electrically connected to a plurality of memory chips 104, the static electricity may be distributed to the plurality of memory chips 104 through the second power pad and the second ground pad. Therefore, damage to the memory chips 104 caused by static electricity can be reduced or substantially prevented.

[0051] Figure 5A is a cross-sectional view of an electronic device assembly including a Figure 2 memory module. Figure 5B and 5C is a cross-sectional view showing the process of mounting a Figure 5A memory module on the first connector. For simplicity of description, content that is substantially the same as that described with reference to Figures 2 to 4 may not be described.

[0052] Referring to Figure 5A , an electronic device assembly 1000 may be provided. The electronic device assembly 1000 may include a main printed circuit board 300, a first connector 200, and a memory module 100a. The memory module 100a may be substantially the same as the memory module 100a described with reference to Figures 2 to 4 . For simplicity of description, the board 112, the first pad 122, and the second pad 124 are shown in the memory module 100a. The main printed circuit board 300 may include a board on which components of a computing system may be mounted. The main printed circuit board 300 may include main conducting wires that electrically connect the components of the computing system. The main conducting wires may be configured to transmit signals and power between the components of the computing system on the main printed circuit board 300. The components of the computing system may be attached (e.g., soldered) to the main printed circuit board 300 or embedded in the main printed circuit board 300.

[0053] The first connector 200 may be coupled to the main printed circuit board 300. In an exemplary embodiment, the first connector 200 may be a SODIMM connector. For example, a SODIMM connector can be used in a compact computing system such as a laptop computer. The first connector 200 may be provided between the main printed circuit board 300 and the memory module 100a. The first connector 200 may provide an electrical connection between the main printed circuit board 300 and the memory module 100a. The first connector 200 may include a housing 210, a first pin 220, and a second pin 230. In an exemplary embodiment, the first connector 200 may further include a fixing member (not shown) for fixing the memory module 100a. For example, fixing members may be provided at both ends of the housing 210 to fix the memory module 100a inserted into the first connector 200.

[0054] The housing 210 may be configured to be coupled to the memory module 100a. The housing 210 may extend longitudinally along a second direction DR2. The housing 210 may have a desired strength and may include an insulating material. For example, the housing 210 may include insulating plastic. The housing 210 may be configured to surround and support the first pin 220 and the second pin 230. The housing 210 may fix the positions of the first pin 220 and the second pin 230. The housing 210 may include a groove 210h into which the memory module 100a is inserted. The housing 210 may include a first portion 210a facing the first pad 122 and a second portion 210b facing the second pad 124. For example, the first portion 210a may face the first surface 112a of the board 112, and the second portion 210b may face the second surface 112b of the board 112. The first portion 210a and the second portion 210b may be spaced apart from each other, and the groove 210h is located between the first portion 210a and the second portion 210b. The housing 210 may be coupled to the main printed circuit board 300.

[0055] The first pin 220 can be inserted into the first part 210a. The first pin 220 can be arranged along the second direction DR2. The first pin 220 can penetrate the first part 210a. The end of the first pin 220 can protrude from the first part 210a. For example, the first pin 220 can protrude from the bottom of the first part 210a in a direction opposite to the third direction DR3. The first pin 220 protruding from the first part 210a can be configured to contact the first pad 122. For example, the first pin 220 can be arranged along the second direction DR2 to correspond to the position of the first pad 122 on the memory module 100a, and when the memory module 100a is inserted into the groove 210h, each first pin 220 can contact a corresponding one of the first pads 122. Therefore, the first pin 220 and the first pad 122 can be electrically connected to each other. The area where the first pin 220 contacts the first pad 122 can be referred to as the first contact area. Some of the first pins 220 can be signal pins. The signal pins can each be electrically connected to the first signal pads. The signal pins can be configured to transmit input signals for the memory chips (e.g., Figure 4 the memory chip 104 therein) to the first signal pads. The signal pins can be configured to receive output signals provided from the memory chips (e.g., Figure 4 the memory chip 104 therein) from the first signal pads. Other pins among the first pins 220 can be power pins. The power pins can be respectively electrically connected to the first power pads. The power pins can supply the power required for the memory chips (e.g., Figure 4 the memory chip 104 therein) to the first power pads. For example, the power pins can apply the driving voltage for the memory chips (e.g., Figure 4 the memory chip 104 therein) to the first power pads. Still other pins among the first pins 220 can be ground pins. The ground pins can each be electrically connected to the first ground pads. The ground pins can be configured to supply the ground voltage required for the memory chips (e.g., Figure 4 the memory chip 104 therein) to the first ground pads.

[0056] The second pin 230 can be inserted into the second part 210b. The second pin 230 can be arranged along the second direction DR2. In a plan view, the second pin 230 can be spaced apart from the first pin 220 in a direction opposite to the first direction DR1. The second pin 230 can penetrate the second part 210b. The end of the second pin 230 can protrude from the second part 210b. For example, the second pin 230 can protrude from the top of the second part 210b along the third direction DR3. The end of the second pin 230 protruding from the second part 210b can be configured to contact the second pad 124. For example, the second pin 230 can be arranged along the second direction DR2 to correspond to the position of the second pad 124 on the memory module 100a, and when the memory module 100a is inserted into the groove 210h, each second pin 230 can contact a corresponding one of the second pads 124. Accordingly, the second pin 230 and the second pad 124 can be electrically connected to each other. The area where the second pin 230 contacts the second pad 124 can be referred to as the second contact area. From the perspective along the third direction DR3, the first contact area can be spaced apart from the second contact area along the first direction DR1. Some of the second pins 230 can be signal pins. The signal pins can each be electrically connected to the second signal pads. The signal pins can be configured to transmit input signals for the memory chips (e.g., the memory chips 104 in Figure 4 ) to the second signal pads. The signal pins can be configured to receive output signals provided from the memory chips (e.g., the memory chips 104 in Figure 4 ) from the second signal pads. Other pins among the second pins 230 can be power pins. The power pins can each be electrically connected to the second power pads. The power pins can supply the power required for the memory chips (e.g., the memory chips 104 in Figure 4 ) to the second power pads. For example, the power pins can apply a driving voltage for the memory chips (e.g., the memory chips 104 in Figure 4 ) to the second power pads. Still other pins among the second pins 230 can be ground pins. The ground pins can each be electrically connected to the second ground pads. The ground pins can be configured to supply the ground voltage required for the memory chips (e.g., the memory chips 104 in Figure 4 ) to the second ground pads.

[0057] To couple the memory module 100a to the first connector 200, as Figure 5B shown, the memory module 100a can be inserted into the groove 210h in an inclined state (denoted as A1). After that, as Figure 5CAs shown, the memory module 100a can be rotated (denoted as A2). When the memory module 100a is rotated (denoted as A2), the second pad 124 can contact the second pin 230 before the first pad 122 contacts the first pin 220.

[0058] When the first pad 122 and the second pad 124 are placed at the same position, the first pad 122 and the second pad 124 can be formed to extend to regions where the first pin 220 and the second pin 230 do not contact, respectively. The first pad 122 and the second pad 124 of the present invention can be disposed at positions corresponding to the first pin 220 and the second pin 230, respectively. Therefore, the first pad 122 and the second pad 124 can be formed to be small. Since the thickness of the region where the first pad 122 and the second pad 124 are not formed can be as small as the thickness of the first pad 122 and the second pad 124, when the memory module 100a is inserted into the first connector 200, the memory module 100a may require a smaller force. In addition, a memory module 100a with improved signal transmission efficiency and improved power transmission efficiency can be provided.

[0059] Figure 6 is a top view of a memory module according to an exemplary embodiment. Figure 7 is Figure 6 a bottom view of the memory module. For simplicity of explanation, only the differences from those described with reference to Figures 2 to 4 will be mainly explained, and the repeated descriptions will not be repeated.

[0060] Reference Figure 6 and Figure 7 , a memory module 100b can be provided. The first pad 122 can include a first power pad 122a, a first ground pad 122b, and a first signal pad 122c. The first power pad 122a can be a plurality of first power pads 122a, the first ground pad 122b can be a plurality of first ground pads 122b, and the first signal pad 122c can be a plurality of first signal pads 122c. Different from those described with reference to Figures 2 to 4As described above, from the perspective along the third direction DR3, the first power pad 122a and the first ground pad 122b may have a first width W1 greater than the width of the first signal pad 122c in the second direction DR2. Since the first power pad 122a and the first ground pad 122b have a relatively large first width W1, the resistance to power transmission can be reduced. Therefore, the power transmission efficiency can be improved. In an exemplary embodiment, the first width W1 of the first power pad 122a and the first width W1 of the first ground pad 122b may be substantially the same. In an exemplary embodiment, the first width W1 of the first power pad 122a may be greater than the first width W1 of the first ground pad 122b. In an exemplary embodiment, the first width W1 of the first power pad 122a may be less than the first width W1 of the first ground pad 122b. For example, the first width W1 of the first power pad 122a may be less than the first width W1 of the first ground pad 122b and greater than the first width W1 of the first signal pad 122c. Since the first signal pad 122c has a relatively small first width W1, impedance matching can be achieved between the signal transmission line and the first signal pad 122c. Therefore, signal reflection between the signal transmission line and the first signal pad 122c can be reduced, thereby improving the signal transmission efficiency.

[0061] The second pad 124 may include a second power pad 124a, a second ground pad 124b, and a second signal pad 124c. In an exemplary embodiment, the second power pad 124a may be a plurality of second power pads 124a, the second ground pad 124b may be a plurality of second ground pads 124b, and the second signal pad 124c may be a plurality of second signal pads 124c. With reference to Figures 2 to 4As described above, from the perspective along the third direction DR3, the second power pad 124a and the second ground pad 124b may have a second width W2 greater than the second width W2 of the second signal pad 124c. Since the second power pad 124a and the second ground pad 124b have a relatively large second width W2, the resistance to power transmission can be reduced. Therefore, the power transmission efficiency can be improved. In an exemplary embodiment, the second width W2 of the second power pad 124a and the second width W2 of the second ground pad 124b may be substantially the same. In an exemplary embodiment, the second width W2 of the second power pad 124a may be greater than the second width W2 of the second ground pad 124b. In an exemplary embodiment, the second width W2 of the second power pad 124a may be less than the second width W2 of the second ground pad 124b. For example, the second width W2 of the second power pad 124a may be less than the second width W2 of the second ground pad 124b and greater than the second width W2 of the second signal pad 124c. Since the second signal pad 124c has a relatively small second width W2, impedance matching can be achieved between the signal transmission line and the second signal pad 124c. Therefore, signal reflection between the signal transmission line and the second signal pad 124c can be reduced, thereby improving the signal transmission efficiency.

[0062] Figure 8 is a top view of a memory module according to an exemplary embodiment. Figure 9 is Figure 8 a bottom view of the memory module. For simplicity of illustration, only the differences from those described with reference to Figures 2 to 4 will be mainly explained, and the repeated descriptions will not be repeated.

[0063] Referring to Figure 8 and Figure 9 , a memory module 100c can be provided. Different from that described with reference to Figures 2 to 4 , the first pad 122 may be composed of first signal pads. The first pad 122 may not include a first power pad and a first ground pad. The second pad 124 may be composed of a second power pad and a second ground pad. Some of the second pads 124 may be second power pads, and other pads may be second ground pads. The second pad 124 may not include a second signal pad. The first width W1 of the first pad 122 may be less than the second width W2 of the second pad 124. Since the first pad 122 (i.e., the first signal pad) has a relatively small first width W1, impedance matching can be achieved between the signal transmission line and the first pad 122. Therefore, signal reflection between the signal transmission line and the first pad 122 is reduced, thereby improving the signal transmission efficiency.

[0064] A second power pad or a second ground pad can be electrically connected to a plurality of memory chips 104. Before the memory module 100c is connected to the first connector 200, static electricity may accumulate in the first connector 200 and the main printed circuit board 300. When the memory module 100c is connected to the first connector 200, the static electricity accumulated in the first connector 200 and the main printed circuit board 300 can flow into the memory module 100c. As referenced Figures 5A to 5C As described, the second power pad and the second ground pad can be electrically connected to the first connector 200 before the first signal pad. Since the second power pad and the second ground pad are electrically connected to a plurality of memory chips 104, the static electricity can be distributed to the plurality of memory chips 104 through the second power pad and the second ground pad. Therefore, damage to the memory chips 104 caused by static electricity can be reduced or substantially prevented.

[0065] Figure 10 is a top view of a memory module according to an example embodiment. Figure 11 is Figure 10 a bottom view of the memory module. Figure 12 is Figure 11 an enlarged view of section AA of. Figure 13 is a cross-sectional view taken along line B-B' in Figure 10 . For simplicity of illustration, only the differences from those described with reference to Figures 2 to 4 are mainly explained, and the repeated descriptions are not repeated.

[0066] Referring to Figures 10 to 13 , a memory module 100d can be provided. The memory module 100d can be a CAMM2 of the Compression Attached Memory Module type. The memory module 100d can include a module printed circuit board 110 and memory chips 104. The memory chips 104 can be substantially the same as the memory chips 104 described with reference to Figures 2 to 4 . The memory module 100d can be coupled to the main printed circuit board 300 described below. The memory module 100d can be arranged parallel to the main printed circuit board 300.

[0067] The module printed circuit board 110 can include a board 112, conductive lines 114, vias 116, and third pads 126. The board 112, conductive lines 114, and vias 116 can be substantially the same as the board 112, conductive lines 114, and vias 116 described with reference to Figures 2 to 4 . The second surface 112b of the board 112 can face the main printed circuit board 300. The first surface 112a of the board 112 can be disposed opposite to the second surface 112b.

[0068] The third pad 126 may be provided on the second surface 112b. Different from that described with reference to Figures 2 to 4 as described, pads (e.g., the first pad 122) may not be provided on the first surface 112a. Each of the third pads 126 may be electrically connected to a third pin 240 described below. For example, each of the third pads 126 may contact a corresponding third pin. The third pads 126 may overlap the memory chip 104 along a third direction DR3. For example, the third pads 126 may be provided on the second surface 112b overlapping the memory chip 104 along the third direction DR3. The third pads 126 may be made of at least one of conductive materials. For example, the third pads 126 may be formed of copper (Cu) or include copper (Cu). The third pads 126 may be signal pads, power pads, or ground pads. The third pad 126 as a signal pad may be referred to as a third signal pad 126c. The third signal pad 126c may be configured to receive an input signal provided from outside the memory module 100d into the memory chip 104, or transmit an output signal provided from the memory chip 104 to the outside of the memory module 100d. The third pad 126 as a power pad may be referred to as a third power pad 126a. The third power pad 126a may be configured to be electrically connected to a terminal outside the memory module 100d that supplies power to the memory chip 104. For example, a driving voltage for the memory chip 104 may be applied to the third power pad 126a. The third pad 126 as a ground pad may be referred to as a third ground pad 126b. The third ground pad 126b may be configured to be electrically connected to a terminal outside the memory module 100d that supplies a ground voltage to the memory chip 104. The vias 116 and the conductive lines 114 may be provided between the third pads 126 and the memory chip 104. The third pads 126 and the memory chip 104 may be electrically connected through the vias 116 and the conductive lines 114. Although the conductive lines 114 are shown as being provided only within the board 112, this is illustrative. In an exemplary embodiment, the third pads 126 may be electrically connected to the conductive lines 114 provided on the first surface 112a or the second surface 112b. The third pads 126 electrically connected to each other and the conductive lines 114 provided on the first surface 112a or the second surface 112b may overlap along the first direction DR1, the second direction DR2, or a combination of the first direction DR1 and the second direction DR2.

[0069] Each third pad 126 may have a third length L3 and a third width W3. The third length L3 may be the dimension of the third pad 126 along a first direction DR1. The third width W3 may be the dimension of the third pad 126 along a second direction DR2. The third pad 126 may have a desired shape. For example, the third pad 126 may have a circular shape, and each of the third length L3 and the third width W3 may correspond to the diameter of the third pad 126. As Figure 12 shown, the third power pad 126a and the third ground pad 126b may have a larger area than the third signal pad 126c. In an exemplary embodiment, the third power pad 126a and the third ground pad 126b may have substantially the same area. In an exemplary embodiment, the third power pad 126a and the third ground pad 126b may have different areas. For example, the third length L3 and the third width W3 of the third power pad 126a and the third ground pad 126b may be greater than the third length L3 and the third width W3 of the third signal pad 126c.

[0070] Since the third power pad 126a and the third ground pad 126b have a relatively large area, the resistance to power transmission can be reduced. Therefore, the power transmission efficiency can be improved. Since each of the third signal pads 126c has a relatively small area, impedance matching can be achieved between the signal transmission line and the third signal pad 126c. Therefore, signal reflection between the signal transmission line and the third signal pad 126c can be reduced, thereby improving the signal transmission efficiency.

[0071] Figure 14 is a cross-sectional view of an electronic device including Figure 10 a memory module. For simplicity of illustration, the content that is the same as that described with reference to Figures 5A to 5C and the content that is substantially the same as that described with reference to Figures 10 to 13 may not be repeated.

[0072] Reference Figure 14 , an electronic device assembly 2000 may be provided. The electronic device assembly 2000 may include a main printed circuit board 300, a memory module 100d, a second connector 202, a cover plate 132, and a backplane 134. The main printed circuit board 300 may be substantially the same as the main printed circuit board 300 described with reference to Figures 5A to 5C . The memory module 100d may be substantially the same as the memory module 100d described with reference to Figures 10 to 13 .

[0073] The second connector 202 can be coupled to the main printed circuit board 300. The second connector 202 can be a CAMM2 connector. For example, a CAMM2 connector can be used in a compact computing system such as a laptop computer. The second connector 202 can be provided between the main printed circuit board 300 and the memory module 100d. The second connector 202 can provide an electrical connection between the main printed circuit board 300 and the memory module 100d. The second connector 202 can include a housing 212 and third pins 240.

[0074] The housing 212 can be disposed between the board 112 and the main printed circuit board 300. For example, the upper surface of the housing 212 can face the second surface 112b. The housing 212 can extend longitudinally along the second direction DR2. The housing 212 can have a desired strength and include at least one of insulating materials. For example, the housing 212 can be formed of or include insulating plastic. The housing 212 can be configured to surround and support the third pins 240. The housing 212 can fix the positions of the third pins 240. The third pins 240 can be placed at desired positions on the upper surface of the housing 212. For example, each of the third pins 240 can be arranged to correspond to the position of a third pad 126 on the memory module 100d, and when the memory module 100d is connected to the housing 212, each third pin 240 can contact a corresponding one of the third pads 126.

[0075] Some of the third pins 240 can be signal pins. The signal pins can each be electrically connected to a third signal pad (e.g., Figure 11 the third signal pad 126c in Figure 11 ). The signal pins can be configured to transmit input signals for the memory chips 104 to the third signal pad (e.g., Figure 11 the third signal pad 126c in Figure 11 ). The signal pins can be configured to receive output signals provided from the memory chips 104 from the third signal pad (e.g., Figure 11 the third signal pad 126c in Figure 11 ). Other pins among the third pins 240 can be power pins. The power pins can each be electrically connected to a third power pad (e.g., Figure 11 the third power pad 126a inFigure 11 The third ground pad 126b) in

[0076] A cover plate 132 may be provided on the memory module 100d. The memory module 100d may be disposed between the cover plate 132 and the second connector 202. A backplane 134 may be provided under the main printed circuit board 300. The main printed circuit board 300 may be disposed between the backplane 134 and the second connector 202. The cover plate 132 and the backplane 134 may be screwed together. The cover plate 132 and the backplane 134 may be configured to bring the memory module 100d, the second connector 202, and the main printed circuit board 300 into close contact with each other and increase the coupling force therebetween.

[0077] Figure 15 is a cross-sectional view for showing an electronic device according to an exemplary embodiment. Figure 16 is Figure 15 an enlarged view of part BB in Figure 5A To simplify the description, differences from those described with reference to

[0078] reference Figure 15 and Figure 16 are described, and an electronic device assembly 1100 may be provided. The electronic device assembly 1100 may include a main printed circuit board 300, a memory module 100e, and a first connector 200. Except for the second pad 124, the memory module 100e may be substantially the same as the memory module 100a described with reference to Figures 2 to 4 To simplify the description, a board 112, a first pad 122, and a second pad 124 are shown in the memory module 100e. The second pad 124 of the memory module 100e may be inserted into the board 112. The surface of the second pad 124 facing the second part 210b of the housing 210 may have a concave shape. For example, the second pad 124 may have a first part on the surface of the board 112 and a second part recessed into the board 112.

[0079] The second pin 230 may be inserted into the concave surface of the second pad 124. The top surface 230u and the side surface 230s of the second pin 230 may contact the second pad 124. For example, the second pin 230 may completely contact the recessed part of the second pad 124. In the exemplary embodiment, the second pad 124 may be composed of a power pad and a ground pad.

[0080] The present invention can provide an electronic device component 1100, in which a power supply voltage or a ground voltage can be stably supplied to a memory chip (e.g., Figure 4 the memory chip 104 in

[0081] by making a second pad 124 contact not only with a top surface 230u of a second pin 230 but also with a side surface 230s of the second pin 230). For example, by making the second pad 124 contact with the top surface 230u and the side surface 230s of the second pin 230, the resistance to power transmission can be reduced.

[0082] Although the present disclosure has been described with reference to embodiments of the present disclosure, it will be apparent to those of ordinary skill in the art that various changes and modifications can be made thereto without departing from the spirit and scope of the present disclosure as set forth in the appended claims.

[0083] Cross - reference to related applications

[0084] This application claims priority to Korean Patent Application No. 10 - 2023 - 0178094, filed with the Korean Intellectual Property Office on December 8, 2023, the contents of which are incorporated herein by reference in their entirety.

Claims

1. A memory module, comprising: A module printed circuit board, including a chip area and a pad area; as well as a memory chip provided in the chip area on the module printed circuit board, wherein the module printed circuit board comprises a board including a first surface and a second surface disposed opposite to each other, a first pad provided on the first surface in the pad area, and a second pad provided on the second surface in the pad area, and The first pad is arranged to be farther away from the chip region than the second pad.

2. The memory module according to claim 1, wherein: The first pad is disposed at a position offset from the second pad along an arrangement direction of the chip region and the pad region.

3. The memory module according to claim 1, The first pad has a pair of first width sides extending along a second direction, the second direction intersecting with a first direction parallel to an arrangement direction of the chip region and the pad region, wherein the second pad has a pair of second width sides extending along the second direction, wherein the board is disposed in the pad region and has a reference edge extending along the second direction, and The distance between one of the pair of first width sides adjacent to the reference side and the reference side is smaller than the distance between one of the pair of second width sides adjacent to the reference side and the reference side. 4 . The memory module of claim 3 , wherein a first center line extending along the second direction and passing through a center of the first pad is spaced apart from a second center line extending along the second direction and passing through a center of the second pad in the first direction.

5. The memory module according to claim 3, wherein: A distance between one of the pair of first width sides disposed away from the reference side and the reference side is different from the distance between one of the pair of second width sides adjacent to the reference side and the reference side.

6. The memory module according to claim 3, wherein: A distance between one of the pair of first width sides disposed away from the reference side and the reference side is the same as a distance between one of the pair of second width sides adjacent to the reference side and the reference side.

7. The memory module according to claim 1, wherein the first pad is a plurality of first pads, wherein the plurality of first pads include a first power pad, a first ground pad and a first signal pad, and The width of the first power pad and the width of the first ground pad are greater than the width of the first signal pad. 8 . The memory module of claim 7 , wherein the width of the first power pad is different from the width of the first ground pad. 9 . The memory module of claim 7 , wherein the width of the first power pad is the same as the width of the first ground pad.

10. The memory module according to claim 7, wherein the second pad is a plurality of second pads, wherein the plurality of second pads include a second power pad, a second ground pad, and a second signal pad, and The width of the second power pad and the width of the second ground pad are greater than the width of the second signal pad.

11. The memory module according to claim 1, wherein the first pad is a plurality of first pads, wherein the second pad is a plurality of second pads, and wherein each of the plurality of first pads has a width smaller than a width of each of the plurality of second pads.

12. An electronic device assembly comprising: Main printed circuit board; Memory module; as well as a connector provided between the main printed circuit board and the memory module, The memory module comprises a module printed circuit board and a memory chip, the module printed circuit board comprises a chip area and a pad area, the memory chip is provided in the chip area on the module printed circuit board, wherein the module printed circuit board comprises a first surface provided on one side of the main printed circuit board, a second surface opposite to the first surface and facing the main printed circuit board, a plurality of first solder pads provided in the solder pad area on the first surface, and a plurality of second solder pads provided in the solder pad area on the second surface, and The plurality of first pads are disposed farther from the chip region than the plurality of second pads.

13. The electronic device assembly according to claim 12, The connector includes a housing, a plurality of first pins inserted into an upper portion of the housing, and a plurality of second pins inserted into a lower portion of the housing. wherein the plurality of first pins protrude from the upper portion of the housing and are electrically connected to the plurality of first pads, and The plurality of second pins protrude from the lower portion of the housing and are electrically connected to the plurality of second pads.

14. The electronic device assembly according to claim 13, wherein: When viewed in a direction perpendicular to the first surface, the plurality of first leads are positioned to be offset from the plurality of second leads in a direction parallel to an arrangement direction of the chip region and the pad region.

15. The electronic device assembly of claim 13, wherein: From a perspective along a direction perpendicular to the first surface, first contact areas where the multiple first pins and the multiple first pads contact are spaced apart from second contact areas where the multiple second pins and the multiple second pads contact are spaced apart in a direction parallel to the arrangement direction of the chip area and the pad area.

16. The electronic device assembly according to claim 12, wherein the plurality of first pads include a first power pad, a first ground pad and a first signal pad, and The width of the first power pad and the width of the first ground pad are greater than the width of the first signal pad.

17. The electronic device assembly according to claim 16, wherein the plurality of second pads include a second power pad, a second ground pad, and a second signal pad, and The width of the second power pad and the width of the second ground pad are greater than the width of the second signal pad. 18 . The electronic device assembly of claim 12 , wherein each of the plurality of first solder pads has a width that is smaller than a width of each of the plurality of second solder pads.

19. The electronic device assembly according to claim 18, wherein the plurality of first pads are signal pads, and Some of the plurality of second pads are power pads, and other pads of the plurality of second pads are ground pads.

20. A memory module, comprising: a plate having a first surface and a second surface disposed opposite to each other; a memory chip provided on the first surface; as well as a plurality of first pads provided on the second surface and overlapping the memory chip along an arrangement direction of the first surface and the second surface, Some of the plurality of first pads have an area smaller than areas of other first pads of the plurality of first pads.

Images