Semiconductor device and preparation method thereof
By designing a thickness gradient gate field plate structure in semiconductor devices, the contradiction between breakdown voltage and on-resistance in the prior art is solved, and the preparation cost is reduced.
Patent Information
- Application Number
- CN202311659238.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-12-05
- Publication Date
- 2025-06-10
AI Technical Summary
While increasing the breakdown voltage, existing semiconductor devices are difficult to reduce the on-resistance, and the production process of the thickness gradient field plate is complicated, resulting in high manufacturing costs.
A semiconductor device is designed, including a substrate, doped region, trench, a dielectric layer and a gate conductive layer. A second trench with gradually increasing groove depth is formed by a single-step etching process on the dielectric layer, and a gate conductive layer is filled therein, forming a gate field plate structure with a gradient in thickness.
A more uniform electric field distribution is achieved, RESURF effect is improved, on-resistance is reduced, and device preparation is reduced complexity and cost.
Smart Images
Figure CN120129285A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of integrated circuit technologies, and particularly to a semiconductor device and a method for manufacturing the same. Background Art
[0002] With the continuous development of semiconductor technologies, the key to improving the performance of semiconductor devices is to achieve high voltage and low on-resistance. To increase the breakdown voltage of devices and alleviate the contradictory relationship between breakdown voltage and on-resistance, the field plate technology is introduced as an effective means. There is a high electric field at the end of the field plate, and the local high electric field can cause the device to break down prematurely. Usually, an oxide dielectric layer is used to reduce the electric field. Since the electric field increases in the direction towards the end of the field plate, the electric field distribution under a field plate with a uniform thickness is not uniform, which limits the further increase of the breakdown voltage. Therefore, a field plate with a gradually changing thickness is used to increase the breakdown voltage. However, the manufacturing process of the field plate with a gradually changing thickness is relatively complex, resulting in a high manufacturing cost of the device. Summary of the Invention
[0003] Based on this, it is necessary to provide a semiconductor device and a method for manufacturing the same in view of the above problems.
[0004] To achieve the above object, in a first aspect, this application provides a semiconductor device, including:
[0005] A substrate;
[0006] A first doped region, disposed in the substrate;
[0007] A first trench, disposed in the first doped region, and opening from the surface of the first doped region and extending along the thickness direction of the substrate;
[0008] A second doped region, disposed in the first doped region and located on one side of the first trench;
[0009] A source region, disposed in the first doped region;
[0010] A dielectric layer, disposed in the first trench; wherein, a second trench is provided on the dielectric layer, the second trench opens from the surface of the dielectric layer and extends along the thickness direction of the substrate, and along the direction away from the second doped region, the trench depth of the second trench gradually increases;
[0011] A gate conductive layer, filling the second trench.
[0012] In one embodiment, the semiconductor device further includes a drain region;
[0013] The drain region is disposed in the first doped region on one side of the first trench and is spaced apart from the second doped region; or,
[0014] The leakage region is disposed in the substrate at the bottom of the first doped region and is adjacent to the first doped region.
[0015] In one embodiment, along the direction away from the second doped region, the groove depth of the second groove increases linearly.
[0016] In one embodiment, the gate conductive layer includes a gate field plate and a control gate. The overlapping portion of the gate conductive layer and the second doped region is the control gate, and the non-overlapping portion of the gate conductive layer and the second doped region is the gate field plate. Along the direction away from the second doped region, the depth of the bottom of the gate field plate gradually increases.
[0017] In one embodiment, the bottom of the gate field plate is an inclined plane and is disposed at an acute angle to the first direction; the first direction is parallel to the thickness direction of the substrate.
[0018] In one embodiment, the semiconductor device further includes a split gate conductive layer, which is embedded in the dielectric layer in the first trench and is located on the side of the second trench away from the substrate surface.
[0019] In a second aspect, an embodiment of the present application provides a method for manufacturing a semiconductor device, including:
[0020] Providing a substrate;
[0021] Forming a first doped region in the substrate;
[0022] Forming a first trench that opens from the surface of the first doped region and extends along the thickness direction of the substrate in the first doped region, and forming a dielectric layer in the first trench;
[0023] Forming a second trench on the dielectric layer by using a single-step etching process. The second trench opens from the surface of the dielectric layer and extends along the thickness direction of the substrate; along the direction away from the second doped region, the groove depth of the second trench gradually increases;
[0024] Forming a gate conductive layer in the second trench, forming a second doped region in the first doped region and on one side of the first trench, and forming a source region in the second doped region.
[0025] In one embodiment, the step of forming a first trench that opens from the surface of the first doped region and extends along the thickness direction of the substrate in the first doped region, and forming a dielectric layer in the first trench includes:
[0026] Forming a first mask layer having a first etching window on the substrate;
[0027] Form the first trench based on the first etching window;
[0028] Form the dielectric layer in the first trench.
[0029] In one embodiment, the step of forming the dielectric layer in the first trench includes:
[0030] Form a first sub-dielectric layer in the first trench by using a thermal oxidation process; the first sub-dielectric layer includes a first sub-part and a second sub-part, the first sub-part covers the sidewall of the first trench, and the second sub-part covers the bottom wall of the first trench; the positive projection of the first mask layer on the substrate covers at least a part of the first sub-part;
[0031] Form a split gate conductive layer in the first trench.
[0032] Form a second sub-dielectric layer in the first trench, and the first sub-dielectric layer and the second sub-dielectric layer together constitute the dielectric layer.
[0033] In one embodiment, the step of forming a second trench on the dielectric layer by using a single-step etching process, where the second trench opens from the surface of the dielectric layer and extends along the thickness direction of the substrate, includes:
[0034] Form a second mask layer having a second etching window on the first mask layer, where the second etching window exposes a part of the second sub-dielectric layer, and exposes the first mask layer above the first sub-part connected to this part of the second sub-dielectric layer;
[0035] Form a second trench on the dielectric layer by using a dry etching process.
[0036] The semiconductor device and its manufacturing method provided by the embodiments of the present application form a second trench on the dielectric layer by using a single-step etching process. Along the direction away from the second doping region, the groove depth of the second trench gradually increases. In this way, on the one hand, a gate field plate structure with a gradually changing thickness can be formed from the surface of the substrate to the bottom of the substrate, which is beneficial to making the electric field of the first doping region more uniform, effectively improving the RESURF (Reduced Surface Field) effect, obtaining a lower on-resistance, and reducing the impact ionization intensity at the gate end, playing a role in improving the hot carrier effect; on the other hand, the embodiments of the present application can reduce the manufacturing difficulty of the device, thereby reducing the manufacturing cost. Description of the Drawings
[0037] To more clearly illustrate the technical solutions in the embodiments or exemplary embodiments of the present application, the following will briefly introduce the drawings required for the description of the embodiments or exemplary embodiments. Obviously, the drawings in the following description are only some embodiments of the present application. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained based on these drawings.
[0038] Figure 1 It is a schematic diagram of a partial structure of a semiconductor device provided by an embodiment of the present application.
[0039] Figure 2 It is a schematic flow diagram of a preparation method of a semiconductor device provided by an embodiment of the present application.
[0040] Figure 3 For Figure 2 It is a schematic flow diagram of S300 in the shown preparation method.
[0041] Figure 4 For Figure 3 It is a schematic flow diagram of S330 in the shown preparation method.
[0042] Figure 5 For Figure 2 It is a schematic flow diagram of S400 in the shown preparation method.
[0043] Figures 6 - 10 For Figure 2 It is a schematic diagram of the structure of the device during the process of the shown preparation method.
[0044] Explanation of reference numerals:
[0045] 1. Semiconductor device; 11. Substrate; 11a. First trench; 11b. Second trench; 11b1. Bottom wall; 11b2. First side wall; 11b3. Second side wall; 12. First doped region; 13. Drain region; 14. Source region; 15. Dielectric layer; 151. First sub-dielectric layer; 1511. First sub-part; 1512. Second sub-part; 152. Second sub-dielectric layer; 153. Thickness-gradient dielectric layer; 16. Gate conductive layer; 161. Gate field plate; 162. Control gate; 17. Split gate conductive layer; 18. Second doped region; 2. First mask layer; 21. First oxide layer; 22. Silicon nitride layer; 23. Second oxide layer; 3. Second mask layer. Detailed implementation manners
[0046] To facilitate the understanding of the present application, the following will describe the present application more comprehensively with reference to the relevant drawings. Embodiments of the present application are shown in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present application more thorough and comprehensive.
[0047] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terms used in the description of this application herein are for the purpose of describing particular embodiments only and are not intended to limit this application.
[0048] It should be understood that when an element or layer is referred to as being "on", "adjacent to", "connected to" or "coupled to" another element or layer, it can be directly on, adjacent to, connected or coupled to the other element or layer, or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on", "directly adjacent to", "directly connected to" or "directly coupled to" another element or layer, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, doping types and / or parts, these elements, components, regions, layers, doping types and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, doping type or part from another element, component, region, layer, doping type or part. Thus, without departing from the teachings of this application, the first element, component, region, layer, doping type or part discussed below may be denoted as the second element, component, region, layer or part; for example, the first doping type may be referred to as the second doping type, and similarly, the second doping type may be referred to as the first doping type; the first doping type and the second doping type are different doping types. For example, the first doping type may be P-type and the second doping type may be N-type, or the first doping type may be N-type and the second doping type may be P-type.
[0049] Spatial relationship terms such as "under", "below", "beneath", "underneath", "above", "over", etc. may be used herein to describe the relationship of one element or feature shown in the figures to other elements or features. It should be understood that in addition to the orientation shown in the figures, spatial relationship terms also include different orientations of the device in use and operation. For example, if the device in the figures is flipped, an element or feature described as "under" or "beneath" or "underneath" another element or feature will be oriented "above" the other element or feature. Thus, the exemplary terms "under" and "beneath" can include both an upper and a lower orientation. In addition, the device may also include additional orientations (such as rotating 90 degrees or other orientations), and the spatial descriptors used herein are to be interpreted accordingly.
[0050] As used herein, the singular forms "a", "an" and "the" may also include the plural forms unless the context clearly dictates otherwise. It should also be understood that the terms "comprises / comprising", "has / including", etc. specify the presence of the stated features, integers, steps, operations, components, parts, or combinations thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, components, parts, or combinations thereof. At the same time, in this specification, the term "and / or" includes any and all combinations of the related listed items.
[0051] Embodiments of the application are described herein with reference to cross-sectional views that are schematic illustrations of ideal embodiments (and intermediate structures) of the present application, so that variations in the shapes shown, for example, due to manufacturing techniques and / or tolerances, can be expected. Thus, embodiments of the present application should not be limited to the specific shapes of the regions shown herein, but include shape deviations due to, for example, manufacturing techniques. For example, an implantation region shown as rectangular typically has rounded or curved features at its edges and / or an implantation concentration gradient, rather than a binary change from the implantation region to the non-implantation region. Similarly, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation occurs. Accordingly, the regions shown in the figures are substantially schematic, and their shapes do not represent the actual shapes of the regions of the device and do not limit the scope of the present application.
[0052] In a first aspect, with reference to Figure 1 shown, an embodiment of the present application provides a semiconductor device 1, which may be a Lateral Double-diffuse MOS (LDMOS) device or a Vertical Double-Diffused MOS (VDMOS) device.
[0053] Specifically, the semiconductor device 1 includes a substrate 11, a first doped region 12, a first trench 11a, a source region 14, a second doped region 18, a dielectric layer 15, and a gate conductive layer 16.
[0054] Among them, the first doping region 12 is disposed in the substrate 11. The first trench 11a is disposed in the first doping region 12, and the first trench 11a opens from the surface of the first doping region 12 and extends along the thickness direction of the substrate 11. The second doping region 18 is disposed in the first doping region 12 and is located on one side of the first trench 11a. The source region 14 is disposed in the second doping region 18. The dielectric layer 15 is disposed in the first trench 11a. Further, a second trench 11b is provided on the dielectric layer 15, and the gate conductive layer 16 is filled in the second trench 11b. Among them, the second trench 11b opens from the surface of the dielectric layer 15 and extends along the thickness direction of the substrate 11. Along the direction away from the second doping region 18, the groove depth of the second trench 11b gradually increases.
[0055] In one example, the material of the substrate 11 may be single-crystalline silicon, polycrystalline silicon, amorphous silicon, silicon-germanium compound, Silicon-On-Insulator (SOI), or Low Temperature Poly-Silicon (LTPS), etc., or other materials known to those skilled in the art. The substrate 11 can provide a support basis for the structural layer on the substrate 11.
[0056] In one example, the first doping region 12 is a drift region.
[0057] In one example, the second doping region 18 is a P well.
[0058] In the embodiment of the present application, with reference to Figure 1 As shown, the direction away from the second doping region 18 refers to the direction away from the second doping region 18 on the horizontal plane. The groove depth of the second trench 11b refers to the depth of the second trench 11b in the longitudinal direction.
[0059] In one example, in the direction from the notch of the first trench 11a to the bottom of the first trench 11a, the dimension of the end of the second trench 11b away from the surface of the dielectric layer 15 gradually decreases along the second direction X. The second direction X is perpendicular to the first direction Y, and the first direction Y is parallel to the thickness direction of the substrate 11.
[0060] Here, the dimension of the second groove 11b in the second direction X can be understood as the thickness of the second groove 11b. In the direction from the surface of the substrate 11 to the bottom of the substrate 11, the thickness of the second groove 11b gradually decreases. The dimension of the gate conductive layer 16 in the second direction X is the thickness of the gate conductive layer 16. Since the gate conductive layer 16 is filled in the second groove 11b, the gate conductive layer 16 has the same morphological characteristics as the second groove 11b, that is, the thickness of the end of the gate conductive layer 16 far from the surface of the substrate 11 gradually decreases. Correspondingly, in the direction from the notch of the first groove 11a to the bottom of the first groove 11a, the dielectric layer 15 located below the gate conductive layer 16 and connected to the gate conductive layer 16 exhibits the characteristic that its dimension in the second direction X gradually increases, that is, a thickness-graded dielectric layer 153 is formed.
[0061] On the one hand, for the semiconductor device 1 provided by the embodiment of the present application, a gate field plate structure with a gradually changing thickness can be formed in the direction from the surface of the substrate 11 to the bottom of the substrate 11, which is beneficial to making the electric field of the first doped region 12 more uniform, effectively improving the RESURF (Reduced Surface Field) effect and obtaining a lower on-resistance. In addition, under a low gate voltage (LowVG) in the on-state, the dimension-graded dielectric layer 15 can also reduce the impact ionization intensity at the gate end, playing a role in improving the hot carrier effect. On the other hand, for the device provided by the embodiment of the present application, a single-step etching direction can be used to form the second groove 11b, thereby reducing the manufacturing difficulty of the device and further reducing the manufacturing cost.
[0062] In one example, the material of the dielectric layer 15 is an oxide. Further, the material of the dielectric layer 15 can be silicon oxide.
[0063] In one example, the material of the thickness-graded dielectric layer 153 is an oxide. Further, the material of the thickness-graded dielectric layer 153 can be silicon oxide.
[0064] In one of the embodiments, the semiconductor device 1 further includes a drain region 13. In one example, the drain region 13 is disposed in the first doped region 12 on one side of the first groove 11a and is spaced apart from the second doped region 18. In this way, an LDMOS device can be formed. Further, the drain region 13 can be disposed on the side of the first groove 11a away from the second doped region 18. In this way, the device performance of the semiconductor device 1 can be further improved.
[0065] In another example, the drain region 13 is disposed in the substrate 11 at the bottom of the first doped region 12 and is adjacent to the first doped region 12. In this way, a VDMOS device can be formed.
[0066] In one embodiment, along the direction away from the second doped region 18, the groove of the second trench 11b increases linearly. Here, "linearly increasing" means gradually increasing according to a preset linear ratio. The present embodiment of the application does not limit the magnitude of the linear ratio.
[0067] The above settings can make the size of the end of the second trench 11b away from the surface of the dielectric layer 15 decrease uniformly along the second direction X, and make the thickness of the gate conductive layer 16 decrease uniformly, and make the size of the thickness-graded dielectric layer 153 increase uniformly along the second direction X. In this way, it is beneficial to make the electric field of the first doped region 12 more uniform, effectively improve the RESURF (Reduced Surface Field) effect, and obtain a lower on-resistance. In addition, at a low gate voltage (Low VG) in the on-state, the thickness-graded dielectric layer 153 with a uniformly changing size can better reduce the impact ionization intensity at the end of the gate conductive layer 16, playing a role in improving the hot carrier effect.
[0068] In one embodiment, in the direction from the notch of the first trench 11a to the bottom of the first trench 11a, the size of the end of the second trench 11b away from the surface of the dielectric layer 15 decreases linearly along the second direction X. Here, it should be noted that "linearly decreasing" means gradually decreasing according to a preset linear ratio. The present embodiment of the application does not limit the magnitude of the linear ratio.
[0069] The above settings can make the size of the end of the second trench 11b away from the surface of the dielectric layer 15 decrease uniformly along the second direction X, and make the thickness of the gate conductive layer 16 decrease uniformly, and make the size of the thickness-graded dielectric layer 153 increase uniformly along the second direction X. In this way, it is beneficial to make the electric field of the first doped region 12 more uniform, effectively improve the RESURF (Reduced Surface Field) effect, and obtain a lower on-resistance. In addition, at a low gate voltage (Low VG) in the on-state, the thickness-graded dielectric layer 153 with a uniformly changing size can better reduce the impact ionization intensity at the gate end, playing a role in improving the hot carrier effect.
[0070] In one embodiment, referring to Figure 10 As shown, the bottom wall 11b1 of the second trench 11b is arranged at an acute angle with the second direction X. In this way, the size of the end of the second trench 11b away from the surface of the dielectric layer 15 can be uniformly reduced, and at the same time, a ramp-type gate field plate structure and a ramp-type thickness-graded dielectric layer 153 are formed.
[0071] In one embodiment, referring to Figure 10As shown, the second trench 11b has a first sidewall 11b2 and a second sidewall 11b3 opposite to each other along the second direction X. The first sidewall 11b2 is disposed at one end of the bottom wall 11b1 of the second trench 11b close to the source region 14, and the second sidewall 11b3 is disposed at one end of the bottom wall 11b1 of the second trench 11b close to the drain region 13. The dimension of the first sidewall 11b2 along the first direction Y is smaller than the dimension of the second sidewall 11b3 along the first direction Y. In one example, the dimension of the first sidewall 11b2 along the first direction Y is the depth of the first sidewall 11b2, and the dimension of the second sidewall 11b3 along the first direction Y is the depth of the second sidewall 11b3.
[0072] With the above arrangement, the dimension of one end of the second trench 11b away from the surface of the dielectric layer 15 along the second direction X can be uniformly reduced, and at the same time, a ramp-type gate field plate structure and a ramp-type thickness-graded dielectric layer 153 are formed.
[0073] It should be noted that the groove wall of the second trench 11b includes a first sidewall 11b2, a second sidewall 11b3, and a bottom wall 11b1.
[0074] In one embodiment, the gate conductive layer 16 includes a gate field plate 161 and a control gate 162. The part of the gate conductive layer 16 overlapping with the second doped region 18 is the control gate 162, and the part of the gate conductive layer 16 not overlapping with the second doped region 18 is the control gate 162. Along the direction away from the second doped region 18, the depth of the bottom of the gate field plate 161 gradually increases. That is, in the direction from the notch of the first trench 11a to the bottom of the first trench 11a, the dimension of the gate field plate 161 along the second direction X gradually decreases.
[0075] In this way, a thickness-graded gate field plate structure can be formed, which is beneficial to making the electric field of the first doped region 12 more uniform, effectively improving the RESURF (Reduced Surface Field) effect, and obtaining a lower on-resistance.
[0076] It should be noted that the thickness of the thickness-graded dielectric layer 153 changes continuously. Specifically, by setting the surface of the thickness-graded dielectric layer 153 in contact with the bottom of the second trench 11b as a smooth surface, the thickness of the thickness-graded dielectric layer 153 can be continuously changed. In the embodiments of the present application, the smooth surface is a non-step surface. In one example, the smooth surface can be a smooth inclined surface, a smooth concave surface, a smooth convex surface, etc.
[0077] In one embodiment, the bottom of the gate field plate 161 is an inclined plane, and is arranged at an acute angle with the first direction Y. The first direction Y is parallel to the thickness direction of the substrate 11. Here, the bottom of the gate field plate 161 being an inclined plane means that the bottom surface of the gate field plate 161 is an inclined plane. In this way, a ramp-type gate field plate 161 and a ramp-type thickness-graded dielectric layer 153 can be formed.
[0078] It should be noted that the gate field plate 161 in the embodiment of the present application is an inclined plane field plate. Compared with the multi-stage field plate structure in the related art, it can make the electric field distribution more uniform and effectively improve the breakdown voltage.
[0079] In one example, the dimension of the control gate 162 in the second direction X is a fixed value, that is: along the thickness direction of the substrate 11, the thickness of the control gate 162 remains unchanged.
[0080] In one example, the cross-sectional shape of the gate field plate 161 is a triangle, and the hypotenuse of the triangle faces the back surface of the substrate 11.
[0081] In one example, a gate dielectric layer (not shown in the figure) is further provided between the gate conductive layer 16 and the sidewall of the first trench 11a.
[0082] In one embodiment, a part of the sidewall of the first trench 11a close to the source region 14 coincides with the sidewall of the second trench 11b close to the source region 14. That is: the first sidewall 11b2 of the second trench 11b coincides with a part of the sidewall of the first trench 11a close to the source region 14. In this way, during the etching process, it is beneficial to make the dimension of the second trench 11b in the second direction X larger, thereby increasing the thickness of the gate conductive layer 16.
[0083] In one embodiment, the semiconductor device 1 further includes a split gate conductive layer 17. The split gate conductive layer 17 is embedded in the dielectric layer 15 in the first trench 11a, and the split gate conductive layer 17 is located on the side of the second trench 11b away from the surface of the substrate 11. Specifically, the split gate conductive layer 17 is spaced apart from the sidewall of the first trench 11a, and a part of the dielectric layer 15 is located between the split gate conductive layer 17 and the sidewall of the first trench 11a. It can be understood that the dielectric layer 15 between the split gate conductive layer 17 and the first trench 11a constitutes a split gate dielectric layer, and the split gate dielectric layer and the split gate conductive layer 17 together constitute a split gate.
[0084] By providing the split gate, it can assist in depleting the first doped region 12 and further improve the breakdown voltage of the device.
[0085] In one embodiment, first trenches 11a are provided on both sides of the second doping region 18 along the second direction X, and a drain region 13 is provided on one side of each first trench 11a away from the second doping region 18. In this way, it is beneficial to improve the arrangement density of cells, thereby improving device performance.
[0086] In a second aspect, referring to Figure 2 , and in combination with Figures 6 - 10 shown, an embodiment of the present application provides a method for manufacturing a semiconductor device, specifically including the following steps:
[0087] S100: Provide a substrate 11. Exemplarily, the material of the substrate 11 can be single-crystalline silicon, polycrystalline silicon, amorphous silicon, germanium-silicon compound, silicon-on-insulator (SOI), or low-temperature poly-silicon (LTPS), etc., or other materials known to those skilled in the art. The substrate 11 can provide a support basis for the structural layer on the substrate 11.
[0088] S200: Form a first doping region 12 in the substrate 11. Exemplarily, the first doping region 12 can be formed by an ion implantation process.
[0089] S300: Form a first trench 11a in the first doping region 12 that opens from the surface of the first doping region 12 and extends along the thickness direction of the substrate 11, and form a dielectric layer 15 in the first trench 11a. Exemplarily, the first trench 11a can be formed on the substrate 11 by an etching process. It can be understood that the first trench 11a is also located in the first doping region 12. In one example, the material of the dielectric layer 15 is silicon oxide.
[0090] S400: Use a single-step etching process to form a second trench 11b on the dielectric layer 15. The second trench 11b opens from the surface of the dielectric layer 15 and extends along the thickness direction of the substrate 11.
[0091] S500: Form a gate conductive layer 16 in the second trench 11b, form a second doping region 18 in the first doping region 12 and on one side of the first trench 11a, and form a source region 14 in the second doping region 18. Among them, along the direction away from the second doping region 18, the depth of the second trench 11b gradually increases.
[0092] Here, it should be noted that the dimension of the second groove 11b in the second direction X can be understood as the thickness of the second groove 11b. In the direction from the surface of the substrate 11 to the bottom of the substrate 11, the thickness of the second groove 11b gradually decreases. The dimension of the gate conductive layer 16 in the second direction X is the thickness of the gate conductive layer 16. Since the gate conductive layer 16 is filled in the second groove 11b, the gate conductive layer 16 has the same morphological characteristics as the second groove 11b, that is, the thickness of the end of the gate conductive layer 16 far from the surface of the substrate 11 gradually decreases. Correspondingly, in the direction from the notch of the first groove 11a to the bottom of the first groove 11a, the dielectric layer 15 located below the gate conductive layer 16 and connected to the gate conductive layer 16 exhibits the characteristic that its dimension in the second direction X gradually increases, that is, a thickness-graded dielectric layer 153 is formed.
[0093] In the manufacturing method of the semiconductor device provided by the embodiment of the present application, compared with the related art that uses multiple oxidations and multiple etching to form a multi-stage field plate structure, the embodiment of the present application uses a single-step etching process to form the second groove 11b and form a gate field plate structure with a thickness gradient in the direction from the surface of the substrate 11 to the bottom of the substrate 11, which can reduce the process steps in the manufacturing process, thereby reducing the manufacturing cost of the device. In addition, the gate field plate structure with a thickness gradient is beneficial to make the electric field of the first doping region 12 more uniform, effectively improve the RESURF (Reduced Surface Field) effect, and obtain a lower on-resistance. Further, at a low gate voltage (Low VG) in the on-state, the dielectric layer 15 with a size gradient can also reduce the impact ionization intensity at the gate end, playing a role in improving the hot carrier effect.
[0094] In one embodiment, referring to Figure 3 , and combining with Figure 6 , Figure 7 , Figure 8 and Figure 9 shown, S300: Form a first groove 11a that opens from the surface of the first doping region 12 and extends along the thickness direction of the substrate 11 in the first doping region 12, and form a dielectric layer 15 in the first groove 11a. The specific steps are as follows:
[0095] S310: Form a first mask layer 2 with a first etching window on the substrate 11.
[0096] In one example, the first mask layer 2 is a hard mask layer. Exemplarily, the first mask layer 2 includes a first oxide layer 21, a silicon nitride layer 22, and a second oxide layer 23 stacked.
[0097] S320: Form a first groove 11a based on the first etching window. Exemplarily, the first groove 11a can be etched and formed by a dry etching process.
[0098] S330: Form a dielectric layer 15 in the first trench 11a. Exemplarily, the dielectric layer 15 can be formed by a chemical vapor deposition process.
[0099] In one embodiment, refer to Figure 3 , and in combination with Figure 7 , Figure 8 and Figure 9 as shown, S330: Form a dielectric layer 15 in the first trench 11a, which specifically includes the following steps:
[0100] S331: Form a first sub-dielectric layer 151 in the first trench 11a by a thermal oxidation process. The first sub-dielectric layer 151 includes a first sub-portion 1511 and a second sub-portion 1512. The first sub-portion 1511 covers the sidewall of the first trench 11a, and the second sub-portion 1512 covers the bottom wall 11b1 of the first trench 11a. The positive projection of the first mask layer 2 on the substrate 11 covers at least a part of the first sub-portion 1511. In an example, the positive projection of the first mask layer 2 on the substrate 11 covers the first sub-portion 1511.
[0101] Here, it should be noted that by using the thermal oxidation process, the sidewall and the bottom wall 11b1 of the first trench 11a will be oxidized, so that the first sub-dielectric layer 151 is formed inside the trench wall of the first trench 11a, that is: the size (CD) of the first trench 11a is enlarged.
[0102] S332: Form a split gate conductive layer 17 in the first trench 11a. Exemplarily, the split gate conductive layer 17 can be formed by a chemical vapor deposition process. In an example, the material of the split gate conductive layer 17 is polysilicon.
[0103] S333: Form a second sub-dielectric layer 152 in the first trench 11a. The first sub-dielectric layer 151 and the second sub-dielectric layer 152 together constitute the dielectric layer 15. It can be understood that the materials of the second sub-dielectric layer 152 and the first sub-dielectric layer 151 are the same.
[0104] It should be noted that in this step, the surface of the substrate 11 will be planarized to remove the excess dielectric layer material. In an example, refer to Figure 8 as shown, during the process of removing the excess dielectric layer material by the planarization process, the second oxide layer 23 of the first mask layer 2 is synchronously removed.
[0105] In one embodiment, refer to Figure 5 , and in combination with S400: Form a second trench 11b on the dielectric layer 15 by a single-step etching process. The second trench 11b opens from the surface of the dielectric layer 15 and extends along the thickness direction of the substrate 11, which specifically includes the following steps:
[0106] S410: A second mask layer 3 having a second etching window is formed on the first mask layer 2. The second etching window exposes a part of the second sub-dielectric layer 152, and the first mask layer 2 above the first sub-part 1511 connected to this part of the second sub-dielectric layer 152 is also exposed.
[0107] S420: A second trench 11b is formed in the dielectric layer 15 by a dry etching process.
[0108] It should be noted that since a part of the first mask layer 2 (the first oxide layer 21 and the silicon nitride layer 22) is located directly above the first trench 11a, there is a difference in the etching rates between the silicon nitride layer 22 and the dielectric layer 15. The etching rate of the silicon nitride layer 22 is slower. In the area blocked by the silicon nitride layer 22, the silicon nitride layer 22 is etched first, then the first oxide layer 21, and then the dielectric layer 15, so that the etching depth below the silicon nitride layer 22 is relatively shallow. In the area without the first mask layer 2 blocking, the dielectric layer 15 is directly etched, so that the etching depth in this area is relatively deep. Finally, a sloped thickness-graded dielectric layer 153 with an increasing thickness can be formed at the bottom.
[0109] In one embodiment, S500: A gate conductive layer 16 is formed in the second trench 11b, a second doped region 18 is formed in the first doped region 12 and on one side of the first trench 11a, and a source region 14 is formed in the second doped region 18. Specifically, it includes the following steps:
[0110] S510: A gate dielectric layer is formed on the sidewalls of the second trench 11b.
[0111] S520: The second trench 11b is filled with a conductive material to form the gate conductive layer 16. It can be understood that after filling the conductive material, a back-etching process will be performed to form the gate conductive layer 16.
[0112] S530: The second doped region 18, the source region 14, and the drain region 13 are formed by an ion implantation process. The structure after the gate conductive layer 16, the second doped region 18, the source region 14, and the drain region 13 are formed is as Figure 1 shown.
[0113] It should be noted that since ion implantation can damage the substrate 11, greatly reducing the mobility and lifetime of electron-hole pairs, and in addition, most of the implanted ions do not occupy lattice positions in a substitutional form. To activate the ions and restore the original mobility, the substrate 11 must be annealed at an appropriate temperature. Annealing can repair lattice defects and also move impurity atoms to lattice sites to activate the impurities. Generally, repairing lattice defects requires a temperature of about 450 - 550 °C, and activating impurities requires 900 - 1000 °C. The activation of impurities is related to time and temperature. The longer the time and the higher the temperature, the more fully the impurities are activated. Commonly used annealing methods for the substrate 11 include high-temperature thermal annealing and rapid thermal annealing (RTA). In one example, a high-temperature thermal annealing process can be used for annealing treatment. Specifically, the silicon wafer is heated to 800 - 1000 °C in a high-temperature furnace and held for 20 - 40 minutes. In another example, a rapid thermal annealing process can be used for annealing treatment. The rapid thermal annealing process has a shorter annealing time compared to the high-temperature thermal annealing process, which can avoid the diffusion of doped ions caused by long-term high temperature and reduce the transient enhanced diffusion of doped ions.
[0114] It should be understood that in the embodiments of the present application, although the steps in the flowchart of the accompanying drawings are shown sequentially according to the indication of the arrows, these steps are not necessarily executed sequentially according to the order indicated by the arrows. Unless there is a clear indication in this article, the execution of these steps has no strict order limitation, and these steps can be executed in other orders. Moreover, at least a part of the steps in the accompanying drawings may include multiple steps or multiple stages. These steps or stages are not necessarily executed at the same moment, but can be executed at different moments. The execution order of these steps or stages is not necessarily sequential, but can be executed alternately or in turn with at least a part of other steps or steps or stages in other steps.
[0115] In the description of this specification, the descriptions referring to terms such as "some embodiments", "other embodiments", "ideal embodiments", etc. mean that the specific features, structures, materials, or features described in connection with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic descriptions of the above terms do not necessarily refer to the same embodiment or example.
[0116] The technical features of the above-described embodiments can be combined arbitrarily. For the sake of brevity of description, not all possible combinations of the technical features of the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, it should be considered to be within the scope described in this specification.
[0117] The above-described embodiments merely represent several implementation manners of the present application. The description thereof is relatively specific and detailed, but it should not be construed as a limitation on the scope of the patent application. It should be noted that for those of ordinary skill in the art, without departing from the concept of the present application, several modifications and improvements can still be made, and these all fall within the protection scope of the present application. Therefore, the protection scope of the patent of the present application shall be subject to the appended claims.
Claims
1. A semiconductor device, characterized in that, comprising: a substrate; a first doped region disposed within the substrate; a first trench disposed within the first doped region, opening from the surface of the first doped region and extending along the thickness direction of the substrate; a second doped region disposed within the first doped region and located on one side of the first trench; a source region disposed within the second doped region; a dielectric layer disposed within the first trench; a second trench is provided on the dielectric layer, the second trench opening from the surface of the dielectric layer and extending along the thickness direction of the substrate, and along the direction away from the second doped region, the depth of the second trench gradually increases; a gate conductive layer filled within the second trench.
2. The semiconductor device according to claim 1, characterized in that: the semiconductor device further comprises a drain region; the drain region is disposed within the first doped region on one side of the first trench and is spaced apart from the second doped region; or, the drain region is disposed within the substrate at the bottom of the first doped region and is adjacent to the first doped region.
3. The semiconductor device according to claim 1, characterized in that, along the direction away from the second doped region, the depth of the second trench increases linearly.
4. The semiconductor device according to claim 1, characterized in that, the gate conductive layer includes a control gate and a gate field plate, the overlapping portion of the gate conductive layer and the second doped region is the control gate, the non-overlapping portion of the gate conductive layer and the second doped region is the gate field plate, and along the direction away from the second doped region, the depth of the bottom of the gate field plate gradually increases.
5. The semiconductor device according to claim 4, characterized in that, the bottom of the gate field plate is an inclined plane and is disposed at an acute angle to a first direction; the first direction is parallel to the thickness direction of the substrate.
6. The semiconductor device according to any one of claims 1-5, characterized in that, the semiconductor device further comprises a split gate conductive layer, the split gate conductive layer is embedded within the dielectric layer within the first trench and is located on the side of the second trench away from the substrate surface.
7. A method for manufacturing a semiconductor device, characterized in that, comprising: providing a substrate; forming a first doped region within the substrate; forming a first trench within the first doped region that opens from the surface of the first doped region and extends along the thickness direction of the substrate, and forming a dielectric layer within the first trench; forming a second trench on the dielectric layer by using a single-step etching process, the second trench opening from the surface of the dielectric layer and extending along the thickness direction of the substrate; forming a gate conductive layer within the second trench, forming a second doped region within the first doped region and on one side of the first trench, and forming a source region within the second doped region; wherein, along the direction away from the second doped region, the depth of the second trench gradually increases.
8. The method for manufacturing a semiconductor device according to claim 7, characterized in that, The step of forming a first trench that opens from the surface of the first doping region and extends along the thickness direction of the substrate in the first doping region, and forming a dielectric layer in the first trench, includes: Forming a first mask layer having a first etching window on the substrate; Forming the first trench based on the first etching window; Forming the dielectric layer in the first trench.
9. The method for manufacturing a semiconductor device according to claim 8, wherein, the step of forming the dielectric layer in the first trench includes: Forming a first sub-dielectric layer in the first trench by using a thermal oxidation process; the first sub-dielectric layer includes a first sub-part and a second sub-part, the first sub-part covers the sidewall of the first trench, and the second sub-part covers the bottom wall of the first trench; at least a part of the first sub-part is covered by the orthographic projection of the first mask layer on the substrate; Forming a split gate conductive layer in the first trench; Forming a second sub-dielectric layer in the first trench, and the first sub-dielectric layer and the second sub-dielectric layer together constitute the dielectric layer.
10. The method for manufacturing a semiconductor device according to claim 9, wherein, the step of forming a second trench that opens from the surface of the dielectric layer and extends along the thickness direction of the substrate by using a single-step etching process includes: Forming a second mask layer having a second etching window on the first mask layer, the second etching window exposes a part of the second sub-dielectric layer, and exposes the first mask layer above the first sub-part connected to the part of the second sub-dielectric layer; Forming the second trench on the dielectric layer by using a dry etching process.