Semiconductor structure and preparation method thereof

Abstract

The invention relates to a semiconductor structure and a preparation method thereof, and the method comprises the steps: providing a substrate, and forming an injection layer on the substrate; forming a buffer layer and a drift layer on the injection layer, and performing laser annealing on the buffer layer and the drift layer from one side away from the substrate; a plurality of conductive channel units arranged at intervals are formed on the upper surface layer of the drift layer, laser annealing is conducted on the conductive channel units from the side away from the substrate, and each conductive channel unit comprises a well region, an emitter region and a contact region, forming a gate structure above the well region; removing the substrate to expose the injection layer; laser annealing is carried out on the injection layer from the side, away from the buffer layer, of the injection layer, and laser wavelengths used in laser annealing of the buffer layer, the drift layer, the conductive channel unit and the injection layer are selected based on light absorption characteristic parameters of the injection layer, the buffer layer and the drift layer. According to the semiconductor structure and the preparation method thereof, the formation of parasitic capacitance is reduced, and the device performance is improved.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and particularly to a semiconductor structure and a method for preparing the same. Background Art

[0002] When designing semiconductor power devices, it is necessary to minimize the on-resistance, reduce the reverse leakage current, and have a fast switching speed under the specified blocking voltage, so as to reduce the conduction loss and switching loss during operation. Silicon carbide (SiC) is considered an excellent material for power switching devices due to its wide energy gap (the bandgap energy of 4H-SiC can reach 3.3 eV), high critical breakdown electric field strength, and high thermal conductivity.

[0003] With the continuous in-depth understanding of SiC devices, the development of SiC devices has evolved from the most commonly used unipolar semiconductor devices, trench-gate metal-oxide-semiconductor field-effect transistors (MOSFETs) or double-injected MOSFETs to the currently more advanced SiC (insulated-gate bipolar transistor) IGBT architecture. IGBT devices have two types: P-channel and N-channel. The P-channel IGBT can be regarded as a hybrid of a P-channel MOSFET and an NPN bipolar transistor, and the N-channel IGBT can be regarded as a hybrid of an N-channel MOSFET and a PNP transistor.

[0004] Compared with the P-channel IGBT, the N-channel IGBT has the characteristic of being compatible with existing power electronic systems and is the currently widely used type. However, the annealing process of N-channel SiC IGBT devices in an Ar environment at 1650°C has problems such as carbon precipitation, a high thermal budget, and obvious parasitic capacitance, especially in N-channel SiC IGBT devices. Therefore, a new process is needed to improve the performance, stability, and consistency of N-channel SiC IGBT devices. Summary of the Invention

[0005] Based on this, it is necessary to provide a semiconductor structure and a method for preparing the same to solve the problem that the thermal budget of N-channel IGBT devices in the prior art is too high and the parasitic capacitance is obvious, resulting in a decline in device performance.

[0006] To achieve the above object, on the one hand, this application provides a semiconductor structure, including the following steps:

[0007] Provide a substrate of a first conductivity type, and form an implantation layer of a second conductivity type on the substrate;

[0008] A buffer layer of a first conductivity type and a drift layer of a first conductivity type are sequentially formed on the injection layer, and laser annealing is performed on the buffer layer and the drift layer from a side far away from the substrate;

[0009] A plurality of conductive channel units arranged at intervals are formed on the upper surface layer of the drift layer, and laser annealing is performed on the conductive channel units from a side far away from the substrate. The conductive channel units include a well region of a second conductivity type, an emitter region of a first conductivity type, and a contact region of a second conductivity type. The emitter region and the contact region are located on the upper surface layer of the well region and the emitter region is adjacent to the contact region;

[0010] A gate structure is formed above the well region;

[0011] The substrate is removed to expose the injection layer;

[0012] Laser annealing is performed on the injection layer from a side of the injection layer far away from the buffer layer.

[0013] In one embodiment, the forming of the buffer layer of a first conductivity type and the drift layer of a first conductivity type on the injection layer and performing laser annealing on the buffer layer and the drift layer from a side far away from the substrate includes:

[0014] The buffer layer is epitaxially formed on the injection layer;

[0015] Laser annealing is performed on the buffer layer from a side far away from the substrate;

[0016] The drift layer is epitaxially formed on the buffer layer;

[0017] Laser annealing is performed on the drift layer from a side far away from the substrate, wherein the laser wavelengths used for performing laser annealing on the buffer layer and the drift layer, performing laser annealing on the conductive channel units, and performing laser annealing on the injection layer are respectively selected based on the light absorption characteristic parameters of the injection layer, the buffer layer, and the drift layer.

[0018] In one embodiment, the forming of a plurality of conductive channel units arranged at intervals on the upper surface layer of the drift layer and performing laser annealing on the conductive channel units includes:

[0019] A plurality of the well regions arranged at intervals are formed on the upper surface layer of the drift layer;

[0020] Laser annealing is performed on the well regions from a side far away from the substrate:

[0021] The emitter region is formed on the upper surface layer of the well region;

[0022] Perform laser annealing on the emitter region from a side away from the substrate;

[0023] Form the contact region adjacent to the emitter region on the upper surface layer of the well region;

[0024] Perform laser annealing on the contact region from a side away from the substrate.

[0025] In one embodiment, the depth of the contact region is greater than that of the emitter region.

[0026] In one embodiment, the orthographic projection of the emitter region on the substrate is located outside the orthographic projection of the gate structure on the substrate.

[0027] In one embodiment, the materials of the implantation layer, the buffer layer, and the drift layer are all silicon carbide.

[0028] In one embodiment, the laser wavelength used for laser annealing of the buffer layer and the drift layer, laser annealing of the conductive channel units, and laser annealing of the implantation layer is 369 nm to 516 nm.

[0029] In one embodiment, after forming a plurality of spaced-apart conductive channel units on the upper surface layer of the drift layer and performing laser annealing on the conductive channel units, it further includes:

[0030] Form a first-conductivity-type ion implantation region between adjacent well regions of the drift layer;

[0031] Perform laser annealing on the ion implantation region from a side away from the substrate.

[0032] In one embodiment, after forming the gate structure located above the well region, it further includes:

[0033] Form an emitter electrically connected to the contact region;

[0034] Before performing laser annealing on the implantation layer from a side of the implantation layer away from the buffer layer, it further includes:

[0035] Form a collector on a side of the implantation layer away from the buffer layer.

[0036] This application also provides a semiconductor structure, which is prepared by using the preparation method of the semiconductor structure as described in any one of the above, and includes:

[0037] An implantation layer of a second conductivity type;

[0038] A buffer layer of a first conductivity type and a drift layer of a first conductivity type are sequentially stacked above the injection layer;

[0039] A plurality of conductive channel units are spaced apart and disposed on the upper surface layer of the drift layer. The conductive channel units include a well region of a second conductivity type, an emitter region of a first conductivity type, and a contact region of a second conductivity type. The emitter region and the contact region are located on the upper surface layer of the well region and the emitter region is adjacent to the contact region;

[0040] A gate structure is located above the well region.

[0041] In the above semiconductor structure and its manufacturing method, a buffer layer and a drift layer are sequentially formed on the injection layer, and laser annealing is performed on the buffer layer and the drift layer from the side far from the substrate, so as to form a plurality of conductive channel units spaced apart on the upper surface layer of the drift layer. Then, laser annealing is performed on the conductive channel units from the side far from the substrate, and laser annealing is performed on the injection layer from the side far from the buffer layer of the injection layer. That is, the laser annealing process is used to process the semiconductor structure from both the front and the back. Combining the characteristics of laser annealing to perform high-temperature heating on a specific area in a very short time, it avoids the long-time high-temperature treatment in the traditional annealing method, reduces the thermal damage and thermal diffusion of the non-target area caused by the thermal influence, effectively repairs the lattice damage caused by ion implantation, improves the activation efficiency of impurity atoms, thereby reducing electron scattering, increasing the channel mobility, reducing the on-resistance, reducing the formation of parasitic capacitance, and improving the device performance; In addition, by setting that the laser wavelengths used for laser annealing of the buffer layer and the drift layer, laser annealing of the conductive channel units, and laser annealing of the injection layer are respectively selected based on the light absorption characteristic parameters of the injection layer, the buffer layer, and the drift layer. That is, by selecting a laser wavelength that matches the light absorption characteristics of the material, it can ensure that the material can absorb laser energy more efficiently, so as to reach the required high temperature in a shorter time, improving the annealing efficiency and the activation efficiency of doped atoms, and effectively improving the repair quality of the lattice damage caused by ion implantation. Description of the Drawings

[0042] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings required for use in the description of the embodiments or the prior art. Obviously, the drawings in the following description are only some embodiments of the present application. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained based on these drawings.

[0043] Figure 1 It is a flowchart of a method for manufacturing a semiconductor structure provided in an embodiment;

[0044] Figure 2Schematic cross-sectional structure diagram after forming an implantation layer, a buffer layer, and a drift layer in a method for manufacturing a semiconductor structure provided in an embodiment;

[0045] Figure 3 Schematic cross-sectional structure diagram after forming a conductive channel unit in a method for manufacturing a semiconductor structure provided in an embodiment;

[0046] Figure 4 Schematic cross-sectional structure diagram after forming a gate structure in a method for manufacturing a semiconductor structure provided in an embodiment;

[0047] Figure 5 Schematic cross-sectional structure diagram after forming a sidewall in a method for manufacturing a semiconductor structure provided in an embodiment;

[0048] Figure 6 Schematic cross-sectional structure diagram after forming an emitter in a method for manufacturing a semiconductor structure provided in an embodiment;

[0049] Figure 7 Schematic cross-sectional structure diagram after removing a substrate in a method for manufacturing a semiconductor structure provided in an embodiment;

[0050] Figure 8 Schematic cross-sectional structure diagram after forming a collector in a method for manufacturing a semiconductor structure provided in an embodiment.

[0051] Explanation of reference numerals:

[0052] 1 - Substrate, 2 - Implantation layer, 3 - Buffer layer, 4 - Drift layer, 5 - Conductive channel unit, 51 - Well region, 52 - Emitter region, 53 - Contact region, 6 - Gate structure, 61 - Gate dielectric layer, 62 - Gate layer, 7 - Sidewall, 8 - Emitter, 81 - Isolation layer, 82 - Contact hole, 83 - Contact layer, 9 - Collector. Detailed implementation manners

[0053] To facilitate understanding of the present application, the present application will be described more comprehensively below with reference to the relevant drawings. Embodiments of the present application are shown in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, these embodiments are provided to make the disclosure of the present application more thorough and comprehensive.

[0054] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those of ordinary skill in the technical field to which this application belongs. The terms used in the description of the present application herein are only for the purpose of describing specific embodiments and are not intended to limit the present application.

[0055] It should be understood that when an element or layer is referred to as "on", "adjacent to", "connected to", or "coupled to" another element or layer, it can be directly on, adjacent to, connected or coupled to the other element or layer, or there may be intervening elements or layers. In contrast, when an element is referred to as "directly on", "directly adjacent to", "directly connected to", or "directly coupled to" another element or layer, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, doping types, and / or portions, these elements, components, regions, layers, doping types, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, doping type, or portion from another element, component, region, layer, doping type, or portion. Thus, without departing from the teachings of this application, the first element, component, region, layer, doping type, or portion discussed below may be denoted as the second element, component, region, layer, or portion; for example, the first doping type may be referred to as the second doping type, and similarly, the second doping type may be referred to as the first doping type; the first doping type and the second doping type are different doping types. For instance, the first doping type may be P-type and the second doping type may be N-type, or the first doping type may be N-type and the second doping type may be P-type.

[0056] Spatial relationship terms such as "under", "below", "lower", "beneath", "above", "upper", etc. may be used herein to describe the relationship of one element or feature shown in the figures to other elements or features. It should be understood that, in addition to the orientation shown in the figures, spatial relationship terms also include different orientations of the device in use and operation. For example, if the device in the figures is flipped, an element or feature described as "under" or "beneath" or "below" another element or feature will be oriented "on" the other element or feature. Thus, the exemplary terms "under" and "below" can include both an upper and a lower orientation. In addition, the device may also include additional orientations (such as rotating 90 degrees or other orientations), and the spatial descriptors used herein are to be interpreted accordingly.

[0057] As used herein, the singular forms "a", "an", and "the" may also include the plural forms unless the context clearly dictates otherwise. It should also be understood that the terms "comprises / include" or "has" etc. specify the presence of the stated features, integers, steps, operations, components, parts, or combinations thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, components, parts, or combinations thereof. At the same time, in this specification, the term "and / or" includes any and all combinations of the related listed items.

[0058] Please refer to Figure 1 , this application provides a method for manufacturing a semiconductor structure, including the following steps:

[0059] Step S1: Provide a substrate 1 of the first conductivity type, and form an implantation layer 2 of the second conductivity type on the substrate 1;

[0060] Step S2: Sequentially form a buffer layer 3 of the first conductivity type and a drift layer 4 of the first conductivity type on the implantation layer, and perform laser annealing on the buffer layer 3 and the drift layer 4 from the side away from the substrate 1;

[0061] Step S3: Form a plurality of spaced-apart conductive channel units 5 on the upper surface layer of the drift layer 4, and perform laser annealing on the conductive channel units 5 from the side away from the substrate 1. The conductive channel units 5 include a well region 51 of the second conductivity type, an emitter region 52 of the first conductivity type, and a contact region 53 of the second conductivity type. The emitter region 52 and the contact region 53 are located on the upper surface layer of the well region 51 and the emitter region 52 is adjacent to the contact region 53;

[0062] Step S4: Form a gate structure 6 above the well region 51;

[0063] Step S5: Remove the substrate 1 to expose the implantation layer 2;

[0064] Step S6: Perform laser annealing on the implantation layer 2 from the side of the implantation layer away from the buffer layer 3. Among them, the laser wavelengths used for performing laser annealing on the buffer layer 3 and the drift layer 4, performing laser annealing on the conductive channel units 5, and performing laser annealing on the implantation layer 2 are selected based on the light absorption characteristic parameters of the implantation layer 2, the buffer layer 3, and the drift layer 4, respectively.

[0065] In the above example, by sequentially forming a buffer layer 3 and a drift layer 4 on the injection layer 2, and performing laser annealing on the buffer layer 3 and the drift layer 4 from the side away from the substrate 1, a plurality of conductive channel units 5 arranged at intervals are formed on the upper surface layer of the drift layer 4, and laser annealing is performed on the conductive channel units 5 from the side away from the substrate 1, and laser annealing is performed on the injection layer 2 from the side of the injection layer away from the buffer layer 3, that is, laser annealing is used to process the semiconductor structure from both the front and the back. Combining the characteristic of laser annealing to perform high-temperature heating on a specific area in an extremely short time, it avoids the long-time high-temperature treatment in the traditional annealing method, reduces the thermal damage and thermal diffusion of the thermal influence on non-target areas, effectively repairs the lattice damage caused by ion implantation, improves the activation efficiency of impurity atoms, thereby reducing electron scattering, increasing the channel mobility, reducing the on-resistance, reducing the formation of parasitic capacitance, and improving the device performance. In addition, by setting that the laser wavelengths used for laser annealing of the buffer layer 3 and the drift layer 4, laser annealing of the conductive channel units 5, and laser annealing of the injection layer 2 are respectively selected based on the light absorption characteristic parameters of the injection layer 2, the buffer layer 3, and the drift layer 4, that is, by selecting a laser wavelength matching the light absorption characteristics of the material, it can be ensured that the material can absorb laser energy more efficiently, so as to reach the required high temperature in a shorter time, improving the annealing efficiency and the activation efficiency of doped atoms, and effectively improving the repair quality of the lattice damage caused by ion implantation.

[0066] Specifically, please refer to Figure 2 , perform steps S1 to S2, provide a substrate 1 of a first conductivity type, and form an injection layer 2 of a second conductivity type on the substrate 1; sequentially form a buffer layer 3 of the first conductivity type and a drift layer 4 of the first conductivity type on the injection layer 2, and perform laser annealing on the buffer layer 3 and the drift layer 4 from the side away from the substrate 1.

[0067] Specifically, the first conductivity type includes one of N-type or P-type, the second conductivity type includes one of N-type or P-type, and the conductivity types of the first conductivity type and the second conductivity type are opposite. In this embodiment, the second conductivity type is P-type and the first conductivity type is N-type to form an N-channel IGBT device.

[0068] Exemplarily, the substrate 1 serves as an initial support substrate for epitaxial growth of subsequent semiconductor layers. The material of the substrate 1 includes silicon carbide (SiC) or other suitable materials. The doping concentration of the substrate 1 can be selected according to actual situations and is not limited herein.

[0069] Exemplarily, the main function of the injection layer 2 is to inject hole carriers into the drift layer 4 to form a conductivity modulation effect, thereby reducing the on-state voltage drop. The buffer layer 3 is located between the injection layer 2 and the drift layer 4, which is used to optimize the electric field distribution, reduce the dynamic loss during turn-off, and suppress the punch-through effect. The drift layer 4 is the core voltage blocking layer. During conduction, the drift layer 4 reduces the resistance through the conductivity modulation effect (double injection of electrons and holes) to achieve a large current capacity.

[0070] Exemplarily, the injection layer 2 is epitaxially formed on the substrate 1. The method for forming the injection layer 2 includes chemical vapor deposition or other suitable methods. The doping concentration of the injection layer 2 is 1.6×10 17 cm -3 ~1.9×10 17 cm -3 . The thickness of the injection layer 2 can be set according to the actual situation and is not limited here. The material of the injection layer 2 includes silicon carbide or other suitable materials.

[0071] In one embodiment, as Figure 2 shown, the buffer layer 3 and the drift layer 4 are sequentially formed on the injection layer 2, and laser annealing is performed on the buffer layer 3 and the drift layer 4 from the side away from the substrate 1, including:

[0072] Epitaxially form the buffer layer 3 on the injection layer; the method for forming the buffer layer 3 includes chemical vapor deposition or other suitable methods. The doping concentration of the buffer layer 3 is 1.0×10 17 cm -3 ~2.0×10 17 cm -3 . The material of the buffer layer 3 includes silicon carbide or other suitable materials; the thickness range of the buffer layer 3 is 40μm - 60μm. In this embodiment, the thickness of the buffer layer 3 is 50μm;

[0073] Perform laser annealing on the buffer layer 3 from the side away from the substrate 1;

[0074] Epitaxially form the drift layer 4 on the buffer layer 3; the method for forming the drift layer 4 includes chemical vapor deposition or other suitable methods. The doping concentration of the drift layer 4 is 2.8×10 14 cm -3 ~3.1×10 14 cm -3 . The material of the drift layer 4 includes silicon carbide or other suitable materials; the thickness range of the drift layer 4 is 90μm - 120μm. In this embodiment, the thickness of the drift layer 4 is 100μm; among them, the silicon carbide material has a wide bandgap, high breakdown voltage, high thermal conductivity, and high-frequency characteristics, and can be used as a good basis for optimizing the breakdown voltage and on-resistance of the device;

[0075] Laser annealing is performed on the drift layer 4 from the side away from the substrate 1. Laser annealing has the characteristic of local heating, which can greatly reduce the thermal budget; the thermal action time of laser annealing is short, which can quickly activate the doped atoms in the buffer layer and the drift layer, improve the process efficiency, and at the same time avoid the lateral / longitudinal diffusion of impurities caused by traditional high-temperature furnace annealing, maintain a steep doping gradient, and ensure the sudden change of the interface concentration between the buffer layer 3 and the drift layer 4; laser annealing can also repair the lattice damage caused by ion implantation in the buffer layer and the drift layer through a rapid melting-recrystallization process, reduce the grain boundary and defect density, reduce carrier scattering, thereby improving the electron / hole mobility and reducing the on-resistance.

[0076] In addition, due to the different thicknesses and doping concentrations of the buffer layer 3 and the drift layer 4, the laser annealing of the buffer layer 3 and the drift layer 4 is carried out separately. A laser with a higher energy density is used for the relatively highly doped buffer layer 3 to ensure that the doped ions are fully activated; a laser with a lower energy density is used for the relatively low-doped drift layer 4 to avoid lattice defects caused by overheating, ensure the repair of lattice damage and maintain low-doping stability. In the subsequent process, the activation requirements of the high- and low-doping regions can be balanced by further dynamically adjusting the laser energy and pulse time; the wavelength and scanning strategy can be optimized to solve the penetration depth and thermal distribution problems; pre-compensated doping or segmented processing can be used to make up for the uneven activation caused by the concentration difference, so as to realize the simultaneous laser annealing of the buffer layer 3 and the drift layer 4 and further improve the process efficiency.

[0077] Specifically, please refer to Figure 3 , perform step S3, form a plurality of conductive channel units 5 arranged at intervals on the upper surface of the drift layer 4, and perform laser annealing on the conductive channel units 5 from the side away from the substrate 1. The conductive channel unit 5 includes a well region 51 of the second conductivity type, an emitter region 52 of the first conductivity type, and a contact region 53 of the second conductivity type. The emitter region 52 and the contact region 53 are located on the upper surface of the well region 51 and the emitter region 52 is adjacent to the contact region 53.

[0078] Exemplarily, the well region 51 is located on the upper surface of the drift layer 4 and is a key region for forming a conductive channel. In this embodiment, when a positive voltage is applied to the gate structure 6, an inversion layer, that is, an N-type channel, will be formed on the surface of the well region 51, so as to realize the conduction of electrons from the emitter region 52 to the drift layer 4. The main function of the emitter region 52 is to provide a large number of electrons, which, under the action of the gate voltage, enter the drift layer 4 through the conductive channel and participate in the conduction process of the device. The main function of the contact region 53 is to inject holes into the drift layer 4 when the device is turned on. These holes recombine with the electrons in the drift layer to further improve the conduction performance of the device and reduce the on-resistance.

[0079] In one embodiment, as Figure 3As shown, a plurality of conductive channel units 5 are formed at intervals on the upper surface of the drift layer 4, and laser annealing is performed on the conductive channel units 5, including:

[0080] A plurality of well regions 51 are formed at intervals on the upper surface of the drift layer 4; the doping concentration of the well regions 51 can be selected according to actual conditions and is not limited here;

[0081] Laser annealing is performed on the well regions 51 from the side away from the substrate 1; wherein, when performing laser annealing on the well regions 51, it also includes forming a first mask (not shown) on the upper surface of the drift layer 4 to protect the regions in the drift layer 4 where the well regions 51 are not formed from being damaged;

[0082] An emitter region 52 is formed on the upper surface of the well regions 51; the doping concentration of the emitter region 52 can be selected according to actual conditions and is not limited here;

[0083] Laser annealing is performed on the emitter region 52 from the side away from the substrate 1; wherein, when performing laser annealing on the emitter region 52, it also includes forming a second mask (not shown) on the upper surface of the drift layer 4 to avoid thermal damage to the regions in the well regions 51 where the emitter region 52 is not formed;

[0084] A contact region 53 adjacent to the emitter region 52 is formed on the upper surface of the well regions 51; the doping concentration of the contact region 53 can be selected according to actual conditions and is not limited here;

[0085] Laser annealing is performed on the contact region 53 from the side away from the substrate 1. Among them, when performing laser annealing on the contact region 53, it also includes forming a third mask (not shown) on the upper surface of the drift layer 4 to avoid thermal damage to the emitter region 52 and well region 51 regions where the contact region 53 is not formed.

[0086] Since the doping concentrations of both the emitter region 52 and the contact region 53 are greater than that of the well region 51, and the conduction type of the emitter region 52 is different from that of both the contact region 53 and the well region 51, therefore, local heating is performed on the well region 51, emitter region 52, and contact region 53 respectively by laser annealing, and the corresponding laser energy density and action time are selected respectively according to the doping concentrations of the well region 51, emitter region 52, and contact region 53. For example, a laser with a lower energy density is selected to perform laser annealing on the well region 51, a laser with a higher energy density is selected to perform laser annealing on the emitter region 52, and a laser with a high energy density is selected to perform laser annealing on the contact region 53.

[0087] Compared with traditional annealing (such as furnace annealing or RTA), the local heating of laser annealing can avoid thermal damage to adjacent structures, and through the instant high temperature of laser annealing, repair the lattice damage caused by ion implantation, activate impurity atoms, form stable electrical characteristics, can increase the impurity activation rate to more than 60%, and can maintain the peak concentration of doped ions close to the theoretical value at the time of implantation. For example, after forming the emitter region 52 and performing laser annealing, the surface ion doping activation concentration can reach 1.0×10 19 cm -3 ~1.0×10 20 cm -3 。

[0088] In addition, in the subsequent process, the laser annealing of the well region 51, the emitter region 52 and the contact region 53 can also be adjusted and optimized according to the corresponding characteristics of the well region 51, the emitter region 52 and the contact region 53, so as to complete the processing of the well region 51, the emitter region 52 and the contact region 53 in one or very few laser annealings, reduce the process steps, and improve the device performance at the same time.

[0089] In one embodiment, the depth of the contact region 53 is greater than that of the emitter region. During the conduction process, holes can be more effectively injected into the drift layer 4. These holes, as minority carriers, can significantly increase the carrier concentration of the drift layer 4, thereby reducing the resistance of the drift layer 4, improving the conduction performance of the device, and suppressing the latch-up effect.

[0090] In one embodiment, after forming a plurality of conductive channel units 5 arranged at intervals on the upper surface layer of the drift layer 4 and performing laser annealing on the conductive channel units 5, it further includes:

[0091] Forming a first-conductive-type ion implantation region (not shown) between adjacent well regions 51 of the drift layer 4. Among them, the formed ion implantation region can adjust the internal electric field distribution of the device. When the device is conducting, it can increase the uniformity of the electric field, reduce the electric field concentration phenomenon, thereby reducing the on-resistance of the device and improving the conduction performance; when the device is turned off, the ion implantation region can withstand a higher reverse voltage, prevent the device from breakdown, and improve the reliability and stability of the device.

[0092] Specifically, please refer to Figures 4 to 5 , perform step S4 to form the gate structure 6 located above the well region 51.

[0093] In one embodiment, as Figure 4 shown, forming the gate structure 6 located above the well region 51 includes:

[0094] A gate dielectric layer 61 is formed over the well region 51 and the drift layer 4; wherein, the material of the gate dielectric layer 61 includes silicon oxynitride, which has a relatively high dielectric constant. The method for forming the gate dielectric layer 61 includes atomic layer deposition, which can achieve thickness and uniformity control at the atomic level. The thickness of the gate dielectric layer 61 is 45 nm to 55 nm;

[0095] A gate electrode layer 62 is formed over the gate dielectric layer 61; the method for forming the gate electrode layer 62 includes chemical vapor deposition or other suitable methods. The gate electrode layer 62 is doped polysilicon, that is, the semiconductor characteristics of the polysilicon gate electrode layer 62 enable its work function to be flexibly adjusted by subsequent doping, and it matches the thermal expansion coefficient of other structures of the device, reducing the interface stress.

[0096] In one embodiment, the orthographic projection of the emitter region 52 on the substrate 1 is located outside the orthographic projection of the gate structure 6 on the substrate 1. That is, the non - overlapping of the gate structure 6 and the emitter region 52 can reduce the coupling capacitance between the two, and can significantly shorten the turn - on and turn - off delay times.

[0097] In one embodiment, as Figure 5 shown, after forming the gate structure 6 over the well region 51, it further includes:

[0098] A sidewall 7 covering the sidewalls of the gate structure 6 is formed. The sidewall 7 is formed by depositing multiple dielectric layers and anisotropic etching. The sidewall 7 is used to protect the interface between the gate structure 6 and the drift layer 4, ensure the stability of the conductance modulation effect, and reduce the on - state voltage drop.

[0099] In one embodiment, after forming the gate structure 6 over the well region 51, it further includes forming an emitter 8 electrically connected to the contact region 53.

[0100] In one embodiment, as Figure 6 shown, forming the emitter 8 electrically connected to the contact region 53 includes:

[0101] An isolation layer 81 covering the gate structure 6 is formed on the upper surface of the drift layer 4; the material of the isolation layer 81 includes at least one of silicon dioxide and silicon nitride. The method for forming the isolation layer 81 includes chemical vapor deposition or other suitable methods. The isolation layer 81 can isolate the conductive channel unit 5 and the gate structure 6, passivate the surface defects of the semiconductor, and provide a guarantee for the subsequent formation of the lead - out circuit;

[0102] A contact hole 82 with the contact region 53 exposed at the bottom is formed in the isolation layer 81; the method for forming the contact hole 82 includes dry etching, wet etching or other suitable methods;

[0103] Form a contact layer 83 to fill the contact hole 82; the method of forming the contact layer 83 includes physical vapor deposition, chemical vapor deposition or other suitable methods. The contact layer 83 includes nickel, titanium, titanium nitride, tungsten. The contact layer achieves ohmic contact through nickel and anti-diffusion filling design through titanium, titanium nitride, and tungsten, realizing low-resistance and highly reliable connection;

[0104] Form an emitter 8 to cover the upper surface of the contact layer 83. The material of the emitter 8 includes copper, aluminum and other suitable materials. The method of forming the emitter 8 includes evaporation sputtering or other suitable methods. As the connection channel between the conductive channel unit 5 and the external circuit, the interconnection between the conductive channel units 5 is completed.

[0105] In one embodiment, a contact hole 82 exposing the gate layer 62 and a contact layer 83 filling the contact hole 82 are further formed in the isolation layer 81 for realizing the electrical signal transmission between the gate structure 6 and the external circuit structure.

[0106] In one embodiment, after forming the contact layer 83, a step of laser annealing is further included to form a stable ohmic contact between the contact layer 83 made of metal material and the contact region 53 and the gate layer 62 made of semiconductor material.

[0107] Specifically, please refer to Figure 7 , perform step S5 to remove the substrate 1 to expose the implanted layer 2.

[0108] In one embodiment, as Figure 7 shown, the method of removing the substrate 1 includes chemical mechanical polishing, wet etching, dry etching or other suitable methods.

[0109] In one embodiment, while removing the substrate 1, the implanted layer 2 is also thinned so that the thickness of the implanted layer 2 meets the required thickness.

[0110] Specifically, please refer to Figure 8 , perform step S6 to perform laser annealing on the implanted layer 2 from the side of the implanted layer away from the buffer layer 3.

[0111] In one embodiment, as Figure 8 shown, before performing laser annealing on the implanted layer 2 from the side of the implanted layer away from the buffer layer 3, it further includes:

[0112] Form a collector 9 on the side of the implanted layer 2 away from the buffer layer 3. The collector 9 is deposited by sputtering or evaporation process, and the material of the collector 9 includes aluminum, titanium, silver, nickel or other suitable materials.

[0113] Among them, the local high temperature of the injection layer 2 is rapidly activated by laser annealing to reduce the lateral diffusion of impurity atoms, form a steep doping concentration gradient to meet the ohmic contact requirements, and at the same time repair the lattice damage caused by ion implantation, reduce the leakage current and increase the breakdown voltage.

[0114] Exemplarily, the laser wavelength used for laser annealing of the buffer layer 3, the drift layer 4, the conductive channel unit 5, and the injection layer 2 is 369 nm to 516 nm. This is because the silicon carbide material used for the injection layer 2, the buffer layer 3, and the drift layer 4 in this application is a material with a wide bandgap, and its bandgap energy is between 2.36 eV and 3.3 eV. Then, according to , where represents the photon energy, with the unit of joule (J) or electron volt (eV), and , is Planck's constant, , represents the frequency of light, represents the speed of light in a vacuum, , represents the wavelength of light. Then, when , When , , a laser with an emitted laser wavelength of 369 nm to 516 nm can be used to implement the laser annealing process. And in the actual production and testing process, using the above wavelength for laser annealing can effectively improve the activation rate of doped atoms and the order degree of atomic arrangement.

[0115] Therefore, during the annealing process, selecting the laser wavelength for annealing based on the light absorption characteristics (such as bandgap energy) of the buffer layer 3, the drift layer 4, the conductive channel unit 5, and the injection layer 2 can ensure that the material can absorb laser energy more efficiently, so as to reach the required high temperature in a shorter time, improve the annealing efficiency and the activation efficiency of doped atoms, and effectively improve the repair quality of the lattice damage caused by ion implantation.

[0116] In one embodiment, the present application further provides a semiconductor structure, and the semiconductor structure is prepared by using the preparation method of the semiconductor structure as described above, including: an injection layer 2 of a second conductivity type, a buffer layer 3 of a first conductivity type, a drift layer 4 of a first conductivity type, a conductive channel unit 5, and a gate structure 6, wherein the buffer layer 3 and the drift layer 4 are sequentially stacked on the injection layer 2; a plurality of conductive channel units 5 are spaced on the upper surface of the drift layer 4, and the conductive channel unit 5 includes a well region 51 of a second conductivity type, an emitter region 52 of a first conductivity type, and a contact region 53 of a second conductivity type, and the emitter region 52 and the contact region 53 are located on the upper surface of the well region 51 and the emitter region 52 is adjacent to the contact region 53; the gate structure 6 is located above the well region 51.

[0117] Exemplarily, the semiconductor structure further includes an emitter 8 and a collector 9, the emitter 8 is electrically connected to the contact region 53, and the collector 9 is located on a side of the injection layer 2 away from the buffer layer 3.

[0118] In the above example, the semiconductor structure prepared by using the preparation method of the semiconductor structure as described above has a low on-resistance and parasitic capacitance, and excellent device performance.

[0119] In the description of this specification, the descriptions with reference to the terms "some embodiments", "other embodiments", "ideal embodiments", etc. mean that the specific features, structures, materials or features described in connection with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic descriptions of the above terms do not necessarily refer to the same embodiment or example.

[0120] The technical features of the above embodiments can be combined arbitrarily. For the sake of brevity of description, not all possible combinations of the technical features of the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, it should be considered as the scope recorded in this specification.

[0121] The above-described embodiments only represent several implementation manners of the present application, and their descriptions are relatively specific and detailed, but should not be construed as a limitation on the scope of the patent application. It should be noted that for those of ordinary skill in the art, without departing from the concept of the present application, several modifications and improvements can still be made, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent of the present application should be subject to the appended claims.

Claims

1. A method for preparing a semiconductor structure, characterized in that: The steps include: Providing a substrate of a first conductivity type, and forming an injection layer of a second conductivity type on the substrate; forming a buffer layer of the first conductivity type and a drift layer of the first conductivity type on the injection layer in sequence, and performing laser annealing on the buffer layer and the drift layer from a side away from the substrate; A plurality of conductive channel units are formed at intervals on the upper surface of the drift layer, and the conductive channel units are laser annealed from a side away from the substrate, wherein the conductive channel units include a well region of the second conductivity type, an emitter region of the first conductivity type, and a contact region of the second conductivity type, wherein the emitter region and the contact region are located on the upper surface of the well region and the emitter region is adjacent to the contact region; forming a gate structure located above the well region; removing the substrate to reveal the implant layer; The injection layer is laser annealed from a side of the injection layer away from the buffer layer, wherein the laser wavelengths used in laser annealing the buffer layer and the drift layer, laser annealing the conductive channel unit, and laser annealing the injection layer are selected based on light absorption characteristic parameters of the injection layer, the buffer layer, and the drift layer, respectively.

2. The method for preparing a semiconductor structure according to claim 1, characterized in that: The step of sequentially forming a buffer layer of the first conductivity type and a drift layer of the first conductivity type on the injection layer, and performing laser annealing on the buffer layer and the drift layer from a side away from the substrate comprises: epitaxially forming the buffer layer on the injection layer; performing laser annealing on the buffer layer from a side away from the substrate; epitaxially forming the drift layer on the buffer layer; The drift layer is laser annealed from a side away from the substrate.

3. The method for preparing a semiconductor structure according to claim 1, characterized in that: The step of forming a plurality of conductive channel units spaced apart from each other on the upper surface of the drift layer and performing laser annealing on the conductive channel units comprises: forming a plurality of the well regions spaced apart from each other on the upper surface of the drift layer; Laser annealing the well region from a side away from the substrate: forming the emitter region on the upper surface of the well region; performing laser annealing on the emitting region from a side away from the substrate; forming the contact region adjacent to the emitter region on the upper surface of the well region; The contact region is laser annealed from a side facing away from the substrate.

4. The method for preparing a semiconductor structure according to claim 1, characterized in that: The contact region has a depth greater than that of the emitter region.

5. The method for preparing a semiconductor structure according to claim 1, characterized in that: An orthographic projection of the emitter region on the substrate is located outside an orthographic projection of the gate structure on the substrate.

6. The method for preparing a semiconductor structure according to claim 1, characterized in that: The injection layer, the buffer layer and the drift layer are all made of silicon carbide.

7. The method for preparing a semiconductor structure according to claim 6, characterized in that: The laser wavelength used when laser annealing is performed on the buffer layer and the drift layer, laser annealing is performed on the conductive channel unit, and laser annealing is performed on the injection layer is 369nm-516nm.

8. The method for preparing a semiconductor structure according to claim 1, characterized in that: After forming a plurality of conductive channel units spaced apart on the upper surface of the drift layer and laser annealing the conductive channel units, the method further comprises: forming an ion implantation region of a first conductivity type between adjacent well regions of the drift layer; The ion implantation region is laser annealed from a side away from the substrate.

9. The method for preparing a semiconductor structure according to claim 1, characterized in that: After forming the gate structure located above the well region, the method further includes: forming an emitter electrode electrically connected to the contact region; Before laser annealing the injection layer from a side of the injection layer away from the buffer layer, the method further comprises: A collector is formed on a side of the injection layer away from the buffer layer.

10. A semiconductor structure, characterized in that: The semiconductor structure is prepared by the method for preparing a semiconductor structure according to any one of claims 1 to 9, comprising: an injection layer of a second conductivity type; A buffer layer of the first conductivity type and a drift layer of the first conductivity type are sequentially stacked above the injection layer; A plurality of conductive channel units are arranged at intervals on the upper surface layer of the drift layer, the conductive channel units include a well region of the second conductivity type, an emitter region of the first conductivity type and a contact region of the second conductivity type, the emitter region and the contact region are located on the upper surface layer of the well region and the emitter region is adjacent to the contact region; The gate structure is located above the well region.

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