Semiconductor structure, method of manufacturing the same, and electronic device

Abstract

The application relates to a semiconductor structure and a manufacturing method thereof and an electronic device, the semiconductor structure comprising: a substrate; a word line arranged on the substrate and extending in a direction perpendicular to the substrate; a multilayer storage unit array arranged in the direction perpendicular to the substrate, each layer of the storage unit array comprising a plurality of active channels arranged in a first direction, the plurality of active channels being arranged at intervals in the extension direction of the word line, and the active channels covering part of the circumferential surface of the word line; at least one first active region arranged on one side of the active channel in a second direction and connected with the active channel; at least one second active region arranged on the other side of the active channel in the second direction relative to the at least one first active region and connected with the active channel; and in the first direction, the size of the active channel is greater than at least one of the size of the part of the first active region connected with the active channel and the size of the part of the second active region connected with the active channel, so that the yield and electrical performance of the semiconductor structure are improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of integrated circuits, and in particular to a semiconductor structure, a manufacturing method thereof, and an electronic device. BACKGROUND

[0002] With the development of integrated circuit technology, the critical dimension of devices is increasingly reduced, and the types and quantities of devices contained in a single chip are also increased, so that any slight difference in process production can affect the performance of the devices.

[0003] In order to reduce the cost of products as much as possible, people want to make as many device units as possible on a limited substrate. Since the advent of Moore's Law, the industry has proposed various semiconductor structure designs and process optimizations to meet people's current product needs. SUMMARY

[0004] Based on this, the present application provides a semiconductor structure, a manufacturing method thereof, and an electronic device.

[0005] In a first aspect, the present application provides a semiconductor structure, comprising:

[0006] a substrate;

[0007] a word line, disposed on the substrate, extending in a direction perpendicular to the substrate;

[0008] a plurality of multilayer storage unit arrays arranged in a direction perpendicular to the substrate, each layer of the storage unit array comprising a plurality of active channels arranged in a first direction; a plurality of the active channels are arranged at intervals along the extension direction of the word line, and the active channel covers part of the peripheral surface of the word line;

[0009] at least one first active region, disposed on one side of the active channel in a second direction and connected with the active channel, the first direction and the second direction are both parallel to the substrate, and the first direction and the second direction intersect;

[0010] at least one second active region, disposed on the other side of the active channel in the second direction relative to at least one first active region, and connected with the active channel;

[0011] In the first direction, the size of the active channel is greater than at least one of the size of the part of the first active region connected with the active channel and the size of the part of the second active region connected with the active channel.

[0012] Optionally, a plurality of the first active regions are arranged at intervals in a direction perpendicular to the substrate, and a plurality of the first active regions are connected with the same active channel.

[0013] Optionally, each of the first active regions and each of the active channels are connected one by one in a direction perpendicular to the substrate.

[0014] Optionally, the word line comprises a main body part extending in a direction perpendicular to the substrate and a partition part arranged on a surface of the main body part, the partition part is arranged in a direction perpendicular to the substrate, and the partition part is arranged between the first active regions adjacent in a direction perpendicular to the substrate and / or between the second active regions adjacent in a direction perpendicular to the substrate.

[0015] Optionally, each of the memory cell arrays further comprises:

[0016] a capacitor, the capacitor comprising a first electrode, a dielectric layer and a second electrode, the first electrode comprising a partial structure of the first active region, the dielectric layer covering a surface of the first electrode, and the second electrode covering a surface of the dielectric layer.

[0017] Optionally, the second active region comprises a body part and a connecting part, the body part extending in the first direction, and the connecting part connecting the body part and the active channel.

[0018] Optionally, a plurality of the word lines are arranged in the first direction, and the second active region is provided with a plurality of connecting parts on a side close to the active channel, and the plurality of connecting parts are arranged in the first direction.

[0019] Optionally, in the first direction, a size of the active channel is greater than a size of the connecting part.

[0020] Optionally, the semiconductor structure further comprises:

[0021] a protective layer and a gate insulating layer, the gate insulating layer, the protective layer and the active channel being sequentially arranged in a direction away from the word line.

[0022] In a second aspect, the present application provides an electronic device comprising the semiconductor structure according to the first aspect.

[0023] In a third aspect, the present application provides a method for manufacturing a semiconductor structure, comprising the following steps:

[0024] providing a substrate, forming a stack structure on the substrate, the stack structure comprising a functional layer and a sacrificial layer, the functional layer comprising at least one active material layer, and the functional layer and the sacrificial layer being alternately arranged in a direction perpendicular to the substrate;

[0025] patterning the stack structure, and the active material layer forming an initial active layer;

[0026] forming at least one channel groove, the channel groove penetrating the stack structure in a direction perpendicular to the substrate, the channel groove dividing the initial active layer into a first active region and a second active region;

[0027] forming a semiconductor layer and a word line in the channel groove in sequence;

[0028] etching to remove at least part of the sacrificial layer and part of the semiconductor layer, the semiconductor layer being divided into a plurality of active channels, the plurality of active channels being arranged in a direction perpendicular to the substrate.

[0029] Optionally, after forming the at least one channel groove, the method for manufacturing the semiconductor structure further comprises the following steps:

[0030] removing part of the functional layer or part of the sacrificial layer exposed by the channel groove, forming a recess on the sidewall of the channel groove, the recess being recessed in a direction parallel to the substrate and away from the channel groove;

[0031] the word line comprising a main body portion extending in a stacking direction of the stack structure and a partition portion arranged on a circumferential surface of the main body portion, the partition portion being arranged in the recess, the partition portion being formed between the first active regions adjacent in the stacking direction of the stack structure and / or between the second active regions adjacent in the stacking direction of the stack structure.

[0032] Optionally, in the stacking direction of the stack structure, the functional layer comprises the active material layer and the dielectric layer arranged alternately.

[0033] Optionally, the method for manufacturing the semiconductor structure further comprises the following steps:

[0034] removing part of the dielectric layer to expose part of the sidewall of the first active region covered by the dielectric layer;

[0035] forming a dielectric layer, the dielectric layer covering the exposed sidewall of the first active region;

[0036] forming a second electrode, the second electrode covering the dielectric layer, the second electrode, the dielectric layer and the first active region forming a capacitor.

[0037] Optionally, the second active region extends in a first direction, the second active region being formed with a connecting portion on a side close to the channel groove, the second active region being connected to the active channel through the connecting portion, the first direction being parallel to the substrate.

[0038] Optionally, in the first direction, a size of the active channel is greater than at least one of a size of the first active region and a size of the connection portion.

[0039] Optionally, etching to remove at least part of the sacrificial layer and etching to remove part of the semiconductor layer comprises:

[0040] forming a first via between adjacent word lines, the first via exposing part of a top surface of the substrate;

[0041] etching the sacrificial layer and the semiconductor layer based on the first via until the semiconductor layer between the adjacent functional layers is removed.

[0042] Optionally, the manufacturing method further comprises the following steps:

[0043] forming a protective layer and a gate insulating layer, the gate insulating layer, the protective layer and the semiconductor layer being sequentially arranged in a direction away from the word line.

[0044] The semiconductor structure, the manufacturing method thereof and the electronic device have the following beneficial effects:

[0045] The semiconductor structure has no process residual conductive film layer between adjacent active channels, which can avoid or reduce the problem of parasitic transistors between adjacent transistors in the semiconductor structure, improve the response speed of the semiconductor structure and improve the electrical performance of the semiconductor structure.

[0046] The semiconductor structure can increase the channel length and reduce the short channel effect by changing the size relationship of the source region (S) / the drain region (D) and the channel in the plane, and can also avoid damage to the channel in the process.

[0047] The manufacturing method of the semiconductor structure adjusts the stacking rule of the stacked structure, sets a sacrificial layer between adjacent functional layers, exposes the semiconductor layer connected with the sacrificial layer by removing the sacrificial layer, removes the semiconductor layer connected with the sacrificial layer, divides the whole semiconductor layer into independently arranged active channels, avoids the existence of residual semiconductor layer between adjacent transistors to generate parasitic channels, effectively simplifies the processing technology, increases the critical window value of the process, reduces the process difficulty and improves the yield of the product. BRIEF DESCRIPTION OF DRAWINGS

[0048] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following will briefly introduce the drawings needed to be used in the embodiments. Obviously, the drawings in the following description are only some embodiments of the present application, and those skilled in the art can obtain other drawings according to these drawings without creative labor.

[0049] Figure 1 Flow chart of a method for fabricating a semiconductor structure according to some embodiments.

[0050] Figure 2 Structure diagram of a stack structure formed on a substrate according to some embodiments.

[0051] Figure 3 Cross-sectional view of a stack structure according to some embodiments, taken along line A-A in Figure 2

[0052] Figure 4 Top view of a stack structure after forming an initial active layer according to some embodiments.

[0053] Figure 5 Top view of a stack structure after forming a support layer according to some embodiments.

[0054] Figure 6 Top view of a stack structure after forming a channel trench according to some embodiments.

[0055] Figure 7 Cross-sectional view of a stack structure according to some embodiments, taken along line B-B in Figure 6

[0056] Figure 8 Cross-sectional view of a stack structure according to some embodiments, taken along line B-B in Figure 6

[0057] Figure 9 Cross-sectional view of a stack structure according to some embodiments, taken along line B-B in Figure 6

[0058] Figure 10 Cross-sectional view of a stack structure according to some embodiments, taken along line B-B in Figure 6

[0059] Figure 11 Cross-sectional view of a stack structure according to some embodiments, taken along line B-B in Figure 6

[0060] Figure 12 Cross-sectional view of a stack structure according to some embodiments, taken along line C-C in Figure 6

[0061] Figure 13 Top view of a stack structure after forming a first via according to some embodiments. ​​​​​​​

[0062] Figure 14 A cross-sectional view taken along line C-C of FIG. 1 1, perpendicular to the substrate, after forming the first via for some embodiments. Figure 6 A cross-sectional view taken along line C-C of FIG. 1 1, perpendicular to the substrate, after forming the first via for some embodiments.

[0063] Figure 15 A cross-sectional view taken along line C-C of FIG. 1 1, perpendicular to the substrate, after forming the first via for some embodiments. Figure 6 A cross-sectional view taken along line C-C of FIG. 1 1, perpendicular to the substrate, after forming the first via for some embodiments.

[0064] Figure 16 A cross-sectional view taken along line C-C of FIG. 1 1, perpendicular to the substrate, after forming the first via for some embodiments. Figure 6 A cross-sectional view taken along line C-C of FIG. 1 1, perpendicular to the substrate, after forming the first via for some embodiments.

[0065] Figure 17 A cross-sectional view taken along line C-C of FIG. 1 1, perpendicular to the substrate, after forming the first via for some embodiments. Figure 6 A cross-sectional view taken along line C-C of FIG. 1 1, perpendicular to the substrate, after forming the first via for some embodiments.

[0066] Figure 18 A cross-sectional view taken along line C-C of FIG. 1 1, perpendicular to the substrate, after forming the first via for some embodiments.

[0067] Figure 19 A cross-sectional view taken along line C-C of FIG. 1 1, perpendicular to the substrate, after forming the first via for some embodiments. Figure 6 A cross-sectional view taken along line C-C of FIG. 1 1, perpendicular to the substrate, after forming the first via for some embodiments.

[0068] Figure 20 A cross-sectional view taken along line C-C of FIG. 1 1, perpendicular to the substrate, after forming the first via for some embodiments. Figure 6 A cross-sectional view taken along line C-C of FIG. 1 1, perpendicular to the substrate, after forming the first via for some embodiments.

[0069] Figure 21 A cross-sectional view taken along line C-C of FIG. 1 1, perpendicular to the substrate, after forming the first via for some embodiments. Figure 6 A cross-sectional view taken along line C-C of FIG. 1 1, perpendicular to the substrate, after forming the first via for some embodiments.

[0070] Figure 22 A cross-sectional view taken along line C-C of FIG. 1 1, perpendicular to the substrate, after forming the first via for some embodiments.

[0071] Figure 23 A cross-sectional view taken along line C-C of FIG. 1 1, perpendicular to the substrate, after forming the first via for some embodiments. Figure 22 A cross-sectional view taken along line C-C of FIG. 1 1, perpendicular to the substrate, after forming the first via for some embodiments.

[0072] Figure 24 A cross-sectional view taken along line C-C of FIG. 1 1, perpendicular to the substrate, after forming the first via for some embodiments. Figure 2 A cross-sectional view taken along line C-C of FIG. 1 1, perpendicular to the substrate, after forming the first via for some embodiments.

[0073] Figure 25 A cross-sectional view taken along line C-C of FIG. 1 1, perpendicular to the substrate, after forming the first via for some embodiments. Figure 2 A cross-sectional view taken along line C-C of FIG. 1 1, perpendicular to the substrate, after forming the first via for some embodiments.

[0074] Figure 26 A cross-sectional view taken along line B-B in FIG. 1 1 of the semiconductor structure provided in some embodiments after forming the capacitor. Figure 6 A cross-sectional view taken along line D-D in FIG. 1 1 of the semiconductor structure provided in some embodiments after forming the capacitor.

[0075] Figure 27 A cross-sectional view taken along line B-B in FIG. 1 1 of the semiconductor structure provided in some embodiments after forming the capacitor. Figure 26 A cross-sectional view taken along line D-D in FIG. 1 1 of the semiconductor structure provided in some embodiments after forming the capacitor.

[0076] Figure 28 A top view of the semiconductor structure provided in some embodiments.

[0077] Figure 29 A cross-sectional view taken along line B-B in FIG. 1 1 of the semiconductor structure provided in some embodiments after forming the capacitor. Figure 28 A cross-sectional view taken along line D-D in FIG. 1 1 of the semiconductor structure provided in some embodiments after forming the capacitor.

[0078] Figure 30 A cross-sectional view taken along line C-C in FIG. 1 1 of the semiconductor structure provided in some embodiments after forming the capacitor. Figure 28 A cross-sectional view taken along line C-C in FIG. 1 1 of the semiconductor structure provided in some embodiments after forming the capacitor.

[0079] BRIEF DESCRIPTION OF THE DRAWINGS

[0080] 10, substrate; 100, memory cell array; 01, capacitor region; 20, stack structure; 21, sacrificial layer; 22, functional layer; 23, active material layer; 130, body portion; 230, connection portion; 123, first active region; 223, second active region; 231, first active material layer; 232, second active material layer; 24, dielectric layer; 241, first dielectric layer; 242, second dielectric layer; 243, third dielectric layer; 31, channel groove; 311, recessed portion; 32, first via; 25, initial active layer; 251, first portion; 252, second portion; 33, first trench; 40, active channel; 41, semiconductor layer; 50, word line; 150, body portion; 250, separation portion; 51, gate insulating layer; 52, gate; 53, protective layer; 60, isolation layer; 61, insulating layer; 70, capacitor; 71, first electrode; 72, dielectric layer; 73, second electrode; 731, first sub-electrode of second electrode; 732, second sub-electrode of second electrode;

[0081] MCT, transistor;

[0082] D1, first direction; D2, second direction. DETAILED DESCRIPTION

[0083] For the purposes of the present application, the following terms are intended to have the meanings set forth below. The following terms are intended to have the following meanings throughout the specification and claims:

[0084] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used in the description herein is for describing particular embodiments only and is not intended to be limiting of the application.

[0085] It will be understood that when an element or layer is referred to as being "on" or "connected to" another element or layer, it can be directly on or connected to the other element or layer or intervening elements or layers can be present. In contrast, when an element is referred to as being "directly on" or "directly connected to" another element or layer, there are no intervening elements or layers present. It will also be understood that, when a term is used herein to refer to a process, operation, or structure, that the term can refer to a single process, operation, or structure, or a combination of processes, operations, or structures.

[0086] It will be understood that, although the terms first, second, third, etc. can be used herein to describe various elements, components, regions, layers and / or sections, these elements, components, regions, layers and / or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section; for example, a first dopant type could be termed a second dopant type, and, similarly, a second dopant type could be termed a first dopant type; a first dopant type and a second dopant type are different dopant types, for example, a first dopant type can be P-type and a second dopant type can be N-type, or a first dopant type can be N-type and a second dopant type can be P-type.​​​​​Spatially relative terms, such as "beneath", "below", "lower", "under", "above", "upper" and the like, can be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use and / or operation in addition to the orientations depicted in the figures. For example, if a device in the figures is turned over, elements described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary term "below" can encompass both an orientation of above and below. The device can also be oriented in the other direction, and the spatially relative terms used herein are intended to encompass such additional

[0087] As used herein, the singular form "a", "an" and "the" include plural references unless the context clearly dictates otherwise. As used herein, the term "comprises" and / or "comprising", when used in this specification, can specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0088] Embodiments of the application are described herein with reference to cross-sectional illustrations that are schematic illustrations of idealized embodiments (and intermediate structures) of the application. As such, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and / or tolerances, are to be expected. Thus, embodiments of the application should not be construed as limited to the particular shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing.

[0089] Referring to Figure 1 The present application provides a method for manufacturing a semiconductor structure, comprising the following steps:

[0090] Step S110: providing a substrate, and forming a stack structure on the substrate, the stack structure comprising a functional layer and a sacrificial layer, the functional layer comprising at least one active material layer, and the functional layer and the sacrificial layer being arranged alternately along a direction perpendicular to the substrate.

[0091] Referring to Figure 2 As shown, the material of the substrate 10 can be silicon (Si), germanium (Ge), or silicon germanium (GeSi), silicon carbide (SiC), silicon-on-insulator (SOI), germanium-on-insulator (GOI), or other semiconductor material such as gallium arsenide and other group III-V compound.

[0092] The stack structure 20 is formed on the substrate 10, and includes the functional layers 22 and the sacrificial layers 21 which are vertically stacked on the substrate 10, the functional layers 22 including at least one layer of active material layers 23, the active material layers 23 and the sacrificial layers 21 being spaced apart along a stacking direction of the stack structure 20, and / or the active material layers 23 being spaced apart between adjacent sacrificial layers 21.

[0093] The sacrificial layers 21 and the functional layers 22 of the stack structure 20 can be alternately stacked in 2 layers to 1024 layers or more. For example, the sacrificial layers 21 and the functional layers 22 can be alternately stacked in 48 layers, 64 layers, 128 layers, 256 layers, 512 layers, etc.

[0094] In some embodiments, along the stacking direction of the stack structure 20, the functional layers 22 include the dielectric layers 24 and the active material layers 23 which are alternately arranged between adjacent sacrificial layers 21. For example, referring to Figure 3 As shown, the functional layers 22 can include a three-layer structure, and along the stacking direction of the stack structure 20, the functional layers 22 can include the first dielectric layer 241, the active material layer 23, and the second dielectric layer 242 which are sequentially arranged, the active material layer 23 being arranged between the first dielectric layer 241 and the second dielectric layer 242, and the active material layer 23 being spaced apart from the sacrificial layers 21 by the first dielectric layer 241 or the second dielectric layer 242.

[0095] Alternatively, referring to Figure 24 As shown, the functional layers 22 can include the first active material layer 231, the dielectric layer 24, and the second active material layer 232 which are sequentially arranged, the dielectric layer 24 spacing apart the first active material layer 231 and the second active material layer 232, and the first active material layer 231 and the second active material layer 232 being connected to the sacrificial layer 21 at the top layer of the functional layers 22 or to the sacrificial layer 21 at the bottom layer of the functional layers 22, respectively.

[0096] Further alternatively, referring to Figure 25 As shown, the functional layers 22 can include a four-layer or five-layer structure, and the dielectric layers 24 and the active material layers 23 are alternately arranged between adjacent sacrificial layers 21.

[0097] The material of the sacrificial layers 21 can include silicon nitride or silicon oxynitride; the material of the dielectric layers 24 can include silicon oxide; and the material of the active material layers 23 can include conductive metal or doped semiconductor material, such as, the material of the active material layers 23 can include aluminum (Al) or aluminum alloy material, tungsten (W) or tungsten alloy material, titanium (Ti) or titanium alloy material, etc., or the material of the active material layers 23 can include P-type conductive doped semiconductor material or N-type conductive doped semiconductor material.

[0098] In the following, referring to Figure 2 , Figure 3In some embodiments, the functional layer 22 comprises a first dielectric layer 241, an active material layer 23, and a second dielectric layer 242 arranged in sequence. The stack structure 20 can be formed on the substrate 10 by the following embodiments:

[0099] The first dielectric layer 241, the active material layer 23, and the second dielectric layer 242 can be formed by any one of a chemical vapor deposition (CVD) process, a physical vapor deposition (PVD) process, an atomic layer deposition (ALD) process, or a sputtering process.

[0100] The sacrificial layer 21 can then be formed by any one of the above deposition processes. The steps of forming the functional layer 22 and the sacrificial layer 21 are repeated to form the stack structure 20 on the substrate 10.

[0101] It can be understood that, in order to avoid damage or contamination of the substrate 10 in subsequent processes, a dielectric layer 24 can be deposited on the substrate 10 before forming the sacrificial layer 21 or the functional layer 22, so as to avoid exposure of the substrate 10 to the process environment and degradation of the electrical properties of the substrate 10.

[0102] Step S120: patterning the stack structure, and forming an initial active layer from the active material layer.

[0103] Referring to Figure 2 , Figure 3 A first mask layer (not shown in the figures) is formed on the top surface of the stack structure 20, and the stack structure 20 is patterned according to the first mask layer. Part of the stack structure 20 is etched and removed, as shown in Figure 4 , the etched and remaining active material layer 23 forms an initial active layer 25. The initial active layer 25 comprises a first portion 251 extending along a second direction D2 and a second portion 252 extending along a first direction D1 different from the second direction D2. The first direction D1 and the second direction D2 are both parallel to the substrate 10, and the first direction D1 and the second direction D2 intersect.

[0104] For example, the first direction D1 and the second direction D2 can form an angle of 30°, 45°, 60°, 90°, 120°, or 150°. In some embodiments, the first direction D1 and the second direction D2 form an angle of 90°, and the first direction D1 and the second direction D2 intersect perpendicularly.

[0105] Then, as shown in Figure 5 , the stack structure 20 is patterned according to Figure 2 , Figure 3 , Figure 4A support layer 60 is deposited to fill the portion of the stacked structure 20 that has been removed. The top surface of the support layer 60 is flush with the top surface of the stacked structure 20. The material of the support layer 60 is selected to have a high etching selectivity with the dielectric layer 24. For example, the material of the support layer 60 may include at least one of silicon nitride or silicon oxynitride.

[0106] Step S130: Form at least one channel trench that penetrates the stacked structure in a direction perpendicular to the substrate, and divide the initial active layer into a first active region and a second active region.

[0107] like Figure 6 As shown, refer to Figure 2 , Figure 3 , Figure 5 A second mask layer (not shown) is formed on the top surface of the stacked structure 20 and the support layer 60. The second mask layer defines a pattern for forming the trench 31. The stacked structure 20 and the support layer 60 are etched according to the second mask layer until the top surface of the substrate 10 is exposed. Figure 7 As shown, at least one channel groove 31 is formed, and the channel groove 31 penetrates the stacked structure 20 along the stacking direction of the stacked structure 20.

[0108] In some embodiments, at least one channel trench 31 is arranged along a first direction D1, which is located in a plane parallel to the substrate 10.

[0109] At least one channel groove 31 divides the initial active layer 25 into a first active region 123 and a second active region 223 disposed opposite each other on both sides of the channel groove 31 along the second direction D2. The width of the channel groove 31 in the first direction D1 is greater than the width of the first active region 123 in the first direction D1 and the width of the portion of the second active region 223 connected to the channel groove 31 in the first direction D1; that is, along the first direction D1, both sides of the channel groove 31 extend into the support layer 60.

[0110] Step S140: A semiconductor layer and word lines are sequentially formed in the trench.

[0111] First, a semiconductor layer 41 is formed in the trench 31, such as Figure 9 As shown, refer to Figure 7 The semiconductor layer 41 can be deposited using any of the following deposition processes: chemical vapor deposition, physical vapor deposition, atomic layer deposition, or sputtering. The semiconductor layer 41 covers the bottom wall and sidewalls of the trench 31, as well as the top surface of the stacked structure 20 and the top surface of the support layer 60. The material of the semiconductor layer 41 may include indium gallium zinc oxide (IGZO).

[0112] In some embodiments, after forming the semiconductor layer 41 and before forming the word line 50, the following steps are also performed:

[0113] Step S140-1: Form a protective layer and a gate insulating layer. The gate insulating layer, protective layer and semiconductor layer are arranged sequentially in a direction away from the word line.

[0114] like Figure 10 As shown, refer to Figure 9 After forming the semiconductor layer 41, a protective layer 53 can be deposited using any of the following deposition processes: chemical vapor deposition, physical vapor deposition, atomic layer deposition, or sputtering. The protective layer 53 covers the surface of the semiconductor layer 41, as shown in the figure. Figure 11 As shown, the protective layer 53 separates the semiconductor layer 41 from the word line 50 formed in subsequent steps, preventing the gate insulating layer 51 from being etched and damaged in the subsequent step of etching the semiconductor layer 41 connected to the sacrificial layer 21 (which will be described in detail in subsequent embodiments), thus affecting the structural integrity and electrical performance of the word line 50.

[0115] The material of the protective layer 53 is selected to achieve a high etching selectivity with the material of the sacrificial layer 21. For example, the material of the protective layer 53 may include silicon oxide.

[0116] Then, a gate insulating layer 51 is formed. For example... Figure 11 , Figure 12 As shown, refer to Figure 10 A high-k dielectric material can be deposited to form a gate insulating layer 51 by means of chemical vapor deposition, physical vapor deposition, atomic layer deposition, or sputtering. The gate insulating layer 51 covers the semiconductor layer 41.

[0117] The material of the gate insulating layer 51 may include hafnium metal or hafnium compounds. For example, the material of the gate insulating layer 51 may include one or more of hafnium oxide (HfO), hafnium silicon oxide (HfSiO), hafnium aluminum oxide (HfAlO), or hafnium tantalum oxide (HfTaO).

[0118] Next, as Figure 11 , Figure 12 As shown, refer to Figure 10 A gate material layer can be deposited in the trench 31 using any of the above deposition processes, forming a plurality of gates 52 spaced apart in the trench 31 along a direction perpendicular to the substrate 10. The material of the gates 52 may include tungsten or a tungsten compound.

[0119] The gate material layer and the gate insulating layer 51 on the top surface of the stack structure 20 are etched away in sequence to form a word line 50 in the channel groove 31, the word line 50 comprising a plurality of gates 52 arranged in a direction perpendicular to the substrate 10.

[0120] Step S150: etching away at least part of the sacrificial layer and etching away part of the semiconductor layer to divide the semiconductor layer into a plurality of active channels arranged in a direction perpendicular to the substrate.

[0121] In some embodiments, the direction perpendicular to the substrate 10 is a direction upward from the substrate 10. Figure 11 、 Figure 12

[0122] In some embodiments, etching away at least part of the sacrificial layer and etching away part of the semiconductor layer comprises the following steps:

[0123] Step S151: forming a first via between adjacent word lines, the first via exposing part of the top surface.

[0124] First, as shown in Figure 13 、 Figure 14 , a third mask layer (not shown in the figure) is formed on the top surface of the stack structure 20 and the support layer 60, the third mask layer defining a pattern for forming the first via 32, the third mask layer exposing part of the top surface of the support layer 60 around the word line 50.

[0125] Then, as shown in Figure 13 、 Figure 14 , the support layer 60 is etched based on the third mask layer to form the first via 32 penetrating through the support layer 60, the first via 32 exposing part of the top surface of the substrate 10 or extending into the substrate 10, the first via 32 being arranged close to the word line 50, the slot wall of the first via 32 exposing part of the structure of each layer of the sacrificial layer 21 connected to the word line 50.

[0126] In the first direction D1, the first via 32 is formed between two adjacent channel grooves 31, the first via 32 and the channel groove 31 being arranged independently in the orthographic projection formed on the substrate 10.

[0127] Step S152: etching the sacrificial layer and the semiconductor layer based on the first via until the semiconductor layer between adjacent functional layers is removed.

[0128] As shown in Figure 15 、 Figure 16 , referring to Figure 11 、 Figure 12 、 Figure 13 、 Figure 14 ​An anisotropic etching process is used to etch the support layer 60 exposed by the first via 32 until the stacked structure 20 is exposed by the first via 32. The sacrificial layer 21 exposed by the first via 32 is then etched. The sacrificial layer 21 surrounding the trench 31 is removed by horizontal etching, exposing the semiconductor layer 41 connected to the sacrificial layer 21. Etching of the semiconductor layer 41 continues until the semiconductor layer 41 connected to the sacrificial layer 21 is completely removed. (Refer to...) Figure 15 , Figure 16 The entire semiconductor layer 41 is divided into multiple independently configured active channels 40. The multiple active channels 40 are arranged at intervals along a direction perpendicular to the substrate 10. The multiple active channels 40 and the multilayer functional layers 22 are arranged in a one-to-one correspondence. Each active channel 40 is connected to the corresponding functional layer 22.

[0129] In some embodiments, the etching process of the sacrificial layer 21 has a high etching selectivity relative to the dielectric layer 24 and the active material layer 23, so as to avoid the process of etching the sacrificial layer 21 consuming the dielectric layer 24 or the active material layer 23 and affecting the integrity of the structure and performance of the final semiconductor structure.

[0130] Reference Figure 16 As shown, a transistor MCT is formed at the node where the word line 50 connects to the first active region 123 and the second active region 223. In some embodiments, the materials of the first active region 123 and the second active region 223 include metallic materials, and the first active region 123, the second active region 223, and the portion of the word line 50 covered by the active channel 40 directly constitute the transistor MCT. The portion of the first active region 123 near the word line 50 forms the source or drain of the transistor MCT, and the portion of the second active region 223 near the word line 50 forms the drain or source of the transistor MCT. The portion of the word line 50 covered by the active channel 40 serves as the gate 52 of the transistor MCT, and the gates 52 of multiple transistor MCTs are connected to the word line 50.

[0131] In some other embodiments, the materials of the first active region 123 and the second active region 223 include doped semiconductor materials. After the first active region 123 and the second active region 223 are formed, conductive ions (which can be P-type conductive ions or N-type conductive ions) are implanted into the side of the first active region 123 near the word line 50 using an ion implantation process to form a first doped region (not shown in the figure).

[0132] Then, the ion implantation process is used to implant conductive ions (which can be N-type conductive ions or P-type conductive ions) to the side of the second active region 223 close to the word line 50 to form a second doped region (not labeled in the figure), the first doped region serves as the source or drain of the transistor MCT, the second doped region serves as the drain or source of the transistor MCT, the part of the word line 50 covered by the active channel 40 serves as the gate 52 of the transistor MCT, and the gates 52 of the plurality of transistors MCT are connected to the word line 50.

[0133] In some embodiments, after the semiconductor layer 41 is cut into a plurality of independently arranged active channels 40, the following steps are further performed: depositing an insulating material to form an insulating layer 61, the insulating layer 61 filling the gap between the functional layers 22 and the first via 32.

[0134] The manufacturing method of the semiconductor structure of the above-mentioned embodiments can improve the response speed of the semiconductor structure and avoid response delay by adjusting the stacking rule of the stacked structure, arranging a sacrificial layer between adjacent functional layers, removing the sacrificial layer to expose the semiconductor layer connected to the sacrificial layer, and then removing the semiconductor layer connected to the sacrificial layer to divide the entire semiconductor layer into independently arranged active channels, thereby avoiding the formation of parasitic transistors (transistors with parasitic channels) by the residual semiconductor layer between adjacent transistors and avoiding the existence of parasitic channels between adjacent transistors.

[0135] The manufacturing method of the semiconductor structure of the above-mentioned embodiments can increase the process window for removing the semiconductor layer by arranging a sacrificial layer, reduce the difficulty of process operation and control for removing the semiconductor layer between adjacent transistors, avoid complex lithography-etching steps, reduce the requirements for equipment and process stability, greatly reduce the process cost and improve the yield.

[0136] Meanwhile, the manufacturing method of the semiconductor structure of the above-mentioned embodiments can avoid damage to the active channel during the process by covering the active channel with surrounding active material layers and dielectric layers, thereby further improving the yield and electrical performance of the semiconductor structure.

[0137] In some embodiments, after the at least one channel groove is formed in step S130, the manufacturing method of the semiconductor structure further includes the following steps:

[0138] Step S1301: removing part of the functional layer or part of the sacrificial layer exposed by the channel groove to form a recess on the side wall of the channel groove, the recess being recessed in a direction parallel to the substrate and away from the channel groove.

[0139] As Figure 8As shown, the trench wall of the channel 31 exposes part of the functional layer 22 (including part of the dielectric layer 24 and part of the active material layer 23), and the trench wall of the channel 31 also exposes part of the sacrificial layer 21.

[0140] In some embodiments, the recess 311 is formed using the following methods:

[0141] like Figure 8 As shown, refer to Figure 7 After forming the trench 31, the stacked structure 20 is etched based on the trench 31, and the functional layer 22 (dielectric layer 24 or active material layer 23) exposed by the sidewall of the trench 300 is etched, or the sacrificial layer 21 exposed by the sidewall of the trench 300 is etched to form the recess 311.

[0142] For example, in some examples, refer to Figure 8 As shown, a suitable etching process can be selected to etch the sacrificial layer 21 exposed by the trench 31. The etching process has a high etching selectivity compared to the dielectric layer 24 and the active material layer 23. The etching removes part of the sacrificial layer 21, forming a recess 311 on the sidewall of the trench 300. The recess 311 is recessed into the sacrificial layer 21. That is, after this step, the trench width of the trench 31 in the sacrificial layer 21 is greater than the trench width of the trench 31 in the dielectric layer 24 and the trench width of the trench 31 in the active material layer 23.

[0143] In other examples, which are not shown in the accompanying drawings, a suitable etching process can be used to etch the dielectric layer 24 exposed by the trench 31. This etching process has a high etching selectivity relative to the sacrificial layer 21 and the active material layer 23, removing a portion of the dielectric layer 24 and forming a recess 311 on the sidewall of the trench 300. The recess 311 is recessed into the dielectric layer 24. That is, after this step, the width of the trench 31 in the dielectric layer 24 is greater than the width of the trench 31 in the sacrificial layer 21 and the width of the trench 31 in the active material layer 23.

[0144] In some embodiments, when forming the semiconductor layer 41, the semiconductor layer 41 covers the trench walls of the channel trench 31 and the trench walls of the recessed portion 311. (Refer to...) Figure 12 When forming word line 50, gate insulating layer 51 covers semiconductor layer 41, word line 50 covers gate insulating layer 51 and fills the unfilled area of ​​trench 31 and the unfilled area of ​​recess 311.

[0145] In some embodiments, reference is made to Figure 12The formed word line 50 includes a main body 150 extending along the stacking direction of the stack structure 20 and a separation part 250 arranged on the circumference of the main body 150, the separation part 250 is arranged at intervals along the stacking direction of the stack structure 20, the separation part 250 is filled in the recessed part 311, and the separation part 250 is formed between the first active regions 123 adjacent along the stacking direction of the stack structure 20 and / or between the second active regions 223 adjacent along the stacking direction of the stack structure 20.

[0146] In some embodiments, referring to Figure 6 As shown, the at least one channel groove 31 is arranged at intervals along the first direction D1, and the second active region 223 formed by the patterned stack structure 20 extends along the first direction D1, and the second active region 223 is formed with a connection part 230 on the side close to the channel groove 31, and the second active region 223 is connected through the connection part 230 and the active channel 40, and the first direction D1 is parallel to the substrate 10.

[0147] For example, in step S120, a plurality of channel grooves 31 arranged at intervals along the first direction D1 are formed in the stack structure 20, so that a plurality of word lines 50 arranged at intervals along the first direction D1 are formed. In the process of patterning the stack structure 20, the second active region 223 extending along the first direction D1 is defined, and a plurality of connection parts 230 are formed on the side of the second active region 223 close to the word line 50, and the plurality of connection parts 230 and the plurality of word lines 50 are arranged correspondingly along the first direction D1, each connection part 230 is connected with the active channel 40 and connected through the active channel 40 and the word line 50. It can be understood that a transistor MCT is formed at the connection node of the word line 50 and the first active region 123 and the second active region 223, and part of the structure of the first active region 123 or part of the structure of the second active region 223, the connection part 230 and the part of the word line 50 covered by the active channel 40 serve as the gate 52, which together constitute the transistor MCT.

[0148] In some embodiments, along the first direction D1, the size of the active channel 40 is greater than at least one of the size of the first active region 123 and the size of the connection part 230.

[0149] For example, the size of the active channel 40 is greater than the size of the first active region 123; or the size of the active channel 40 is greater than the size of the connection part 230; or the size of the active channel 40 can be greater than the size of the first active region 123 and the size of the connection part 230 at the same time.

[0150] Referring to Figure 6As shown, the active channel 40 is patterned in a stacked structure 20 with the size of the active region 123 or the connection portion 230 in the first direction D1 being larger than the size of the active region 123 or the connection portion 230. For example, the size of the active channel 40 in the first direction D1 is a first width d1. By controlling the patterning process, d1 is made much larger than the size d2 of the formed first active region 123 and the connection portion 230 in the first direction D1, thereby increasing the channel length of the transistor MCT. When the size of AA is further reduced, the short-channel effect of the transistor MCT can be avoided. At the same time, the process of preferentially forming the first active region 123 and the second active region 223 can avoid damage to the active channel 40 by the process, ensuring the structural and performance integrity of the active channel 40.

[0151] According to an exemplary embodiment, some embodiments include all the steps of the above embodiments, and some embodiments differ from the above embodiments in that, after forming the semiconductor layer and before forming the word lines, the following steps are further included:

[0152] According to some embodiments, including all the steps of the above embodiments, after patterning the layered structure, the following steps are further included:

[0153] Step S160: Remove part of the dielectric layer to expose part of the sidewall of the first active region covered by the dielectric layer.

[0154] In some embodiments, removing part of the dielectric layer to expose part of the sidewall of the first active region covered by the dielectric layer can be achieved using the following methods:

[0155] Step S161: Define the capacitor region, etch away the support layer located in the capacitor region to form a first trench, and expose the substrate through the first trench.

[0156] Reference Figure 18 , Figure 19 As shown, a fourth mask layer (not shown in the figure) is formed on the top surface of the support layer 60. The capacitor region 01 is defined according to the layout and structure of the word line 50 and the layout and structure of the first active region 123 or the second active region 223 (see reference). Figure 13 On the fourth mask layer, a capacitance region 01 is defined (refer to...). Figure 18 The pattern is shown in the image. (Refer to the image.) Figure 18 When defining capacitor region 01, capacitor region 01 is defined on one side of the first active region 123 along the second direction D2.

[0157] Then, the capacitor region 01 (reference) is removed by etching according to the fourth mask layer. Figure 18 The support layer 60, in the capacitor region 01 (refer to) Figure 18A first trench 33 is formed, which exposes a portion of the structure of the first active region 123 away from the word line 50. The first trench 33 also exposes a portion of the structure of the dielectric layer 24 connected to the first active region 123.

[0158] Step S162: Based on the first trench etching stack structure, remove part of the dielectric layer.

[0159] like Figure 20 As shown, refer to Figure 19 Anisotropic etching is used to etch the dielectric layer 24 exposed by the first trench 33, exposing all the sidewalls of the end of the first active region 123 away from the word line 20, increasing the dielectric layer 72 formed subsequently (see reference). Figure 21 or Figure 29 The increased contact area between the capacitor 70 and the first active region 123 is beneficial for improving the formed capacitor 70 (refer to...). Figure 21 or Figure 29 Storage capacity.

[0160] Step S170: Form a dielectric layer that covers the exposed sidewalls of the first active region.

[0161] Reference Figure 21 As shown, a dielectric layer 72 is deposited using an atomic layer deposition process, and the dielectric layer 72 uniformly covers the exposed sidewalls of the first active region 123.

[0162] The material of dielectric layer 72 may include at least one of strontium titanate (SrTiO3), aluminum oxide (Al2O3), zirconium oxide (ZrO) or hafnium oxide (HfO2).

[0163] Step S180: Form a second electrode, the second electrode is covered by a dielectric layer, and the part of the first active region covered by the dielectric layer is used as the first electrode. The second electrode, the dielectric layer and the first electrode form a capacitor.

[0164] Reference Figure 22 , Figure 29 As shown, the first active region 123 covered by the dielectric layer 72 serves as the first electrode 71. Each first electrode 71, along with the dielectric layer 72 and the second electrode 73 on its surface, forms a capacitor 70 in the capacitor region 01. The capacitor 70 is disposed on one side of the word line 50. The capacitor 70 and the word line 50 are separated by an etched dielectric layer 24 to prevent short circuits between the capacitor 70 and the word line 50.

[0165] In some embodiments, the second electrode 73 may be formed in the following manner: (Refer to...) Figure 21 First, the second electrode first sub-electrode 731 can be deposited using atomic layer deposition process, and the second electrode first sub-electrode 731 covers the surface of dielectric layer 72.

[0166] The material of the second electrode first sub-electrode 731 can include a high melting point metal, such as at least one of cobalt (Co), titanium (Ti), nickel (Ni), tungsten (W), and / or molybdenum (Mo); or, the material of the second electrode first sub-electrode 731 can also include a metal nitride, such as titanium nitride, titanium silicon nitride, titanium aluminum nitride, tantalum nitride, tantalum silicon nitride, tantalum aluminum nitride, and / or tungsten nitride.

[0167] Then, referring to Figure 22 , Figure 23 , Figure 29 , the second electrode second sub-electrode 732 can be formed again by any one of a chemical vapor deposition process, a physical vapor deposition process, an atomic layer deposition process, or a sputtering deposition process, the second electrode second sub-electrode 732 covering the surface of the second electrode first sub-electrode 731 and filling the unfilled regions between the second electrode first sub-electrodes 731 and the regions not filled by the first trench 33 (see Figure 19 ).

[0168] The material of the second electrode second sub-electrode 732 can include a semiconductor material doped with conductive ions or a conductive metal. For example, the material of the second electrode second sub-electrode 732 can include monocrystalline silicon or polycrystalline silicon, and the material of the second electrode second sub-electrode 732 can also include at least one of metallic tungsten, cobalt, titanium, and / or nickel.

[0169] It can be understood that, when the semiconductor structure is in a working state, the second electrode first sub-electrode 731 and the second electrode second sub-electrode 732 jointly serve as the second electrode 73 of the capacitor 70.

[0170] In some embodiments, after the capacitor 70 is formed, an insulating material is deposited to fill the gap between the capacitors 70, so as to avoid short-circuiting of adjacent capacitors 70 and also to reduce the coupling capacitance of the capacitors 70, and the insulating material and the support layer 60 jointly support the semiconductor structure.

[0171] According to an exemplary embodiment, some embodiments and the above-described embodiments differ in that, in step S110, as shown in Figure 24 , the functional layer 22 includes, in sequence along the stacking direction of the stack structure 20, a first active material layer 231, a dielectric layer 24, and a second active material layer 232.

[0172] As shown in Figure 26 , Figure 27 , according to Figure 24The semiconductor structure formed by the stack structure 20 shown in the figure, one side of each active channel 40 is connected with two first active regions 123, the other side of each active channel 40 is connected with two second active regions 223, the regions of the same active channel 40, the two first active regions 123, the two second active regions 223 and the region where the word line 50 intersects form two transistors MCT.

[0173] According to Figure 24 The semiconductor structure formed by the stack structure 20 shown in the figure, each active channel 40 is connected with two first active regions 123 and two second active regions 223, and the end of the two first active regions 123 away from the word line 50 serves as the first electrode 71 of the capacitor 70. The capacitor 70 formed is a cup-shaped capacitor, which increases the proportion of the first electrode 71 in the capacitor 70, increases the storage area of the dielectric layer 72 and the first electrode 71, and further improves the storage capacity of the capacitor 70. The 2T1C structure formed by the capacitor 70 and the two transistors MCT further improves the integration density of the semiconductor structure.

[0174] According to an exemplary embodiment, some embodiments and the difference between the above-mentioned embodiments are that, in step S110, as shown in 25, the functional layer 22 includes, in the stacking direction of the stack structure 20, a first dielectric layer 241, a first active material layer 231, a second dielectric layer 242, a second active material layer 232 and a third dielectric layer 243 arranged in sequence.

[0175] According to Figure 25 The semiconductor structure formed by the stack structure 20 shown in the figure and the above-mentioned embodiments according to Figure 24 The semiconductor structure formed by the stack structure 20 shown in the figure is the same as the above-mentioned embodiments, and as Figure 26 , Figure 27 Each active channel 40 is connected with two first active regions 123 on one side and two second active regions 223 on the other side, the capacitor 70 is a cup-shaped capacitor, and the capacitor 70 and the two transistors MCT form a 2T1C structure.

[0176] Referring to Figure 25 The first active material layer 231 in the functional layer 22 is separated from the sacrificial layer 21 by the first dielectric layer 241, and the second active material layer 232 is separated from the sacrificial layer 21 by the third dielectric layer 243, avoiding direct contact between the first active material layer 231, the second active material layer 232 and the sacrificial layer 21, and avoiding damage to the first active material layer 231 and the second active material layer 232 by etching process during the process, to ensure the integrity of the structure and performance of the semiconductor structure formed.

[0177] Some embodiments provide a semiconductor structure, as Figure 28 , Figure 29、 Figure 30 As shown in FIG. 1, referring to Figure 21 、 Figure 22 、 Figure 23 、 Figure 24 、 Figure 26 The semiconductor structure of some embodiments includes a substrate 10, a word line 50, a plurality of multilayer memory cell arrays 100 arranged in a direction perpendicular to the substrate 10, at least one first active region 123, and at least one second active region 223. The word line 50 is arranged on the substrate 10 and extends in a direction perpendicular to the substrate 10. Each of the plurality of multilayer memory cell arrays 100 includes a plurality of active channels 40 arranged in a first direction D1. The plurality of active channels 40 are arranged in a direction perpendicular to the word line 50. The active channel 40 covers part of the circumferential surface of the word line 50. The at least one first active region 123 is arranged on one side of the active channel 40 in a second direction D2 and connected to the active channel 40. The first direction D1 and the second direction D2 are parallel to the substrate 10. The first direction D1 and the second direction D2 intersect. The at least one second active region 223 is arranged on the other side of the active channel 40 in the second direction D2 relative to the at least one first active region 123 and connected to the active channel 40. In the first direction D1, the size of the active channel 40 is greater than at least one of the size of the part of the first active region 123 connected to the active channel 40 and the size of the part of the second active region 223 connected to the active channel 40.

[0178] The angle between the first direction D1 and the second direction D2 can be 30°, 45°, 60°, 90°, 120°, or 150°. In some embodiments, the angle between the first direction D1 and the second direction D2 is 90°, and the first direction D1 and the second direction D2 intersect perpendicularly.

[0179] As shown in FIG. 1, referring to Figure 28 、 Figure 29 、 Figure 30 The node where the word line 50 and the connection of the first active region 123 and the second active region 223 are formed as a transistor MCT. The part of the first active region 123 close to the word line 50 forms the source or the drain of the transistor MCT. The part of the second active region 223 close to the word line 50 forms the drain or the source of the transistor MCT. The part of the word line 50 covered by the active channel 40 is the gate 52 of the transistor MCT. The gates 52 of the plurality of transistors MCT are connected to the word line 50.

[0180] The semiconductor structure provided by some embodiments has a plurality of active channels 40 independently arranged on the same word line 50. There is no process residual conductive film layer between adjacent active channels 40. In this way, the parasitic capacitance between adjacent transistors of the semiconductor structure can be avoided or reduced, the response speed of the semiconductor structure can be improved, the response delay can be avoided, and the yield and electrical performance of the semiconductor structure can be improved.

[0181] In some embodiments, as shown in Figure 28 , Figure 29 , Figure 30 shown, referring to Figure 22 , Figure 23 , Figure 26 , a plurality of first active regions 123 are spaced apart along a direction perpendicular to the substrate 10, and the plurality of first active regions 123 are connected to a same active channel 40. Two or more adjacent first active regions 123 are connected to the same active channel 40.

[0182] For example, one side of each active channel 40 is connected to two first active regions 123, and the other side of each active channel 40 is connected to two second active regions 223. The region where each active channel 40 is located, the first active regions 123, the second active regions 223, and a part of the word line 50 covered by the active channel 40 together form a transistor MCT.

[0183] That is, the region of each active channel 40 forms two transistors MCT, which improves the integration of the semiconductor structure. It can be understood that the number of first active regions 123 and second active regions 223 connected by the active channel 40 can be adjusted adaptively, for example, the active channel 40 can also be connected to three or more first active regions 123 and three or more second active regions 223.

[0184] In some embodiments, referring to Figure 22 , Figure 26 , Figure 27 , Figure 29 , Figure 30 , a plurality of first active regions 123 are connected to a plurality of active channels 40 one by one along a direction perpendicular to the substrate 10. Two adjacent first active regions 123 are connected to two adjacent active channels 40 one by one.

[0185] In some embodiments, referring to Figure 12 shown, the word line 50 includes a main body portion 150 extending along a direction perpendicular to the substrate 10 and a partition portion 250 arranged on the circumferential surface of the main body portion 150. The partition portion 250 is spaced apart along a direction perpendicular to the substrate 10, and the partition portion 250 is arranged between two adjacent first active regions 123 along a direction perpendicular to the substrate 10 and / or between two adjacent second active regions 223 along a direction perpendicular to the substrate 10.

[0186] In some examples, along a direction perpendicular to the substrate 10, the partition 250 of the word line 50 is arranged between adjacent first active regions 123 or between adjacent second active regions 223, and the partition 250 can be in contact with a part of the bottom surface of the first active region 123 or a part of the top surface of the first active region 123, or in contact with a part of the bottom surface of the second active region 223 or a part of the top surface of the second active region 223.

[0187] In some examples, along a direction perpendicular to the substrate 10, the partition 250 of the word line 50 is arranged between adjacent first active regions 123 or between adjacent second active regions 223, and the partition 250 is spaced apart from the first active region 123 above the partition 250 and the first active region 123 below the partition 250, or the partition 250 is spaced apart from the second active region 223 above the partition 250 and the second active region 223 below the partition 250.

[0188] In some other examples, the partitions 250 are spaced apart along a direction perpendicular to the substrate 10, and the partitions 250 are in contact with the first active regions 123 and the second active regions 223.

[0189] The partition 250 of the word line 50 is in contact with the first active region 123 and the second active region 223 on both sides of the word line 50, i.e., the width of the word line 50 between the first active region 123 and the second active region 223 is greater than the width of the body 150.

[0190] In some examples, referring to FIGS. 1-3, Figure 21 , Figure 22 , Figure 23 , Figure 26 , Figure 28 , Figure 29 , Figure 30 each layer of the memory cell array 100 further includes a capacitor 70, the capacitor 70 including a first electrode 71, a dielectric layer 72, and a second electrode 73, the first electrode 71 including a part of the structure of the first active region 123, the dielectric layer 72 covering a surface of the first electrode 71, and the second electrode 73 covering a surface of the dielectric layer 72.

[0191] In some examples, the second electrode 73 includes a first sub-electrode 731 of the second electrode and a second sub-electrode 732 of the second electrode. The first sub-electrode 731 of the second electrode covers a surface of the dielectric layer 72, and the first sub-electrode 731 of the second electrode encloses a closed figure, and the second sub-electrode 732 of the second electrode covers the first sub-electrode 731 of the second electrode and fills the closed figure.

[0192] In a working state of the semiconductor structure, the first sub-electrode 731 of the second electrode and the second sub-electrode 732 of the second electrode jointly serve as the second electrode 73 of the capacitor 70.

[0193] In some embodiments, referring to Figure 18 The second active region 223 includes a body part 130 and a connecting part 230, the body part 130 extends along the first direction D1, and the connecting part 230 connects the body part 130 and the active channel 40.

[0194] In some embodiments, referring to Figure 18 The plurality of word lines 50 are arranged at intervals along the first direction D1, the second active region 223 is provided with a plurality of connecting parts 230 near one side of the active channel 40, and the plurality of connecting parts 230 are arranged at intervals along the first direction D1.

[0195] The plurality of connecting parts 230 and the plurality of active channels 40 are one-to-one corresponding, and the second active region 223 is connected to the corresponding active channel 40 through the connecting part 230.

[0196] In some embodiments, referring to Figure 18 Along the first direction D1, the size of the active channel 40 is greater than the size of the connecting part 230.

[0197] In some embodiments, referring to Figure 29 , Figure 22 or Figure 26 The semiconductor structure further includes a protection layer 53 and a gate insulating layer 51, and the gate insulating layer 51, the protection layer 53 and the active channel 40 are sequentially arranged in a direction away from the word line 50.

[0198] The protection layer 53 covers the bottom wall and the side wall of the word line 50, the gate insulating layer 51 covers the protection layer 53, and the active channel 40 is separated by the gate insulating layer 51, the protection layer 53 and the word line 50.

[0199] The semiconductor structure of the present application can increase the channel length and reduce the short channel effect by changing the size relationship of the source region (S) / drain region (D) and the channel in the plane, and can also avoid damage to the channel during the process.

[0200] Some embodiments provide a memory including the semiconductor structure described in the above embodiments. The memory in some embodiments may be Dynamic Random Access Memory (DRAM). However, the memory in some embodiments may also be Static Random-Access Memory (SRAM), flash EPROM, ferroelectric Random-Access Memory (FRAM), magnetic Random-Access Memory (MRAM), phase-change Random-Access Memory (PRAM), etc.

[0201] Some embodiments provide an electronic device that includes the memory or semiconductor structure described in the above embodiments. The electronic device can be a mobile phone, computer, tablet computer, television, artificial intelligence device, etc.

[0202] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features of the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0203] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.

Claims

1. A semiconductor structure, characterized in that, include: Substrate; The character lines are disposed on the substrate and extend in a direction perpendicular to the substrate; A multilayer memory cell array disposed along a direction perpendicular to the substrate, each layer of the memory cell array including a plurality of active channels arranged along a first direction; The plurality of active channels are spaced apart along the extension direction of the word line, and the active channels cover a portion of the periphery of the word line; At least one first active region is disposed on one side of the active channel in the second direction and connected to the active channel, wherein both the first direction and the second direction are parallel to the substrate and intersect each other; At least one second active region is disposed on the opposite side of the active channel in the second direction relative to at least one first active region, and is connected to the active channel; Along the first direction, the size of the active channel is greater than at least one of the size of the portion of the first active region connected to the active channel and the size of the portion of the second active region connected to the active channel.

2. The semiconductor structure according to claim 1, characterized in that, Along a direction perpendicular to the substrate, a plurality of first active regions are spaced apart, and the plurality of first active regions are connected to the same active channel.

3. The semiconductor structure according to claim 1, characterized in that, Along a direction perpendicular to the substrate, a plurality of first active regions and a plurality of active channels are connected one-to-one.

4. The semiconductor structure according to claim 1, characterized in that, The word line includes a main body extending in a direction perpendicular to the substrate and a partition portion disposed on the periphery of the main body. The partition portions are spaced apart in a direction perpendicular to the substrate and are disposed between first active regions adjacent in a direction perpendicular to the substrate and / or between second active regions adjacent in a direction perpendicular to the substrate.

5. The semiconductor structure according to any one of claims 1-4, characterized in that, Each layer of the memory cell array also includes: A capacitor, the capacitor including a first electrode, a dielectric layer and a second electrode, the first electrode including a portion of the structure of a first active region, the dielectric layer covering the surface of the first electrode, and the second electrode covering the surface of the dielectric layer.

6. The semiconductor structure according to claim 5, characterized in that, The second active region includes a body portion and a connecting portion, the body portion extending along the first direction, and the connecting portion connecting the body portion and the active channel.

7. The semiconductor structure according to claim 6, characterized in that, The multiple word lines are arranged at intervals along the first direction, and the second active region is provided with multiple connecting parts on the side near the active channel, and the multiple connecting parts are arranged at intervals along the first direction.

8. The semiconductor structure according to claim 7, characterized in that, Along the first direction, the size of the active channel is larger than the size of the connector.

9. The semiconductor structure according to claim 1, characterized in that, Also includes: A protective layer, a gate insulating layer, the gate insulating layer, the protective layer, and the active channel are arranged sequentially in a direction away from the word line.

10. An electronic device, characterized in that, Includes the semiconductor structure as described in any one of claims 1-9.

11. A method for fabricating a semiconductor structure, characterized in that, Includes the following steps: A substrate is provided, and a stacked structure is formed on the substrate, the stacked structure including a functional layer and a sacrificial layer, the functional layer including at least one active material layer along a direction perpendicular to the substrate, the functional layer and the sacrificial layer being alternately disposed; The stacked structure is patterned, and the active material layer forms an initial active layer; At least one trench is formed, the trench penetrating the stacked structure in a direction perpendicular to the substrate, the trench dividing the initial active layer into a first active region and a second active region; A semiconductor layer and word lines are sequentially formed in the trench. The sacrificial layer is etched away in a way that removes at least a portion of the semiconductor layer, and the semiconductor layer is divided into a plurality of active channels, the plurality of active channels being spaced apart along a direction perpendicular to the substrate.

12. The method for fabricating a semiconductor structure according to claim 11, characterized in that, After forming at least one trench, the method for fabricating the semiconductor structure further includes the following steps: Remove a portion of the functional layer or a portion of the sacrificial layer exposed by the trench, and form a recess on the sidewall of the trench, the recess being recessed in a direction parallel to the substrate and away from the trench; The word line includes a main body extending along the stacking direction of the stacked structure and a partition portion disposed on the periphery of the main body. The partition portions are spaced apart along the stacking direction of the stacked structure and fill the recessed portion. The partition portions are formed between first active regions adjacent along the stacking direction of the stacked structure and / or between second active regions adjacent along the stacking direction of the stacked structure.

13. The method for fabricating a semiconductor structure according to claim 11, characterized in that, Along the stacking direction of the stacked structure, the functional layer includes alternating active material layers and dielectric layers.

14. The method for fabricating a semiconductor structure according to claim 13, characterized in that, The method for fabricating the semiconductor structure further includes the following steps: Remove part of the dielectric layer to expose part of the sidewall of the first active region covered by the dielectric layer; A dielectric layer is formed, which covers the exposed sidewall of the first active region; A second electrode is formed, which covers the dielectric layer. The portion of the first active region covered by the dielectric layer serves as the first electrode. The second electrode, the dielectric layer, and the first electrode form a capacitor.

15. The method for fabricating a semiconductor structure according to claim 11, characterized in that, The second active region extends along the first direction, and a connecting portion is formed on the side of the second active region near the channel trench. The second active region is connected to the active channel through the connecting portion, and the first direction is parallel to the substrate.

16. The method for fabricating a semiconductor structure according to claim 15, characterized in that, Along the first direction, the size of the active channel is greater than at least one of the size of the first active region and the size of the connection portion.

17. The method for fabricating a semiconductor structure according to claim 11, characterized in that, Etching away at least a portion of the sacrificial layer, etching away a portion of the semiconductor layer, including: A first via is formed between adjacent word lines, the first via exposing a portion of the top surface of the substrate; Based on the first via, the sacrificial layer and the semiconductor layer are etched until the semiconductor layer located between the adjacent functional layers is removed.

18. The method for fabricating a semiconductor structure according to claim 17, characterized in that, The manufacturing method further includes the following steps: A protective layer and a gate insulating layer are formed, wherein the gate insulating layer, the protective layer and the semiconductor layer are arranged sequentially in a direction away from the word line.

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