Fan-out wafer level packaging structure and packaging method of integrated photosensitive chip

Abstract

The invention discloses a fan-out wafer level packaging structure and packaging method of an integrated photosensitive chip, and the packaging structure comprises a glass substrate, the first surface of the glass substrate is provided with at least one blind groove and at least one first metal interconnection hole, and the second surface of the glass substrate is provided with a second metal interconnection hole communicated with the at least one blind groove; the photosensitive chip forms a bonding wall body in an area around a photosensitive area of the photosensitive chip so as to be embedded into the blind groove, the photosensitive area faces the bottom surface of the blind groove, and a protection cavity is formed between the photosensitive area and the bottom surface of the blind groove through the bonding wall body; the rewiring structures are respectively formed on the first surface and the second surface of the glass substrate, and one rewiring structure is electrically connected with the semiconductor chip; the other rewiring structure interconnects the photosensitive chip with the first rewiring structure through the second metal interconnection hole and the first metal interconnection hole; and the passivation layer of the second redistribution structure is opened in the light-transmitting area to form an opening. According to the packaging structure, the photosensitive area is not influenced by reconstruction, the protection performance is good, and the optical performance is not influenced.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor packaging technology, and in particular to a fan-out wafer-level packaging structure and a packaging method for an integrated photosensitive chip. Background Art

[0002] A photosensitive chip is an electronic device that can emit or receive light and convert light into electrical signals. It is used in electronic devices such as digital cameras and digital video cameras, such as optical communication chips, image sensor chips, etc. It needs to maintain a good optical environment in the cavity to avoid dust, moisture, etc. that affect the optical performance.

[0003] Cavity protection in chip packaging can usually be achieved in the following ways: 1. Metal cover packaging: Use a metal cover to cover the chip and form a sealed cavity with the packaging substrate. The metal cover can provide good electromagnetic shielding and physical protection, and is usually sealed by welding or bonding. 2. Ceramic packaging: Ceramic materials themselves have good airtightness and stability. Through precise ceramic processing technology, a package with a cavity structure can be manufactured and sealed with materials such as metal or glass. 3. Injection molding: Use special injection molding materials to form a sealed cavity structure around the chip; the process parameters need to be strictly controlled during the injection molding process to ensure the airtightness and integrity of the package. 4. Wafer-level packaging (WLP): Encapsulation is performed at the wafer level, and the cavity is formed by processes such as deposition of thin films, photolithography, and etching, and is encapsulated with sealing materials. 5. Glass sealing: The glass is welded to the metal frame or ceramic frame of the package to achieve a sealed cavity. 6. Use of sealant: Fill high-performance sealant between the chip and the packaging structure, and form airtight protection after curing.

[0004] The photosensitive chip has a photosensitive area in a certain area for emitting or receiving light. Due to the nature of the photosensitive area, wiring or plastic sealing on it will affect the photosensitive area of ​​the chip during the packaging process, causing the overall optical performance to decline, thereby affecting the overall performance of the chip. The use of fan-out wafer-level packaging structure to package photosensitive chips can solve the wiring problem of photosensitive chips to a certain extent, but it will be accompanied by the plastic sealing material will contaminate the photosensitive surface, causing the photosensitivity of the chip to be seriously affected.

[0005] In the related art, the photosensitive chip is formed into a single photosensitive package by utilizing the mounting cavity of the substrate, which is then protected by a glass protection structure and buried in a plastic package to realize multi-chip integration, so as to solve the problem of plastic material contaminating the photosensitive surface. However, the production process is complicated, the process is difficult, the cost is high, the CTE of the plastic package is large, the warping is large, and the processing risk is large. Therefore, the packaging structure of the photosensitive chip still needs to be further improved. Summary of the invention

[0006] The present invention aims to solve at least one of the technical problems in the above technologies to some extent. For this purpose, the object of the present invention is to provide a fan-out wafer-level packaging structure and a packaging method integrating a photosensitive chip. The packaging method enables the photosensitive area to be unaffected by reconstruction, has good protection performance, is not affected by optical performance, can perform better cavity protection, has a simple processing technology, can directly perform multi-chip integration, and can reduce the size and thickness of the overall package.

[0007] To achieve the above object, a first aspect of the present invention provides a fan-out wafer-level packaging method integrating a photosensitive chip, which includes the following steps:

[0008] Provide a glass substrate and a semiconductor chip. The glass substrate has opposite first and second surfaces. The semiconductor chip includes a photosensitive chip, and the photosensitive chip forms a bonding wall in the area around its photosensitive area;

[0009] Open at least one blind groove and at least one blind hole in the glass substrate from the first surface, and metallize the blind hole to form a first metal interconnect hole;

[0010] Open a through hole in the glass substrate from the second surface, which communicates with at least one of the blind grooves;

[0011] Embed the semiconductor chip in the blind groove, wherein the photosensitive chip is embedded in the blind groove communicating with the through hole, the photosensitive area is arranged facing the bottom surface of the blind groove, and the photosensitive chip forms a protection cavity between the photosensitive area and the bottom surface of the blind groove through the bonding wall;

[0012] Fabricate a first redistribution structure on the first surface of the glass substrate, and the first redistribution structure is electrically connected to the semiconductor chip;

[0013] Metallize the through hole to form a second metal interconnect hole;

[0014] Fabricate a second redistribution structure on the second surface of the glass substrate. The second redistribution structure is interconnected with the photosensitive chip through the second metal interconnect hole, and the second redistribution structure is interconnected with the first redistribution structure through the first metal interconnect hole;

[0015] Form an opening exposing the second surface on the passivation layer of the second redistribution structure, and the opening is aligned with the photosensitive area to construct a light-transmitting area.

[0016] A fan-out wafer-level packaging method integrating a photosensitive chip according to the present invention can directly integrate the photosensitive chip and other chips into a glass substrate during the process of multi-chip integrated packaging. The processing technology is simple, the cost is low, the integration degree is high, the overall performance can be improved, the glass substrate is integrated, the complex glass bonding process is avoided, and the airtightness is effectively improved; compared with the plastic packaging fan-out solution, the glass-based fan-out can better improve the warping effect caused by CTE mismatch and the chip offset effect caused by the plastic packaging process, and improve the yield of products; in addition, the front circuit of the chip is led to the back for production through the glass-based vertical interconnection structure, and the circuit avoids the photosensitive surface, so that the photosensitive area of the chip is 100% utilized, the overall optical performance is not affected, and the glass top layer protects the photosensitive surface as a cavity, which can effectively avoid the contamination of the photosensitive surface and does not affect the light transmittance, further realizing the photosensitive characteristics of the chip. Glass has good anti-embossing strength to ensure that the photosensitive area of the chip is not affected by reconstruction; furthermore, the glass-based can achieve vertical interconnection, and chip stacking can be performed on the second-layer wiring structure.

[0017] In addition, a fan-out wafer-level packaging method integrating a photosensitive chip proposed above according to the present invention may further have the following additional technical features:

[0018] Optionally, it further includes: manufacturing an external pad on the first-layer wiring structure or / and the second-layer wiring structure, and manufacturing bumps on the external pad.

[0019] Optionally, it further includes thinning the second surface of the glass substrate, then metallizing the through holes and manufacturing the second-layer wiring structure.

[0020] Optionally, at least one first blind groove and at least one second blind groove are formed by opening holes in the glass substrate from the first surface;

[0021] A through hole communicating with the first blind groove is formed by opening a hole in the glass substrate from the second surface;

[0022] The semiconductor chip further includes a first chip. The photosensitive chip is embedded in the first blind groove, and the first chip is embedded in the second blind groove;

[0023] The first-layer wiring structure is electrically connected to both the photosensitive chip and the first chip.

[0024] Optionally, the passivation layer of the first-layer wiring structure covers the first surface and fills the blind groove to cover the surface of the semiconductor chip.

[0025] Optionally, the bonding wall is a dry film layer or a glue layer symmetrically arranged on both sides of the photosensitive area to fix the photosensitive chip in the blind groove.

[0026] Optionally, the number of the second metal via holes corresponds to the number of the lead pads of the photosensitive chip, and the second metal via holes are arranged on both sides of the light-transmitting region.

[0027] To achieve the above object, a second aspect of the present invention provides a fan-out wafer-level packaging structure integrated with a photosensitive chip, including:

[0028] A glass substrate having opposite first and second surfaces, the first surface having at least one blind groove and at least one first metal via hole, and the second surface having a second metal via hole communicating with at least one of the blind grooves;

[0029] A semiconductor chip including a photosensitive chip, the photosensitive chip forming a bonding wall around its photosensitive region to be embedded in the blind groove communicating with the second metal via hole, the photosensitive region facing the bottom surface of the blind groove, and a protection cavity being formed between the photosensitive region and the bottom surface of the blind groove by the bonding wall of the photosensitive chip;

[0030] A first redistribution layer formed on the first surface of the glass substrate, the first redistribution layer being electrically connected to the semiconductor chip;

[0031] A second redistribution layer formed on the second surface of the glass substrate, the second redistribution layer being interconnected with the photosensitive chip through the second metal via hole, and the second redistribution layer being interconnected with the first redistribution layer through the first metal via hole; an opening exposing the second surface is provided on the passivation layer of the second redistribution layer, and the opening is aligned with the photosensitive region to construct a light-transmitting region.

[0032] According to the fan-out wafer-level packaging structure of the present invention, the photosensitive chip and other chip systems can be integrally integrated in the glass substrate, the optical performance is not affected, the glass substrate is integrated, the complex glass bonding process is avoided, and the airtightness is effectively improved.

[0033] In addition, according to the fan-out wafer-level packaging structure integrated with a photosensitive chip proposed above in the present invention, the following additional technical features may further be included:

[0034] Optionally, an external pad is further provided on the first redistribution layer or / and the second redistribution layer, and bumps are provided on the external pad.

[0035] Optionally, the semiconductor chip further includes a first chip;

[0036] The first surface has at least one first blind groove and at least one second blind groove, the first blind groove communicates with the second metal via hole and is used for embedding the photosensitive chip; the second blind groove is used for embedding the first chip;

[0037] The first layer of wiring structure is electrically connected to both the photosensitive chip and the first chip. Description of the Drawings

[0038] Figure 1 It is a process flow chart of the fan-out wafer-level packaging method for the integrated photosensitive chip in the embodiment of the present invention;

[0039] Figure 2 It is a cross-sectional schematic view of the fan-out wafer-level packaging method for the integrated photosensitive chip in the embodiment of the present invention;

[0040] Figures 3 to 11 It is a cross-sectional schematic view of the packaging structure showing the steps of the fan-out wafer-level packaging method for the integrated photosensitive chip illustrated in the embodiment of the present invention;

[0041] Figures 12 - 14 It is a cross-sectional schematic view of the steps for fabricating the bonding wall of the photosensitive chip in the embodiment of the present invention;

[0042] Figure 15 It is a cross-sectional schematic view of chip stacking for the fan-out wafer-level packaging structure of the integrated photosensitive chip in the embodiment of the present invention;

[0043] Reference Numeral Explanation:

[0044] Glass substrate 100, first surface 100a, second surface 100b, blind groove 101, first blind groove 101a, second blind groove 101b, blind hole 102, through hole 103, first metal via 104, second metal via 105;

[0045] Semiconductor chip 200, photosensitive chip 210, bonding wall 211, first chip 220;

[0046] First layer of wiring structure 300, first metal wire layer 310, external pad 320, first passivation layer 330;

[0047] Bump 400;

[0048] Second layer of wiring structure 500, second passivation layer 510, first opening 511, second metal wire layer 520. Detailed Embodiments

[0049] The embodiments of the present invention will be described in detail below. Examples of the embodiments are shown in the drawings, where the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described by referring to the drawings below are exemplary and are intended to explain the present invention, and should not be construed as limiting the present invention.

[0050] To better understand the above technical solution, the exemplary embodiments of the present invention will be described in more detail below with reference to the accompanying drawings. Although the exemplary embodiments of the present invention are shown in the drawings, it should be understood that the present invention can be implemented in various forms and should not be limited by the embodiments set forth herein. On the contrary, these embodiments are provided so that the present invention can be more thoroughly understood and the scope of the present invention can be fully conveyed to those skilled in the art.

[0051] Considering that during the process of integrating and packaging an existing photosensitive chip with other chips (e.g., logic chips), wiring or plastic will affect the photosensitive area of the photosensitive chip, resulting in a decline in optical performance; or the photosensitive chip needs to be pre-fabricated into a single package and then integrated with other chips, with a relatively high process difficulty and processing risk.

[0052] Therefore, the present invention provides a fan-out wafer-level packaging method for integrating a photosensitive chip, which not only solves the wiring problem of the photosensitive chip and ensures the optical performance of the packaging structure, but also solves the problem of high process difficulty in integrating and packaging with other chips. Therefore, the fan-out wafer-level packaging structure of the integrated photosensitive chip of the present invention can achieve 100% utilization of the photosensitive area of the chip, with the overall optical performance unaffected and a high product yield.

[0053] For the fan-out wafer-level packaging method of the integrated photosensitive chip, please refer to Figure 1 , which shows the process flow chart of this packaging method, including the following steps:

[0054] S1: Provide a glass substrate and a semiconductor chip. The glass substrate has opposite first and second surfaces. The semiconductor chip includes a photosensitive chip, and the photosensitive chip forms a bonding wall in the area around its photosensitive area.

[0055] S2: Open at least one blind groove and at least one blind hole in the glass substrate from the first surface, and metallize the blind hole to form a first metal interconnect hole.

[0056] S3: Open a through hole in the glass substrate from the second surface, which is communicated with at least one of the blind grooves.

[0057] S4: Embed the semiconductor chip in the blind groove, wherein the photosensitive chip is embedded in the blind groove communicated with the through hole, the photosensitive area is arranged facing the bottom surface of the blind groove, and a protection cavity is formed between the photosensitive area and the bottom surface of the blind groove through the bonding wall of the photosensitive chip.

[0058] S5: Fabricate a first redistribution structure on the first surface of the glass substrate, and the first redistribution structure is electrically connected to the semiconductor chip.

[0059] S6: Metallize the through holes to form second metal interconnection holes;

[0060] S7: Fabricate a second redistribution layer structure on the second surface of the glass substrate, where the second redistribution layer structure is interconnected with the photosensitive chip through the second metal interconnection holes, and the second redistribution layer structure is interconnected with the first redistribution layer structure through the first metal interconnection holes;

[0061] S8: Form an opening exposing the second surface on the passivation layer of the second redistribution layer structure, where the opening is aligned with the photosensitive area to construct a light-transmitting area.

[0062] This method uses a glass substrate for the package of the fan-out package structure. First, blind grooves 101 and blind holes 102 are formed on the glass substrate 100. Through holes 103 are formed under some of the blind grooves 101 to communicate the blind grooves 101 with the through holes 103. The blind holes 102 are metallized so that the blind holes 102 become first metal interconnection holes. Then, the semiconductor chip 200 is embedded in the blind grooves 101. Then, WLP packaging is performed above the semiconductor chip 200 and on the first surface. After that, the second surface of the glass substrate 100 is thinned and the through holes 103 are metallized to form second metal interconnection holes. Then, a second redistribution layer structure 400 is formed on the second surface, so that the circuits on the front of the photosensitive chip 210 are led to the first redistribution layer structure 300 through the second metal interconnection holes, the second redistribution layer structure 400, and the first metal interconnection holes in sequence. In this way, the circuits on the front of the photosensitive chip 210 are led to the back for fabrication through the glass vertical interconnection structure, and the circuits avoid the photosensitive surface, enabling 100% utilization of the photosensitive area of the photosensitive chip 210 without affecting the overall optical performance. By embedding the photosensitive chip 210 in the glass blind grooves and using the glass at the bottom of the grooves to protect the photosensitive area, multi-chip integration is performed. The glass manufacturing process is simple, low-cost, and has good anti-embossing strength, ensuring that the photosensitive area of the photosensitive chip 210 is not affected by the reconstruction, and can solve the deficiency that the photosensitive surface cannot be realized due to the contamination of the photosensitive surface by the molding compound. Compared with the plastic package fan-out solution, using a glass-based fan-out can better improve the warping effect caused by CTE mismatch and the chip offset effect caused by the plastic packaging process, resulting in yield loss. Using fan-out packaging for multi-chip integration eliminates the substrate, can reduce the size and thickness of the overall package, and has good heat dissipation and electrical performance.

[0063] Thus, in the process of multi-chip integrated packaging, this packaging method can directly integrate the photosensitive chip 210 and other chips into the glass substrate 100 as a whole. The process is simple, with low cost and high integration, which can improve the overall performance. Compared with the plastic packaging fan-out solution, the glass-based fan-out can better improve the warping effect caused by CTE mismatch and the chip offset effect caused by the plastic packaging process, and improve the yield of products. In addition, by using the glass-based vertical interconnection structure to lead the front circuit of the chip to the back for production, the circuit avoids the photosensitive surface, enabling 100% utilization of the photosensitive area of the chip. The overall optical performance is not affected, and the glass top layer protects the photosensitive surface as a cavity, effectively preventing the photosensitive surface from being contaminated and not affecting the light transmittance, further realizing the photosensitive characteristics of the chip. The glass has good anti-embossing strength, ensuring that the photosensitive area of the chip is not affected by reconstruction. Moreover, the glass-based can achieve vertical interconnection, and chip stacking can be done on the second-layer wiring structure.

[0064] The following will further introduce the fan-out wafer-level packaging method for integrated photosensitive chips in conjunction with Figures 3 to 11 which specifically includes:

[0065] First, perform step S1 to provide a glass substrate 100 and a semiconductor chip 200. The glass substrate 100 has opposite first surface 100a and second surface 100b. According to an embodiment of the present invention, the glass substrate 100 can be made of glass materials such as silicate glass, borosilicate glass, sodium magnesium glass, and quartz. The glass substrate 100 has opposite first surface 100a and second surface 100b. It can be understood that the first surface 100a is the front of the glass substrate 100, and the second surface 100b is the back of the glass substrate 100. The glass substrate 100 can be cleaned first.

[0066] According to an embodiment of the present invention, the thickness and size of the glass substrate 100 can be designed according to actual needs. For example, the thickness of the finished product after thinning can be 250 - 350 μm.

[0067] The semiconductor chip 200 includes a photosensitive chip 210 and a first chip 220. For the photosensitive chip 210, please refer to Figures 12 to 14, a bonding wall 211 may be first formed in the area around the photosensitive area on the front side of the photosensitive chip 210, that is, the light-blocking area. Specifically, the photosensitive chip wafer may form a dry film layer or a glue layer on two opposite sides of the photosensitive area on the front side through a lithography process to construct the bonding wall. The glue layer may be a photoresist, and then the photosensitive chip wafer is cut to form individual photosensitive chips 210. For each photosensitive chip 210, its bonding wall 211 is a dry film layer or a glue layer formed on two opposite side edges of the photosensitive area on the front side of the photosensitive chip 210, and the dry film layer or the glue layer forms a second opening on the circuit of the photosensitive chip 210 to facilitate the subsequent second metal interconnection hole to be electrically connected to the circuit. The dry film layer or the glue layer may be pre-fixed corresponding to the blind groove 101 containing the through hole 103.

[0068] Then, please refer to Figure 3 , perform step S2, open at least one blind groove 101 and at least one blind hole 102 on the glass substrate 100 from the first surface 100a, and metalize the blind hole 102 to form a first metal interconnection hole 104. Specifically, different-sized blind grooves 101 and blind holes 102 can be prepared on the first surface 100a of the glass substrate 100 by means of laser-induced combined with wet etching. That is to say, the blind groove 101 penetrates part of the glass substrate 100, which extends from the first surface 100a to part of the glass substrate 100 and does not completely penetrate the glass substrate 100. In this way, the process reliability of the subsequent process can be ensured. The number of blind grooves 101 is designed according to the number of chips to be integrated. For example, in the present embodiment of Figure 4 , two blind grooves 101 are shown, and the sizes of the two blind grooves 101 are different. The two blind grooves 101 can be designed with different widths according to the size of the chip. For the metalization of the blind hole 102, a metal layer containing copper, tin, nickel, or other suitable conductive materials can be formed through a metal electroplating or deposition process to form the first metal interconnection hole 104, and the number of the first metal interconnection holes 104 can be determined according to specific design requirements.

[0069] Next, please refer to Figure 4 , perform step S3, open a through hole 103 on the glass substrate 100 from the second surface 100b, which is communicated with at least one blind groove 101. According to a specific embodiment of the present invention, a through hole 103 communicated with the first blind groove 101a can be opened on the glass substrate 100 from the second surface 100b. That is to say, the front side can be protected first, and then the through hole structure can be formed on the back side. The front side protection can be a paste film layer or a tape, or a temporary bonding carrier. The formation of the through hole 103 can be carried out on the second surface 100b of the glass substrate 100 by means of laser-induced combined with wet etching. Specifically, as Figure 5As shown, the position of the through hole 103 can correspond to the position of the second opening on the bonding wall 211, and the number of through holes 103 matches the number of second openings. More specifically, the width of the through hole 103 can gradually decrease from the second surface 100b to the first blind groove 101a, which is convenient for subsequent metallization of the through hole 103.

[0070] Subsequently, please refer to Figure 5 and Figure 6 , and perform step S4 to embed the semiconductor chip 200 in the blind groove 101, where the photosensitive chip 210 is embedded in the blind groove 101 communicating with the through hole 103, the photosensitive area is arranged facing the bottom surface of the blind groove 101, and a protective cavity is formed between the photosensitive area of the photosensitive chip 210 and the bottom surface of the blind groove 101 through the bonding wall 211; specifically, the photosensitive chip 210 can be embedded in the first blind groove 101a, and the photosensitive chip 210 is pre-fixed in the first blind groove 101a by the bonding wall 211; during this process, the second opening of the bonding wall 211 is aligned with the through hole 103. Then, the first chip 220 is embedded in the second blind groove 101b, and the first chip 220 is mounted in the second blind groove 101b by using the film layer or adhesive layer provided on the back surface of the first chip 220. In this way, a glass-based reconstructed wafer can be formed after the glass substrate 100 is integrally cured.

[0071] Next, please refer to Figure 7 and Figure 8 , and perform step S5 to fabricate a first-level rewiring structure 300 on the first surface 100a of the glass substrate 100, and the first-level rewiring structure 300 is electrically connected to the semiconductor chip 200. Specifically, as Figure 8 shown, in Figure 7On the basis of the glass-based reconstructed wafer, a back film layer or tape is used to protect the second surface 100b of the glass substrate 100; then, dry film filling is performed on the first surface 100a to fix the semiconductor chip 200. That is to say, when manufacturing the first redistribution layer structure 300 on the first surface 100a of the glass substrate 100, first, the first passivation layer 330 of the first redistribution layer structure 300 covers the first surface 100a and fills the blind vias 101 to cover the surface of the semiconductor chip 200, thereby fixing the semiconductor chip 200. Among them, within the first blind via 101a, the first passivation layer 330 is filled to the outside of the bonding wall 211. If the passivation layer is a photoresist, it is formed by a photoresist spin coating process; if it is a dry film layer, a vacuum laminating process is used to fill the gap between the chip and the glass. Preferably, in this embodiment, the first passivation layer (i.e., the first passivation layer 330) is a dry film, which is formed by a vacuum laminating process and is mainly used to fill the gap; the passivation layers of the subsequent layers of the first redistribution layer structure 300 are photoresists, which are formed by a spin coating process. Then, a wiring pattern is formed on the passivation layer by photolithography, and then a metal conductive material is filled in the wiring pattern to form the first metal wire layer 310 electrically connected to the semiconductor chip 200. More specifically, a titanium adhesion layer and a copper seed layer can be first formed by PVD in the wiring pattern, and then a metal layer (copper or other metal conductive materials) is filled by electroplating to complete the RDL wiring and form the first redistribution layer structure 300. The number of layers of the first redistribution layer structure 300 can be selected according to needs, and electronic signals are routed through the first redistribution layer structure 300.

[0072] After that, as Figure 8 shown, a plurality of under bump metallurgies (UBMs) 320 are fabricated on the first redistribution layer structure 300, and bumps 400 are fabricated on the under bump metallurgies 320; that is to say, the under bump metallurgies 320 are fabricated on the first redistribution layer structure 300, and the bumps 400 are fabricated such that the packaging structure can be electrically connected to a PCB board. Specifically, a photoresist can be first covered on the outer surface of the first redistribution layer structure 300; the photoresist is patterned to form a plurality of pad cavities penetrating the photoresist; then, a conductive material is filled into each pad cavity to fabricate a plurality of under bump metallurgies 320, and each under bump metallurgy 320 is electrically connected to the first metal wire layer 310 of the first redistribution layer structure 300; finally, bumps 400 are fabricated on the under bump metallurgies 320, and the bumps 400 can be solder balls or copper pillars, etc. In a more specific embodiment, a photoresist can be formed by a photoresist spin coating process to cover the outer surface of the first redistribution layer structure 300, and then a photolithography opening is formed at the position where the under bump metallurgies 320 need to be fabricated by photolithography. A titanium adhesion layer and a copper seed layer are formed on the photolithography opening by PVD, and finally, the under bump metallurgies 320 are formed by an electroplating hole filling method.

[0073] Among them, the external pad 320 can be fabricated by extending out of the pad cavity and covering the top of the dry film layer located at the periphery of the pad cavity.

[0074] In addition, the bumps 400 can be fabricated by printing and ball placement to form solder balls; or copper pillars can be formed through an electroplating process. Then, the film layer or tape on the second surface 100b is removed.

[0075] Next, as Figure 9 shown, temporary protection is performed on the front side of the first rewiring structure 300 and the bumps 400. Specifically, the first rewiring structure 300 and the bumps 400 can be temporarily bonded to the carrier substrate using a bonding adhesive.

[0076] Subsequently, as Figure 10 shown, the second surface 100b of the glass substrate 100 is thinned to expose the first metal via 104; specifically, the back side of the glass substrate 100 can be ground and thinned and then subjected to CMP processing to reduce the overall thickness of the glass substrate 100.

[0077] After that, please refer to Figure 11 , perform step S6 to metallize the via 103 to form the second metal via 105. Metallization can form a metal layer containing copper, tin, nickel, or other suitable conductive materials through a metal electroplating or deposition process to form the second metal via 105, and the second metal via 105 is connected to the circuit of the photosensitive chip 210 through the second opening of the bonding wall 211.

[0078] Next, please refer to Figure 11 , perform step S7 to fabricate the second rewiring structure 500 on the second surface 100b of the glass substrate 100. The second rewiring structure 500 is interconnected with the photosensitive chip 211 through the second metal via 105, and the second rewiring structure 500 is interconnected with the first rewiring structure 300 through the first metal via 104. That is to say, steps S6 and S7 connect the circuit on the front side of the photosensitive chip 210 to the first rewiring structure 300 on its back side for vertical interconnection.

[0079] Specifically, the second rewiring structure 500 may include a second passivation layer 510 and a second metal line layer 520, and the second metal line layer 520 connects the second metal via 105 and the first metal via 104.

[0080] Subsequently, please refer to Figure 11, perform step S8: form an opening (first opening 511) exposing the second surface 100b on the passivation layer (second passivation layer 510) of the second-level wiring structure 500. The first opening 511 is aligned with the photosensitive region to construct a light-transmitting region. That is, the second passivation layer 510 is opened in the light-transmitting region, and the first opening 511 overlaps with the photosensitive region, thus ensuring the photosensitive characteristics of the photosensitive region. The first opening 511 can be formed by means of existing technologies such as photolithography.

[0081] Finally, debond the first-level wiring structure 300 and the bumps 400 from the carrier substrate; that is, perform debonding on the front surface of the glass substrate 100. The debonding can be carried out by means of existing laser debonding or thermal debonding methods.

[0082] Thus far, as Figure 2 shown, a fan-out wafer-level packaging structure integrating a photosensitive chip is fabricated.

[0083] Please refer to Figure 2 , an embodiment of the present application provides a fan-out wafer-level packaging structure integrating a photosensitive chip. The fan-out wafer-level packaging structure includes a glass substrate 100 having opposite first surface 100a and second surface 100b. The first surface 100a has at least one blind groove 101 and at least one first metal interconnect hole 104. The second surface 100b has a second metal interconnect hole 105 communicating with at least one blind groove 101; a semiconductor chip 200 including a photosensitive chip 210. The photosensitive chip 210 forms a bonding wall 211 in the region around its photosensitive region to be embedded in the blind groove 101 communicating with the second metal interconnect hole 105. The photosensitive region is disposed facing the bottom surface of the blind groove 101, and the photosensitive chip 210 forms a protection cavity between the photosensitive region and the bottom surface of the blind groove 101 through the bonding wall 211; a first-level wiring structure 300 formed on the first surface 100a of the glass substrate 100, and the first-level wiring structure 300 is electrically connected to the semiconductor chip 200; a second-level wiring structure 500 formed on the second surface 100b of the glass substrate 100. The second-level wiring structure 500 is interconnected with the photosensitive chip 210 through the second metal interconnect hole 105, and the second-level wiring structure 500 is interconnected with the first-level wiring structure 300 through the first metal interconnect hole 104; an opening exposing the second surface 100b is provided on the passivation layer of the second-level wiring structure 500, and the opening is aligned with the photosensitive region to construct a light-transmitting region.

[0084] That is to say, the fan-out wafer-level packaging structure can integrally integrate the photosensitive chip with other chip systems in the glass substrate, with high product yield and unaffected optical performance.

[0085] In a specific example, the fan-out wafer-level packaging structure further includes bumps 400 disposed on the first redistribution structure 300, and the bumps 400 are electrically connected to the first metal line layer 310 of the first redistribution structure 300. More specifically, the first redistribution structure 300 is formed on the first surface 100a, and its first metal line layer 310 is electrically connected to the semiconductor chip 200. Then, the semiconductor chip 200 is connected to the PCB board through the bumps 400, so that the semiconductor chip 200 is electrically connected to the circuit of the PCB board. Among them, an external pad 320 electrically connected to the first metal line layer 310 can be fabricated on the first redistribution structure 300 first, and then the bumps 400 are fabricated on the external pad 320.

[0086] In addition, for the first redistribution structure 300, it has a first passivation layer 330. The first passivation layer 330 covers the first surface 100a and fills the blind vias 101 to cover the surface of the semiconductor chip 200. It can be understood that when fabricating the first redistribution structure 300, the blind vias 101 are filled with the first passivation layer 330 first, which can realize the fixation of the semiconductor chip 200. Among them, the first passivation layer 330 can be a dry film.

[0087] For the semiconductor chip 200, it is embedded in the blind vias 101 and can be embedded by means of mounting. For example, for the photosensitive chip 210, the bonding wall 211 on its front surface can be fabricated first, and then the photosensitive chip 210 with the bonding wall 211 is embedded in the blind vias 101 communicating with the second metal via 105. The bonding wall 211 can pre-fix the photosensitive chip 210 in the blind vias 101 to prevent it from shifting. Among them, the bonding wall 211 can be a dry film layer or an adhesive layer to realize pre-fixing the photosensitive chip 210 at the bottom of the blind vias 101. In addition, for other semiconductor chips 200, they can be directly mounted on the bottom of their corresponding blind vias 101 through an adhesive layer or the like.

[0088] More specifically, the semiconductor chip 200 in this embodiment further includes a first chip 220; the first surface 100a has at least one first blind via 101a and at least one second blind via 101b. The first blind via 101a communicates with the second metal via 105 to embed the photosensitive chip 210; the second blind via 101b is adapted to embed the first chip 220. That is to say, two types of blind vias 101 are formed on the first surface 100a. One type of blind via 101 communicates with the second metal via 105 to embed the photosensitive chip 210. The photosensitive chip 210 is connected to the first metal via 104 through the second metal via 105 and the second redistribution structure 500, and then connected to the first redistribution structure 300; the other type of blind via 101 extends from the first surface 100a to a part of the glass substrate 100 and does not completely penetrate the glass substrate 100 to embed the first chip 220. The first chip 220 can be directly mounted in the second blind via 101b through an adhesive layer or the like.

[0089] In addition, the fan-out wafer-level package structure is designed such that external pads can also be provided on the second rewiring structure 500, and bumps are fabricated on the external pads to connect to other chips for chip stacking. For example Figure 15 the package structure shown.

[0090] In the description of the present invention, it should be understood that the orientation or positional relationships indicated by terms such as "center", "longitudinal", "transverse", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", etc. are based on the orientation or positional relationships shown in the drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus should not be construed as a limitation to the present invention.

[0091] In addition, the terms "first" and "second" are only used for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, features defined with "first" and "second" may explicitly or implicitly include one or more of such features. In the description of the present invention, "a plurality of" means two or more unless otherwise specifically defined.

[0092] In the present invention, unless otherwise clearly defined and limited, terms such as "mounted", "connected", "connected to", "fixed" and the like should be understood in a broad sense. For example, it may be a fixed connection, a detachable connection, or integrated; it may be a mechanical connection or an electrical connection; it may be directly connected or indirectly connected through an intermediate medium, and it may be the internal communication of two elements or the interaction relationship between two elements. For those of ordinary skill in the art, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0093] In the present invention, unless otherwise clearly defined and limited, the first feature being "above" or "below" the second feature may include the first and second features being in direct contact, or may include the first and second features not being in direct contact but being in contact through additional features therebetween. Moreover, the first feature being "above", "over" and "on" the second feature includes the first feature being directly above and obliquely above the second feature, or merely indicating that the first feature has a higher horizontal height than the second feature. The first feature being "below", "beneath" and "under" the second feature includes the first feature being directly below and obliquely below the second feature, or merely indicating that the first feature has a lower horizontal height than the second feature.

[0094] In the description of this specification, the description with reference to terms such as "one embodiment", "some embodiments", "examples", "specific examples", or "some examples" means that the specific features, structures, materials, or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representations of the above terms should not be understood as necessarily referring to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described may be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art can combine and combine the different embodiments or examples described in this specification.

[0095] Although the embodiments of the present invention have been shown and described above, it can be understood that the above embodiments are exemplary and should not be construed as limiting the present invention. Those of ordinary skill in the art can make changes, modifications, substitutions, and variations to the above embodiments within the scope of the present invention.

Claims

1. A fan-out wafer-level packaging method for an integrated photosensitive chip, characterized in that: The following steps are involved: A glass substrate and a semiconductor chip are provided, wherein the glass substrate has a first surface and a second surface opposite to each other, and the semiconductor chip includes a photosensitive chip, wherein a bonding wall is formed in an area around a photosensitive area of ​​the photosensitive chip; Opening the glass substrate from the first surface to form at least one blind groove and at least one blind hole, and metalizing the blind hole to form a first metal interconnection hole; Opening a hole in the glass substrate from the second surface to form a through hole communicating with at least one of the blind grooves; The semiconductor chip is embedded in the blind groove, wherein the photosensitive chip is embedded in the blind groove communicating with the through hole, the photosensitive area is arranged facing the bottom surface of the blind groove, and the photosensitive chip forms a protective cavity between the photosensitive area and the bottom surface of the blind groove through the bonding wall; Fabricate a first redistribution structure on the first surface of the glass substrate, wherein the first redistribution structure is electrically connected to the semiconductor chip; Metallizing the through hole to form a second metal interconnection hole; A second rewiring structure is fabricated on the second surface of the glass substrate, wherein the second rewiring structure is interconnected with the photosensitive chip through the second metal interconnection hole, and the second rewiring structure is interconnected with the first rewiring structure through the first metal interconnection hole; An opening is formed on the passivation layer of the second redistribution structure to expose the second surface, and the opening is aligned with the photosensitive area to construct a light-transmitting area.

2. The fan-out wafer-level packaging method of the integrated photosensitive chip according to claim 1, characterized in that: Also includes: An external pad is fabricated on the first redistribution structure and / or the second redistribution structure, and a bump is fabricated on the external pad.

3. The fan-out wafer-level packaging method of the integrated photosensitive chip according to claim 1, characterized in that: The method also includes thinning the second surface of the glass substrate, and then metalizing the through hole and manufacturing the second redistribution structure.

4. The fan-out wafer-level packaging method of the integrated photosensitive chip according to claim 1, characterized in that: Opening a hole in the glass substrate from the first surface to form at least one first blind groove and at least one second blind groove; Opening a hole in the glass substrate from the second surface to form the through hole communicating with the first blind groove; The semiconductor chip further includes a first chip, the photosensitive chip is embedded in the first blind groove, and the first chip is embedded in the second blind groove; The first rewiring structure is electrically connected to both the photosensitive chip and the first chip.

5. The fan-out wafer-level packaging method of the integrated photosensitive chip according to claim 1 or 4, characterized in that: The passivation layer of the first redistribution structure covers the first surface and fills the blind trench to cover the surface of the semiconductor chip.

6. The fan-out wafer-level packaging method of the integrated photosensitive chip according to claim 1, characterized in that: The bonding wall is a dry film layer or glue layer symmetrically arranged on both sides of the photosensitive area to fix the photosensitive chip in the blind groove.

7. The fan-out wafer-level packaging method of the integrated photosensitive chip according to claim 1, characterized in that: The number of the second metal interconnection holes corresponds to the number of the lead-out pads of the photosensitive chip, and the second metal interconnection holes are arranged on both sides of the light-transmitting area.

8. A fan-out wafer-level packaging structure with an integrated photosensitive chip, characterized in that: include: A glass substrate having a first surface and a second surface opposite to each other, wherein the first surface has at least one blind groove and at least one first metal interconnection hole, and the second surface has a second metal interconnection hole communicating with at least one blind groove; A semiconductor chip, comprising a photosensitive chip, wherein a bonding wall is formed in the area around the photosensitive region of the photosensitive chip so as to be embedded in the blind groove communicating with the second metal interconnection hole, wherein the photosensitive region is arranged facing the bottom surface of the blind groove, and the photosensitive chip forms a protective cavity between the photosensitive region and the bottom surface of the blind groove through the bonding wall; A first redistribution structure is formed on a first surface of the glass substrate, wherein the first redistribution structure is electrically connected to the semiconductor chip; A second rewiring structure is formed on the second surface of the glass substrate, the second rewiring structure is interconnected with the photosensitive chip through the second metal interconnection hole, and the second rewiring structure is interconnected with the first rewiring structure through the first metal interconnection hole; The passivation layer of the second redistribution structure has an opening exposing the second surface, and the opening is aligned with the photosensitive area to construct a light-transmitting area.

9. The fan-out wafer-level packaging structure according to claim 8, characterized in that: It also includes an external pad arranged on the first rewiring structure and / or the second rewiring structure, and a bump is arranged on the external pad.

10. The fan-out wafer-level packaging structure according to claim 8, characterized in that: The semiconductor chip further includes a first chip; The first surface has at least one first blind groove and at least one second blind groove, the first blind groove communicates with the second metal interconnection hole and is used to embed the photosensitive chip; the second blind groove is used to embed the first chip; The first rewiring structure is electrically connected to both the photosensitive chip and the first chip.

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