Micro LED epitaxial wafer with vertical structure and preparation method and application of micro LED epitaxial wafer
By forming a polar inverted layer on the substrate of the micro LED, and using it as a peeling sacrificial layer, combined with Cu-Cu bonding and multi-layer passivation layer technology, the problems of crystal quality, peeling efficiency and bonding heat budget of micro LED epitaxial sheets are solved, and efficient and low-cost micro LED chip preparation is achieved.
Patent Information
- Application Number
- CN202510291151.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-03-12
- Publication Date
- 2025-06-10
AI Technical Summary
In the existing micro LED technology, the crystal quality of the epitaxial sheet is difficult to meet the demand for high integration, the method of peeling the substrate is inefficient and costly, and the traditional bonding method has problems such as high-temperature alignment offset and plasma damage.
The epitaxial structure is grown by a method of forming a polar inversion layer on the substrate, and the polar inversion layer is used as a peeling sacrificial layer to achieve chip bonding at low temperatures through Cu-Cu bonding, while multiple passivation layers are deposited on the side walls to reduce plasma damage.
The crystal quality of the epitaxial structure is improved, the cost and time of chip stripping is reduced, the thermal budget and plasma damage is reduced, and the overall performance of micro LED chips is improved.
Smart Images
Figure CN120129367A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the technical field of semiconductor light-emitting devices, and particularly to a vertical structure micro-LED epitaxial wafer, a preparation method thereof, and an application thereof. Background Art
[0002] A micro light-emitting diode (micro-LED) is a semiconductor device that converts electrical energy into light energy. Due to its advantages such as small size, long lifespan, high integration, and low energy consumption, it is widely used in fields such as lighting, display screens, and backlights. With the development of micro-LED technology, it has good application scenarios in augmented reality (AR), virtual reality (VR), and visible light communication, and is considered to be the next-generation display technology.
[0003] The crystal quality of the LED epitaxial wafer directly affects the display effect. Compared with traditional large-size LEDs, the chip size of micro-LEDs is smaller, making the statistical fluctuation of the threading dislocation density between chips on the same epitaxial wafer more significant. Therefore, micro-LEDs require epitaxial wafers with a lower defect density. In addition, vertical structure micro-LEDs need to strip the substrate, which requires an efficient and non-destructive substrate stripping technology, which has an important impact on the mechanical strength and structural integrity of the chips. The commonly used stripping methods are divided into mechanical stripping, chemical stripping, and laser stripping. Currently, the main method used is laser stripping, but its equipment cost is high and it requires precise control of the laser power and beam spot size, and the stripping efficiency is low.
[0004] In addition, the bonding method of micro-LEDs mainly uses the method of heating and pressurizing to perform eutectic alloy bonding between the die and the pad. Currently, Au-In bonding, Au-Au bonding, and Au-Sn bonding are mostly used for bonding, but the price of Au is relatively high, resulting in an increase in production costs. At the same time, the high bonding temperature also increases the thermal budget, which does not conform to the commercial development trend of micro-LEDs; moreover, traditional bonding methods also need to overcome problems such as alignment offset caused by the different thermal expansion coefficients of the transfer head and the target substrate due to the increase in temperature. Due to the reduction of the chip size, the influence of defect states related to the non-radiative recombination process on the sidewalls increases, resulting in a significant reduction in the light emission efficiency of the chips. The traditional method uses plasma-enhanced atomic layer deposition (PEALD) passivation method to reduce the dangling bonds on the sidewalls. However, the PEALD method will cause plasma damage to the chip surface and affect the chip quality. Summary of the Invention
[0005] Aiming at the deficiencies of the prior art, the present invention provides a vertical structure micro-LED epitaxial wafer, which sequentially includes a first substrate, a polarity inversion layer, and an epitaxial structure from bottom to top; wherein, the polarity of the lowermost end of the epitaxial structure is opposite to that of the polarity inversion layer; The material of the polarity inversion layer is aluminum oxynitride.
[0006] Further, a metal reflective layer is further disposed on the top of the epitaxial structure, and a second substrate bonded to the metal reflective layer.
[0007] Further, the metal reflective layer and the second substrate are bonded by Cu-Cu bonding.
[0008] Further, a bonding layer is further disposed between the first substrate and the polarity inversion layer.
[0009] The present invention also provides a method for preparing a vertical structure micro-LED epitaxial wafer, including, Preparing aluminum nitride with nitrogen polarity on a first substrate, and performing heat treatment to form a polarity inversion layer; Growing an epitaxial structure on the surface of the polarity inversion layer of the first substrate with the polarity inversion layer, wherein the polarity of the lowermost end of the epitaxial structure is opposite to that of the polarity inversion layer.
[0010] Further, after growing the epitaxial structure on the surface of the polarity inversion layer of the first substrate, the epitaxial structure is further bonded to a second substrate, specifically including, Growing a metal reflective layer and a first bonding metal layer on the epitaxial structure in sequence; Growing a second bonding metal layer on the second substrate; Bonding the epitaxial structure to the second substrate through the first bonding metal layer and the second bonding metal layer.
[0011] Further, both the first bonding metal layer and the second bonding metal layer are sequentially stacked by Ti with a thickness of 20-50 nm, Cu with a thickness of 200-500 nm, and Ag with a thickness of 20-50 nm; The temperature of the bonding is 120-150 °C.
[0012] During bonding contact, the interface consists of a passivated metal bonding region and a non-bonding region. As the temperature increases, Cu atoms diffuse through the passivation layer (Ag) into the non-bonding region, effectively filling the voids with Cu atoms.
[0013] Further, the first substrate is nitrided, and the nitriding treatment specifically includes, Performing hydrogen cleaning on sapphire at 1100 °C for 5 min; Introducing NH 3 into the MOVPE reactor to nitride the sapphire surface for 20 min.
[0014] The heat treatment lasts for 20-60 min at 800-1000 °C.
[0015] It should be noted that in the present invention, the materials of the first substrate and the second substrate do not need to be strictly limited. Exemplarily, the first substrate can be silicon, silicon on insulator, sapphire, etc., and preferably sapphire; based on the preparation process flow, the second substrate is a conductive material, and can be p-type silicon exemplarily.
[0016] The epitaxial structure is a conventional structure in the art, and can be any blue light epitaxy, green light epitaxy, and red light epitaxy or their combined structure. The basic epitaxial structure includes an n-type material layer, a multi-quantum well active layer, and a p-type material layer from bottom to top.
[0017] The bonding layer is provided to ensure better growth of the epitaxial structure on the first substrate, and the material does not need to be strictly limited. If the epitaxial structure is Ga-based, then the bonding layer can be undoped GaN.
[0018] The present invention also provides an application of the above-mentioned vertical structure micro-LED epitaxial wafer in the preparation of micro-LED chips, including, Etching the polarity inversion layer to separate the epitaxial structure from the first substrate; Preparing an extraction electrode for the epitaxial structure, and preparing a protective layer and a passivation layer on the side of the epitaxial structure to obtain a micro-LED chip.
[0019] Further, the etching is carried out by electrochemical etching, and the etching voltage is 20 - 50V; The material of the protective layer is HfO 2 .
[0020] Further, the passivation layer sequentially includes SiO 2 layer and SiN layer.
[0021] Plasma enhanced atomic layer deposition (PEALD) process has various advantages for thin film processes. On the other hand, due to the photon and ion bombardment of the plasma, PEALD inevitably involves the formation of defects on the sidewalls of the epitaxial structure. The HfO 2 of the protective layer has a relatively high metal oxide bond dissociation energy, which can reduce the dissociation reaction of O during the PEALD process. Preparing the HfO 2 protective layer during the PEALD process can effectively reduce plasma damage. At the same time, the SiO 2 and SiN double-layer passivation layer can effectively improve the chip leakage current characteristics and improve the chip stability.
[0022] Compared with the prior art, the present invention has the following beneficial effects: The present invention can grow a better-quality epitaxial structure through the polarity inversion layer on the substrate. At the same time, the polarity inversion layer is used as a sacrificial layer for subsequent chip peeling, reducing the economic cost of chip peeling and improving the peeling efficiency. Description of the Drawings
[0023] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings required for the description of the embodiments or the prior art. Obviously, the following drawings are some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.
[0024] Figure 1 Shows a schematic structural diagram of the product obtained in step S102 of Embodiment 1; Figure 2 Shows a schematic structural diagram of the product obtained in step S103 of Embodiment 1; Figure 3 Shows a schematic structural diagram of the product obtained in step S104 of Embodiment 1; Figure 4 Shows a schematic structural diagram of the product obtained in step S105 of Embodiment 1; Figure 5 Shows a schematic structural diagram of the product obtained in step S106 of Embodiment 1; Figure 6 Shows a schematic structural diagram of the product obtained in step S107 of Embodiment 1; Figure 7 Shows a schematic structural diagram of the product obtained in step S108 of Embodiment 1; Figure 8 Shows a schematic structural diagram of the product obtained in step S109 of Embodiment 1; Figure 9 Shows a schematic structural diagram of the product obtained in step T101 of Application Example 1; Figure 10 Shows a schematic structural diagram of the product obtained in step T102 of Application Example 1; Figure 11 Shows a schematic structural diagram of the product obtained in step T103 of Application Example 1; Figure 12 Shows a schematic structural diagram of the product obtained in step T104 of Application Example 1; Figure 13 Shows a schematic structural diagram of the product obtained in step T105 of Application Example 1; Figure 14 Shows a schematic structural diagram of the micro-LED chip prepared in Application Example 1; Explanation of reference numerals: 1. Sapphire nitride substrate; 2. Undoped GaN layer; 3. N-polar AlN layer; 4. Polarity inversion layer; 5. n-GaN layer; 6. InGaN / GaN multi-quantum well active layer; 7. p-GaN layer; 8. Metal reflective layer; 9. p-type silicon substrate; 10. Bonding metal layer; 11. n electrode; 12. p electrode; 13. Protective layer; 14. SiO 2 layer; 15. SiN layer. Detailed implementation manners
[0025] In the ranges disclosed in the present invention, the endpoints and any values of the ranges are not limited to the exact ranges or values, and these ranges or values should be understood to include values close to these ranges or values. For numerical ranges, between the endpoint values of each range, between the endpoint values of each range and individual point values, and between individual point values, they can be combined with each other to obtain one or more new numerical ranges, and these numerical ranges should be regarded as specifically disclosed in the present invention.
[0026] Next, the technical solutions in the embodiments of the present invention will be clearly and completely described in conjunction with the specific embodiments and the specification drawings of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the scope of protection of the present invention.
[0027] Embodiment 1 A method for preparing a vertical structure micro-LED epitaxial wafer, the steps are as follows, S101. Nitride the sapphire substrate to obtain a sapphire nitride substrate 1. The nitridation process is to perform a 5-minute hydrogen cleaning on the sapphire at 1100 °C; introduce NH 3 into the MOVPE reactor and keep it for 20 minutes; S102. As Figure 1 shown, using metalorganic chemical vapor deposition (MOVPE), on the sapphire nitride substrate 1, trimethylgallium, trimethylaluminum, and NH 3 are used as precursors of Ga, Al, and N respectively, and an undoped GaN layer 2 with a thickness of 145 nm and an N-polar AlN layer 3 with a thickness of 10 nm are sequentially prepared; S103. As Figure 2 shown, transfer the product obtained in step S102 to an electric furnace in an oxygen atmosphere at 900 °C and anneal it for 30 minutes to convert the N-polar AlN layer 3 into aluminum oxynitride (AlO x N y ), to obtain a polarity inversion layer 4; S104. As Figure 3As shown, an n-GaN layer 5 with a thickness of 2.5 μm is grown on the polarity-inverted layer by MOVPE, where the polarity of the polarity-inverted layer 4 is opposite to that of the n-GaN layer 5; S105. As Figure 4 shown, an InGaN / GaN multi-quantum well active layer 6 with 8 periods and a thickness of about 150 nm is grown on the n-GaN layer 5; S106. As Figure 5 shown, a p-GaN layer 7 with a thickness of 500 nm is grown on the InGaN / GaN multi-quantum well active layer 6; S107. As Figure 6 shown, by using the ion beam sputtering method, Ag with a thickness of 120 nm and TiW with a thickness of 70 nm are sequentially sputtered on the p-GaN layer 7 to form a metal reflective layer 8; S108. As Figure 7 shown, Ti, Cu, and Ag with thicknesses of 30 nm, 300 nm, and 30 nm are sequentially grown on the metal reflective layer 8 and the p-type silicon substrate 9 respectively to form a bonding metal layer 10; S109. As Figure 8 shown, at a temperature of 120 - 150 °C, the bonding metal layer 10 is bonded, and the metal reflective layer 8 and the p-type silicon substrate 9 are bonded together by using Cu-Cu bonding to obtain a vertical structure micro-LED epitaxial wafer.
[0028] Example 2 It is basically the same as Example 1, except that in step S102, an undoped GaN layer is not prepared.
[0029] Application Example 1 The application of the vertical structure micro-LED epitaxial wafer prepared in Example 1 in the preparation of a micro-LED chip is as follows. T101. As Figure 9 shown, the vertical structure micro-LED epitaxial wafer is etched by inductively coupled plasma, and the through holes are dry-etched until the polarity-inverted layer 4 is exposed; T102. As Figure 10 shown, the polarity-inverted layer 4 is etched by electrochemical etching at an etching voltage of 30 V, so that the epitaxial structure is peeled off from the sapphire nitride substrate 1; T103. As Figure 11 shown, an n electrode 11 and a p electrode 12 are respectively prepared on the n-GaN layer 5 and the p-GaN layer 7 of the epitaxial structure by electron beam evaporation technology, where the n electrode 11 is stacked by Cr, Pt, and Au with thicknesses of 8 nm, 20 nm, and 2 μm respectively; the p electrode 12 is stacked by Ti and Au with thicknesses of 10 nm and 5 nm respectively.
[0030] T104. As shown in Figure 12 , through the thermal atomic layer deposition (T-ALD) technique, using hafnium diethylamide and water as precursors, a layer of HfO is deposited on the side of the epitaxial structure 2 as the protective layer 13; T105. As shown in Figure 13 , through the plasma-enhanced atomic layer deposition technique, using SiH 4 and N 2 O as precursors, a SiO layer is deposited on the surface of the protective layer 13 2 layer 14; T106. Through the T-ALD technique, using SiCl 4 and NH 3 as precursors, a SiN layer is deposited on the surface of the SiO 2 layer 14 to obtain the micro-LED chip as shown in Figure 14 .
[0031] The results show that for the micro-LED chip prepared in this application example, the epitaxial growth quality is improved through the polarity inversion layer, and the polarity inversion layer is used as a sacrificial layer during the lift-off process to improve the lift-off efficiency; the use of the Ag-based alloy can reduce the Cu-Cu bonding energy at low temperature and reduce the thermal budget of chip integration; three passivation layers are deposited on the sidewalls to reduce the sidewall effect and minimize plasma damage.
[0032] Overall, the present invention solves the problems of low epitaxial growth quality, difficult lift-off, high thermal budget, and sidewall damage of traditional Micro-LED chips through three special means, providing a new method for realizing the industrialization of Micro-LED.
[0033] Finally, it should be noted that the above are only the preferred embodiments of the present invention and are not used to limit the present invention. Although the present invention has been described in detail with reference to the foregoing embodiments, for those skilled in the art, they can still modify the technical solutions recorded in the foregoing embodiments, or perform equivalent replacements for some of the technical features. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of the present invention shall be included within the protection scope of the present invention.
Claims
1. A vertical structure micro LED epitaxial wafer, characterized in that: It includes, from bottom to top, a first substrate, a polarity inversion layer, and an epitaxial structure; wherein the polarity of the bottom end of the epitaxial structure is opposite to that of the polarity inversion layer; The material of the polarity reversal layer is aluminum nitride oxide.
2. The vertical structure micro LED epitaxial wafer according to claim 1, characterized in that: A metal reflective layer and a second substrate bonded to the metal reflective layer are also provided on the top of the epitaxial structure.
3. The vertical structure micro LED epitaxial wafer according to claim 2, characterized in that: The metal reflective layer is bonded to the second substrate via Cu-Cu bonding.
4. The vertical structure micro LED epitaxial wafer according to any one of claims 1 to 3, characterized in that: A bonding layer is further disposed between the first substrate and the polarity inversion layer.
5. A method for preparing a vertical structure micro LED epitaxial wafer, characterized in that: include, Preparing nitrogen-polar aluminum nitride on a first substrate and performing heat treatment to form a polarity inversion layer; An epitaxial structure is grown on the surface of the polarity inversion layer of the first substrate having the polarity inversion layer, wherein the polarity of the lowermost end of the epitaxial structure is opposite to that of the polarity inversion layer.
6. The method for preparing a vertical structure micro LED epitaxial wafer according to claim 5, characterized in that: After growing an epitaxial structure on the surface of the polarity inversion layer of the first substrate, bonding the epitaxial structure to the second substrate is performed, specifically including: sequentially growing a metal reflective layer and a first bonding metal layer on the epitaxial structure; growing a second bonding metal layer on a second substrate; The epitaxial structure is bonded to the second substrate via the first bonding metal layer and the second bonding metal layer.
7. The method for preparing a vertical structure micro LED epitaxial wafer according to claim 6, characterized in that: The first bonding metal layer and the second bonding metal layer are both formed by sequentially stacking Ti with a thickness of 20-50 nm, Cu with a thickness of 200-500 nm, and Ag with a thickness of 20-50 nm; The bonding temperature is 120-150°C.
8. The method for preparing a vertical structure micro LED epitaxial wafer according to any one of claims 5 to 7, characterized in that: The first substrate is also subjected to nitridation treatment; The heat treatment lasts for 20-60 min at 800-1000°C.
9. A use of the vertical structure micro LED epitaxial wafer according to any one of claims 1 to 4 in preparing a micro LED chip, characterized in that: include, Etching the polarity inversion layer so that the epitaxial structure is peeled off from the first substrate; An extraction electrode of the epitaxial structure is prepared, and a protective layer and a passivation layer are prepared on the side of the epitaxial structure to obtain a micro LED chip.
10. The use according to claim 8, characterized in that: The etching is performed by electrochemical etching, and the etching voltage is 20-50V; The material of the protective layer is HfO2.