Micro-LED light extraction structure and preparation process

Abstract

The invention discloses a Micro-LED light extraction structure, which relates to the field of photoelectricity and comprises first glass for bearing the light extraction structure, a photoresist curing film layer which is arranged on the first surface of the first glass structure and is imprinted and cured by a PDMS template, and a micro lens array arranged on the second surface of the first glass structure, and the surface of the micro-lens array is matched with the PDMS template to be subjected to surface roughening through a nanoimprint process. Meanwhile, the invention further discloses a preparation method of the Micro-LED light extraction structure. According to the invention, a set of PDMS template is adopted to respectively carry out roughening treatment on the glass surface and impressing transfer roughening treatment on the lens surface, so that the light emitting rate is improved, and the light extraction rate of the whole Micro-LED is effectively improved.

Description

Technical Field

[0001] The present invention relates to the field of optoelectronic displays, and particularly to a preparation process for improving the light extraction symmetric flip-chip structure Micro-LED. Background Art

[0002] Micro-LED, also known as mLED or μLED, is a new type of display technology. The Micro-LED technology uses LED light-emitting components with a size of 1 to 60 micrometers to construct a display array to achieve image display. It miniaturizes the traditional inorganic LED array, enabling each LED pixel point with a size of about 10 micrometers to be independently positioned and lit. The Micro-LED display technology is based on the miniaturization and matrixization of micro light-emitting diodes (LEDs), with the size of a single light-emitting unit being less than 50 μm and being highly densely integrated on the chip. As a new type of display technology, Micro-LED has significant advantages such as high brightness, high contrast, high resolution, low power consumption, and long lifespan, and has broad application prospects and development potential in multiple fields.

[0003] In the prior art, the light extraction efficiency of Micor-LED is poor, and the diffuse reflection effect of the light extraction structure is also poor.

[0004] In addition, Micro-LED chips can be divided into: horizontal structure, vertical structure, and flip-chip structure according to the position of the electrodes. The flip-chip structure has the following advantages compared with the other two structures: 1. Excellent heat dissipation performance. The flip-chip structure Micro-LED realizes more efficient heat dissipation by shortening the heat flow path from the heat source to the substrate. 2. High light extraction efficiency. The downward design of the electrodes of the flip-chip structure Micro-LED avoids blocking the emitted light, thereby improving the light extraction efficiency. 3. More uniform current distribution. The flip-chip structure optimizes the electrode layout and current path, enabling the current to be more evenly distributed on the chip surface, thereby improving the light emission efficiency and reliability. However, in the flip-chip structure, an etching platform needs to be fabricated on the light-emitting layer, which will result in a loss of some area, thereby affecting the light emission efficiency and performance of the Micro-LED. And because the p-type electrode is located on one side of the etching platform, the carrier transport distribution in the Micro-LED is uneven, thereby affecting the light emission uniformity. Summary of the Invention

[0005] In view of the above-mentioned partial defects in the prior art, the technical problem to be solved by the present invention is to provide a preparation process for improving the light extraction symmetric flip-chip structure Micro-LED, aiming to improve the light emission efficiency and performance of the Micro-LED and make the Micro-LED emit light more uniformly.

[0006] To achieve the above object, in the first aspect of the present invention, a Micro-LED light extraction structure is provided, and the structure includes:

[0007] A first glass for carrying the light extraction structure;

[0008] A photoresist cured film layer which is imprinted and cured by a PDMS template on the first surface of the first glass structure;

[0009] A microlens array disposed on the second surface of the first glass structure; the surface of the microlens array is roughened by a nanoimprint process in cooperation with the PDMS template.

[0010] In the second aspect of the present invention, a method for preparing a Micro-LED light extraction structure is provided, and the process includes a light extraction structure manufacturing step, including:

[0011] Step SA: Obtain a first silicon wafer that has been surface-roughened as a micro-nano pattern master, uniformly mix polydimethylsiloxane monomer and crosslinking agent, after evacuating and removing bubbles, uniformly spin-coat it on the micro-nano pattern master, heat and cure it after standing, and obtain a polydimethylsiloxane micro-nano structure opposite to the micro-nano pattern master after peeling, that is, a PDMS template;

[0012] Step SB: Coat a photoresist solvent on the first surface of the first glass, invert and imprint the PDMS template on the photoresist solvent, and cure the photoresist solution on the first surface of the first glass by ultraviolet exposure curing, and peel off the PDMS template;

[0013] Step SC: Coat a photoresist on the second surface of the first glass, form a photoresist column through photolithography, then melt the top of the photoresist column by thermal reflux to form an arc structure, and finally obtain a microlens array;

[0014] Step SD: Imprint the PDMS template on the microlens array on the second surface side of the first glass, roughen the surface of the microlens array by a nanoimprint process, and finally form a first light extraction structure;

[0015] Step SE: Place the light extraction structure on the light-emitting surface of the Micro-LED, add a refractive index matching liquid and attach it to the light-emitting surface of the Micro-LED to improve the light extraction efficiency of the Micro-LED.

[0016] Optionally, the process further includes a Micro-LED manufacturing step:

[0017] Step S1: Sequentially lithograph a substrate buffer layer, an n-type layer, a multi-quantum well active region layer, a p-type layer, and a window layer on a first substrate; coat an indium tin oxide layer on the window layer, and bond the indium tin oxide layer to the surface of a sapphire substrate through a first glue layer; strip the first substrate to form an initial substrate on the sapphire substrate.

[0018] Step S2: Coat a first silicon dioxide layer on the substrate buffer layer; coat a first photoresist layer on the first silicon dioxide layer, expose and develop the first photoresist layer, and perform a stepped thinning process on the first photoresist layer so that the first photoresist has a double-stepped structure with a high middle and low around; lithograph the first silicon dioxide layer to form an etched protection layer with a symmetric mesa structure; wherein, the connection between the steps in the double-stepped structure is a slope with a first preset angle.

[0019] Step S3: Perform plasma etching on the initial substrate from one side of the etched protection layer, etch the initial substrate into the window layer, and form a first etched platform at the center position of the initial substrate through the etched protection layer; wherein, the first etched platform is symmetrically mesa-shaped.

[0020] Step S4: Coat a second silicon dioxide layer on the surface of the initial substrate; lithograph the second silicon dioxide layer to obtain an isolation protection layer for isolating the side of the first etched platform.

[0021] Step S5: Coat a first metal conductive layer on the surface of the initial substrate; lithograph the first metal conductive layer to form an n-region metal electrode on the substrate buffer layer respectively, and form a ring-shaped and symmetric p-region metal electrode on the window layer and the isolation protection layer.

[0022] Step S6: Lithograph corresponding n-region pads and p-region pads on the n-region metal electrode and the p-region metal electrode respectively to obtain a symmetric flip-chip structure Micro-LED.

[0023] Optionally, in step S3, it further includes:

[0024] Etch the initial substrate into the p-type layer, and form a first etched platform through the etched protection layer.

[0025] Optionally, before step S2, the process further includes:

[0026] Determine the shape and size of the etched protection layer according to the etching rate of each layer of the initial substrate in plasma etching, the etching rate of silicon dioxide in plasma etching, and the shape and size of the first etched platform.

[0027] Determine the position and thickness of the thinning process for the first photoresist layer according to the shape and size of the etched protective layer.

[0028] Optionally, the etched portion in step S3 includes the first etched protective layer, the substrate buffer layer, the n-type layer, the multi-quantum well active region layer, the p-type layer, and the window layer, and the etched protective layer is completely etched away.

[0029] Optionally, the angle between the edge of the first etching platform and the bottom surface of the first etching platform is 65° - 80°.

[0030] Optionally, the thickness of the window layer is greater than the thickness of the p-type layer.

[0031] Optionally, the thickness of the window layer formed by etching is 400 nm - 4 μm.

[0032] Optionally, the lithography process includes: coating photoresist, exposure, development, and etching.

[0033] Advantages of the present invention: 1. The present invention uses a set of PDMS templates to roughen the glass surface and perform imprint transfer roughening on the lens surface respectively, improving the light extraction rate and effectively enhancing the overall light extraction efficiency of Micro-LEDs. 2. The first etching platform for preparing Micro-LEDs in the present invention is a symmetric center-symmetric platform-like structure. Under the condition of the same volume as the etching platform in the prior art, the first etching platform of the present invention is narrow at the top and wide at the bottom. Therefore, the etching area of the light-emitting layer can be reduced, thereby reducing the impact on the light-emitting efficiency and performance of Micro-LEDs and improving the light-emitting efficiency and performance of Micro-LEDs. 3. The p-region metal electrode for preparing Micro-LEDs in the present invention is annular and the overall structure of the Micro-LED is symmetric, avoiding the situation where carrier transport aggregates on one side, making the carrier transport more uniform, and thus increasing the light-emitting uniformity of Micro-LEDs. 4. The p-region metal electrode of the present invention covers the isolation protection layer, which can reflect the light emitted by the Micro-LED and make it emit from the light-emitting port, avoiding the reduction of the light-emitting rate caused by the light emitted by the flip-chip structure Micro-LED leaking from the side. 5. Due to the symmetric structure, the Micro-LED of the present invention can reduce the incident angle of part of the light emitted from the multi-quantum well active region layer on the window layer, thereby reducing total internal reflection and avoiding the problem of reduced light-emitting efficiency caused by total internal reflection consumption. 6. For the Micro-LED prepared in the present invention, its p-region metal electrode is connected to the window layer. On the one hand, it reduces the local high resistance when carriers pass through the P-type layer from the corners, resulting in a lower voltage drop of the p-region metal electrode, enabling more carriers to recombine, and thus improving the light-emitting efficiency; on the other hand, since the p-region metal electrode is no longer directly connected to the p-type layer, carriers will not aggregate at the connection between the p-region metal electrode and the p-type layer, and thus the carrier transport distribution is more uniform, making the light emission more uniform.

[0034] In summary, the present invention improves the light-emitting efficiency and light-emitting performance of Micro-LEDs and makes the light emission of Micro-LEDs more uniform. Description of the Drawings

[0035] Figure 1 is a process flow diagram of a preparation process for an improved light extraction symmetric flip-chip structure Micro-LED provided by a specific embodiment of the present invention;

[0036] Figure 2 is a process flow diagram of the symmetric flip-chip structure Micro-LED in step S1 provided by a specific embodiment of the present invention;

[0037] Figure 3 is a process flow diagram of the symmetric flip-chip structure Micro-LED in step S2 provided by a specific embodiment of the present invention;

[0038] Figure 4 It is a process flow diagram of a symmetric flip-chip structure Micro-LED in step S3 provided by a specific embodiment of the present invention;

[0039] Figure 5 It is a process flow diagram of a symmetric flip-chip structure Micro-LED in step S4 provided by a specific embodiment of the present invention;

[0040] Figure 6 It is a process flow diagram of a symmetric flip-chip structure Micro-LED in step S5 provided by a specific embodiment of the present invention;

[0041] Figure 7 It is a top view structure diagram of the product in step S5 provided by a specific embodiment of the present invention;

[0042] Figure 8 It is a change diagram of a symmetric flip-chip structure Micro-LED in step S6 provided by a specific embodiment of the present invention;

[0043] Figure 9 It is a structure diagram of a finished product of a symmetric flip-chip structure Micro-LED provided by a specific embodiment of the present invention;

[0044] Figure 10 It is a partial optical path comparison diagram of a symmetric flip-chip structure Micro-LED and a prior art Micro-LED provided by a specific embodiment of the present invention;

[0045] Figure 11 It is a structure diagram of multiple finished products of a symmetric flip-chip structure Micro-LED provided by a specific embodiment of the present invention;

[0046] Figure 12 It is a process flow chart of PDMS template manufacturing provided by a specific embodiment of the present invention;

[0047] Figure 13 It is a process flow chart of lens array manufacturing provided by a specific embodiment of the present invention;

[0048] Figure 14 It is a process flow chart of light extraction structure manufacturing provided by a specific embodiment of the present invention. Detailed Embodiment

[0049] The present invention discloses a preparation process for improving the light extraction of a symmetric flip-chip structure Micro-LED. Those skilled in the art can draw on the content of this article and appropriately improve the technical details to implement it. It should be particularly noted that all similar substitutions and modifications are obvious to those skilled in the art, and they are all considered to be included in the present invention. The method and application of the present invention have been described through preferred embodiments. Relevant personnel can obviously make changes or appropriate alterations and combinations to the methods and applications described herein without departing from the content, spirit, and scope of the present invention to implement and apply the technology of the present invention.

[0050] In the first embodiment of the present invention, a Micro-LED light extraction structure is provided, and the structure includes:

[0051] A first glass for carrying the light extraction structure;

[0052] A photoresist cured film layer imprinted and cured through a PDMS template on the first surface of the first glass structure;

[0053] A microlens array disposed on the second surface of the first glass structure; the surface of the microlens array is roughened by a nanoimprint process in cooperation with the PDMS template.

[0054] In the second embodiment of the present invention, a preparation process for a Micro-LED light extraction structure is provided, and the process includes: a Micro-LED manufacturing step and a light extraction structure manufacturing step.

[0055] Among them, the Micro-LED manufacturing step includes:

[0056] Step S1: Photolithographically pattern a substrate buffer layer, an n-type layer, a multi-quantum well active region layer, a p-type layer, and a window layer on a first substrate in sequence; coat an indium tin oxide layer on the window layer, bond the indium tin oxide layer to the surface of a sapphire substrate through a first glue layer; strip the first substrate to form an initial substrate on the sapphire substrate;

[0057] Step S2: Coat a first silicon dioxide layer on the substrate buffer layer; coat a first photoresist layer on the first silicon dioxide layer, expose and develop the first photoresist layer, and perform a stepped thinning process on the first photoresist layer to make the first photoresist have a double-stepped structure that is high in the middle and low around; perform photolithography on the first silicon dioxide layer to form an etching protection layer with a symmetric mesa structure; wherein, the connection between the steps in the double-stepped structure is a slope with a first preset angle;

[0058] Step S3: Perform plasma etching on the initial substrate from one side of the etching protection layer, etch the initial substrate into the window layer, and form a first etching platform at the central position of the initial substrate through the etching protection layer; wherein, the first etching platform is a symmetric table shape.

[0059] Step S4: Coat a second silicon dioxide layer on the surface of the initial substrate; perform photolithography on the second silicon dioxide layer to obtain an isolation protection layer for isolating the side of the first etching platform.

[0060] Step S5: Coat a first metal conductive layer on the surface of the initial substrate; perform photolithography on the first metal conductive layer to form an n-region metal electrode on the substrate buffer layer respectively, and form a ring-shaped and symmetric p-region metal electrode on the window layer and the isolation protection layer.

[0061] Step S6: Photolithograph corresponding n-region pads and p-region pads on the n-region metal electrode and the p-region metal electrode respectively to obtain a symmetric flip-chip structure Micro-LED.

[0062] In the following example description, the first substrate uses a gallium arsenide substrate, and other substrates can be used in actual applications, such as a sapphire substrate, and the present invention is not limited thereto; similarly, in this example, the substrate buffer layer uses a gallium arsenide buffer layer, an n-type aluminum gallium nitride layer is used as the n-type layer, a p-type aluminum gallium nitride layer is used as the P-type layer, and gallium nitride is used as the window layer. The above is illustrative and does not limit the protection scope of the present invention.

[0063] As Figure 1-11 shown, the process of this example includes:

[0064] Step S1: Photolithograph a gallium arsenide buffer layer 102, an n-type aluminum gallium nitride layer 103, a multi-quantum well active region layer 104, a p-type aluminum gallium nitride layer 105, and a gallium nitride window layer 106 on the gallium arsenide substrate 101 in sequence; coat an indium tin oxide layer 107 on the gallium nitride window layer 106, bond the surface of the indium tin oxide layer 107 to the surface of the sapphire substrate 109 through the first glue layer 108; strip the gallium arsenide substrate 101 to form an initial substrate on the sapphire substrate 109.

[0065] In this specific embodiment, the process of Step S1 can be as Figure 2 shown.

[0066] It should be noted that gallium arsenide (GaAs), gallium buffer layer (GaAs), n-type aluminum gallium nitride layer 103 (n-AlGaN), multi-quantum well active region layer 104 (MQW), p-type aluminum gallium nitride layer 105 (p-AlGaN), gallium nitride window layer 106 (GaN), indium tin oxide layer 107 (ITO) are their chemical formulas in the brackets.

[0067] In this specific embodiment, the thickness of the gallium nitride window layer 106 is greater than that of the p-type aluminum gallium nitride layer 105.

[0068] In this specific embodiment, the thickness of the gallium nitride window layer 106 formed by etching is 400 nm - 4 μm.

[0069] It should be noted that the thickness of the gallium nitride window layer 106 is greater than that of the p-type aluminum gallium nitride layer 105. Therefore, when etching to the gallium nitride window layer 106, there is a relatively large tolerance rate to ensure that the gallium nitride window layer 106 will not be etched through, thereby improving the yield. The indium tin oxide layer is transparent and does not block the light output. Sapphire has high optical transparency, and its transmittance in the ultraviolet to near-infrared band exceeds 85%, providing an important guarantee for the high light output of the LED device.

[0070] It is worth mentioning that the sapphire substrate 109 is a shared substrate and can bond multiple initial substrates.

[0071] Step S2: Deposit a first silicon dioxide layer on the gallium arsenide buffer layer 102; coat a first photoresist layer 111 on the first silicon dioxide layer, expose and develop the first photoresist layer 111, and perform a stepped thinning process on the first photoresist layer 111 to make the first photoresist have a double-stepped structure with a high middle and low around; perform photolithography on the first silicon dioxide layer to form an etching protection layer 110 with a symmetric mesa structure.

[0072] Among them, the connection between the steps in the double-stepped structure is a ramp with a first preset angle.

[0073] In this specific embodiment, the process of step S2 is as Figure 3 shown. The chemical formula of the silicon dioxide layer is SiO2.

[0074] It should be noted that through the thinning process of the photoresist, since the thinner part of the photoresist is consumed faster during the etching process, the etching time of the first silicon dioxide layer at the thinner part is longer and the etching is deeper, thereby forming an etching protection layer 110 with a symmetric mesa structure.

[0075] In this embodiment, before step S2, the process further includes:

[0076] Determine the shape and size of the etching protection layer 110 according to the etching rates of each layer of the initial substrate in plasma etching, the etching rate of silicon dioxide in plasma etching, and the shape and size of the first etching platform;

[0077] Determine the position and thickness of the thinning process for the first photoresist layer 111 according to the shape and size of the etching protection layer 110.

[0078] It should be noted that in this way, the shape and size of the first etching platform can be effectively controlled to meet the requirements.

[0079] Step S3: Perform plasma etching on the initial substrate from one side of the etching protection layer 110, etch the initial substrate into the gallium nitride window layer 106, and form a first etching platform at the center position of the initial substrate through the etching protection layer 110.

[0080] Among them, the first etching platform is a symmetric table shape.

[0081] In this specific embodiment, the process of step S3 is as Figure 4 shown.

[0082] It should be noted that due to the symmetric table-shaped structure of the etching protection layer 110, the etching time at each position of the initial substrate is different (the etching time at the center is short, and the surrounding is low), and thus a symmetric table-shaped first etching platform is formed. ICP etching, that is, plasma etching, is a technology that uses the high-density plasma generated by the glow discharge of gas to bombard the surface of the material for etching. The basic principle of ICP etching is that under a low vacuum pressure, the RF output generated by the ICP RF power supply is output to the annular coupling coil, and a certain proportion of mixed etching gas undergoes coupled glow discharge to generate high-density plasma (including ions, electrons, active particles, photons, and excited atoms). The power directly affects the ionization rate of the plasma, thereby affecting the density of the plasma. Under the action of the RF of the lower electrode, these heavy ions physically bombard the surface of the chip, the chemical bonds of the semiconductor material in the chip pattern area are broken, and the active particles react chemically with the material in the pattern area to generate volatile substances, which are removed from the chip in the form of gas and pumped away through the vacuum pipeline, so as to transfer the pattern on the photoresist mask to the chip.

[0083] In this specific embodiment, since it is only etched to the surface of the gallium nitride window layer 106, and the thicknesses of the n-type aluminum gallium nitride layer 103 and the p-type aluminum gallium nitride layer 105 are basically the same. As shown in the figure, there is also a gallium arsenide buffer layer 102 above the n-type aluminum gallium nitride layer 103. Therefore, on the premise that the volume of the first etching platform is the same as that of the prior art, the loss area of its multi-quantum well active region layer 104 is small, and thus the influence on the luminous efficiency and luminous performance is also small.

[0084] In this specific embodiment, in step S3, it further includes:

[0085] Etch the initial substrate into the p-type aluminum gallium nitride layer 105, and form a first etching platform through the etching protection layer 110.

[0086] It should be noted that the prior art can also achieve the function by etching to the p-type aluminum gallium nitride layer 105.

[0087] In this specific embodiment, in step S3, the etching part includes a first etching protection layer 110, a gallium arsenide buffer layer 102, an n-type aluminum gallium nitride layer 103, a multi-quantum well active region layer 104, a p-type aluminum gallium nitride layer 105, and a gallium nitride window layer 106, and the etching protection layer 110 is completely etched away.

[0088] In this specific embodiment, the angle between the edge of the first etching platform and the bottom surface of the first etching platform is 65° - 80°.

[0089] It should be noted that a larger angle indicates that the etched loss areas of each layer of the initial substrate are almost the same, which is more conducive to light emission. The first etching platform is a symmetric platform shape, and its side has a slope, which can facilitate the coating in step S4.

[0090] Step S4: Coat a second silicon dioxide layer on the surface of the initial substrate; perform photolithography on the second silicon dioxide layer to obtain an isolation protection layer 112 for isolating the side surface of the first etching platform.

[0091] In this specific embodiment, the process of step S4 is as Figure 5 shown.

[0092] Step S5: Coat a first metal conductive layer 113 on the surface of the initial substrate; perform photolithography on the first metal conductive layer 113 to form an n-region metal electrode 114 on the gallium arsenide buffer layer 102 respectively, and form a ring-shaped and symmetric p-region metal electrode 115 on the gallium nitride window layer 106 and the isolation protection layer 112.

[0093] In this specific embodiment, the process of step S5 is as Figure 6 shown.

[0094] It should be noted that the material of the first metal layer can be metals and metal alloys such as gold (Au), germanium (Ge), and nickel (Ni).

[0095] Figure 7 is a top view structural schematic diagram of the product of step S5.

[0096] Step S6: Photolithograph corresponding n-region pads 116 and p-region pads 117 on the n-region metal electrode 114 and the p-region metal electrode 115 respectively to obtain a symmetric flip-chip structure Micro-LED.

[0097] In this specific embodiment, the process of step S6 is as Figure 8 shown. Finally, the finished product can be as Figure 9 shown. Figure 11 is a structural schematic diagram of multiple finished products on the same substrate.

[0098] It is worth mentioning that the schematic diagram of the partial optical path comparison between the symmetric flip-chip structure Micro-LED provided by the embodiments of the present invention and the Micro-LED of the prior art can be as Figure 10 shown in Figure 10 which, θ 1 <θ 2 . For the prior art, the incident angle of some light rays emitted from the quantum well active region layer on the gallium nitride window layer 106 is larger, there is more total reflection, and the light loss is large. However, in the embodiments of the present invention, the incident angle of some light rays emitted from the multi-quantum well active region layer 104 on the gallium nitride window layer 106 can be reduced, thereby reducing total reflection and avoiding the problem of reduced luminous efficiency caused by total reflection consumption.

[0099] In this specific embodiment, the lithography process includes: coating photoresist, exposure, development, and etching.

[0100] The first etching platform for preparing the Micro-LED in the embodiments of the present invention is a symmetric center-symmetric table-like structure. Under the condition of the same volume as the etching platform of the prior art, the first etching platform of the embodiments of the present invention is narrow at the top and wide at the bottom. Therefore, the light-emitting layer can reduce the etching area, thereby reducing the impact on the luminous efficiency and performance of the Micro-LED and improving the luminous efficiency and performance of the Micro-LED.

[0101] The p-region metal electrode 115 of the Micro-LED prepared in the embodiments of the present invention is annular and the overall structure of the Micro-LED is symmetric, avoiding the situation where carrier transport aggregates on one side, making the carrier transport more uniform, and thereby increasing the luminous uniformity of the Micro-LED. 3. The p-region metal electrode 115 of the embodiments of the present invention covers the isolation protection layer 112, and can reflect the light emitted by the Micro-LED to make it emit from the light-emitting port, avoiding the reduction of the luminous rate caused by the light emitted by the flip-chip structure Micro-LED leaking from the side.

[0102] Due to the symmetric structure, the Micro-LED in the embodiments of the present invention can reduce the incident angle of some light rays emitted from the multi-quantum well active region layer 104 on the gallium nitride window layer 106, thereby reducing total reflection and avoiding the problem of reduced luminous efficiency caused by total reflection consumption.

[0103] In the Micro-LED prepared in the embodiment of the present invention, the p-region metal electrode 115 is connected to the gallium nitride window layer 106. On the one hand, carriers do not need to pass through the p-type aluminum gallium nitride layer 105 (which has resistance) anymore, and the voltage drop of the p-region metal electrode 115 becomes lower, enabling more carriers to recombine, thereby improving the luminous efficiency. On the other hand, since the p-region metal electrode 115 is no longer directly connected to the p-type aluminum gallium nitride layer 105, carriers will not accumulate at the connection between the p-region metal electrode 115 and the p-type aluminum gallium nitride layer 105, and thus the carrier transport distribution becomes more uniform, making the light emission more uniform.

[0104] In summary, the embodiment of the present invention improves the luminous efficiency and luminous performance of the Micro-LED, and makes the light emission of the Micro-LED more uniform.

[0105] Furthermore, the process provided in this embodiment further includes a step of fabricating a light extraction structure, including:

[0106] Step S7: Obtain a first silicon wafer that has undergone surface roughening treatment as a micro-nano pattern master. Uniformly mix a polydimethylsiloxane monomer and a crosslinking agent in a preset ratio. After evacuating and removing bubbles, spin-coat it uniformly on the micro-nano pattern master, heat and cure it after standing, and obtain a polydimethylsiloxane micro-nano structure opposite to the micro-nano pattern master, that is, a PDMS template after peeling.

[0107] Step S8: Coat a photoresist solvent on the first surface of the first glass. Invert and imprint the PDMS template on the photoresist solvent, and cure the photoresist solution on the first surface of the first glass by ultraviolet exposure curing, and peel off the PDMS template.

[0108] As Figure 12 shown, the roughened silicon wafer is obtained by etching with a KOH solution and heating at 80 °C for 15 min, and is used as the micro-nano pattern master 201. The PDMS soft film 202 is prepared by a soft printing method. A polydimethylsiloxane monomer and a crosslinking agent are uniformly mixed in a preset ratio. After evacuating and removing bubbles, spin-coat it uniformly on the micro-nano pattern master 201, heat and cure it after standing, and obtain a polydimethylsiloxane micro-nano structure opposite to the micro-nano pattern master, that is, the PDMS template 202 after peeling. Then, spin-coat the ultraviolet photoresist NOA63 on the glass substrate. Then, drop the photoresist NOA63 on the glass substrate and spin-coat it at a speed of 2000 rpm for 60 s. After the spin-coating is completed, press the prepared PDMS soft template with microstructures on the photoresist, gently press the PDMS template to make it fully contact with the photoresist, and then slowly remove the bubbles with small tweezers. Finally, cure the sample under ultraviolet light emitted by a xenon lamp with an irradiance of 12 mW / cm2 for 15 min. Finally, peel off the PDMS template, and a roughened surface of the photoresist film is prepared on the glass substrate.

[0109] Step S9. Apply photoresist on the second surface of the first glass, form photoresist columns through photolithography, then melt the top of the photoresist columns through thermal reflux to form an arc structure, and finally obtain a microlens array.

[0110] As Figure 13 shown, drop photoresist AZ4620 on the cleaned glass wafer, and use the spin coating process to spin coat for 30 s at a speed of 2000 rpm to obtain a uniform photoresist film with a thickness of about 3 μm. Then pre-bake the glass substrate and bake it in an oven at 100 °C for 10 min to remove excess solvent and moisture in the photoresist. Next, place the designed mask plate on the glass, and under the irradiation of an ultraviolet high-pressure mercury lamp, expose the photoresist template, and the ultraviolet exposure time is 180 s. Then use the developer solution matching the photoresist for development to remove the solvent residue between the photoresist columns prepared by photolithography. Finally, place the entire sample on a hot plate and heat it at 140 °C for 15 min for the thermal reflux process. The photoresist at the top of the cured photoresist columns will melt under the action of high temperature, and due to the action of its surface tension, a hemispherical structure with a certain curvature will be formed at its top, and finally the microlens array 204 is obtained.

[0111] As Figure 14 shown, step S10. Press the PDMS template on the microlens array 204 on the second surface side of the first glass, and roughen the surface of the microlens array through nanoimprint lithography to finally form a first light extraction structure.

[0112] Step S11. Place the light extraction structure on the light-emitting surface of the Micro-LED, add a refractive index matching liquid and attach it to the light-emitting surface of the Micro-LED to improve the light extraction efficiency of the Micro-LED.

[0113] It should be noted that in this article, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the term "comprising", "including" or any other variant thereof is intended to cover non-exclusive inclusion, so that a process, method, article or device comprising a series of elements not only includes those elements, but also includes other elements not expressly listed, or also includes elements inherent to such process, method, article or device. Without further limitation, an element defined by the statement "comprising a..." does not exclude the existence of additional identical elements in the process, method, article or device comprising the element.

[0114] Each embodiment in this specification is described in a related manner. For the same or similar parts among the embodiments, reference can be made to each other. Each embodiment focuses on the differences from other embodiments. In particular, for the system embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and reference can be made to the relevant part of the method embodiment for the related content.

[0115] The above are only the preferred embodiments of the present invention, and are not intended to limit the protection scope of the present invention. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of the present invention are included in the protection scope of the present invention.

Claims

1. A Micro-LED light extraction structure, characterized in that: The structure comprises: a first glass for carrying a light extraction structure; A photoresist cured film layer is disposed on the first surface of the first glass structure and is printed and cured by a PDMS template; A microlens array is arranged on the second surface of the first glass structure; the surface of the microlens array is roughened by nanoimprinting process in cooperation with the PDMS template.

2. A method for preparing a Micro-LED light extraction structure, characterized in that: The process includes a light extraction structure fabrication step, including: Step SA, obtaining a first silicon wafer that has been subjected to a surface roughening treatment as a micro-nano pattern master, uniformly mixing a polydimethylsiloxane monomer and a cross-linking agent in a preset ratio, and evenly spin-coating the mixture on the micro-nano pattern master after vacuuming and degassing, and heating and curing the mixture after standing, and peeling off to obtain a polydimethylsiloxane micro-nano structure opposite to the micro-pattern master, i.e., a PDMS template; Step SB, coating a photoresist solvent on the first surface of the first glass, placing the PDMS template upside down and imprinting it on the photoresist solvent, curing the photoresist solution on the first surface of the first glass by UV exposure, and peeling off the PDMS template; Step SC, coating the second surface of the first glass with photoresist, forming a photoresist column by photolithography, and then melting the top of the photoresist column by thermal reflow to form an arc structure, and finally obtaining a microlens array; Step SD, imprinting the PDMS template on the microlens array on the second surface side of the first glass, roughening the surface of the microlens array by nanoimprinting process, and finally forming a first light extraction structure; Step SE, placing the light extraction structure on the light emitting surface of the Micro-LED, adding a refractive index matching liquid and attaching it to the light emitting surface of the Micro-LED to improve the light extraction efficiency of the Micro-LED.

3. A method for preparing a Micro-LED light extraction structure according to claim 2, characterized in that: The process also includes the following Micro-LED production steps: Step S1, sequentially photolithographically etching a substrate buffer layer, an n-type layer, a multi-quantum well active region layer, a p-type layer, and a window layer on a first substrate; coating an indium tin oxide layer on the window layer, and bonding the indium tin oxide layer to the surface of a sapphire substrate through a first glue layer; peeling off the first substrate, and forming an initial matrix on the sapphire substrate; Step S2, coating a first silicon dioxide layer on the substrate buffer layer; coating a first photoresist layer on the first silicon dioxide layer, exposing and developing the first photoresist layer, and performing a step-thinning process on the first photoresist layer so that the first photoresist has a double-step structure with a high middle and low surroundings; performing photolithography on the first silicon dioxide layer to form an etching protection layer with a symmetrical terrace-shaped structure; wherein the connection between the steps in the double-step structure is a slope with a first preset angle; Step S3, performing plasma etching on the initial substrate from one side of the etching protection layer, etching the initial substrate into the window layer, and forming a first etching platform at the center of the initial substrate through the etching protection layer; wherein the first etching platform is symmetrically table-shaped; Step S4, coating a second silicon dioxide layer on the surface of the initial substrate; performing photolithography on the second silicon dioxide layer to obtain an isolation protection layer for isolating the side of the first etching platform; Step S5, coating a first metal conductive layer on the surface of the initial substrate; performing photolithography on the first metal conductive layer to form an n-region metal electrode on the substrate buffer layer, and to form a ring-shaped symmetrical p-region metal electrode on the window layer and the isolation protection layer; Step S6, respectively photolithography corresponding n-region pads and p-region pads on the n-region metal electrode and the p-region metal electrode to obtain a symmetrical flip-chip structure Micro-LED.

4. The process for preparing a symmetrical flip-chip Micro-LED with improved light extraction according to claim 3, characterized in that: The step S3 also includes: The initial substrate is etched into the p-type layer, and a first etching platform is formed through the etching protection layer.

5. The process for preparing a symmetrical flip-chip Micro-LED with improved light extraction according to claim 3, characterized in that: Before step S2, the process further includes: Determining the shape and size of the etching protection layer according to the etching speed of each layer of the initial substrate in the plasma etching, the etching speed of silicon dioxide in the plasma etching, and the shape and size of the first etching platform; The position and thickness of the first photoresist layer to be thinned are determined according to the shape and size of the etching protection layer.

6. The process for preparing a symmetrical flip-chip Micro-LED with improved light extraction according to claim 3, characterized in that: The etched portion in step S3 includes the first etching protection layer, the substrate buffer layer, the n-type layer, the multi-quantum well active region layer, the p-type layer and the window layer, and the etching protection layer is completely etched away.

7. The process for preparing a symmetrical flip-chip Micro-LED with improved light extraction according to claim 3, characterized in that: The angle between the edge of the first etching platform and the bottom surface of the first etching platform is 65°-80°.

8. The process for preparing a symmetrical flip-chip Micro-LED with improved light extraction according to claim 3, characterized in that: The thickness of the window layer is greater than the thickness of the p-type layer.

9. The process for preparing a symmetrical flip-chip Micro-LED with improved light extraction according to claim 3, characterized in that: The thickness of the window layer formed by etching is 400nm-4μm.

10. The process for preparing a symmetrical flip-chip Micro-LED with improved light extraction according to claim 3, characterized in that: The photolithography process includes: coating photoresist, exposure, development and etching.

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