Memory device fragmentization analysis based on logical-to-physical table

Abstract

The invention relates to fragmented evaluation in a memory system. In one example, a method for operating a memory controller includes receiving, from a host, a request for a fragmentation level of a file stored in a memory device. The method further includes determining a read performance level of the file based on a logic-to-physical (L2P) address mapping table corresponding to the file, without reading the file from the memory device. The method also includes determining a fragmentation level based on the read performance level.

Description

Technical Field

[0001] The present disclosure generally relates to memory devices and memory systems, and more particularly, to systems and methods for defragmenting memory devices. Background Art

[0002] Data stored in a memory device may become fragmented over time. Fragmentation may slow down the performance of the memory device by reducing the access and processing speed of the memory device. In some embodiments, fragmentation further results in undesirable damage and data loss in the memory device. Defragmentation is a process of reducing the degree of fragmentation by reorganizing the data of the memory device to achieve faster access and better system performance. Summary of the Invention

[0003] The present disclosure relates to fragmentation assessment in a memory system. In one example, a method for operating a memory controller includes receiving, from a host, a request for a fragmentation level of a file stored in a memory device. The method further includes determining a read performance level of the file based on a logical-to-physical (L2P) address mapping table corresponding to the file, without reading the file from the memory device. The method further includes determining the fragmentation level based on the read performance level.

[0004] Although generally described as computer-implemented software that processes and transforms corresponding data embodied on a tangible medium, some or all aspects may be computer-implemented methods or further included in corresponding systems or other devices for performing the described functions. Details of these and other aspects and embodiments of the present disclosure are set forth in the accompanying drawings and the following description. Other features, objects, and advantages of the present disclosure will become apparent from the description, the drawings, and the claims. Brief Description of the Drawings

[0005] Figure 1 A block diagram of an example system having a memory device is shown in accordance with some aspects of the present disclosure.

[0006] Figures 2A - 2B An example storage product is shown in accordance with some aspects of the present disclosure.

[0007] Figure 3 A schematic circuit diagram of an example memory device including peripheral circuits is shown in accordance with some aspects of the present disclosure.

[0008] Figure 4 A block diagram of an example system including a memory device, a memory controller, and a host is shown in accordance with some aspects of the present disclosure.

[0009] Figures 5A - 5C An example logical address and physical address of a file according to some aspects of the present disclosure are shown.

[0010] Figure 6 A flowchart of an example method for fragmentation assessment according to some aspects of the present disclosure is shown.

[0011] Figure 7 A graph showing an example read performance curve according to some aspects of the present disclosure is shown.

[0012] Like reference numerals and names in the various figures indicate like elements. Detailed Description

[0013] The defragmentation process can rearrange fragmented files to store file data pieces in adjacent or even contiguous physical locations in a memory device. For example, the Universal Flash Storage (UFS) protocol provides a file based optimization (FBO) function. The FBO function allows the host and the flash device (e.g., a NAND device) to cooperate during the defragmentation process. The host can first evaluate how fragmented the files in the flash device are by querying the fragmentation level (also referred to as the degree of fragmentation) of the files from the flash device. When the host knows the fragmentation level of the file, the host can determine whether to defragment the file based on the fragmentation level. If so, the host can instruct the flash device to defragment the file to improve file access performance.

[0014] The fragmentation level of a file can be measured or evaluated in different ways. For example, the controller can read the file from the flash device to determine how the file is scattered in different locations of the flash device. This may not be an efficient way because it occupies the resources and processing capabilities of the flash device and even the host. Additionally, frequent memory read operations may reduce the reliability of the flash device due to read interference phenomena. Another fragmentation assessment method involves estimating the performance of the flash device based on the real-time distribution of data between the physical addresses of the flash device. This method may use complex algorithms and is difficult to implement when the real-time data distribution is complex. Therefore, efficient and practical fragmentation assessment techniques are needed.

[0015] The present disclosure provides fragmentation assessment techniques based on a logic-to-physical (L2P) address mapping table (also referred to as an L2P table or an L2P mapping table). In some embodiments, a controller may receive a request from a host for the fragmentation level of a file stored in a memory device. The controller may determine the read performance level of the file based on the L2P address mapping table corresponding to the file, without reading the file from the memory device. The controller may determine the fragmentation level based on the read performance level and return the fragmentation level to the host.

[0016] The techniques described in the present disclosure may be implemented to achieve one or more of the following advantages. First, compared to some existing methods, the proposed fragmentation assessment technique avoids reading actual file data from physical addresses, and thus is more efficient and consumes fewer resources. Second, the proposed fragmentation assessment technique may not reduce the reliability of the memory device. Third, the proposed fragmentation assessment technique can provide more accurate results because the distribution of the file among different planes of the memory device is considered.

[0017] The above aspects and some other aspects of the present disclosure are discussed in more detail below.

[0018] Figure 1 A block diagram of an example system 100 having a memory device is shown in accordance with some aspects of the present disclosure. System 100 may be a mobile phone, a desktop computer, a laptop computer, a tablet computer, an in-vehicle computer, a game console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, or any other suitable electronic device having a storage. As Figure 1 shown, system 100 may include a host 108 having a host memory 110 and a host processor 112, and a memory system 102 having one or more memory devices 104 and a memory controller 106.

[0019] The host 108 can be a processor of an electronic device, such as a central processing unit (CPU), or a system-on-chip (SoC), such as an application processor (AP). The host 108 can be coupled to the memory controller 106 and be configured to send data to or receive data from the memory device 104 through the memory controller 106. For example, the host 108 can send program data during a programming operation or receive read data during a read operation. The main processor 112 can be a control unit (CU) or an arithmetic logic unit (ALU). The main memory 110 can be a memory unit including registers or a cache memory. The host 108 is configured to receive instructions and commands from the memory controller 106 of the memory system 102 and send instructions and commands to the memory controller 106 of the memory system 102, and execute or implement multiple functions and operations provided in the present disclosure, which will be described later.

[0020] The memory device 104 can be any memory device disclosed in the present disclosure, such as a NAND flash memory device. It should be noted that NAND flash is only an example of a memory device for illustrative purposes. It can include any suitable solid-state non-volatile memory, such as NOR flash, ferroelectric RAM (FeRAM), phase-change memory (PCM), magnetoresistive random-access memory (MRAM), spin-transfer torque magnetic random-access memory (STT-RAM), or resistive random-access memory (RRAM), etc. In some embodiments, the memory device 104 includes a three-dimensional (3D) NAND flash memory device.

[0021] As Figure 1 shown, the memory device 104 can include one or more dies 114. The dies 114 can also be referred to as memory cell arrays and include multiple planes 116. Each plane 116 can include multiple physical blocks 118.

[0022] The memory controller 106 can be implemented by a microprocessor, a microcontroller (also known as a microcontroller unit (MCU)), a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), a programmable logic device (PLD), a state machine, gated logic, discrete hardware circuits, and other suitable hardware, firmware, and / or software configured to perform the various functions described in detail below.

[0023] According to some embodiments, a memory controller 106 is coupled to a memory device 104 and a host 108 and is configured to control the memory device 104. The memory controller 106 may manage data stored in the memory device 104 and communicate with the host 108. In some embodiments, the memory controller 106 is designed to operate in a low-duty-cycle environment, such as a secure digital (SD) card, a compact Flash (CF) card, a universal serial bus (USB) flash drive, or other media for electronic devices (such as personal computers, digital cameras, mobile phones, etc.). In some embodiments, the memory controller 106 is designed to operate in a high-duty-cycle environment, such as a solid state drive (SSD) or an embedded multi-media-card (eMMC) (which is used as data storage for mobile devices such as smart phones, tablets, laptops, etc.) and enterprise storage arrays. The memory controller 106 may be configured to control the operation of the memory device 104 by providing instructions such as read instructions to the memory device 104, such as read operations, erase operations, and programming operations. For example, the memory controller 106 may be configured to provide a read instruction to the peripheral circuit of the memory device 104 to control a read operation. The memory controller 106 may also be configured to manage various functions related to data stored or to be stored in the memory device 104, including but not limited to bad block management, garbage collection, logical-to-physical address translation, wear leveling, etc. In some embodiments, the memory controller 106 is also configured to process an error correction code (ECC) for data read from or written to the memory device 104. The memory controller 106 may also perform any other suitable functions, such as formatting the memory device 104.

[0024] The memory controller 106 can communicate with external devices (e.g., host 108) according to a specific communication protocol. For example, the memory controller 106 can communicate with external devices through at least one of various interface protocols, such as USB protocol, MMC protocol, peripheral component interconnection (PCI) protocol, PCI-express (PCI-E) protocol, advanced technology attachment (ATA) protocol, serial ATA protocol, parallel ATA protocol, small computer small interface (SCSI) protocol, enhanced small disk interface (ESDI) protocol, integrated drive electronics (IDE) protocol, FireWire protocol, etc. The memory controller 106 is configured to receive commands from the host 108 and send commands to the host 108, and execute or implement multiple functions and operations provided in the present disclosure, which will be described later.

[0025] The memory controller 106 and one or more memory devices 104 can be integrated into various types of memory devices, for example, included in the same package, such as a universal Flash storage (UFS) package or an eMMC package. That is, the memory system 102 can be implemented and packaged into different types of terminal electronic products. In Figure 2A In one example as shown, the memory controller 106 and a single memory device 104 can be integrated into a memory card 202. The memory card 202 can include a PC card (PCMCIA, Personal Computer Memory Card International Association), CF card, smart media (SM) card, memory stick, multimedia card (MMC, RS-MMC, MMCmicro), SD card (SD, miniSD, microSD, SDHC), UFS, etc. The memory card 202 can also include a memory card connector 204 that couples the memory card 202 to a host (e.g., Figure 1 the host 108 in Figure 2B In another example as shown, the memory controller 106 and multiple memory devices 104 can be integrated into an SSD 206. The SSD 206 can also include a component that couples the SSD 206 to a host (e.g., Figure 1The SSD connector 208 coupled to the host 108 therein. In some embodiments, the storage capacity and / or operating speed of the SSD 206 are greater than the storage capacity and / or operating speed of the memory card 202.

[0026] Figure 3 FIG. shows a schematic circuit diagram of an example memory device 300 including peripheral circuits in accordance with some aspects of the present disclosure. The memory device 300 may be Figure 1 An example of the memory device 104 therein. It should be noted that the NAND flash memory disclosed herein is only one example of a memory device for illustrative purposes. It may include any suitable solid-state non-volatile memory, such as NOR flash memory, FeRAM, PCM, MRAM, STT-RAM, or RRAM, etc. The memory device 300 may include a die or a memory cell array 114 and a peripheral circuit 302 coupled to the memory cell array 114. The memory cell array 114 may be a NAND flash memory cell array, where the memory cells 306 are provided in the form of an array of NAND memory strings 308, and each NAND memory string 308 extends vertically above a substrate (not shown). In some embodiments, each NAND memory string 308 includes a plurality of memory cells 306 coupled in series and vertically stacked. Each memory cell 306 may hold a continuous analog value, such as a voltage or a charge, depending on the number of electrons trapped within the region of the memory cell 306. Each memory cell 306 may be a floating-gate type memory cell including a floating-gate transistor or a charge-trapping type memory cell including a charge-trapping transistor.

[0027] In some embodiments, each memory cell 306 is a single-level cell (SLC) that has two possible memory states and can thus store one bit of data. For example, a first memory state "0" may correspond to a first voltage range, and a second memory state "1" may correspond to a second voltage range. In some embodiments, each memory cell 306 is a multi-level cell (MLC) capable of storing more than a single bit of data in more than four memory states. For example, an MLC may store two bits per cell, three bits per cell (also referred to as a triple-level cell (TLC)), or four bits per cell (also referred to as a quad-level cell (QLC)). Each MLC can be programmed to assume a range of possible nominal storage values. In one example, if each MLC stores two bits of data, the MLC can be programmed to assume one of three possible programmed levels from an erased state by writing one of three possible nominal storage values to the cell. A fourth nominal storage value may be used for the erased state.

[0028] As Figure 3 shown, each NAND memory string 308 may include a source select gate (SSG) transistor 310 at its source end and a drain select gate (DSG) transistor 312 at its drain end. The SSG transistor 310 and the DSG transistor 312 may be configured to activate the selected NAND memory string 308 (a column of the array) during a read operation and a program operation. In some embodiments, the sources of the NAND memory strings 308 in the same physical block 118 are coupled through the same source line (SL) 314 (e.g., a common SL). In other words, according to some embodiments, the NAND memory strings 308 in the same physical block 118 have an array common source (ACS). According to some embodiments, the drain of the DSG transistor 312 of each NAND memory string 308 is coupled to a corresponding bit line 316, and data may be read from or written to the bit line 316 via an output bus (not shown). In some embodiments, each NAND memory string 308 is configured to be selected or deselected by applying a select voltage (e.g., higher than the threshold voltage of the DSG transistor 312) or a deselected voltage (e.g., 0V) to the gate of the corresponding DSG transistor 312 through one or more DSG lines 313 and / or by applying a select voltage (e.g., higher than the threshold voltage of the SSG transistor 310) or a deselected voltage (e.g., 0V) to the gate of the corresponding SSG transistor 310 through one or more SSGs 315.

[0029] As Figure 3As shown, the NAND memory strings 308 can be organized into multiple physical blocks 118, and each physical block can have a common source line 314 coupled to the ACS, for example. In some embodiments, each physical block 118 is the basic data unit for an erase operation, that is, the memory cells 306 on the same physical block 118 are erased simultaneously. To erase the memory cells 306 in a selected physical block 118, an erase voltage (Vers), such as a high positive voltage (e.g., 20V or higher), can be used to bias the source line 314 coupled to the selected physical block 118 and the unselected physical blocks 118 in the same plane as the selected physical block 118. The memory cells 306 of adjacent NAND memory strings 308 can be coupled through word lines 318, and the word lines 318 select which row of memory cells 306 is affected by read operations and program operations. The peripheral circuit 302 can be coupled to the memory cell array 114 through bit lines 316, word lines 318, source lines 314, SSG lines 315, and DSG lines 313. The peripheral circuit 302 can include any suitable analog, digital, and mixed-signal circuits for facilitating the operation of the memory cell array 114 by applying voltage signals and / or current signals to each target memory cell 306 and sensing voltage signals and / or current signals from each target memory cell 306 through the bit lines 316, word lines 318, source lines 314, SSG lines 315, and DSG lines 313. The peripheral circuit 302 can include various types of peripheral circuits formed using metal-oxide-semiconductor (MOS) technology.

[0030] Figure 4 FIG. 400 is a block diagram of an example system 400 including a memory device 104, a memory controller 106, and a host 108, showing some aspects in accordance with the present disclosure. In some embodiments, the memory device 104 is a NAND device. As Figure 4As shown, the host 108 may include a host memory 110 and a host processor 112. The host memory 110 may store logical addresses, such as logical block addresses (LBAs) of files (e.g., file 404), and inode 406 of the file (e.g., inode). The host processor 112 may include or be coupled to an inode update module 408 (e.g., inode update module). The inode update module 408 is configured to update inode 406 of the file. Note that an inode (e.g., inode) may be a data structure in a Unix-style file system that describes a file system object such as a file or a directory. It may be a file data structure that stores information about any Linux file other than its name and data. It stores metadata of the file, including the file size, the device on which the file is stored, the user and group IDs associated with the file, or the permissions required to access the file.

[0031] As Figure 4 shown, the memory controller 106 may include a controller processor 410, such as a memory chip controller (MCC) or a memory controller unit (MCU). The controller processor 410 is configured to control modules to execute commands or instructions to perform the functions disclosed in the present disclosure. The controller processor 410 may also be configured to control the operation of each peripheral circuit by generating and sending various control signals (e.g., read commands for read operations). The controller processor 410 may also send clock signals to other peripheral circuits 302 at a desired frequency, period, and duty cycle to coordinate the operation of each peripheral circuit 302, such as for synchronization.

[0032] Memory controller 106 may also include at least one of volatile controller memory 412 and non-volatile controller memory 414. In some embodiments, memory controller 105 may include both volatile controller memory 412 and non-volatile controller memory 414. In some embodiments, memory controller 105 may include volatile controller memory 412 or non-volatile controller memory 414. Volatile controller memory 412 may include registers or caches, allowing for faster access and processing speeds to read, write, or erase data stored therein, but may not retain stored information after power loss. In some embodiments, volatile controller memory 412 includes dynamic random-access memory (DRAM) or static random-access memory (SRAM). Non-volatile controller memory 414 may retain stored information even after power loss. In some embodiments, non-volatile controller memory 414 includes NAND, NOR, FeRAM, PCM, MRAM, STT-RAM, or RRAM. In some embodiments, non-volatile controller memory 414 may not be provided in memory controller 106. For example, non-volatile controller memory 414 is arranged outside memory controller 106 but is coupled to memory controller 106.

[0033] As Figure 4 shown, memory controller 106 may include a memory controller interface 416 configured to receive commands or instructions from host 108 and send commands or instructions to host 108. In some embodiments, memory controller interface 416 is coupled to controller processor 410 and is configured to receive and send commands or instructions that cause controller processor 410 to perform the functions disclosed in this disclosure.

[0034] The L2P address mapping table can be stored in various locations of the system 400. The L2P address mapping table 418 can be stored in non-volatile memory, such as the memory device 104 (e.g., a NAND device) and the non-volatile controller memory 414. In this way, the address mapping data in the L2P address mapping table 418 is not erased after a power outage. In some embodiments, the L2P address mapping table is stored in volatile memory such as the volatile controller memory 412 and processed. In some embodiments, after the system boots or restarts, the L2P address mapping table can be loaded from the memory device 104 or the non-volatile controller memory 414 and stored in the volatile controller memory 412 to achieve faster access and processing speeds periodically. In some embodiments, the L2P address mapping table 418 can include address mapping data corresponding to the file 404 in the host memory 110.

[0035] The memory controller 106 can include an address mapping table update module ( Figure 4 not shown in the figure), which is configured to generate and update the L2P address mapping table 418. The address mapping table update module can be implemented by a firmware program in the firmware of the controller processor 410. In some embodiments, the address mapping table update module is located in the controller processor 410 or coupled to the controller processor 410, and can be controlled by the controller processor 410 to execute commands and instructions from the host 108. For example, the address mapping table update module is configured to execute a mapping update command received from the host 108 and update the L2P address mapping table 418 accordingly.

[0036] Figures 5A - 5C An example logical address and physical address of a file 500 according to some aspects of the present disclosure are shown. The file 500 is an example of the Figure 4 file 404. As Figure 5A shown, the inode 502 of the file 500 can include a list of LBA segments 504, 506, 508, and 510. Each of the LBA segments 504, 506, 508, and 510 includes one or more consecutive LBAs. It should be understood that Figure 5A the LBA segments 504, 506, 508, and 510 in the figure are for illustrative purposes only, and the LBA segments in actual embodiments can include more LBAs than the Figure 5A LBA segments in the figure. The data of the file 500 is stored in the physical address of the memory device. Figure 5B An example L2P address mapping table 520 is shown, where the logical address of the file 500 is mapped to the physical address of the file 500 in the memory device. The L2P address mapping table 520 can be Figure 4An example of the L2P address mapping table 418. When the controller reads the file 500, the controller first determines the physical address according to the L2P address mapping table 520, and then reads the data from the physical address. As Figure 5B shown, each logical block address (LBA) of the file 500 is mapped to a physical block address (PBA). It should be understood that although the L2P address mapping table 520 indicates that the file 500 is stored in the PBA shown by the L2P address mapping table 520, the index number of the PBA of the file 500 is for illustrative purposes and may be different from the PBA in the memory device in actual implementations. Figure 5C An example showing that the physical addresses of the file 500 are scattered among the respective planes of two dies 530 and 532 of the memory device is shown. In this example, each of the two dies has four planes. Die 530 includes planes 534, 536, 538, and 540, and die 532 includes planes 542, 544, 546, and 548. The PBA of the file 500 is located among the eight planes of the memory device.

[0037] Figure 6 A flowchart of an example method 600 for fragmentation assessment according to some aspects of the present disclosure is shown. The method 600 may be executed by a memory controller (e.g., Figure 1 the memory controller 106 in Figure 6 ). The operations shown in the method 600 may not be exhaustive, and other operations may also be performed before, after, or between any of the shown operations. Additionally, some operations may be performed simultaneously, or in an order different from the Figure 4 order shown. In some implementations, the method 600 may be executed by a firmware program of a controller processor (e.g., Figure 4 the controller processor 410 in

[0038] At 602, the memory controller receives a request from a host. The request may query the fragmentation level of a file stored in a memory device. The request may include the logical address of the file. For example, the request may indicate an inode, which includes one or more LBAs of the file (e.g., Figure 5B LBAs 1-7, 10, 12-13, and 17-22). In some embodiments, the request is an FBO request under the UFS 4.0 technical standard.

[0039] At 604, the memory controller reads the L2P address mapping table associated with the file. In some embodiments, the memory controller may load the L2P address mapping table from volatile controller memory (e.g., Figure 4 volatile controller memory 412 in Figure 4 or non-volatile controller memory (e.g., Figure 1 non-volatile controller memory 414 in

[0040] ). The L2P address mapping table in the volatile controller memory or non-volatile controller memory may be loaded from the memory device (e.g., Figure 1 memory device 104 in

[0040] ).

[0040] At 606, the memory controller determines the average consecutive physical address length of the file. The memory controller may first determine the physical address of the file based on the logical address of the file and the L2P address mapping table. The physical address of the file may be divided into one or more physical address segments, and each physical address segment includes one or more consecutive physical addresses. In some embodiments, each physical address is a PBA of a predetermined size (e.g., 4K bytes). In some embodiments, the average consecutive physical address length may be determined based on the number of one or more physical address segments and how many consecutive physical addresses each physical address segment includes.

[0041] For example, the file includes 4 physical address segments. The first physical address segment has 2 consecutive PBAs. The second physical address segment has 4 consecutive PBAs. The third physical address segment has 6 consecutive PBAs. The fourth physical address segment has 8 consecutive PBAs. Thus, the file has an average of 5 consecutive PBAs (i.e., the sum of 2, 4, 6, and 8 divided by 4 is 5). In this example, the size of the PBA is 4K bytes (KB). Thus, the memory controller may determine that the average consecutive physical address length of the file is 20KB.

[0042] In some embodiments, the average consecutive physical address length of the file may be determined using the following algorithm executed by the memory controller.

[0043] Step 1: Set the initial value of the PBA consecutive segment counter to 1. Determine the first LBA of the file based on the inode of the file. Determine the PBA mapped to the first LBA according to the L2P address mapping table of the file. Set the PBA mapped to the first LBA as the current PBA.

[0044] Step 2: Determine the next LBA of the file and the next PBA mapped to the next LBA. Check whether the next PBA is the subsequent physical address of the current PBA. If so: Keep the PBA consecutive segment counter unchanged (because the consecutive PBA segment is not broken); Update the current PBA to the next PBA. If not: Increment the PBA consecutive segment counter by 1 (because the consecutive PBA segment is broken); Update the current PBA to the next PBA.

[0045] Step 3: Repeat Step 2 until the last LBA of the file has been checked. Divide the file length by the PBA consecutive segment counter to determine the average consecutive physical address length of the file.

[0046] At 608, the memory controller determines the read performance level based on the average consecutive physical address length and the read performance curve. The read performance curve may represent an estimate of the random read performance of the memory device for a given chunk size. In some embodiments, the read performance curve is determined by performing a random read test or experiment on the memory device. In the random read experiment, files of various chunk sizes are located at random physical addresses of the memory device, and the read speed of the files is measured. The chunk size may be the continuous storage space occupied by each smallest unit of the file.

[0047] Figure 7 FIG. 700 shows an illustration 700 of an exemplary read performance curve 702 in accordance with some aspects of the present disclosure. The horizontal axis of illustration 700 measures the random read chunk size in KB. The vertical axis of illustration 700 measures the read performance in megabytes per second (MB / S). The read performance curve 702 is plotted by connecting the data points 704. Each data point 704 is determined by performing a read performance test on the memory device. The read performance test may involve reading files of various chunk sizes and measuring the actual read speed. In some embodiments, the read performance curve 702 is pre-determined. Given the average consecutive physical address length, the memory controller can determine the read performance level by finding the point on the read performance curve 702 where the random read chunk size (on the horizontal axis) is equal to the average consecutive physical address length and determining the read performance of the point on the vertical axis.

[0048] Return reference Figure 6Method 600, at 610, the memory controller compares the average consecutive physical address length of the file with a threshold. For example, the threshold can be 16KB. If the average consecutive physical address length is greater than the threshold, method 600 proceeds to 612, where the memory controller returns the read performance level as the fragmentation level of the file to the host. If the average consecutive physical address length is equal to or less than the threshold, method 600 proceeds to 614.

[0049] At 614, the memory controller determines a value based on the distribution of the physical addresses of the file. At 616, the memory controller adjusts the read performance level based on this value. At 618, the memory controller returns the adjusted read performance level as the fragmentation level of the file to the host.

[0050] If a file is highly fragmented (i.e., the average consecutive physical address length is small), then the distribution of the file across different planes of the memory device also affects the fragmentation level of the file. In such a case, a file whose physical addresses are more evenly spread across all the planes of the memory device can be considered more fragmented. For example, Figure 5C shows file 500 (referred to as file A) spread across 8 planes of 2 dies of the memory device. Assume there is another file (referred to as file B) that has a similar average consecutive physical address length as file 500 but is stored only in planes 534 and 536 of die 530. Then file A and file B can have a similar read performance level based on the read performance curve. But file B is more fragmented because it occupies fewer planes in the memory device. Thus, when the average consecutive physical address length of a file is less than the threshold, the memory controller can more accurately evaluate the fragmentation level of the file by adjusting the read performance level using a value determined according to the physical address distribution of the file.

[0051] In some embodiments, the memory controller can use the following algorithm to adjust the read performance level.

[0052] Step 1: Determine the total number of planes (e.g., N) in which one piece of data of the file is stored. Count how many physical addresses of the file are in each plane. P i represents the number of physical addresses of the file located in plane i (1 ≤ i ≤ N). In some embodiments, the memory device includes multiple dies, and each die includes multiple planes. In such a case, all the planes in the memory device should be considered, even if they may belong to different dies.

[0053] Step 2: Calculate the average number of physical addresses

[0054] Step 3: Calculate the standard deviation of P i (1 ≤ i ≤ N):

[0055] Step 4: Determine the value as and determine the adjusted read performance level as the read performance level divided by For example, Figure 5C shows that file 500 has PBAs distributed in 8 planes. N = 8. P 1 = 2. P 2 = 5. P 3 = 1. P 4 = 1. P 5 = 3. P 6 = 3. P 7 = 0. P 8 = 1. S = 1.5. The value of file 500 is 1.5625. The adjusted read performance level of file 500 can be the read performance level determined by the read performance curve (e.g., read performance curve 702) and then divided by 1.5625.

[0056] It should be appreciated that the above algorithm for adjusting the read performance level of a file is merely an example for illustrative purposes. The memory controller can use any other suitable method to adjust the read performance level of a file based on the distribution of the physical addresses of the file. In some embodiments, the host receives the fragmentation level from the memory controller. When it is determined that the fragmentation level is higher than the fragmentation level threshold, the host can send a command to the memory controller. The command instructs the memory controller to perform defragmentation. Method 600 can also include the memory controller receiving the command and performing defragmentation based on the received command.

[0057] Although this specification includes many specific implementation details, these should not be construed as limitations on the scope that can be claimed, but rather as descriptions of features that may be specific to particular embodiments. Certain features described in the context of separate embodiments in this specification can also be implemented combinatorially in a single embodiment. Conversely, the various features described in the context of a single embodiment can also be implemented separately or in any sub-combination in multiple embodiments. Additionally, although the previously described features may be described as acting in certain combinations and even initially claimed as such, in some cases, one or more features from the claimed combination can be deleted from the combination, and the claimed combination can be directed to a sub-combination or a variant of the sub-combination. As used in this disclosure, the terms "a," "an," or "the" are used to include one or more than one, unless the context clearly indicates otherwise. Unless otherwise specified, the term "or" is used to refer to a non-exclusive "or." The statement "at least one of A and B" has the same meaning as "A, B, or A and B." Also, the wording or terms used in this disclosure and not otherwise defined are for descriptive purposes only and not for purposes of limitation. The use of any section headings is for the purpose of assisting in reading the document and should not be construed as limiting; the information related to a section heading may appear within or outside of that particular section.

[0058] As used in this disclosure, the terms "about" or "approximately" may permit a degree of variability in a numerical value or range, e.g., within 10%, 5%, or 1% of the stated value or the stated range limitation.

[0059] As used in this disclosure, the term "substantially" means most or majority, such as at least about 50%, 60%, 70%, 80%, 90%, 95%, 96%, 97%, 98%, 99%, 99.5%, 99.9%, 99.99%, or at least about 99.999% or more.

[0060] Values expressed in a range format should be interpreted in a flexible manner to include not only the explicitly recited values as the range limitations, but also each value or sub-range included within that range as if each value and sub-range were explicitly recited. For example, a range of "0.1% to about 5%" or "0.1% to 5%" should be interpreted to include from about 0.1% to about 5%, as well as the individual values (e.g., 1%, 2%, 3%, and 4%) and sub-ranges within the specified range (e.g., 0.1% to 0.5%, 1.1% to 2.2%, 3.3% to 4.4%). Unless otherwise specified, the statement "X to Y" has the same meaning as "about X to about Y." Similarly, unless otherwise specified, the statement "X, Y, or Z" has the same meaning as "about X, about Y, or about Z."

[0061] Specific embodiments of the subject matter have been described. Other embodiments, variations, and permutations of the described embodiments are within the scope of the appended claims and will be apparent to those skilled in the art. Although operations are described in a particular order in the figures or claims, such operations need not be performed in the particular order shown or in a sequential order, nor need all of the illustrated operations be performed (some operations may be considered optional) to achieve the desired result. In some cases, multitasking or parallel processing (or a combination of multitasking and parallel processing) may be advantageous and may be performed as deemed appropriate.

[0062] Moreover, the separation or integration of the various system modules and components in the foregoing embodiments is not required in all embodiments, and the described components and systems may generally be integrated together or packaged into multiple products.

[0063] Accordingly, the previously described example embodiments do not define or limit the present disclosure. Other changes, substitutions, and variations are possible without departing from the spirit and scope of the present disclosure.

[0064] According to one aspect of the present disclosure, a method for operating a memory controller is disclosed. The method includes receiving, from a host, a request for a fragmentation level of a file stored in a memory device. The method further includes determining a read performance level of the file based on a logical-to-physical (L2P) address mapping table corresponding to the file without reading the file from the memory device. The method further includes determining the fragmentation level based on the read performance level.

[0065] In some embodiments, the request includes a plurality of logical addresses of the file. Determining the read performance level of the file includes: reading the L2P address mapping table from the memory device; determining an average consecutive physical address length of the file based on the plurality of logical addresses of the file and the L2P address mapping table; and determining the read performance level based at least on the average consecutive physical address length and a predetermined read performance curve.

[0066] In some embodiments, determining the average consecutive physical address length of the file includes: mapping the plurality of logical addresses to physical address segments according to the L2P address mapping table. Each physical address segment includes one or more consecutive physical addresses. Determining the average consecutive physical address length of the file further includes determining the average consecutive physical address length. The average consecutive physical address length is determined based on the sum of the number of one or more consecutive physical addresses included in each physical address segment and the number of physical address segments.

[0067] In some embodiments, each of the plurality of logical addresses is a logical block address (LBA), and each of the physical address segments is a physical block address (PBA).

[0068] In some embodiments, a predetermined read performance curve is determined by performing a random read experiment on a memory device using test data of various block sizes.

[0069] In some embodiments, determining a read performance level includes: determining an initial read performance level corresponding to an average consecutive physical address length based on a predetermined read performance curve, and determining whether the average consecutive physical address length is greater than a threshold.

[0070] In some embodiments, determining a read performance level further includes: in response to determining that the average consecutive physical address length is greater than the threshold, determining the read performance level as the initial read performance level.

[0071] In some embodiments, determining a read performance level further includes: in response to determining that the average consecutive physical address length is not greater than the threshold, determining the read performance level as the initial read performance level adjusted by a value. The value is determined based on the distribution of the physical addresses of a file among a plurality of planes of the memory device.

[0072] In some embodiments, the read performance level is determined based on the initial read performance level and the value. The value is determined according to the degree of uniformity of the dispersion of the physical addresses of a file among a plurality of planes of the memory device. If the physical addresses of a file are more evenly dispersed among the plurality of planes of the memory device, the value is smaller.

[0073] In some embodiments, the memory device includes a three-dimensional (3D) NAND flash memory device.

[0074] In some embodiments, the request is a file-based optimization (FBO) request under the Universal Flash Storage (UFS) 4.0 technical standard.

[0075] In some embodiments, the method further includes returning a fragmentation level to the host. The method further includes receiving a command from the host to perform defragmentation. The host sends the command in response to determining that the fragmentation level is higher than a fragmentation level threshold. The method further includes performing defragmentation based on the received command.

[0076] According to another aspect of the present disclosure, a memory system is disclosed. The memory system includes a memory device and a memory controller. The memory controller includes one or more processors and a computer storage medium. The computer storage medium is coupled to the one or more processors and stores programming instructions for execution by the one or more processors to cause the memory controller to perform operations. The operations include: receiving, from a host, a request for a fragmentation level of a file stored in the memory device; determining a read performance level of the file based on a logical-to-physical (L2P) address mapping table corresponding to the file without reading the file from the memory device; and determining the fragmentation level based on the read performance level.

[0077] In some embodiments, the request includes a plurality of logical addresses of the file. Determining the read performance level of the file includes: reading the L2P address mapping table from the memory device; determining an average consecutive physical address length of the file based on the plurality of logical addresses of the file and the L2P address mapping table; and determining the read performance level based at least on the average consecutive physical address length and a predetermined read performance curve.

[0078] In some embodiments, determining the average consecutive physical address length of the file includes: mapping the plurality of logical addresses to physical address segments according to the L2P address mapping table. Each physical address segment includes one or more consecutive physical addresses. Determining the average consecutive physical address length of the file further includes determining the average consecutive physical address length. The average consecutive physical address length is determined according to the sum of the number of one or more consecutive physical addresses included in each physical address segment and the number of physical address segments.

[0079] In some embodiments, each logical address in the plurality of logical addresses is a logical block address (LBA), and each physical address in the physical address segment is a physical block address (PBA).

[0080] In some embodiments, the predetermined read performance curve is determined by performing a random read experiment on the memory device using test data of various block sizes.

[0081] In another aspect of the present disclosure, a non-transitory computer storage medium is disclosed. The non-transitory computer storage medium is coupled to one or more processors of a memory controller and stores programming instructions for execution by the one or more processors to cause the memory controller to perform operations. These operations include: receiving, from a host, a request for a fragmentation level of a file stored in a memory device; determining a read performance level of the file based on a logical-to-physical (L2P) address mapping table corresponding to the file, without reading the file from the memory device; and determining the fragmentation level based on the read performance level.

[0082] In some embodiments, the request includes a plurality of logical addresses of the file. Determining the read performance level of the file includes: reading the L2P address mapping table from the memory device; determining an average consecutive physical address length of the file based on the plurality of logical addresses of the file and the L2P address mapping table; and determining the read performance level based at least on the average consecutive physical address length and a predetermined read performance curve.

[0083] In some embodiments, determining the average consecutive physical address length of the file includes mapping the plurality of logical addresses to physical address segments according to the L2P address mapping table. Each physical address segment includes one or more consecutive physical addresses. Determining the average consecutive physical address length of the file further includes determining the average consecutive physical address length. The average consecutive physical address length is determined based on the sum of the number of one or more consecutive physical addresses included in each physical address segment and the number of physical address segments.

[0084] The foregoing description of the specific embodiments can be easily modified and / or adapted to various applications. Accordingly, such adaptations and modifications are intended to fall within the meaning and scope of the equivalents of the disclosed embodiments based on the teachings and guidance presented herein.

[0085] The width and scope of the present disclosure should not be limited by any of the above example embodiments, but should be defined only by the appended claims and their equivalents. Accordingly, other embodiments are also within the scope of the claims.

Claims

1. A method for operating a memory controller, comprising: receiving, from a host, a request for a fragmentation level of a file stored in a memory device; determining a read performance level of the file based on a logical-to-physical (L2P) address mapping table corresponding to the file, without reading the file from the memory device; and determining the fragmentation level based on the read performance level.

2. The method according to claim 1, wherein the request includes a plurality of logical addresses of the file, and wherein determining the read performance level of the file comprises: reading the L2P address mapping table from the memory device; determining an average consecutive physical address length of the file based on the plurality of logical addresses of the file and the L2P address mapping table; and determining the read performance level based at least on the average consecutive physical address length and a predetermined read performance curve.

3. The method according to claim 2, wherein determining the average consecutive physical address length of the file comprises: mapping the plurality of logical addresses to physical address segments according to the L2P address mapping table, wherein each physical address segment in the physical address segments includes one or more consecutive physical addresses; and determining the average consecutive physical address length, wherein the average consecutive physical address length is determined based on the sum of the number of the one or more consecutive physical addresses included in each physical address segment in the physical address segments and the number of the physical address segments.

4. The method according to claim 3, wherein: each logical address in the plurality of logical addresses is a logical block address (LBA); and each physical address in the physical address segments is a physical block address (PBA).

5. The method according to claim 2, wherein the predetermined read performance curve is determined by performing a random read experiment on the memory device using test data of various block sizes.

6. The method according to claim 2, wherein determining the read performance level comprises: determining an initial read performance level corresponding to the average consecutive physical address length based on the predetermined read performance curve; and determining whether the average consecutive physical address length is greater than a threshold.

7. The method according to claim 6, wherein determining the read performance level further comprises: in response to determining that the average consecutive physical address length is greater than the threshold, determining the read performance level as the initial read performance level.

8. The method according to claim 6, wherein determining the read performance level further comprises: in response to determining that the average consecutive physical address length is not greater than the threshold, determining the read performance level as the initial read performance level adjusted by a value, the value being determined based on the distribution of the physical addresses of the file among a plurality of planes of the memory device.

9. The method according to any one of claims 1-8, wherein: the read performance level is determined based on the initial read performance level and the value; The value is determined based on the degree of even distribution of the physical address of the file among the multiple planes of the memory device; and If the physical address of the file is more evenly distributed among the multiple planes of the memory device, the value is smaller.

10. The method according to any one of claims 1-9, wherein, The memory device includes a three-dimensional (3D) NAND flash memory device.

11. The method according to any one of claims 1-10, wherein, The request is a file-based optimization (FBO) request under the Universal Flash Storage (UFS) 4.0 technical standard.

12. The method according to any one of claims 1-11, further comprising: Returning the fragmentation level to the host; Receiving a command for defragmentation from the host, wherein the host sends the command in response to determining that the fragmentation level is higher than a fragmentation level threshold; and Performing the defragmentation based on the received command.

13. A memory system, comprising: A memory device; and A memory controller, the memory controller includes one or more processors and a computer storage medium, wherein the computer storage medium is coupled to the one or more processors and stores programming instructions for the one or more processors to execute to cause the memory controller to perform operations, the operations including: Receiving a request for the fragmentation level of a file stored in the memory device from a host; Determining the read performance level of the file based on a logical-to-physical (L2P) address mapping table corresponding to the file, without reading the file from the memory device; and Determining the fragmentation level based on the read performance level.

14. The memory system according to claim 13, wherein, The request includes a plurality of logical addresses of the file, and wherein determining the read performance level of the file includes: Reading the L2P address mapping table from the memory device; Determining the average consecutive physical address length of the file based on the plurality of logical addresses of the file and the L2P address mapping table; and Determining the read performance level based at least on the average consecutive physical address length and a predetermined read performance curve.

15. The memory system according to claim 14, wherein, Determining the average consecutive physical address length of the file includes: Mapping the plurality of logical addresses to physical address segments according to the L2P address mapping table, wherein each physical address segment in the physical address segments includes one or more consecutive physical addresses; and Determining the average consecutive physical address length, wherein the average consecutive physical address length is determined based on the sum of the number of the one or more consecutive physical addresses included in each physical address segment in the physical address segments and the number of the physical address segments.

16. The memory system according to any one of claims 13-15, wherein: Each logical address in the plurality of logical addresses is a logical block address (LBA); and Each physical address in the physical address segment is a physical block address (PBA).

17. The memory system according to claim 14, wherein, the predetermined read performance curve is determined by performing a random read experiment on the memory device using test data of various block sizes.

18. A non-transitory computer storage medium, wherein, the non-transitory computer storage medium is coupled to one or more processors of a memory controller and stores programming instructions for execution by the one or more processors to cause the memory controller to perform operations, the operations including: receiving, from a host, a request for a fragmentation level of a file stored in a memory device; determining a read performance level of the file based on a logical-to-physical (L2P) address mapping table corresponding to the file without reading the file from the memory device; and determining the fragmentation level based on the read performance level.

19. The non-transitory computer storage medium according to claim 18, wherein, the request includes a plurality of logical addresses of the file, and wherein determining the read performance level of the file includes: reading the L2P address mapping table from the memory device; determining an average consecutive physical address length of the file based on the plurality of logical addresses of the file and the L2P address mapping table; and determining the read performance level based at least on the average consecutive physical address length and a predetermined read performance curve.

20. The non-transitory computer storage medium according to claim 18 or 19, wherein, determining the average consecutive physical address length of the file includes: mapping the plurality of logical addresses to a physical address segment according to the L2P address mapping table, wherein each physical address segment in the physical address segment includes one or more consecutive physical addresses; and determining the average consecutive physical address length, wherein the average consecutive physical address length is determined based on the sum of the number of the one or more consecutive physical addresses included in each physical address segment in the physical address segment and the number of the physical address segments.

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