Inline encryption solution for non-volatile memory standard (NVMe) storage devices

Abstract

Various embodiments include a method implemented in an inline cryptographic module of a non-volatile memory standard (NVMe) device. An embodiment may include storing a data buffer address for an NVMe command and an NVMe security identifier for the NVMe command in association with each other, wherein the NVMe security identifier includes an NVMe command identifier for the NVMe command and an NVMe command commit queue identifier; storing a security context for the NVMe command and the NVMe security identifier in association with each other; retrieving a security context for an NVMe command based on an association of a data buffer address for the NVMe command with an NVMe security identifier for the NVMe command and an association of the NVMe security identifier with a security context for the NVMe command; and implementing a cryptographic function for data of the NVMe command using information for a security context of the NVMe command.

Description

[0001] Related Applications

[0002] This application claims the benefit of priority from Indian Patent Application No. 202241063945, filed on Nov. 9, 2022; the entire content of which is incorporated herein by reference. Background of the Invention

[0003] The nonvolatile memory express (NVMe) protocol implementation for solid-state memory devices enables fast and high-throughput communication between an NVMe memory device and a system-on-chip (SoC). A fast peripheral component interface (PCIe) controller can be configured to implement NVMe protocol communication between the NVMe device and components of the SoC. Data transmitted to and from the NVMe device at the SoC is vulnerable to manipulation by malicious actors. Summary of the Invention

[0004] Aspects include apparatus and methods for implementing an in-line cryptographic module for a system-on-chip (SoC) for a nonvolatile memory express (NVMe) device. Aspects may include: storing, in association with each other, a data buffer address for an NVMe command and an NVMe security identifier for the NVMe command, where the NVMe security identifier includes an NVMe command identifier for the NVMe command and an NVMe command submission queue identifier; storing, in association with each other, a security context for the NVMe command and the NVMe security identifier; retrieving the security context for the NVMe command based on the association of the data buffer address for the NVMe command with the NVMe security identifier for the NVMe command and the association of the NVMe security identifier with the security context for the NVMe command; and using information of the security context for the NVMe command to implement a cryptographic function for data of the NVMe command.

[0005] Some aspects further include: configuring, by an NVMe driver, at the in-line cryptographic module, a structure for storing, in association with each other, the data buffer address for the NVMe command and the NVMe security identifier for the NVMe command, using information of the NVMe command; and configuring, by the NVMe driver, at the in-line cryptographic module, a structure for storing, in association with each other, the security context for the NVMe command and the NVMe security identifier, using information of the NVMe command.

[0006] Some aspects also include: receiving the NVMe command from an NVMe drive; using information of the NVMe command to configure a structure for storing the data buffer address for the NVMe command and the NVMe security identifier for the NVMe command in association with each other; and using information of the NVMe command to configure a structure for storing the security context for the NVMe command and the NVMe security identifier for the NVMe command in association with each other.

[0007] Some aspects also include updating an NVMe command submission queue tail pointer with a doorbell register address.

[0008] Some aspects also include: based on the association between the data buffer address for the NVMe command and the NVMe security identifier for the NVMe command and the association between the NVMe security identifier and the security context for the NVMe command, using information of the security context for the NVMe command to generate a hash value for the NVMe command, wherein the hash value is used by an NVMe device to be included in a device hint for the NVMe command.

[0009] Some aspects also include: receiving, from an NVMe device, a device hint for the NVMe command, the device hint including the hash value of the NVMe command; and using information of the device hint for the NVMe command to configure a structure for storing the data buffer address for the NVMe command and the NVMe security identifier for the NVMe command in association with each other.

[0010] Some aspects also include: using the hash value to verify the device hint for the NVMe command, wherein using information of the device hint for the NVMe command to configure the structure for storing the data buffer address for the NVMe command and the NVMe security identifier for the NVMe command in association with each other may include: in response to determining that the device hint is valid, using information of the device hint for the NVMe command to configure the structure for storing the data buffer address for the NVMe command and the NVMe security identifier for the NVMe command in association with each other.

[0011] Further aspects include a computing device including a plurality of processors configured to perform operations of any of the methods outlined above. Further aspects include a computing device having units for performing any of the functions of the methods outlined above. Further aspects include a power management integrated circuit configured to perform any of the methods outlined above. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] The accompanying drawings, which are incorporated herein and form a part of this specification, illustrate example embodiments in various embodiments and, together with the general description given above and the detailed description given below, serve to explain the features of the present invention.

[0013] Figure 1 is a component block diagram showing an example computing device suitable for implementing various embodiments.

[0014] Figure 2 is a component block diagram showing an example inline cryptographic non-volatile memory express (NVMe) system suitable for implementing various embodiments.

[0015] Figure 3 is a component block diagram showing an example inline cryptographic module for implementing various embodiments.

[0016] Figure 4 is a process flow diagram showing a method of inline cryptography for an NVMe device according to some embodiments.

[0017] Figure 5 is a process flow diagram showing a method of inline cryptography for an NVMe device with doorbell forwarding according to some embodiments.

[0018] Figure 6 is a component block diagram showing an example inline cryptographic module including a hash module for implementing various embodiments.

[0019] Figure 7A and Figure 7B is a process flow diagram showing a method of inline cryptography for an NVMe device with device hint management according to some embodiments.

[0020] Figure 8 is a component block diagram showing an example mobile computing device suitable for implementing various embodiments.

[0021] Figure 9 is a component block diagram showing an example mobile computing device suitable for implementing various embodiments.

[0022] Figure 10 is a component block diagram showing an example server suitable for implementing various embodiments. DETAILED DESCRIPTION

[0023] The various embodiments are described in detail with reference to the accompanying drawings. Wherever possible, the same reference numerals will be used throughout the drawings to refer to the same or like parts. References to specific examples and implementations are for illustrative purposes only and are not intended to limit the scope of the claims.

[0024] Each embodiment includes a method for implementing an in-line cryptographic module for a system-on-chip (SoC) for a Non-Volatile Memory Express (NVMe) device and a computing device implementing such method. In some embodiments, the in-line cryptographic module may be configured by an NVMe driver implemented on the SoC with an address lookup structure and a security context lookup structure. In some embodiments, the in-line cryptographic module may be enabled to configure itself with an address lookup structure and a security context lookup structure. These structures may be used together by the in-line cryptographic module to identify a security context for an NVMe command to perform cryptographic functions such as encrypting and / or decrypting data for an NVMe transaction between the SoC and the NVMe device. In some embodiments, the in-line cryptographic module may be enabled to forward an indication of a pending NVMe command, such as a doorbell signal, to the NVMe device. In some embodiments, the in-line cryptographic module may be enabled to generate and verify a hash value for a device hint for an NVMe transaction to evaluate the integrity of the device hint for evaluating how to process the NVMe transaction.

[0025] The terms “computing device” and “mobile device” are used interchangeably herein to refer to any one or all of the following: cellular phone, smartphone, personal or mobile multimedia player, personal digital assistant (PDA), notebook computer, tablet computer, convertible notebook / tablet computer (2-in-1 computer), smartbook, ultrabook, netbook, handheld computer, wireless e-mail receiver, multimedia Internet-enabled cellular phone, mobile gaming console, wireless game controller, and similar personal electronic devices that include memory and a programmable processor. The term “computing device” may also refer to a fixed computing device, which includes a personal computer, desktop computer, all-in-one computer, workstation, supercomputer, mainframe computer, embedded computer, server, home theater computer, and gaming console.

[0026] The NVMe protocol implementation for memory devices enables fast and high-throughput communication between an NVMe memory device and an SoC. A Rapid Peripheral Component Interconnect (PCIe) controller may be configured to implement NVMe protocol communication between the NVMe device and components of the SoC. Data transmitted to and from the NVMe device at the SoC is vulnerable to manipulation by malicious actors.

[0027] Each embodiment solves and corrects the aforementioned problems of NVMe protocol communication by providing an inline cryptographic function to protect data at the SoC for transfer to and from the NVMe device. The inline cryptographic module may maintain information related to NVMe commands and the security context for those commands. The inline cryptographic module may use the information stored at the inline cryptographic module to implement a cryptographic function to encrypt data sent from the SoC to the NVMe device and / or decrypt data received at the SoC from the NVMe device. For example, such information may include: the association of identification information for the NVMe transaction with the encryption algorithm and one or more encryption key holes for retrieving one or more encryption keys from an encryption key storage structure. The inline cryptographic module may encrypt and / or decrypt the data of the NVMe transaction based on the information stored at the inline cryptographic module, using the encryption algorithm and one or more encryption keys accessible to the inline cryptographic module.

[0028] In some embodiments, further steps may be taken to protect the NVMe transaction by enabling the inline cryptographic module to generate and verify a hash value for the NVMe transaction. The inline cryptographic module may use the information stored at the inline cryptographic module to generate a hash value for the NVMe transaction and provide it to the NVMe device to be returned in the device prompt associated with the NVMe transaction. The hash value may be used to ensure that the information associated with a particular NVMe transaction sent to the NVMe device has not been altered when it is sent back to the cryptographic module in the device prompt. The inline cryptographic module may use a combination of the information from the device prompt and the information stored at the inline cryptographic module to generate another hash value. For example, such information stored at the inline cryptographic module may include: the association of identification information for the NVMe transaction with the hash algorithm and one or more hash key holes for retrieving one or more hash keys from a hash key storage structure. The inline cryptographic module may generate a hash based on the information stored at the inline cryptographic module, using the hash algorithm and one or more hash keys accessible to the inline cryptographic module. The hash may be included in the device prompt for the NVMe transaction. The inline cryptographic module may compare the hashes to evaluate the integrity of the device prompt based on whether the hashes match, for evaluating how to process the NVMe transaction.

[0029] Figure 1A system is shown that includes a computing device 10 suitable for use with various embodiments. The computing device 10 may include a system-on-chip (SoC) 12 having a processor 14, a memory 16, a memory interface 34, an inline cryptographic module 38, a communication interface 18, a storage memory interface 20, a clock controller 30, and an interconnect 32. The computing device 10 may further include communication components 22, such as a wired or wireless modem, a storage memory 24, an antenna 26 for establishing a wireless communication link, a power manager 28, and a memory 36. The processor 14 may include any one of a variety of processing devices, such as multiple processor cores.

[0030] The term "system-on-chip" (SoC) is used herein to refer to a group of interconnected electronic circuits, typically but not exclusively, including processing devices, memory, and communication interfaces. Processing devices may include various different types of processors 14 and processor cores, such as general-purpose processors, central processing units (CPUs), digital signal processors (DSPs), graphics processing units (GPUs), accelerated processing units (APUs), security processing units (SPUs), neural network processing units (NPUs), subsystem processors for specific components of a computing device, such as an image processor for a camera subsystem or a display processor for a display, auxiliary processors, single-core processors, multi-core processors, controllers, and microcontrollers. Processing devices may further embody other hardware and hardware combinations, such as field-programmable gate arrays (FPGAs), application-specific integrated circuits (ASICs), other programmable logic devices, discrete gate logic, transistor logic, performance monitoring hardware, watchdog hardware, and time bases. The integrated circuit may be configured such that the components of the integrated circuit are located on a single semiconductor material, such as silicon.

[0031] The SoC 12 may include one or more processors 14. The computing device 10 may include more than one SoC 12, thereby increasing the number of processors 14 and processor cores. The computing device 10 may further include processors 14 that are not associated with the SoC 12. Each of the processors 14 may be configured for a specific purpose that may be the same as or different from other processors 14 of the computing device 10. One or more of the processors 14 and processor cores of the same or different configurations may be grouped together. A group of processors 14 or processor cores may be referred to as a multiprocessor cluster.

[0032] The computing device 10 may include any number and combination of memories, such as the memory 16 integrated into the SoC 12 and the memory 36 separate from the SoC 12. Either of the memories 16, 36 may be a volatile or non-volatile memory configured to store data and processor-executable code for access by the processor 14. The computing device 10 and / or the SoC 12 may include one or more memories 16, 36 configured for various purposes. The one or more memories 16, 36 may include volatile memories such as random access memory (RAM) or main memory, including static RAM (SRAM) such as the memory 16, dynamic RAM (DRAM) such as the memory 36, or cache memory.

[0033] The memories 16, 36 may be configured to temporarily store a limited amount of data. For example, data may be received from a data sensor or subsystem. As another example, the data may be data and / or processor-executable code instructions requested from the non-volatile memories 16, 24, 36 and loaded into the memories 16, 36 from the non-volatile memories 16, 24, 36 based on various factors for anticipated future access. As another example, the data may be intermediate processing data and / or processor-executable code instructions generated by the processor 14 and temporarily stored for future quick access without being stored in the non-volatile memories 16, 24, 36.

[0034] The memory interface 34 may work in concert with the memory 36 to enable the computing device 10 to store and retrieve data and processor-executable code on the memory 36. The memory interface 34 may control access to the storage memory 36 and allow the processor 14 to read data from and write data to the memory 36.

[0035] The storage memory interface 20 and the storage memory 24 may work in concert to allow the computing device 10 to store data and processor-executable code on a non-volatile storage medium, such as a non-volatile memory standard (NVMe) memory device. The storage memory 24 may be configured very similarly to the embodiment of the memory 16, where the storage memory 24 may store data or processor-executable code for access by one or more of the processors 14. The non-volatile storage memory 24 may retain information after the power of the computing device 10 has been turned off. When the power is turned back on and the computing device 10 restarts, the information stored on the storage memory 24 may be available to the computing device 10. The storage memory interface 20 may control access to the storage memory 24 and allow the processor 14 to read data from and write data to the storage memory 24.

[0036] The inline cryptographic module 38 can be configured to implement cryptographic functions for data of transactions for the memory storage device 24, such as encryption and decryption. Data transmitted between the memory 36 and the storage memory 24 can be encrypted and decrypted by the inline cryptographic module 38 to protect the stored data and the memory storage device 24 by encrypting the data, and to make the encrypted data retrieved from the memory storage device 24 usable by the SoC by decrypting the data. The inline cryptographic module 38 can be configured to implement hash generation and verification for device prompts related to data transmitted between the memory 36 and the storage memory 24 to evaluate the integrity of the device prompts for evaluating whether to use the data.

[0037] The power manager 28 can be configured to control the power state of one or more power rails (not shown) for power delivery to components of the SoC 12. In some embodiments, the power manager 28 can be configured to control the amount of power provided to components of the SoC 12. For example, the power manager 28 can be configured to control the connection between components of the SoC 12 and the power rails. As another example, the power manager 28 can be configured to control the amount of power on the power rails connected to components of the SoC 12. The power manager 28 can be configured as a power management integrated circuit (power management IC or PMIC).

[0038] The clock controller 30 can be configured to control clock signals transmitted to components of the SoC 12. For example, the clock controller 30 can gate components of the SoC 12 by disconnecting the components of the SoC 12 from the clock signals, and can ungate components of the SoC 12 by connecting the components of the SoC 12 to the clock signals.

[0039] The interconnect 32 can be a communication structure configured to communicatively connect components of the SoC 12, such as a communication bus. The interconnect 32 can transmit signals between components of the SoC 12. In some embodiments, the interconnect 32 can be configured to control signals between components of the SoC 12 by controlling the timing and / or transmission path of the signals.

[0040] Some or all components of the computing device 10 and / or the SoC 12 can be differently arranged and / or combined while still serving the functions of the various embodiments. The computing device 10 is not limited to one component of each type, and multiple instances of each component can be included in various configurations of the computing device 10.

[0041] Figure 2 An example of an inline cryptographic NVMe system 200 suitable for implementing various embodiments is shown. Refer to the attached Figure 1 and 2, for example, an inline cryptographic NVMe system 200 can be implemented in a computing device (e.g., Figure 1 the computing device 10 in), including a memory 36, a SoC 202 (e.g., Figure 1 the SoC 12 in), and an NVMe device 214 (or NVMe memory device) (e.g., Figure 1 the storage memory 24 in) that are connected to each other via various communication buses.

[0042] The SoC 202 can include a processor 14, a Peripheral Component Interconnect Express (PCIe) controller 212 (e.g., Figure 1 the storage memory interface 20 in), and an inline cryptographic module 38 that are connected to each other via various communication buses. The processor 14 can be configured to implement software, such as an application 204, including an advanced operating system, a kernel 206, an NVMe driver 208, and a PCIe driver 210. The PCIe controller 212 can manage communication between the components of the SoC 202 (including the inline cryptographic module 38) and the NVMe device 214. Such communication can include communication for preparing and implementing, at the NVMe device 214, NVMe commands from the processor 14 for data transactions (such as read and / or write transactions).

[0043] The inline cryptographic module 38 can be a hardware module integrated into the SoC 202. The inline cryptographic module 38 can implement cryptographic functions, such as encryption, decryption, and / or bypass, for the data of the NVMe commands. For example, the inline cryptographic module 38 can encrypt data sent to the NVMe device 214 and decrypt data received from the NVMe device 214. The cryptographic functions implemented by the inline cryptographic module 38 can be any known, proprietary, and / or to-be-developed encryption and decryption means. For example, the inline cryptographic module 38 can provide per-application and / or file-based cryptographic functions. Software running on the SoC 202, the NVMe driver 208, and / or the application 204 can issue requests to use a specific algorithm and set of encryption keys for encryption, use a specific security context, and / or request that data be sent without encryption. Setting the security context, encryption keys, and / or encryption algorithm can be implemented by any software, the NVMe driver 208, and / or the application 204 running on the SoC 202, while using the security context, encryption keys, and / or encryption algorithm to encrypt or decrypt data can be done by another software entity. The inline cryptographic module 38 can also support secure key management. In some examples, the inline cryptographic module 38 can operate independently of the PCIe fabric and its different layers, achieve scalable storage throughput, and comply with the NVMe device protocol. In other examples, the inline cryptographic module 38 can be part of the PCIe controller 212. The inline cryptographic module 38 is further described herein.

[0044] Figure 3 An example of an inline cryptographic module 38 for implementing various embodiments is shown. Referring to the appendix Figures 1-3 , the inline cryptographic module 38 may be configured with a buffer address lookup structure 300, a security context structure 302, an encryption module 304, and a decryption module 306. For ease of explanation and clarity, the encryption module 304 and the decryption module 306 are described herein as separate components consistent with non-limiting embodiments. However, such separate description is not intended to limit the scope of the claims and the specification, and in some implementations and embodiments, the encryption module 304 and the decryption module 306 may be implemented as a single combined module.

[0045] The buffer address lookup structure 300 may be a data structure configured to store various data in association with each other, such as tables, arrays, linked lists, graphs, etc. For example, the buffer address lookup structure 300 may store data of at least the following items in association with each other: the buffer address of the memory 36 (referred to herein as the buffer address) and the NVMe security identifier (ID) for the NVMe command. The buffer address may be used by the NVMe command to write data from the buffer address of the memory 36 to the NVMe device 214 and / or read data from the NVMe device 214 into the buffer address of the memory 36. The NVMe security ID may be a combination of data (such as the NVMe command identifier for the NVMe command and the NVMe command submission queue identifier). The NVMe command submission queue identifier may identify the NVMe command submission queue to which the NVMe drive 208 may write the NVMe command. The NVMe command submission queue may trigger a doorbell signal configured to indicate to the NVMe device 214 that the NVMe command in the NVMe command submission queue is ready to execute when the NVMe command reaches the end of the NVMe command submission queue. The NVMe command ID may identify the NVMe command. The buffer address lookup structure 300 may also store data of the sector offset for the NVMe command in association with the buffer address and the NVMe security ID. The sector offset may be used to generate an initialization vector for the cryptographic function. The initialization vector may be used as an input to the encryption algorithm and is configured to affect the encryption of data in such a way that repeatedly encrypted data results in different encrypted values. The buffer address lookup structure 300 may store any amount of associated data, such as more than one set of associated data for more than one NVMe command.

[0046] The security context structure 302 can be a data structure configured to store various data in association with each other, such as tables, arrays, linked lists, graphs, etc. For example, the security context structure 302 can store data of the following items in association with each other: the security context for the NVMe command and the NVMe security ID. The NVMe security IDs in the buffer address lookup structure 300 and the security context structure 302 for the same NVMe command can be the same. The security context can include a combination of security-related information (such as, encryption algorithms, one or more encryption key slots for retrieving one or more encryption keys from the encryption key storage structure, etc.). In some examples, the security context can be provided by an application executed by the processor 14, and the NVMe command originates from the execution of the application. The security context structure 302 can store any amount of associated data, such as more than one set of associated data for more than one NVMe command.

[0047] The buffer address lookup structure 300 and the security context structure 302 can be configured at the in-line cryptographic module 38 during the NVMe command submission phase. In some examples, the NVMe drive (e.g., Figure 2 the NVMe drive 208 in) can configure the buffer address lookup structure 300 and the security context structure 302 at the in-line cryptographic module 38 in response to receiving an NVMe command issued by a processor (e.g., the processor 14). The NVMe drive can provide data for populating the buffer address lookup structure 300 and the security context structure 302 to the in-line cryptographic module 38, and the in-line cryptographic module 38 can store the data as the buffer address lookup structure 300 and the security context structure 302. Such data can include any combination of the buffer address for the NVMe command, the NVMe security ID, the sector offset, and / or the security context. In such examples, the NVMe drive can maintain the same address information at two different locations (the SoC memory (e.g., Figure 1 the memories 16, 36 in) and the buffer address lookup structure 300).

[0048] In some examples, the inline cryptographic module 38 may configure the buffer address lookup structure 300 and the security context structure 302 at the inline cryptographic module 38 in response to receiving an NVMe command from the NVMe drive. The inline cryptographic module 38 may process the NVMe command, extract data for populating the buffer address lookup structure 300 and the security context structure 302, and the inline cryptographic module 38 may store the data as the buffer address lookup structure 300 and the security context structure 302. Configuring the buffer address lookup structure 300 and the security context structure 302 by the inline cryptographic module 38 (instead of the NVMe drive) eliminates the address redundancy issues described previously and maintains data integrity. Additionally, the software overhead for configuring the buffer address lookup structure 300 in the inline cryptographic module 38 is reduced.

[0049] The inline cryptographic module 38 may be configured to forward a doorbell signal that is configured to indicate a pending NVMe command to the NVMe device (e.g., Figure 1 the storage memory 24 in Figure 2 the NVMe device 214 in). For example, the inline cryptographic module 38 may update the NVMe command submission queue tail pointer to the "doorbell" register of the NVMe device. According to known implementations of the NVMe protocol, forwarding the doorbell signal may allow bypassing or eliminating software configured to write to two doorbells and may ensure synchronization of the operations of the cryptographic module 38 and the NVMe device.

[0050] In response to receiving an NVMe transaction from the NVMe device, the inline cryptographic module 38 may use the information from the NVMe transaction to implement cryptographic functions for the data of the NVMe transaction. For example, the inline cryptographic module 38 may retrieve a buffer address from the NVMe transaction and use the buffer address to retrieve associated data, such as an NVMe security ID, from the buffer address lookup structure 300. In some examples, the inline cryptographic module 38 may use the buffer address to retrieve an associated sector offset from the buffer address lookup structure 300. The inline cryptographic module 38 may use the retrieved NVMe security ID to retrieve the associated security context for the NVMe command from the security context structure 302.

[0051] Using the retrieved information, such as sector offset and / or security context, the encryption module 304 and / or the decryption module 306 can implement cryptographic functions for the data of the NVMe transaction. For example, the retrieved information may include a security context from the security context structure 302, which may include an encryption algorithm, one or more encryption key slots for retrieving one or more encryption keys from the encryption key storage structure, and the like. The encryption module 304 can use the information of the retrieved security context to encrypt the data for the NVMe transaction to be sent to the NVMe device. The decryption module 306 can use the information of the retrieved security context to decrypt the data for the NVMe transaction received from the NVMe device.

[0052] As another example, the retrieved information may include a sector offset from the buffer address lookup structure 300. The encryption module 304 can use the retrieved sector offset to generate an initialization vector, and use the initialization vector together with the information of the retrieved security context to encrypt the data for the NVMe transaction to be sent to the NVMe device. The decryption module 306 can use the retrieved sector offset to generate an initialization vector, and use the initialization vector together with the information of the retrieved security context to decrypt the data for the NVMe transaction received from the NVMe device. The encryption module 304 can input the unencrypted data for the NVMe command, one or more encryption keys, and / or the initialization vector into the encryption algorithm, and generate the encrypted data for the NVMe command. The decryption module 306 can input the encrypted data for the NVMe command, one or more encryption keys, and / or the initialization vector into the encryption algorithm, and generate the decrypted data for the NVMe command.

[0053] Figure 4 A method for an inline cryptographic method for an NVMe device according to some embodiments is shown. Referring to the appendix Figures 1-4 , method 400 can be in a computing device (e.g., Figure 1 the computing device 10 in), in a processor (e.g., Figure 1 and 2 the processor 14 in, Figures 1-3 the inline cryptographic module 38 in), in software executed in general hardware, in dedicated hardware (e.g., Figures 1-3 the inline cryptographic module 38 in, Figure 3 the encryption module 304, the decryption module 306 in), or a software-configured processor and dedicated hardware (such as in a power management system including other individual components (e.g., Figure 2in an in-line cryptographic NVMe system 200) a processor that executes software, and various memory / cache controllers) in combination. To cover alternative configurations enabled in various embodiments, the hardware implementing method 400 is referred to herein as an "in-line cryptographic device". The units for implementing method 400 may include a processor (e.g., 14, 38, 304, 306).

[0054] In block 402, the in-line cryptographic device may store a security context structure (e.g., Figure 2 the security context structure 302 in Figure 3 configured by the NVMe drive 208 in). The in-line cryptographic device may receive data for populating the security context structure from the NVMe drive and store the data as the security context structure. The in-line cryptographic device may store various data associated with each other in the security context structure. For example, the security context structure may store data for the following items associated with each other: the NVMe security ID for the NVMe command and the security context for the NVMe command. The NVMe security ID may be a combination of data (such as the NVMe command identifier and the NVMe command submission queue identifier for the NVMe command). The security context may include a combination of security-related information (such as an encryption algorithm, one or more key slots, etc.). In some examples, the security context may be provided by an application executed by a processor (e.g., Figure 1 and 2 the processor 14 in), and the NVMe command originates from the execution of the application. In some examples, the in-line cryptographic device that stores the security context structure configured by the NVMe drive in block 402 may include an in-line cryptographic module (e.g., Figures 1-3 the in-line cryptographic module 38 in).

[0055] In block 404, the in-line cryptographic device may store a buffer address lookup structure configured by the NVMe drive (e.g., Figure 3The buffer address lookup structure 300). The inline cryptographic device can receive data for populating the buffer address query structure from the NVMe drive and store the data as the buffer address query structure. The inline cryptographic devices can store various data associated with each other in the buffer address query structure. For example, the buffer address lookup structures can store data for at least the following items associated with each other: the NVMe security ID for the NVMe command and the buffer address. The NVMe security ID in the buffer address lookup structure and the security context structure for the same NVMe command can be identical. The buffer address lookup structure can also store data for the sector offset for the NVMe command in association with the buffer address and the NVMe security ID. The sector offset can be used to generate an initialization vector for cryptographic functions. In some examples, the inline cryptographic device storing the buffer address lookup structure configured by the NVMe drive in block 404 can include an inline cryptographic module.

[0056] In block 406, the inline cryptographic device can receive an NVMe transaction from the NVMe device (e.g., Figure 1 the storage memory 24 in Figure 2 the NVMe device 214 in Figure 1 the storage memory interface 20 in Figure 2 the PCIe controller 212 in

[0057] The NVMe transaction can be how the NVMe device implements the NVMe command, such as read and / or write transactions. The NVMe transaction can be received by the inline cryptographic device from the NVMe device via a device interface (e.g.,

[0058] In block 410, the inline cryptographic device may retrieve a security context associated with the NVMe security ID. The inline cryptographic device may use the retrieved NVMe security ID to retrieve an associated security context for the NVMe command from a security context structure. In some examples, the inline cryptographic device that retrieves the security context associated with the NVMe security ID in block 410 may include an inline cryptographic module.

[0059] In block 412, the inline cryptographic device may calculate a sector number for implementing the NVMe transaction. The inline cryptographic device may calculate the sector number by known means using the buffer address of the NVMe transaction and the associated sector offset retrieved from the buffer address lookup structure. In some examples, the inline cryptographic device that calculates the sector number for implementing the NVMe transaction in block 412 may include an inline cryptographic module.

[0060] In block 414, the inline cryptographic device may calculate an initialization vector for implementing the cryptographic functionality of the NVMe transaction. The inline cryptographic device may use the sector number to calculate the initialization vector by known means. In some examples, the inline cryptographic device that calculates the initialization vector for implementing the cryptographic functionality of the NVMe transaction in block 414 may include an inline cryptographic module.

[0061] In block 416, the inline cryptographic device may perform cryptographic functions for implementing the NVMe transaction. Using the retrieved and calculated information, such as the security context and the initialization vector, the inline cryptographic device may perform cryptographic functions on the data for the NVMe transaction. For example, the inline cryptographic device may encrypt data to be sent to the NVMe device for the NVMe transaction. As another example, the inline cryptographic device may decrypt data received from the NVMe device for the NVMe transaction. In some examples, the inline cryptographic device that performs cryptographic functions for implementing the NVMe transaction in block 416 may include an inline cryptographic module, an encryption module (e.g., Figure 3 304) and / or a decryption module (e.g., Figure 3 Decryption module 306 in ).

[0062] Figure 5 A method for inline password for NVMe devices with doorbell forwarding according to some embodiments is shown. Figures 1-5 The method 500 may be performed on a computing device (e.g., Figure 1 In the computing device 10), in the processor (e.g., Figure 1 and 2 Processor 14, Figures 1-3 In software executed in an inline cryptographic module 38 in the embodiment of the present invention, in general-purpose hardware, in dedicated hardware (e.g., Figures 1-3 Inline password module 38,Figure 3 in the encryption module 304, the decryption module 306), or in a combination of a software-configured processor and dedicated hardware (such as a processor that executes software within a power management system that includes other individual components (e.g., Figure 2 within the inline cryptographic NVMe system 200), and various memory / cache controllers). To cover alternative configurations enabled in various embodiments, the hardware implementing method 500 is referred to herein as an "inline cryptographic device". The units for implementing method 500 may include a processor (e.g., 14, 38, 304, 306).

[0063] In block 502, the inline cryptographic device may receive an NVMe command from an NVMe drive (e.g., Figure 2 the NVMe drive 208 in Figure 1 and 2 the processor 14 in Figures 1-3 may execute an application from which the NVMe command originated and is sent to the NVMe drive. The NVMe drive may submit the NVMe command by updating the NVMe command submission queue. The NVMe drive may also forward the NVMe command to the inline cryptographic device. In some examples, the inline cryptographic device that receives the NVMe command from the NVMe drive in block 502 may include an inline cryptographic module (e.g.,

[0064] In block 504, the inline cryptographic device may configure a security context structure (e.g., Figure 2 the security context structure 302 in

[0065] at the inline cryptographic device. The inline cryptographic device may process the NVMe command, extract data for populating the security context structure, and the inline cryptographic device may store the data as the security context structure. The inline cryptographic device may store various data associated with each other in the security context structure. For example, the security context structure may store data for the following items associated with each other: the security context for the NVMe command and the NVMe security ID. The NVMe security ID may be a combination of data (such as the NVMe command identifier for the NVMe command and the NVMe command submission queue identifier). The security context may include a combination of security-related information (such as an encryption algorithm, one or more key slots, etc.). In some examples, the security context may be provided by an application executed by the processor from which the NVMe command originated. In some examples, the inline cryptographic device that configures the security context structure at the inline cryptographic device in block 504 may include an inline cryptographic module.

[0065] In block 506, the inline cryptographic device may configure a buffer address lookup structure (e.g., Figure 2The buffer address lookup structure 300) therein. The inline cryptographic device can process NVMe commands, extract data for populating the buffer address lookup structure, and the inline cryptographic device can store the data as the buffer address lookup structure. The inline cryptographic devices can store various data in the buffer address lookup structure in relation to each other. For example, the buffer address lookup structure can store data for at least the following items in relation to each other: the NVMe security ID for the NVMe command and the buffer address. The NVMe security ID in the buffer address lookup structure and the security context structure for the same NVMe command can be identical. The buffer address lookup structure can also store data for the sector offset for the NVMe command in relation to the buffer address and the NVMe security ID. The sector offset can be used to generate an initialization vector for cryptographic functions. In some examples, the inline cryptographic device that configures the buffer address lookup structure at block 506 can include an inline cryptographic module.

[0066] At block 508, the inline cryptographic device can update the NVMe command submission queue tail pointer to the doorbell register address. The inline cryptographic device can be configured to forward a doorbell signal that is configured to indicate a pending NVMe command to the NVMe device (e.g., Figure 1 the storage memory 24 in Figure 2 the NVMe device 214 therein). The inline cryptographic device can update the NVMe command submission queue tail pointer to the doorbell register of the NVMe device. In some examples, the inline cryptographic device that updates the NVMe command submission queue tail pointer to the doorbell register address at block 508 can include an inline cryptographic module.

[0067] The inline cryptographic device can implement blocks 406 - 416 described with the same numbered blocks of method 400 as described herein with reference to Figure 4 In some examples, the inline cryptographic device that implements blocks 406 - 416 can include an inline cryptographic module, an encryption module (e.g., Figure 3 the encryption module 304 in Figure 3 ), and / or a decryption module (e.g.,

[0068] Figure 6 shows an example of an inline cryptographic module 38 for implementing various embodiments. Referring to the attached Figures 1-6 , as described herein with reference to Figure 3As described for the same numbered items of the inline cryptographic module 38, the inline cryptographic module 38 may be configured with a buffer address lookup structure 300, a security context structure 302, an encryption module 304, and a decryption module 306. The inline cryptographic module 38 may be further configured with a hash module 600, and the inline cryptographic module 38 may use the hash module 600 to evaluate the integrity of the device hint to evaluate how to process the NVMe transaction.

[0069] The hash module 600 may include a hash generation module 602 and a hash verification module 604. The hash generation module 602 may be configured to generate a hash value for each buffer address of the NVMe command. The hash value may sign the buffer address where the data to be read or written is located in the local SoC memory (e.g., Figure 1 and 2 memory 16, 36). The hash generation module 602 may receive information from the NVMe drive (e.g., Figure 2 NVMe drive 208 in Figure 1 ), and retrieve security context information from the security context structure 302 to generate a hash value for the buffer address. The information received from the NVMe drive may be for the NVMe command submitted to the NVMe command submission queue, and may include the buffer address, the NVMe security ID, the sector offset, the cookie, predefined text or data, and / or other information that may assist in processing the device hint, as further described herein. The information retrieved from the security context structure 302 may be information associated with the NVMe security ID received from the NVMe drive, and may include the hash algorithm, one or more hash key slots for retrieving one or more hash keys from the hash key storage structure, etc. The hash generation module 602 may use the hash algorithm together with one or more hash keys retrieved using one or more hash key slots to generate a hash value for the buffer address, the NVMe security ID, the sector offset, the cookie, predefined text or data, and / or other information that may assist in processing the device hint. The hash value may be provided to the NVMe device (e.g., Figure 2 PCIe controller 212 in Figure 2 NVMe device 214 in Figure 1 and 2 SoC 12, 202 in

[0070] The generation module 602 can receive device hint information for an NVMe transaction from an NVMe device via a device interface, such as, and retrieve security context information from the security context structure 302 to generate a hash value for the device hint of the NVMe transaction. The information from the device hint can include an NVMe security ID, a buffer address, a sector offset, a cookie, predefined text or data, and / or other information that can assist in processing the device hint. The information retrieved from the security context structure 302 can be information associated with the NVMe security ID received from the NVMe drive, and can include a hash algorithm, one or more hash key slots for retrieving one or more hash keys from a hash key storage structure, etc. The hash generation module 602 can use the hash algorithm together with one or more hash keys retrieved using one or more hash key slots to generate hash values for the buffer address, the NVMe security ID, and the sector offset.

[0071] The hash verification module 604 can be configured to compare the hash value from the device hint with the hash value generated based on the information of the device hint to evaluate the integrity of the device hint for the NVMe transaction. The hash verification module 604 can retrieve the hash value from the device hint, receive the hash value generated based on the information of the device hint from the hash generation module 602, and compare the hash values. The hash verification module 604 can determine that the device hint is not corrupted in response to the hash values matching, and determine that the device hint is corrupted in response to the hash values not matching. Whether the device hint is corrupted can also indicate whether the data of the NVMe transaction associated with the device hint is corrupted.

[0072] The inline cipher module 38 can configure the buffer address lookup structure 300 by utilizing the information from the device hint in response to the hash verification module 604 determining that the NVMe transaction associated with the device hint is not corrupted. The inline cipher module 38 can process the device hint, extract the data for populating the buffer address lookup structure 300, and the inline cipher module 38 can store the data as the buffer address lookup structure 300. The inline cipher module 38 configures the buffer address lookup structure 300 in response to the verification of the hash of the device hint, reducing the size, and thereby reducing the resources used by the inline cipher module 38 to maintain the buffer address lookup structure 300, and increasing the security of the NVMe transaction.

[0073] Figure 7A and 7B illustrates a method of an inline cipher method for an NVMe device with device hint management according to some embodiments. Referring to the attached Figures 1-7B , methods 700a, 700b can be in a computing device (e.g., Figure 1 the computing device 10 in), in a processor (e.g., Figure 1 and2 in the processor 14 in Figures 1-3 in the software executed in the in - line cryptographic module 38 in, in general - purpose hardware, in dedicated hardware (e.g., Figures 1-3 in the in - line cryptographic module 38 in Figure 3 in the encryption module 304, decryption module 306 in Figure 6 in the hash module 600, hash generation module 602, hash verification module 604 in, or in a combination of a software - configured processor and dedicated hardware (such as a processor executing software within a power management system (e.g., Figure 2 in the in - line cryptographic NVMe system 200 in) and various memory / cache controllers). To cover alternative configurations enabled in various embodiments, the hardware for implementing methods 700a, 700b is referred to herein as an "in - line cryptographic device". The units for implementing methods 700a, 700b may include processors (e.g., 14, 38, 304, 306, 600, 602, 604).

[0074] For method 700a, the in - line cryptographic device may implement boxes similar to box 402 described with the same - numbered boxes of method 400 herein for reference Figure 4 In some examples, the in - line cryptographic device implementing box 402 may include an in - line cryptographic module (e.g., Figures 1-3 and the in - line cryptographic module 38 in 6).

[0075] In box 702, the in - line cryptographic device may receive information from an NVMe drive (e.g., Figure 2 the NVMe drive 208 in). The information received from the NVMe drive may be for one or more NVMe commands submitted to the NVMe command submission queue and may include buffer addresses, NVMe security IDs, and sector offsets. In some examples, the in - line cryptographic device receiving information from the NVMe drive in box 702 may include an in - line cryptographic module.

[0076] In box 704, the in - line cryptographic device may generate hash values for one or more buffer addresses. To generate the hash values, the in - line cryptographic device may obtain from a security context structure (e.g., Figure 3 and 6The inline cryptographic device may retrieve information from a security context structure 302 in block 704 that includes information associated with an NVMe security ID received from the NVMe drive, such as a hash algorithm, one or more hash key slots for retrieving one or more hash keys from a hash key storage structure, and the like. The inline cryptographic device may use a hash algorithm with one or more hash keys retrieved using the one or more hash key slots to generate a hash value for a buffer address, an NVMe security ID, and a sector offset. In some examples, the inline cryptographic device that generates hash values ​​for one or more buffer addresses in block 704 may include an inline cryptographic module, a hash module (e.g., Figure 6 ) and / or a hash generation module (e.g., Figure 6 Hash generation module 602 in ).

[0077] In block 706, the inline cryptographic device may send a request to an NVMe device (e.g., Figure 2 The NVMe device 214 in the inline cryptographic device provides a hash value to include in the device hint. The inline cryptographic device can be connected via a device interface (e.g., Figure 1 The storage memory interface 20, Figure 2 The PCIe controller 212 in block 706 provides a hash value to the NVMe device to be included in a device hint for the NVMe transaction to be sent back to the inline cryptographic device. The hash sent to the NVMe device may be sent in association with other information, such as a portion of the device hint for the NVMe transaction that may be returned by the NVMe device. The device hint sent to the NVMe device may include a hash, an NVMe security ID, a buffer address, a sector offset, a cookie, predefined text or data, and / or other information that may assist in processing the device hint. In some examples, the inline cryptographic device that provides the hash value to the NVMe device in block 706 may include an inline cryptographic module.

[0078] In method 700b, in block 710, an inline cryptographic device may receive NVMe transactions and device hints from an NVMe device. The NVMe transactions and device hints may be received via a device interface. In some examples, the inline cryptographic device that receives NVMe transactions and device hints from the NVMe device in block 710 may include an inline cryptographic module, a hash module, and / or a hash generation module.

[0079] In block 712, the inline cryptographic device may use the information from the device hint to generate a hash value. The inline cryptographic device may process the device hint and extract information from the device hint, which includes the NVMe security ID, buffer address, sector offset for the NVMe transaction, cookie, predefined text or data, and / or other information that may assist in processing the device hint. The inline cryptographic device may also retrieve security context information from the security context structure to generate a hash value for the NVMe transaction. The information retrieved from the security context structure 302 may be information associated with the NVMe security ID of the device hint and may include a hash algorithm, one or more hash key slots for retrieving one or more hash keys from the hash key storage structure, etc. The inline cryptographic device may use the hash algorithm together with one or more hash keys retrieved using one or more hash key slots to generate a hash value for the buffer address, NVMe security ID, and sector offset. In some examples, the inline cryptographic device that uses the information from the device hint to generate a hash value in block 712 may include an inline cryptographic module, a hash module, and / or a hash generation module.

[0080] In optional block 714, the inline cryptographic device may compare the hash value generated using the information from the device hint with a verification value. For example, referring to Figure 7A , a part of the information extracted from the device hint may include a hash value previously generated by the inline cryptographic device and sent to the NVMe device in blocks 704 and 706 of method 700a. The hash value generated using the information from the device hint and the hash value from the device hint may be compared to evaluate the integrity of the device hint for the NVMe transaction. As another example, the hash value generated using the information from the device hint may be compared with a predefined value to evaluate the integrity of the device hint for the NVMe transaction. In some examples, the inline cryptographic device that compares the hash value generated using the information from the device hint with a verification value in optional block 714 may include an inline cryptographic module, a hash module, and / or a hash verification module (e.g., Figure 6 the hash verification module 604 in

[0081] In decision block 716, the inline cryptographic device may determine whether the device hint is valid. For example, based on the comparison of the values in optional block 714, the inline cryptographic device may determine whether the hash values are the same or different. Any known or proprietary means for verifying hash values may be used to verify the device hint. In some examples, the inline cryptographic device that determines whether the device hint is valid in decision block 716 may include an inline cryptographic module, a hash module, and / or a hash verification module.

[0082] In response to determining that the device hint is invalid (i.e., determining that box 716 = "No"), in box 710, the inline cryptographic device may receive an NVMe transaction and a device hint from the NVMe device. In response to determining that the device hint is valid (i.e., determining that box 716 = "Yes"), in box 718, the inline cryptographic device may use the information from the device hint for the NVMe transaction to configure the buffer address lookup structure (e.g., Figure 3 and 6 the buffer address lookup structure 300). The inline cryptographic device may process the device hint, extract data for populating the buffer address lookup structure, and may store the data as the buffer address lookup structure. In some examples, the inline cryptographic device that configures the buffer address lookup structure using the information from the device hint for the NVMe transaction in box 718 may include an inline cryptographic module.

[0083] The inline cryptographic device may implement operations in boxes 408 - 416 similar to those described in the similarly numbered boxes of method 400 herein with reference to Figure 4 In some examples, the inline cryptographic device that implements boxes 408 - 416 may include an inline cryptographic device, an encryption module (e.g., Figure 3 the encryption module 304 in Figure 3 ), and / or a decryption module (e.g.,

[0084] the decryption module 306 in Figures 1-7B ). Figure 8 Each embodiment (including but not limited to the embodiments described above with reference to the accompanying

[0085] The mobile computing device 800 may have one or more wireless signal transceivers 808 (e.g., Peanut, Bluetooth, Zigbee, Wi-Fi, RF radio) and antennas 810 for sending and receiving communications, which are coupled to each other and / or to the processor 802. The transceivers 808 and antennas 810 may be used with the circuitry mentioned above to implement various wireless transmission protocol stacks and interfaces. The mobile computing device 800 may include a cellular network wireless modem chip 816, which enables communication via the cellular network and is coupled to the processor.

[0086] The mobile computing device 800 may include a peripheral device connection interface 818 coupled to the processor 802. The peripheral device connection interface 818 may be configured to accept a single type of connection, or may be configured to accept various types of physical and communication connections, either jointly or exclusively, such as Universal Serial Bus (USB), FireWire, Thunderbolt, or PCIe. The peripheral device connection interface 818 may also be coupled to a similarly configured peripheral device connection port (not shown).

[0087] The mobile computing device 800 may also include a speaker 814 for providing audio output. The mobile computing device 800 may also include a housing 820 made of plastic, metal, or a combination of materials for enclosing all or some of the components described herein. The mobile computing device 800 may include a power supply 822 coupled to the processor 802, such as a disposable or rechargeable battery. The rechargeable battery may also be coupled to the peripheral device connection port to receive a charging current from a source external to the mobile computing device 800. The mobile computing device 800 may also include physical buttons 824 for receiving user input. The mobile computing device 800 may also include a power button 826 for turning on and off the mobile computing device 800.

[0088] Various embodiments (including but not limited to the embodiments described above with reference to the appended Figures 1-7B drawings) may be implemented in a variety of computing systems including a laptop computer 900, examples of which are shown in Figure 9is shown. Many laptop computers include a touchpad touch surface 917 that serves as a pointing device for the computer and can thus receive drag, scroll, and flick gestures similar to those described above implemented on a computing device equipped with a touch screen display. Laptop computer 900 typically includes a processor 902 coupled to volatile memory 912 and a mass non-volatile memory (e.g., a hard disk drive 913 of flash memory). Additionally, computer 900 may have one or more antennas 908 for transmitting and receiving electromagnetic radiation, and the antennas 908 may be connected to a wireless data link and / or a cellular phone transceiver 916 coupled to the processor 902. Computer 900 may also include a floppy disk drive 914 and a compact disc (CD) drive 915 coupled to the processor 902. In a notebook configuration, the computer housing includes a touchpad 917, a keyboard 918, and a display 919, all of which are coupled to the processor 902. Other configurations of computing devices may include a computer mouse or trackball (e.g., via a USB input) coupled to the processor, which, as is known, may also be used in conjunction with the various embodiments.

[0089] The various embodiments (including but not limited to the embodiments referenced above with Figures 1-7B reference to the appended) may also be implemented in a fixed computing system. Such as, any of a variety of commercially available servers. In Figure 10 is shown an example server 1000. Such a server 1000 typically includes one or more multi-core processor components 1001, which are coupled to volatile memory 1002 and a mass non-volatile memory (such as a disk drive 1004). As Figure 10 shown, the multi-core processor components 1001 may be added to the server 1000 by inserting them into a rack of the components. Server 1000 may also include a floppy disk drive, a compact disc (CD) or digital versatile disc (DVD) drive 1006 coupled to the processor 1001. Server 1000 may also include a network access port 1003 coupled to the multi-core processor component 1001 for establishing a network interface connection to a network 1005 (such as a local area network, the Internet, a public switched telephone network, and / or a cellular data network (e.g., CDMA, TDMA, GSM, PCS, 3G, 4G, 5G, LTE, or any other type of cellular data network) coupled to other broadcast system computers and servers).

[0090] Computer program code, or "program code," for execution on a programmable processor to implement the operations of the various embodiments may be written in a high-level programming language such as C, C++, C#, Smalltalk, Java, JavaScript, VisualBasic, Structured Query Language (e.g., Transact-SQL), Perl, or in various other programming languages. Program code or programs stored on a computer-readable storage medium as used in this application may refer to machine language code (such as, object code) whose format is understandable by a processor.

[0091] The following paragraphs introduce example implementations. Although some of the example implementations in the following paragraphs are described in terms of example systems, devices, or methods, further example implementations may include: the example systems or devices discussed in the following paragraphs being implemented as methods for performing the operations of the example systems or devices; the example systems, devices, or methods discussed in the following paragraphs being implemented by a computing device that includes an in-line cryptographic module configured to perform the operations of the example systems or devices; the example systems, devices, or methods discussed in the following paragraphs being implemented by a computing device that includes a processing device configured with processing device-executable instructions to perform the operations of the example systems or devices; a computing device including units for performing the functions of the example systems, devices, or methods; and the example systems, devices, or methods discussed in the following paragraphs being implemented as a non-transitory processor-readable storage medium having processor-executable instructions stored thereon, the processor-executable instructions being configured to cause a processor of a computing device to perform the operations of the example systems, devices, or methods.

[0092] Example 1. A method implemented in an in-line cryptographic module of a system-on-chip (SoC) for a non-volatile memory express (NVMe) device, comprising: storing, in association with each other, a data buffer address for an NVMe command and an NVMe security identifier for the NVMe command, wherein the NVMe security identifier includes an NVMe command identifier for the NVMe command and an NVMe command submission queue identifier; storing, in association with each other, a security context for the NVMe command and the NVMe security identifier; retrieving the security context for the NVMe command based on the association of the data buffer address for the NVMe command with the NVMe security identifier for the NVMe command and the association of the NVMe security identifier with the security context for the NVMe command; and implementing a cryptographic function for data of the NVMe command using information of the security context for the NVMe command.

[0093] Example 2. The method according to Example 1 further includes: using the information of the NVMe command through an NVMe driver to configure, at the in-line cryptographic module, a structure for storing the data buffer address for the NVMe command and the NVMe security identifier for the NVMe command in association with each other; and using the information of the NVMe command through the NVMe driver to configure, at the in-line cryptographic module, a structure for storing the security context for the NVMe command and the NVMe security identifier for the NVMe command in association with each other.

[0094] Example 3. The method according to Example 1 further includes: receiving the NVMe command from an NVMe driver; using the information of the NVMe command to configure a structure for storing the data buffer address for the NVMe command and the NVMe security identifier for the NVMe command in association with each other; and using the information of the NVMe command to configure a structure for storing the security context for the NVMe command and the NVMe security identifier for the NVMe command in association with each other.

[0095] Example 4. The method according to any one of Examples 1-3 further includes: updating the NVMe command submission queue tail pointer using a doorbell register address.

[0096] Example 5. The method according to any one of Examples 1-4 further includes: generating a hash value for the NVMe command using the information of the security context for the NVMe command based on the association between the data buffer address for the NVMe command and the NVMe security identifier for the NVMe command and the association between the NVMe security identifier and the security context for the NVMe command, wherein the hash value is used by the NVMe device to be included in a device hint for the NVMe command.

[0097] Example 6. The method according to any one of Examples 1-5 further includes: receiving a device hint for the NVMe command from an NVMe device, the device hint including the hash value of the NVMe command; and using the information of the device hint for the NVMe command to configure a structure for storing the data buffer address for the NVMe command and the NVMe security identifier for the NVMe command in association with each other.

[0098] Example 7. The method according to Example 6 further includes: using the hash value to verify the device hint for the NVMe command, wherein configuring the structure for storing the data buffer address for the NVMe command and the NVMe security identifier for the NVMe command in association with each other using the information of the device hint for the NVMe command includes: in response to determining that the device hint is valid, configuring the structure for storing the data buffer address for the NVMe command and the NVMe security identifier for the NVMe command in association with each other using the information of the device hint for the NVMe command.

[0099] The foregoing method descriptions and process flow diagrams are provided only as illustrative examples and are not intended to require or imply that the operations of the various embodiments must be performed in the order presented. As will be appreciated by those skilled in the art, the order of operations in the foregoing embodiments may be performed in any order. Words such as "thereafter", "then", "next", etc. are not intended to limit the order of operations; these words are only used to guide the reader through the description of the method. Additionally, for example, the use of the words "a", "an", or "the" to refer to a claim element in the singular should not be construed as limiting the element to the singular.

[0100] The various illustrative logical blocks, modules, circuits, and algorithmic operations described in connection with the embodiments can be implemented as electronic hardware, computer software, or combinations thereof. To clearly illustrate this interchangeability of hardware and software, the various illustrative components, blocks, modules, circuits, and operations have been described above generally in terms of their functionality. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the overall system. Those skilled in the art may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be regarded as causing a departure from the scope of the claims.

[0101] The hardware for implementing the various illustrative logics, logic blocks, modules, and circuits described in connection with the aspects disclosed herein can be implemented or performed using a general-purpose processor, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. The general-purpose processor may be a microprocessor, but in the alternative, the processor may be any conventional processor, controller, microcontroller, or state machine. The processor may also be implemented as a combination of computing devices, e.g., a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration. Alternatively, some methods or operations may be performed by circuitry specific to a given function.

[0102] In one or more embodiments, the described functions may be implemented in hardware, software, firmware, or any combination thereof. If implemented in software, the functions may be stored as one or more instructions or code on a non-transitory computer-readable medium or a non-transitory processor-readable medium. The operations of the methods or algorithms disclosed herein may be embodied in a processor-executable software module, which may reside on a non-transitory computer-readable or processor-readable storage medium. The non-transitory computer-readable or processor-readable storage medium may be any storage medium accessible by a computer or a processor. By way of example and not limitation, such non-transitory computer-readable or processor-readable medium may include RAM, ROM, EEPROM, flash memory, CD-ROM or other optical disk storage, disk storage or other magnetic storage devices, or any other medium that can be used to store the desired program code in the form of instructions or data structures and that can be accessed by a computer. As used herein, "disk" and "optical disk" include compact disk (CD), laser disk, optical disk, digital versatile disk (DVD), floppy disk, and Blu-ray disk, where disks typically reproduce data magnetically, while optical disks use lasers to optically reproduce data. Combinations of the above are also included within the scope of non-transitory computer-readable and processor-readable media. Additionally, the operations of a method or algorithm may reside as one or any combination or set of code and / or instructions on a non-transitory processor-readable medium and / or a computer-readable medium, which may be incorporated into a computer program product.

[0103] The foregoing description of the disclosed embodiments enables any person skilled in the art to practice or use the claims. Various modifications to these aspects will be apparent to those skilled in the art, and the general principles defined herein can be applied to other embodiments and implementations without departing from the scope of the claims. Thus, the present disclosure is not intended to be limited to the embodiments and implementations shown herein, but is to be accorded the widest scope consistent with the appended claims and the principles and novel features disclosed herein.

Claims

1. A method implemented in an in-line cryptographic module of a system-on-chip (SoC) for a Non-Volatile Memory Express (NVMe) device, comprising: storing, in association with each other, a data buffer address for an NVMe command and an NVMe security identifier for the NVMe command, wherein the NVMe security identifier includes an NVMe command identifier and an NVMe command submission queue identifier for the NVMe command; storing, in association with each other, a security context for the NVMe command and the NVMe security identifier; retrieving a security context for the NVMe command based on the association of the data buffer address for the NVMe command with the NVMe security identifier of the NVMe command and the association of the NVMe security identifier with the security context for the NVMe command; and implementing a cryptographic function for data of the NVMe command using information of the security context for the NVMe command.

2. The method according to claim 1, further comprising: configuring, by an NVMe driver, at the in-line cryptographic module, a structure for storing, in association with each other, the data buffer address for the NVMe command and the NVMe security identifier for the NVMe command using information of the NVMe command; and configuring, by the NVMe driver, at the in-line cryptographic module, a structure for storing, in association with each other, the security context for the NVMe command and the NVMe security identifier using information of the NVMe command.

3. The method according to claim 1, further comprising: receiving the NVMe command from an NVMe driver; using information of the NVMe command to configure a structure for storing, in association with each other, the data buffer address for the NVMe command and the NVMe security identifier for the NVMe command; and using information of the NVMe command to configure a structure for storing, in association with each other, the security context for the NVMe command and the NVMe security identifier.

4. The method according to claim 1, further comprising: updating an NVMe command submission queue tail pointer using a doorbell register address.

5. The method according to claim 1, further comprising: generating, based on the association of the data buffer address for the NVMe command with the NVMe security identifier of the NVMe command and the association of the NVMe security identifier with the security context for the NVMe command, a hash value for the NVMe command using information of the security context for the NVMe command, wherein the hash value is used to be included by the NVMe device in a device hint for the NVMe command.

6. The method according to claim 1, further comprising: receiving a device hint for the NVMe command from the NVMe device, the device hint including a hash value of the NVMe command; and Configure a structure for storing the data buffer address for the NVMe command and the NVMe security identifier for the NVMe command in association with each other using the information prompted by the device for the NVMe command.

7. The method according to claim 6, further comprising: Verifying the device prompt for the NVMe command using the hash value, wherein configuring the structure for storing the data buffer address for the NVMe command and the NVMe security identifier for the NVMe command in association with each other using the information prompted by the device for the NVMe command comprises: in response to determining that the device prompt is valid, configuring the structure for storing the data buffer address for the NVMe command and the NVMe security identifier for the NVMe command in association with each other using the information prompted by the device for the NVMe command.

8. A computing device, comprising: An in-line cryptographic module of a system-on-chip (SoC) for a non-volatile memory express (NVMe) device, the in-line cryptographic module being configured to: Store the data buffer address for the NVMe command and the NVMe security identifier for the NVMe command in association with each other, wherein the NVMe security identifier includes the NVMe command identifier and the NVMe command submission queue identifier for the NVMe command; Store the security context for the NVMe command and the NVMe security identifier in association with each other; Retrieve the security context for the NVMe command based on the association between the data buffer address for the NVMe command and the NVMe security identifier for the NVMe command and the association between the NVMe security identifier and the security context for the NVMe command; and Implement a cryptographic function for the data of the NVMe command using the information of the security context for the NVMe command.

9. The computing device according to claim 8, wherein the cryptographic module is further configured to: Configure, at the in-line cryptographic module, a structure for storing the data buffer address for the NVMe command and the NVMe security identifier for the NVMe command in association with each other using the information of the NVMe command through the NVMe driver; and Configure, at the in-line cryptographic module, a structure for storing the security context for the NVMe command and the NVMe security identifier in association with each other using the information of the NVMe command through the NVMe driver.

10. The computing device according to claim 8, wherein the cryptographic module is further configured to: Receive the NVMe command from the NVMe driver; Configure a structure for storing the data buffer address for the NVMe command and the NVMe security identifier for the NVMe command in association with each other using the information of the NVMe command; and Configure a structure for storing the security context and the NVMe security identifier for the NVMe command in association with each other using the information of the NVMe command.

11. The computing device according to claim 8, wherein, the cryptographic module is further configured to update the NVMe command submission queue tail pointer with the doorbell register address.

12. The computing device according to claim 8, wherein, the cryptographic module is further configured to: based on the association between the data buffer address for the NVMe command and the NVMe security identifier of the NVMe command, and the association between the NVMe security identifier and the security context for the NVMe command, use the information of the security context for the NVMe command to generate a hash value for the NVMe command, wherein the hash value is used by the NVMe device to be included in the device hint for the NVMe command.

13. The computing device according to claim 8, wherein, the cryptographic module is further configured to: receive a device hint for the NVMe command from the NVMe device, the device hint including the hash value of the NVMe command; and configure a structure for storing the data buffer address for the NVMe command and the NVMe security identifier for the NVMe command in association with each other using the information of the device hint for the NVMe command.

14. The computing device according to claim 13, wherein, the cryptographic module is further configured to: use the hash value to verify the device hint for the NVMe command; and in response to determining that the device hint is valid, configure the structure for storing the data buffer address for the NVMe command and the NVMe security identifier for the NVMe command in association with each other using the information of the device hint for the NVMe command.

15. A computing device, comprising: a unit for storing the data buffer address for a Non-Volatile Memory Express (NVMe) command and the NVMe security identifier for the NVMe command in association with each other, wherein the NVMe security identifier includes the NVMe command identifier and the NVMe command submission queue identifier for the NVMe command; a unit for storing the security context for the NVMe command and the NVMe security identifier in association with each other; a unit for retrieving the security context for the NVMe command based on the association between the data buffer address for the NVMe command and the NVMe security identifier of the NVMe command, and the association between the NVMe security identifier and the security context for the NVMe command; and a unit for implementing a cryptographic function for the data of the NVMe command using the information of the security context for the NVMe command.

16. The computing device according to claim 15, further comprising: A unit for configuring, at the in-line cryptographic module, a structure for storing, in association with each other, the data buffer address for the NVMe command and the NVMe security identifier for the NVMe command, using the information of the NVMe command via the NVMe drive; And A unit for configuring, at the in-line cryptographic module, a structure for storing, in association with each other, the security context for the NVMe command and the NVMe security identifier for the NVMe command, using the information of the NVMe command via the NVMe drive.

17. The computing device according to claim 15, further comprising: A unit for receiving the NVMe command from the NVMe drive; A unit for configuring, using the information of the NVMe command, a structure for storing, in association with each other, the data buffer address for the NVMe command and the NVMe security identifier for the NVMe command; And A unit for configuring, using the information of the NVMe command, a structure for storing, in association with each other, the security context for the NVMe command and the NVMe security identifier for the NVMe command.

18. The computing device according to claim 15, further comprising: A unit for updating the NVMe command submission queue tail pointer with the doorbell register address.

19. The computing device according to claim 15, further comprising: A unit for generating, based on the association between the data buffer address for the NVMe command and the NVMe security identifier for the NVMe command and the association between the NVMe security identifier and the security context for the NVMe command, a hash value for the NVMe command using the information of the security context for the NVMe command, wherein the first value is for inclusion by the NVMe device in a device hint for the NVMe command.

20. The computing device according to claim 15, further comprising: A unit for receiving, from the NVMe device, a device hint for the NVMe command, the device hint including a first hash value of the NVMe command; And A unit for configuring, using the information of the device hint for the NVMe command, a structure for storing, in association with each other, the data buffer address for the NVMe command and the NVMe security identifier for the NVMe command.

21. The computing device according to claim 20, further comprising: A unit for verifying the device hint for the NVMe command using the hash value Among them, the unit configured to use the information of the device hint for the NVMe command to configure the structure for storing the data buffer address for the NVMe command and the NVMe security identifier for the NVMe command in association with each other includes: a unit configured to, in response to determining that the device hint is valid, use the information of the device hint for the NVMe command to configure the structure for storing the data buffer address for the NVMe command and the NVMe security identifier for the NVMe command in association with each other.

22. A non-transitory processor-readable medium having processor-executable instructions stored thereon, the processor-executable instructions being configured to cause a processor to perform operations including the following: Store a data buffer address for a Non-Volatile Memory Express (NVMe) command and an NVMe security identifier for the NVMe command in association with each other, Wherein, The NVMe security identifier includes an NVMe command identifier for the NVMe command and an NVMe command submission queue identifier; Store a security context for the NVMe command and the NVMe security identifier in association with each other; Retrieve the security context for the NVMe command based on the association between the data buffer address for the NVMe command and the NVMe security identifier for the NVMe command and the association between the NVMe security identifier and the security context for the NVMe command; And Use the information of the security context for the NVMe command to implement a cryptographic function for the data of the NVMe command.

23. The non-transitory processor-readable medium according to claim 22, Wherein, The stored processor-executable instructions are configured to cause the processor to perform operations further including the following: Configure, via an NVMe driver, a structure for storing the data buffer address for the NVMe command and the NVMe security identifier for the NVMe command in association with each other at the in-line cryptographic module using the information of the NVMe command; And Configure, via the NVMe driver, a structure for storing the security context for the NVMe command and the NVMe security identifier in association with each other at the in-line cryptographic module using the information of the NVMe command.

24. The non-transitory processor-readable medium according to claim 22, Wherein, The stored processor-executable instructions are configured to cause the processor to perform operations further including the following: Receive the NVMe command from the NVMe driver; Use the information of the NVMe command to configure a structure for storing the data buffer address for the NVMe command and the NVMe security identifier for the NVMe command in association with each other; And Configure a structure for storing the security context and the NVMe security identifier for the NVMe command in association with each other using the information of the NVMe command.

25. The non-transitory processor-readable medium according to claim 22, wherein, the stored processor-executable instructions are configured to cause the processor to perform operations that further include: updating the NVMe command submission queue tail pointer with the doorbell register address.

26. The non-transitory processor-readable medium according to claim 22, wherein, the stored processor-executable instructions are configured to cause the processor to perform operations that further include: generating a hash value for the NVMe command using the information of the security context for the NVMe command based on the association between the data buffer address for the NVMe command and the NVMe security identifier of the NVMe command and the association between the NVMe security identifier and the security context for the NVMe command, wherein the hash value is used by the NVMe device to be included in the device hint for the NVMe command.

27. The non-transitory processor-readable medium according to claim 22, wherein, the stored processor-executable instructions are configured to cause the processor to perform operations that further include: receiving, from the NVMe device, a device hint for the NVMe command, the device hint including the hash value of the NVMe command; and configuring a structure for storing the data buffer address for the NVMe command and the NVMe security identifier for the NVMe command in association with each other using the information of the device hint for the NVMe command.

28. The non-transitory processor-readable medium according to claim 27, wherein, the stored processor-executable instructions are configured to cause the processor to perform operations that further include: verifying the device hint for the NVMe command using the hash value, wherein configuring the structure for storing the data buffer address for the NVMe command and the NVMe security identifier for the NVMe command in association with each other using the information of the device hint for the NVMe command includes: in response to determining that the device hint is valid, configuring the structure for storing the data buffer address for the NVMe command and the NVMe security identifier for the NVMe command in association with each other using the information of the device hint for the NVMe command.

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