Drive circuit for power semiconductor element, and power conversion device

Abstract

A power semiconductor element (1a) includes a first main electrode on a high potential side, a second main electrode on a low potential side, a gate electrode as a control electrode, and a diode connected in anti-parallel between the first main electrode and the second main electrode. A drive circuit (10a) for a power semiconductor element (1a) is provided with: a control circuit (11) for selectively applying an ON bias voltage and an OFF bias voltage to a gate of the power semiconductor element (1a) in accordance with a control signal (GSWa) input from the outside; a detection circuit (18) that detects the amount of gate charge of the power semiconductor element (1a); and a determination circuit (19) that determines, on the basis of the amount of gate charge detected by the detection circuit (18), whether or not the diode of the power semiconductor element (1a) is executing a freewheeling operation.

Description

Technical Field

[0001] The present disclosure relates to a drive circuit for a semiconductor element for power use and a power conversion device. Background Art

[0002] A drive circuit of a semiconductor element for power use such as a MOSFET (Metal Oxide Semiconductor Filed Effect Transistor) and an IGBT (Insulated Gate Bipolar Transistor) (hereinafter also simply referred to as "semiconductor element") is configured to control the current flowing through the semiconductor element by turning on (connecting) / off (disconnecting) the semiconductor element by applying a gate bias to the gate. Such a drive circuit is also called a "gate drive circuit".

[0003] In the gate bias, there are a turn-on bias for turning on the semiconductor element and a turn-off bias for turning off the semiconductor element. The turn-on bias is a voltage above the gate threshold voltage of the semiconductor element, and the turn-off bias is a voltage less than the gate threshold voltage. The gate threshold voltage of a general IGBT and a normally-off MOSFET is about 2 to 7V. Therefore, generally, the turn-on bias is set to about 15 to 20V, and the turn-off bias is set to -15 to 0V.

[0004] In a power conversion device, a bridge circuit in which two semiconductor elements are connected in series is used. The drive circuit alternately turns on these two semiconductor elements in accordance with a control signal provided from a control device. However, when one semiconductor element is turned off and the other semiconductor element is turned on, if the turn-on periods overlap, there is a possibility of a short-circuit phenomenon in which the two semiconductor elements are turned on simultaneously and an excessive current flows. In order to prevent this short-circuit phenomenon, a dead time during which both of the two semiconductor elements are turned off is set.

[0005] However, when the dead time becomes long, distortion occurs in the waveforms of the voltage and current input to and output from the power conversion device or it becomes an obstacle to high-frequency operation, so there is a demand for minimizing the dead time as much as possible.

[0006] In addition, it is known that there is a lifetime for the application of a gate bias in the oxide film of the gate of a semiconductor element. In order to extend the lifetime of the oxide film, it is necessary to relax the electric field applied to the oxide film or shorten the application time of the gate bias.

[0007] As a technique for suppressing the deterioration development of semiconductor elements, for example, a drive circuit that drives an upper-branch switch and a lower-branch switch is disclosed in Japanese Unexamined Patent Application Publication No. 2019-68691 (Patent Document 1). In this drive circuit, among the body diodes respectively provided in the upper-branch switch and the lower-branch switch, the diode through which a freewheeling current flows during the dead time is set as the target diode, the switch having the target diode is set as the target switch, and the remaining switches are set as opposite-branch switches. The drive circuit is configured to maintain the gate bias of the target switch at a negative voltage during a period (hereinafter also referred to as a specified period) from a timing after the start timing of the dead time, which is just after the target switch has switched to the cut-off state, to a midway point during the period until the opposite-branch switch becomes conductive, and then maintain the gate bias of the target switch at a cut-off voltage until the end of the next dead time. Here, the negative voltage refers to a voltage less than 0, and the cut-off voltage is a voltage of 0 or more and less than the gate threshold voltage.

[0008] Prior Art Documents

[0009] Patent Documents

[0010] Patent Document 1: Japanese Unexamined Patent Application Publication No. 2019-68691 Summary of the Invention

[0011] The drive circuit described in Patent Document 1 prevents the target switch from self-turning on when the opposite-branch switch switches to the conductive state by maintaining the gate bias of the target switch at a negative voltage during the above-specified period.

[0012] However, in Patent Document 1, it is necessary to maintain the gate bias of the target switch at a negative voltage during the period from the end of the dead time, which is just after the target switch has switched to the cut-off state, to the completion of the turn-on of the opposite-branch switch. Therefore, it is necessary to have a time margin during the period from the end of the dead time to the switching of the gate bias from the negative voltage to the cut-off voltage. In this case, the time for applying a negative voltage to the gate of the target switch becomes longer, which may affect the lifetime of the oxide film. On the other hand, when there is no time margin during the above period, the gate bias of the target switch cannot be maintained at a negative voltage until the opposite-branch switch is turned on completely, so there is a possibility that the target switch will self-turn on.

[0013] That is, in order to prevent the self-turn-on of the target switch, it is necessary to apply a negative voltage without excessive shortage for the period required for the turn-on of the opposite-branch switch, but it is difficult to correctly grasp such a period only by the information input to the drive circuit of the target switch. To solve this problem, there is a method of separately preparing an insulated signal for detecting the timing of the turn-on of the opposite-branch switch, but this method has problems in terms of mounting area and cost.

[0014] In addition, in Patent Document 1, in order to determine which of the upper-branch switch and the lower-branch switch is the target switch, a sensing terminal that outputs a minute current correlated with the current flowing between the first terminal and the second terminal is provided at each branch switch, and the flowing direction of the current is detected based on the minute current output from the sensing terminal. In this method, since it is necessary to provide sensing terminals for all semiconductor elements, there is a problem in terms of cost.

[0015] The present disclosure has been made to solve such problems, and a main object thereof is to provide a drive circuit that can determine a freewheeling operation of a diode of a power semiconductor element with a simple configuration.

[0016] A drive circuit according to an aspect of the present disclosure is a drive circuit that drives a power semiconductor element. The power semiconductor element has a first main electrode on a high-potential side, a second main electrode on a low-potential side, a gate as a control electrode, and a diode that is anti-parallel connected between the first main electrode and the second main electrode. The drive circuit includes: a control circuit that selectively applies a conduction bias voltage and a cutoff bias voltage to the gate of the power semiconductor element in accordance with a control signal input from the outside; a detection circuit that detects the gate charge amount of the power semiconductor element; and a determination circuit that determines whether the diode of the power semiconductor element is performing a freewheeling operation based on the gate charge amount detected by the detection circuit.

[0017] According to the present disclosure, it is possible to determine a freewheeling operation of a power semiconductor element with a simple configuration. Thereby, it is possible to find a timing at which the power semiconductor element is performing a freewheeling operation, and to appropriately activate a circuit for suppressing self-turn-on of the power semiconductor element. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 is a main circuit structure diagram of a power conversion device according to Embodiment 1.

[0019] Figure 2 is a block diagram showing a structural example of a gate drive circuit according to a comparative example.

[0020] Figure 3 is a diagram for explaining the operation of a semiconductor element.

[0021] Figure 4 is a diagram for explaining the operation of a semiconductor element.

[0022] Figure 5 is showing Figure 4 the operation timing chart of the semiconductor element shown.

[0023] Figure 6 is a diagram for explaining self-turn-on of an N-side semiconductor element.

[0024] Figure 7 It is a block diagram showing a structural example of the gate drive circuit according to Embodiment 1.

[0025] Figure 8 It is a timing chart showing the operation of the semiconductor element.

[0026] Figure 9 It is a flowchart showing the operation of the gate drive circuit according to Embodiment 1.

[0027] Figure 10 It is a diagram showing a circuit structural example of the gate drive circuit according to Embodiment 1.

[0028] Figure 11 It is a block diagram showing a structural example of the gate drive circuit according to Embodiment 3.

[0029] Figure 12 It is a block diagram showing a structural example of the gate drive circuit according to Embodiment 4.

[0030] Figure 13 It is a diagram showing a circuit structural example of the gate drive circuit according to Embodiment 4.

[0031] Figure 14 It is a timing chart showing the operation of the semiconductor element.

[0032] Figure 15 It is a flowchart showing the operation of the gate drive circuit according to Embodiment 4. Detailed Embodiments

[0033] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the drawings. In addition, hereinafter, the same or corresponding parts in the drawings are denoted by the same reference numerals, and the description thereof will not be repeated in principle.

[0034] Embodiment 1.

[0035] <Structural Example of Power Conversion Device>

[0036] Figure 1 It is a main circuit structure diagram of the power conversion device according to Embodiment 1 of the present disclosure. The power conversion device 100 according to Embodiment 1 is a three-phase (U, V, W) structure inverter that performs bidirectional power conversion between a DC power supply 110 and a motor 120 as a load. The motor 120 is, for example, an induction motor or a synchronous motor. The power conversion device 100 is not limited to an inverter. For example, it may also be a non-insulated synchronous rectifier converter.

[0037] As Figure 1As shown, the power conversion device 100 includes three branches 12U, 12V, 12W and six gate drive circuits 10a to 10f. The three branches 12U, 12V, 12W are connected in parallel with each other between the DC positive bus bar PL and the DC negative bus bar NL. The DC positive bus bar PL is electrically connected to the positive terminal of the DC power supply 110. The DC negative bus bar NL is electrically connected to the negative terminal of the DC power supply 110. In this specification, "electrically connected" means a direct connection or a connection state that can transmit electric energy through connection via other elements.

[0038] Branch 12U has two power semiconductor elements (hereinafter also simply referred to as "semiconductor elements") 1a, 1b connected in series. Branch 12V has two semiconductor elements 1c, 1d connected in series. Branch 12W has two semiconductor elements 1e, 1f connected in series. That is, each of the branches 12U, 12V, 12W is composed of a bridge circuit. The connection nodes of the semiconductor elements 1a, 1b, the connection nodes of the semiconductor elements 1c, 1d, and the connection nodes of the semiconductor elements 1e, 1f are connected to the motor 120.

[0039] Hereinafter, when not particularly distinguishing each of the semiconductor elements 1a to 1f, they are sometimes collectively referred to as "semiconductor element 1". In addition, in the branches 12U, 12V, 12W, the semiconductor elements 1a, 1c, 1d whose high-potential-side main electrodes are connected to the DC positive bus bar PL and whose low-potential-side main electrodes are connected to the motor 120 are sometimes referred to as "P-side semiconductor elements". The semiconductor elements 1b, 1d, 1f whose high-potential-side main electrodes are connected to the motor 120 and whose low-potential-side main electrodes are connected to the DC negative bus bar NL are sometimes referred to as "N-side semiconductor elements".

[0040] In Figure 1 , as the semiconductor element 1, a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) is used, but any voltage-driven semiconductor element such as an IGBT (Insulated Gate Bipolar Transistor) can be used.

[0041] The semiconductor element 1 has a diode connected in anti-parallel. The diode is provided to allow a freewheeling current to flow when the corresponding semiconductor element 1 is turned off. When the semiconductor element 1 is a MOSFET, the freewheeling diode can also be constituted by a parasitic diode (body diode). When the semiconductor element 1 is an IGBT without an internal diode, the freewheeling diode is constituted by a diode connected in anti-parallel with the IGBT.

[0042] The control device 130 generates control signals for controlling the conduction and cutoff of the semiconductor elements 1a to 1f, namely gate command signals GSWa to GSWf. Specifically, the control device 130 generates a gate command signal GSW of H (logical high) level during the period when the semiconductor element 1 should conduct (turn on), and generates a gate command signal GSW of L (logical low) level during the period when the semiconductor element 1 should cut off (turn off). The gate command signal GSW of H level corresponds to a "conduction command", and the gate command signal GSW of L level corresponds to a "cutoff command".

[0043] The gate drive circuits 10a to 10f are provided corresponding to the semiconductor elements 1a to 1f respectively. The gate drive circuits 10a to 10f drive the corresponding semiconductor elements 1 respectively in accordance with the gate command signals GSWa to GSWf provided from the control device 130, thereby controlling the conduction and cutoff operations of the semiconductor elements 1a to 1f. Specifically, each of the gate drive circuits 10a to 10f is configured to apply a conduction bias voltage to the control electrode (gate) of the corresponding semiconductor element 1 in response to the gate command signal GSW (conduction command) of H level, and apply a cutoff bias voltage to the gate terminal of the corresponding semiconductor element 1 in response to the gate command signal GSW (cutoff command) of L level. Hereinafter, when not particularly distinguishing each of the gate drive circuits 10a to 10f, they are sometimes collectively referred to as the "gate drive circuit 10".

[0044] Thereby, the power conversion device 100 can perform an inversion operation of converting the DC power supplied from the DC power supply 110 into three-phase AC power and supplying it to the motor 120, and a rectification operation of converting the three-phase AC power supplied from the motor 120 into DC power and supplying it to the DC power supply 110.

[0045] <Structure of the gate drive circuit>

[0046] Next, the structure of the gate drive circuit 10 according to Embodiment 1 will be described.

[0047] (Structural example of the gate drive circuit according to the comparative example)

[0048] First, as a comparative example of the gate drive circuit according to Embodiment 1, the structure of a general gate drive circuit will be described.

[0049] Figure 2FIG. 0 is a block diagram showing a structural example of the gate drive circuit 10a according to the comparative example. The gate drive circuit 10a drives the P-side semiconductor element 1a. Since the gate drive circuit 10a that drives the P-side semiconductor element 1a and the gate drive circuit 10b that drives the N-side semiconductor element 1b have substantially the same structure, hereinafter, the structure of the gate drive circuit 10a will be representatively described.

[0050] As Figure 2 shown, the gate drive circuit 10a is configured to include an input terminal T1, output terminals T2 and T3, a control circuit 21, switches 25a and 25b, and a gate resistor 26.

[0051] The input terminal T1 is connected to a control device 130 (see Figure 1 ). The input terminal T1 transmits the gate command signal GSWa provided from the control device 130 to the control circuit 21. The output terminal T2 is connected to the gate, which is the control electrode of the semiconductor element 1a. The output terminal T3 is connected to the source, which is the low-potential-side main electrode of the semiconductor element 1a, and the reference node 13.

[0052] The control circuit 21 includes a conduction bias power supply Vp for generating a conduction bias voltage Vp applied to the gate of the semiconductor element 1a and a cut-off bias power supply Vn for generating a cut-off bias voltage Vn applied to the gate of the semiconductor element 1a. The positive terminal of the conduction bias power supply Vp is connected to the power supply node 12, and the negative terminal is connected to the reference node 13. The positive terminal of the cut-off bias power supply Vn is connected to the reference node 13, and the negative terminal is electrically connected to the output node 14.

[0053] The switch 25a is connected between the power supply node 12 and the output node 14. The switch 25b is connected between the output node 14 and the negative terminal of the cut-off bias power supply Vn. The gate resistor 26 is connected between the output node 14 and the output terminal T2.

[0054] The control circuit 21 selectively turns on and off the switches 25a and 25b according to the gate command signal GSWa. Specifically, when the gate command signal GSWa is at the H level, the control circuit 21 turns on the switch 25a and turns off the switch 25b. As a result, the output node 14 is connected to the power supply node 12, so that the conduction bias power supply Vp is connected between the output terminals T2 and T3. Consequently, a conduction bias voltage Vp is applied between the gate and the source of the semiconductor element 1a. The conduction bias voltage Vp is a voltage higher than the gate threshold voltage Vth of the semiconductor element 1.

[0055] On the other hand, when the gate command signal GSwa is at the L level, the control circuit 21 turns off the switch 25a and turns on the switch 25b. As a result, the output node 14 is connected to the negative terminal of the cut-off bias power supply Vn, so the cut-off bias power supply Vn is connected between the output terminals T2 and T3. Consequently, a cut-off bias voltage Vn is applied between the gate and source of the semiconductor element 1a. The cut-off bias voltage Vn is a voltage smaller than the gate threshold voltage Vth of the semiconductor element 1.

[0056] In the following description, the voltage applied between the gate and source of the semiconductor element 1a (hereinafter referred to as "gate voltage") is denoted as Vga, the voltage applied between the drain and source of the semiconductor element 1a (hereinafter referred to as "drain voltage") is denoted as Vdsa, and the current flowing through the drain of the semiconductor element 1a (hereinafter referred to as "drain current") is denoted as Ida. The gate voltage of the semiconductor element 1b is denoted as Vgb, the drain voltage of the semiconductor element 1b is denoted as Vdsb, and the drain current of the semiconductor element 1b is denoted as Idb.

[0057] (On - off operation of semiconductor elements 1a and 1b)

[0058] The semiconductor elements 1a and 1b constituting the branch 12U are turned on and off complementarily by the gate drive circuits 10a and 10b. In addition, during the on - off operation of the semiconductor elements 1a and 1b, a dead - time Td is set, which is the period when both the semiconductor elements 1a and 1b are in the cut - off state, in such a way that the on - periods of the P - side semiconductor element 1a and the N - side semiconductor element 1b do not overlap each other.

[0059] Figure 3 And Figure 4 is a diagram for explaining the operation of the semiconductor elements 1a and 1b. In the following description, the phase current flowing through the winding of the motor 120 is denoted as IL. The direction from the connection node of the semiconductor elements 1a and 1b to the winding is defined as the positive direction of the phase current IL, and the direction from the winding to the connection node of the semiconductor elements 1a and 1b is defined as the negative direction of the phase current IL.

[0060] In Figure 3 , the on - off operation of the semiconductor elements 1a and 1b when the flow direction of the phase current IL is in the positive direction is shown. During the on - period of the semiconductor element 1a, as shown in Figure 3 (A), the semiconductor element 1b is in the cut - off state. Therefore, the current flows from the drain of the semiconductor element 1a through the source to the winding.

[0061] During the dead - time Td, as shown in Figure 3As shown in (B), the semiconductor elements 1a and 1b are in the cut-off state. Since the winding functions to keep the current flowing continuously, the freewheeling current flows through the diode of the semiconductor element 1b to the winding.

[0062] Next, during the conduction period of the semiconductor element 1b, as Figure 3 shown in (C), the semiconductor element 1a is in the cut-off state. The semiconductor element 1b conducts, so that the freewheeling current flows from the source of the semiconductor element 1b to the drain through the winding.

[0063] During the period when the freewheeling current flows through the diode, losses are generated due to the forward voltage of the diode. Generally, this loss is greater than the loss generated due to the on-resistance of the MOSFET. Therefore, during the freewheeling period except for the dead time Td, the semiconductor element 1b is made to conduct, so that the freewheeling current flows through the semiconductor element 1b (see Figure 3 (C)).

[0064] In Figure 4 , the on-off operations of the semiconductor elements 1a and 1b are shown in the case where the flowing direction of the phase current IL is the negative direction. During the conduction period of the semiconductor element 1b, as Figure 4 shown in (A), the semiconductor element 1a is in the cut-off state. Therefore, the current flows from the winding to the source through the drain of the semiconductor element 1a.

[0065] During the dead time Td, as Figure 4 shown in (B), the semiconductor elements 1a and 1b are in the cut-off state. Since the winding functions to keep the current flowing continuously, the freewheeling current flows through the diode of the semiconductor element 1a to the winding.

[0066] Next, during the conduction period of the semiconductor element 1a, as Figure 4 shown in (C), the semiconductor element 1a is in the cut-off state. The semiconductor element 1a conducts, so that the freewheeling current flows from the winding to the drain through the source of the semiconductor element 1a. As described above, in order to reduce the loss, during the freewheeling period except for the dead time Td, the semiconductor element 1a is made to conduct, so that the freewheeling current flows through the semiconductor element 1a.

[0067] In this specification, the operation of flowing current positively from the drain to the source of the semiconductor element 1 is defined as the "SW (switch) operation". In contrast, the operation of flowing current (freewheeling current) from the diode of the semiconductor element 1 or the source of the semiconductor element 1 to the drain is defined as the "freewheeling operation".

[0068] In as Figure 3When the phase current IL flows in the positive direction as shown, the semiconductor element 1a on the P side performs the SW operation, and the semiconductor element 1b on the N side performs the freewheeling operation. In Figure 4 When the phase current IL flows in the negative direction as shown, the semiconductor element 1b on the N side performs the SW operation, and the semiconductor element 1a on the P side performs the freewheeling operation.

[0069] (Operation of the gate drive circuit according to the comparative example)

[0070] Next, the operation of the gate drive circuit according to the comparative example will be described.

[0071] Figure 5 is a timing chart showing Figure 4 the operations of the semiconductor elements 1a and 1b shown. In Figure 5 it, waveforms of the drain voltage Vds, drain current Id, gate voltage Vg, gate charge Qg, gate current Ig, and gate command signal GSW of the semiconductor elements 1a and 1b are shown. In each waveform, the solid line represents the waveform of the semiconductor element 1a on the P side, and the dashed line represents the waveform of the semiconductor element 1b on the N side.

[0072] In addition, the gate charge Qg is the charge accumulated in the Cgd (gate-source capacitance) and Cgs (gate-source capacitance) which are the parasitic capacitances of the gate of the semiconductor element 1. The gate charge Qg can be obtained by integrating the gate current Ig with respect to time. Regarding the gate current Ig, the direction of charging the gate parasitic capacitances Cgd and Cgs is defined as the positive direction, and the direction of discharging from the gate parasitic capacitances Cgd and Cgs is defined as the negative direction. In the following description, the gate charge Qg of the semiconductor element 1a is denoted as Qga, and the gate charge Qg of the semiconductor element 1b is denoted as Qgb.

[0073] As Figure 5 shown, at time t0, the gate command signal GSWa is at the L level, and the gate command signal GSWb becomes the H level. In response to the L-level gate command signal GSWa, the gate drive circuit 10a turns on the switch 15b and turns off the switch 15a, thereby applying the cut-off bias voltage Vn to the gate of the semiconductor element 1a. Therefore, the gate voltage Vga of the semiconductor element 1a becomes the cut-off bias voltage Vn, and the semiconductor element 1a becomes the cut-off state. Therefore, the drain current Ida = 0, and the drain voltage Vdsa = VDC. VDC corresponds to the voltage between the terminals of the DC power supply 110. Since the gate parasitic capacitances Cgd and Cgs of the semiconductor element 1a are discharged, the gate charge Qga becomes 0.

[0074] On the other hand, in response to the gate command signal GSWb at the H level, the gate drive circuit 10b turns on the switch 15a and turns off the switch 15b, thereby applying the conduction bias voltage Vp to the gate of the N-side semiconductor element 1b. As a result, the gate voltage Vgb of the semiconductor element 1b becomes the conduction bias voltage Vp, and the semiconductor element 1b becomes conductive.

[0075] As Figure 4 (A) shows, a forward current flows between the drain and source of the semiconductor element 1b, and the semiconductor element 1b performs the SW operation. The drain current Idb is equal to the magnitude of the phase current IL, and the drain voltage Vdsa = 0. The gate parasitic capacitances Cgs and Cgd of the semiconductor element 1b are charged by the gate current Igb, so the gate charge Qgb becomes Qh.

[0076] At time t1, when the gate command signal GSWb transitions from the H level to the L level, the semiconductor element 1b becomes non-conductive. Specifically, in response to the gate command signal GSWb at the L level, the gate drive circuit 10b turns off the switch 15a and turns on the switch 15b, thereby switching the voltage applied to the gate of the semiconductor element 1b from the conduction bias voltage Vp to the cut-off bias voltage Vn.

[0077] As a result, the charges stored in the gate parasitic capacitances Cgs and Cgd of the semiconductor element 1b are discharged via the gate resistor 26 and the switch 25b, so the gate charge Qgb gradually decreases from Qh. Therefore, the gate voltage Vgb gradually decreases from the conduction bias voltage Vp toward the cut-off bias voltage Vn.

[0078] When the gate voltage Vgb is less than the gate threshold voltage Vth, the semiconductor element 1b starts to turn off. When the semiconductor element 1b turns off, the drain current Idb starts to decrease, and the drain voltage Vdsb starts to increase. During the period from time t1 until the discharge of the gate parasitic capacitances Cgs and Cgd is completed and the gate charge Qgb becomes 0, a gate current Igb (discharge current) flows.

[0079] In response to the semiconductor element 1b becoming non-conductive, as Figure 4As shown in (B), a freewheeling current flows through the diode of the semiconductor element 1a. In response to the start of the freewheeling current flowing through the diode, the drain voltage Vdsa of the semiconductor element 1a starts to decrease, and the drain current Ida starts to increase. When the change in voltage with respect to time during the transition period in which the drain voltage Vdsa changes rapidly is set to dv / dt, a displacement current (Cgd×dv / dt) flows through the gate-drain capacitance Cgd of the semiconductor element 1a during the period when dv / dt occurs. This displacement current flows through the gate resistor 26, causing the gate voltage Vga to decrease. In addition, since the gate parasitic capacitances Cgd and Cgs are charged by the displacement current, the gate charge Qga increases from 0 to Qa. Qa is greater than 0 and less than Qh.

[0080] The period from time t1 to t2 corresponds to the dead time Td. During the dead time Td, the freewheeling current continues to flow through the diode of the semiconductor element 1a.

[0081] At time t2, when the gate command signal GSWa transitions from the L level to the H level, the semiconductor element 1a is turned on. Specifically, in response to the H-level gate command signal GSWa, the gate drive circuit 10a turns on the switch 15a and turns off the switch 15b, thereby switching the voltage applied to the gate of the semiconductor element 1a from the cut-off bias voltage Vn to the cut-off bias voltage Vp.

[0082] As a result, the gate current Iga flows from the power supply node 12 through the gate resistor 26 to the gate of the semiconductor element 1a, and the gate parasitic capacitances Cgs and Cgd are charged. The gate charge Qga gradually increases from Qa to reach Qh. After the charging is completed, no gate current Iga flows. Thereafter, since the conduction bias voltage Vp is continuously applied to the gate of the semiconductor element 1a, the semiconductor element 1a is maintained in the on state. As Figure 4 As shown in (C), a freewheeling current flows between the drain and source of the semiconductor element 1a, and the semiconductor element 1a performs a freewheeling operation.

[0083] At time t3, when the gate command signal GSWa transitions from the H level to the L level, the semiconductor element 1a is turned off. Specifically, in response to the L-level gate command signal GSWa, the gate drive circuit 10a turns off the switch 15a and turns on the switch 15b, switching the voltage applied to the gate of the semiconductor element 1a from the conduction bias voltage Vp to the cut-off bias voltage Vn.

[0084] Accordingly, the charges accumulated in the gate parasitic capacitances Cgs and Cgd of the semiconductor element 1a are discharged via the gate resistor 26 and the switch 25b. The gate charge amount Qga gradually decreases from Qh, and the gate voltage Vga gradually decreases from the conduction bias voltage Vp toward the cut-off bias voltage Vn. When the gate voltage Vga is less than the gate threshold voltage Vth, the semiconductor element 1a starts to cut off.

[0085] When the semiconductor element 1a becomes cut off, as Figure 4 (B) shows, a freewheeling current starts to flow in the diode of the semiconductor element 1a. Accordingly, the drain voltage Vdsa and the drain current Ida are maintained at constant values without change even when the semiconductor element 1a is turned off.

[0086] The period from time t3 to t4 corresponds to the dead time Td. During the dead time Td, since the diode of the semiconductor element 1a performs a freewheeling operation, the gate charge amount Qga does not decrease to 0 and Qa is maintained. Qa corresponds to the charge amount accumulated during the dead time Td (the period from time t1 to t2) after the semiconductor element 1b is turned off. That is, it can be seen that the gate charge amount Qgb of the semiconductor element 1b during the SW operation decreases to 0 after being turned off, while the gate charge amount Qga of the semiconductor element 1a during the freewheeling operation does not decrease to 0 after being turned off.

[0087] At time t4, when the gate command signal GSWb transitions from the L level to the H level, the semiconductor element 1b is turned on. Specifically, in response to the gate command signal GSWb at the H level, the gate drive circuit 10b turns on the switch 15a and turns off the switch 15b, thereby switching the voltage applied to the gate of the semiconductor element 1b from the cut-off bias voltage Vn to the conduction bias voltage Vp.

[0088] Accordingly, the gate current Igb flows from the power supply node 12 to the gate of the semiconductor element 1b via the gate resistor 26, and the gate parasitic capacitances Cgs and Cgd are charged. The gate charge amount Qgb gradually increases from 0 and reaches Qh. After the charging is completed, no gate current Igb flows. Thereafter, since the conduction bias voltage Vp is continuously applied to the gate of the semiconductor element 1b, the semiconductor element 1b is maintained in the conduction state. As Figure 4 (A) shows, a forward current flows between the drain and source of the semiconductor element 1b, and the semiconductor element 1b performs the SW operation.

[0089] In response to the turn-on of semiconductor element 1b, a drain current Idb starts to flow through semiconductor element 1b. In response to the start of the flow of drain current Idb, the drain voltage Vdsb of semiconductor element 1b starts to decrease, and the drain current Idb starts to increase. As a result, the freewheeling current flowing through the diode of semiconductor element 1a decreases, and the drain voltage Vdsa starts to increase. A reverse voltage is applied to the diode of semiconductor element 1a, so after an instantaneous recovery current flows through the diode, the diode turns off.

[0090] Via the recovery operation of the diode of semiconductor element 1a, the drain voltage Vdsa changes sharply. During the period when the change dv / dt of the drain voltage Vdsa with respect to time occurs, a displacement current (Cgd×dv / dt) flows through the gate-drain capacitance Cgd of semiconductor element 1a. This displacement current flows through the gate resistor 26, causing the gate voltage Vga to rise. In addition, the gate parasitic capacitances Cgd and Cgs are discharged by the displacement current, so the gate charge Qga decreases from Qa to 0.

[0091] Above, the operation waveforms when semiconductor element 1b performs the SW operation and semiconductor element 1a performs the freewheeling operation in the case where the phase current IL < 0 have been described. In the case where the phase current IL > 0, semiconductor element 1a performs the SW operation and semiconductor element 1b performs the freewheeling operation, but their operation waveforms can be considered Figure 5 similarly.

[0092] (Turn-on phenomenon)

[0093] As Figure 5 shown, when the semiconductor element 1b performing the SW operation is turned on ( Figure 5 at time t4), a sharp voltage change dv / dt is applied between the drain and source of the semiconductor element 1a performing the freewheeling operation. As a result, a displacement current (Cgd·dv / dt) flows through the gate resistor 26, so the gate voltage Vga instantaneously increases. When the gate voltage Vga exceeds the gate threshold voltage Vth, the turned-off semiconductor element 1a may be erroneously turned on. Such a phenomenon where the semiconductor element 1a is randomly turned on is called "turn-on".

[0094] In addition, when the semiconductor element 1a performing the freewheeling operation is turned on ( Figure 5 at time t2), the drain voltage Vdsb of the semiconductor element 1b performing the SW operation does not change, so the semiconductor element 1b does not experience turn-on.

[0095] In branch 12U formed by a bridge circuit, turn-on may also occur when semiconductor element 1a performs the SW operation and semiconductor element 1b performs the freewheeling operation. Figure 6 is a diagram for explaining the turn-on of semiconductor element 1b.

[0096] As Figure 3 shown in (B), when the semiconductor elements 1a and 1b are in the off state, a freewheeling current flows through the diode of the semiconductor element 1b. When the semiconductor element 1a is turned on in this state, due to the recovery operation of the diode of the semiconductor element 1b, a sharp voltage change dv / dt occurs between the drain and source of the semiconductor element 1b. During this period, the drain voltage Vdsb linearly rises from 0 to VDC. During the occurrence of dv / dt, a displacement current i (= Cgd × dv / dt) flows through the gate parasitic capacitances Cgd and Cgs of the semiconductor element 1a, and thus the gate-source capacitance Cgs is instantaneously charged. As a result, the gate voltage Vga rises and the semiconductor element 1b turns on by itself.

[0097] When the semiconductor element 1b turns on by itself, since the semiconductor elements 1a and 1b conduct simultaneously, an excessive short-circuit current instantaneously flows from the DC positive bus bar PL to the DC negative bus bar NL. Due to the loss generated by this short-circuit current, there is a possibility of damaging the semiconductor elements 1a and 1b.

[0098] (Structural example of the gate drive circuit according to Embodiment 1)

[0099] As described above, when the semiconductor element 1 performing the SW operation is turned on, the semiconductor element 1 performing the freewheeling operation may turn on by itself. Therefore, if the rise of the gate voltage Vg of the semiconductor element 1 performing the freewheeling operation can be suppressed in synchronization with the timing of turning on the semiconductor element 1 performing the SW operation, the self-turn-on of this semiconductor element 1 can be prevented.

[0100] Here, when focusing on Figure 5 the operation waveforms of the semiconductor elements 1a and 1b shown, it can be seen that the waveforms of the gate current Ig and the gate charge Qg are different in the semiconductor element 1b performing the SW operation and the semiconductor element 1b performing the freewheeling operation.

[0101] Specifically, in the semiconductor element 1b performing the SW operation, a gate current Igb temporarily flows when the semiconductor element 1b is turned on and off. On the other hand, no gate current Iga flows when the semiconductor element 1a is turned on and off. In contrast, in the semiconductor element 1a performing the freewheeling operation, a gate current Iga temporarily flows not only when the semiconductor element 1a is turned on and off, but also when the semiconductor element 1b is turned on and off.

[0102] In addition, in the semiconductor element 1b performing the SW operation, the gate charge Qgb decreases to 0 when turned off. In contrast, in the semiconductor element 1a performing the freewheeling operation, the gate charge Qga becomes Qa and does not decrease to 0 when turned off. Further, the gate charge Qga of the semiconductor element 1a decreases to 0 according to the turn-on of the semiconductor element 1b.

[0103] Therefore, it is possible to determine whether the semiconductor element 1 is performing the SW operation or the freewheeling operation based on the waveform of the gate current Ig or the gate charge Qg. Thus, if it is possible to determine that the semiconductor element 1 is performing the freewheeling operation, it is possible to suppress the instantaneous rise of the gate voltage Vg at the timing when the other semiconductor element 1 is turned on, that is, at the timing when the diode of the semiconductor element 1 performs the recovery operation. In addition, it is possible to know the timing when the diode of the semiconductor element 1 performs the recovery operation based on the timing when the gate charge Qg decreases from Qa to 0.

[0104] The gate drive circuit 10 according to Embodiment 1 is configured to determine whether the diode of the corresponding semiconductor element 1 is performing the freewheeling operation based on the waveform of the gate charge Qg of the corresponding semiconductor element 1. Further, when it is determined that the diode of the corresponding semiconductor element 1 is performing the freewheeling operation, the gate drive circuit 10 is configured to: detect the timing when the diode of the semiconductor element 1 performs the recovery operation based on the waveform of the gate charge Qg, and temporarily reduce the cut-off bias voltage Vn applied to the gate of the semiconductor element 1 in accordance with the detected timing.

[0105] Hereinafter, the detailed structure of the gate drive circuit 10 according to Embodiment 1 will be described. In addition, since the gate drive circuits 10a to 10f have substantially the same structure, the structure of the gate drive circuit 10a will be representatively described below.

[0106] Figure 7 is a block diagram showing a structural example of the gate drive circuit 10a according to Embodiment 1. As Figure 7 shown, the gate drive circuit 10a includes an input terminal T1, output terminals T2 and T3, a control circuit 11, a switch 15, a cut-off bias switching circuit 16, a gate charge detection circuit 18, and a freewheeling operation determination circuit 19.

[0107] The input terminal T1 is connected to the control device 130 (see Figure 1 ). The input terminal T1 transmits the gate command signal GSWa provided from the control device 130 to the control circuit 11. The output terminal T2 is connected to the gate serving as the control electrode of the semiconductor element 1a. The output terminal T3 is connected to the source serving as the low-potential side main electrode of the semiconductor element 1a and the reference node 13.

[0108] The control circuit 11 has a conduction bias power supply Vp for generating a conduction bias voltage Vp applied to the gate of the semiconductor element 1a, a cut-off bias power supply Vnh for generating a cut-off bias voltage Vnh applied to the gate of the semiconductor element 1a, and a cut-off bias power supply Vnl for generating a cut-off bias voltage Vnl. The control circuit 11 is different from Figure 2 the control circuit 21 shown in that it has two types of cut-off bias power supplies Vnh and Vnl.

[0109] The conduction bias voltage Vp is a voltage higher than the gate threshold voltage Vth of the semiconductor element 1. The cut-off bias voltages Vnh and Vnl are voltages smaller than the gate threshold voltage Vth of the semiconductor element 1. The cut-off bias voltage Vnh is higher than the cut-off bias voltage Vnl. When the gate threshold voltage Vth of a general normally-off MOSFET and IGBT is about 2 to 7V, the conduction bias voltage Vp can be set to 15 to 20V, for example. The cut-off bias voltage Vnh can be set to 0 to -10V, for example. The cut-off bias voltage Vnl can be set to -2 to -15V, for example. In addition, the magnitude (absolute value) of Vnh has a relationship of being definitely smaller than that of Vnl. The cut-off bias voltage Vnh corresponds to an embodiment of the "first value", and the cut-off bias voltage Vnl corresponds to an embodiment of the "second value".

[0110] The positive terminal of the conduction bias power supply Vp is connected to the power supply node 12, and the negative terminal is connected to the reference node 13. The positive terminal of the cut-off bias power supply Vnh is connected to the reference node 13, and the negative terminal is electrically connected to the output node 14. The positive terminal of the cut-off bias power supply Vnl is connected to the reference node 13, and the negative terminal is connected to the output node 14.

[0111] The switch 15 is connected between the power supply node 12 and the output node 14.

[0112] The cut-off bias switching circuit 16 has a switch 16h and a switch 16l. The switch 16h is connected between the output node 14 and the negative terminal of the cut-off bias power supply Vnh. The switch 16l is connected between the output node 14 and the negative terminal of the cut-off bias power supply Vnl. A gate resistor 17 is connected between the output node 14 and the output terminal T2.

[0113] The gate charge detection circuit 18 detects the gate charge Qg by time-integrating the gate current Ig flowing through the gate resistor 17. In Figure 7In the example, the gate charge detection circuit 18 is configured to obtain the gate current Ig based on the voltage across the terminals of the gate resistor 17, and perform time integration on it to detect the gate charge Qg. There are various methods for integrating the gate current Ig, such as the method of using an operational amplifier for integration, the method of using a CR filter for integration, etc. The method for detecting the gate current Ig can be any method. The gate charge detection circuit 18 outputs the detected value of the gate charge Qga to the freewheeling operation determination circuit 19.

[0114] The freewheeling operation determination circuit 19 determines whether the diode of the semiconductor element 1a is performing a freewheeling operation based on the detected value of the gate charge Qg. Specifically, the freewheeling operation determination circuit 19 has a predetermined threshold Qb, and compares the threshold Qb with the detected value of the gate charge Qg to determine whether the diode of the semiconductor element 1a is performing a freewheeling operation.

[0115] In response to the gate command signal GSWa, the control circuit 11 selectively turns on and off the switch 15 and the cutoff bias switching circuit 16. Specifically, when the gate command signal GSWa is at the H level, the control circuit 11 turns on the switch 15 and turns off the cutoff bias switching circuit 16. As a result, the output node 14 is connected to the power supply node 12, so a conduction bias power supply Vp is connected between the output terminals T2 and T3. As a result, a conduction bias voltage Vp is applied between the gate and source of the semiconductor element 1a.

[0116] On the other hand, when the gate command signal GSWa is at the L level, the control circuit 11 turns off the switch 15 and turns on the cutoff bias switching circuit 16. The cutoff bias switching circuit 16 selectively turns on the switches 16h and 16l according to the determination result provided by the freewheeling operation determination circuit 19. When the switch 16h is turned on, the output node 14 is connected to the negative terminal of the cutoff bias power supply Vnh, so the cutoff bias power supply Vnh is connected between the output terminals T2 and T3. As a result, a cutoff bias voltage Vnh is applied between the gate and source of the semiconductor element 1a. When the switch 16l is turned on, the output node 14 is connected to the negative terminal of the cutoff bias power supply Vnl, so the cutoff bias power supply Vnl is connected between the output terminals T2 and T3. As a result, a cutoff bias voltage Vnl is applied between the gate and source of the semiconductor element 1a.

[0117] That is, the cutoff bias switching circuit 16 is configured to be able to switch the gate voltage Vga of the semiconductor element 1a between the cutoff bias voltage Vnh and the cutoff bias voltage Vnl according to the determination result of the freewheeling operation determination circuit 19.

[0118] (Operation of the gate drive circuit according to Embodiment 1)

[0119] Next, the operation of the gate drive circuit 10a according to Embodiment 1 will be described.

[0120] Figure 8 It is a timing chart showing the operations of the semiconductor elements 1a and 1b. In Figure 8 it, waveforms of the drain voltage Vds, drain current Id, gate voltage Vg, gate charge Qg, gate current Ig, and gate command signal GSW of the semiconductor elements 1a and 1b are shown. In each waveform, the solid line represents the waveform of the P-side semiconductor element 1a, and the dashed line represents the waveform of the N-side semiconductor element 1b.

[0121] Figure 8 The shown timing chart is compared with the timing chart shown in Figure 5 The waveform of the gate voltage Vga of the semiconductor element 1b is different. Since the other waveforms are the same as those shown in Figure 5 the detailed description thereof is omitted.

[0122] As Figure 8 shown, at time t0, the gate command signal GSWa is at the L level, and the gate command signal GSWb becomes the H level. In the gate drive circuit 10a, the control circuit 11 responds to the L-level gate command signal GSWa, turns off the switch 15, and turns on the cut-off bias switching circuit 16. The gate charge Qga of the semiconductor element 1a becomes 0. The freewheeling operation determination circuit 19 compares the gate charge Qga with the threshold value Qb. The threshold value Qb is set to a value greater than 0 and equal to or less than the gate charge Qa during the dead time Td. Since Qga < Qb, the freewheeling operation determination circuit 19 determines that the semiconductor element 1a is not in the freewheeling operation.

[0123] The cut-off bias switching circuit 16 responds to the determination that the semiconductor element 1a is not in the freewheeling operation, turns on the switch 16h, and turns off the switch 16l, thereby applying the cut-off bias voltage Vnh to the gate of the semiconductor element 1a. The gate voltage Vga of the semiconductor element 1a becomes the cut-off bias voltage Vnh, and the semiconductor element 1a becomes the cut-off state. Therefore, the drain current Ida = 0, and the drain voltage Vdsa = VDC. VDC corresponds to the voltage between the terminals of the DC power supply 110. The gate parasitic capacitances Cgd and Cgs of the semiconductor element 1b are discharged, so the gate charge Qga becomes 0.

[0124] When the gate command signal GSWb transitions from the H level to the L level at time t1, the semiconductor element 1b turns off. In the gate drive circuit 10b, in response to the gate command signal GSWb at the L level, the control circuit 11 turns off the switch 15 and turns on the cut-off bias switching circuit 16. The cut-off bias switching circuit 16 first turns on the switch 16h and turns off the switch 16l, thereby applying the cut-off bias voltage Vnh to the gate of the semiconductor element 1b. The gate voltage Vgb of the semiconductor element 1b becomes the cut-off bias voltage Vnh, so the charges stored in the gate parasitic capacitors Cgs and Cgd of the semiconductor element 1b are discharged, and thus the gate charge amount Qgb gradually decreases from Qh. In response to the completion of the discharge of the gate parasitic capacitors Cgs and Cgd, the gate charge amount Qgb becomes 0.

[0125] The freewheeling operation determination circuit 19 compares the gate charge amount Qgb with the threshold value Qb. Since Qgb < Qb, the freewheeling operation determination circuit 19 determines that the diode of the semiconductor element 1b is not in the freewheeling operation. In response to determining that the diode of the semiconductor element 1b is not in the freewheeling operation, the cut-off bias switching circuit 16 maintains the switch 16h in the on state, thereby continuously applying the cut-off bias voltage Vnh to the gate of the semiconductor element 1b.

[0126] In response to the cut-off of the semiconductor element 1b, a freewheeling current flows through the diode of the semiconductor element 1a. During the transition period in which the drain voltage Vdsa changes sharply in response to the start of the freewheeling current flowing through the diode, a displacement current (Cgd × dv / dt) flows through the gate-drain capacitance Cgd of the semiconductor element 1a. This displacement current flows through the gate resistor 26, thereby reducing the gate voltage Vga. In addition, the gate parasitic capacitors Cgd and Cgs are charged by the displacement current, so the gate charge amount Qga increases from 0 to Qa.

[0127] The period from time t1 to t2 corresponds to the dead time Td. During the dead time Td, the freewheeling current continuously flows through the diode of the semiconductor element 1a.

[0128] When the gate command signal GSWa transitions from the L level to the H level at time t2, the semiconductor element 1a turns on. Specifically, in response to the gate command signal GSWa at the H level, the gate drive circuit 10a turns on the switch 15 and turns off the cutoff bias switching circuit 16, thereby switching the voltage applied to the gate of the semiconductor element 1a from the cutoff bias voltage Vnh to the cutoff bias voltage Vp. The gate current Iga flows from the power supply node 12 through the gate resistor 17 to the gate of the semiconductor element 1a. The gate parasitic capacitances Cgs and Cgd are charged, so the gate charge Qga gradually increases from Qa to reach Qh. A freewheeling current flows between the drain and source of the semiconductor element 1a, and the semiconductor element 1a is performing a freewheeling operation.

[0129] When the gate command signal GSWa transitions from the H level to the L level at time t3, the semiconductor element 1a turns off. In the gate drive circuit 10a, the control circuit 11 turns off the switch 15 and turns on the cutoff bias switching circuit 16 in response to the gate command signal GSWa at the L level. The cutoff bias switching circuit 16 first turns on the switch 16h and turns off the switch 16l, thereby applying the cutoff bias voltage Vnh to the gate of the semiconductor element 1a. The gate voltage Vga of the semiconductor element 1a becomes the cutoff bias voltage Vnh, so the charges stored in the gate parasitic capacitances Cgs and Cgd of the semiconductor element 1a are discharged, and the gate charge Qga gradually decreases.

[0130] The gate voltage Vga gradually decreases from the conduction bias voltage Vp toward the cutoff bias voltage Vn. When the gate voltage Vga is less than the gate threshold voltage Vth, the semiconductor element 1a starts to turn off. When the semiconductor element 1a turns off, a freewheeling current starts to flow through the diode of the semiconductor element 1a. Therefore, the drain voltage Vdsa and the drain current Ida are maintained at a constant value without change even after the semiconductor element 1a turns off.

[0131] Here, as described in Figure 5 , during the dead time Td from time t3 to t4, the diode of the semiconductor element 1a performs a freewheeling operation, so the gate charge Qga does not decrease to 0 and Qa is maintained. Qa corresponds to the charge accumulated during the dead time Td (the period from time t1 to t2) after the semiconductor element 1b turns off.

[0132] The freewheeling operation determination circuit 19 compares the gate charge Qga in the dead time Td with the threshold value Qb. Since Qga (= Qa) > Qb, the freewheeling operation determination circuit 19 determines that the diode of the semiconductor element 1a is in the freewheeling operation. In response to the determination that the diode of the semiconductor element 1a is in the freewheeling operation, the cut-off bias switching circuit 16 turns off the switch 16h and turns on the switch 16l. As a result, the gate voltage Vga of the semiconductor element 1a is switched from the cut-off bias voltage Vnh to the cut-off bias voltage Vnl.

[0133] In addition, the timing for switching the gate voltage Vga from the cut-off bias voltage Vnh to the cut-off bias voltage Vnl is preferably set to the timing after the flow of the gate current Iga ends in response to the turn-off of the semiconductor element 1a (time t3). This timing can be obtained based on the time constants of the gate parasitic capacitances Cgd and Cgs of the semiconductor element 1a and the gate resistor 17. Alternatively, the timing for switching the gate voltage Vga can be obtained based on the fall time (FallTime) Tf, etc. of the semiconductor element 1a recorded in a data sheet or the like. The fall time Tf represents the time it takes for the semiconductor element 1a to turn off and the drain voltage Vdsa to rise from 10% of the maximum voltage Vdc to 90%.

[0134] When the gate command signal GSWb transitions from the L level to the H level at time t4, the semiconductor element 1b turns on. Specifically, in response to the gate command signal GSWb at the H level, the gate drive circuit 10b turns on the switch 15 and turns off the cut-off bias switching circuit 16, thereby switching the voltage applied to the gate of the semiconductor element 1b from the cut-off bias voltage Vnh to the cut-off bias voltage Vp.

[0135] When the drain current Idb starts to flow through the semiconductor element 1b in response to the turn-on of the semiconductor element 1b, the drain voltage Vdsa of the semiconductor element 1a changes sharply via the recovery operation of the diode of the semiconductor element 1a. During the period when there is a change dv / dt of the drain voltage Vdsa with respect to time, a displacement current (Cgd × dv / dt) flows through the gate-drain capacitance Cgd of the semiconductor element 1a. This displacement current flows through the gate resistor 17, causing the gate voltage Vga to rise and the gate charge Qga to decrease from Qa to 0.

[0136] However, during the dead time Td from time t3 to t4, the gate voltage Vga of the semiconductor element 1a is switched from the cut-off bias voltage Vnh to the cut-off bias voltage Vnl. Therefore, even if the gate voltage Vga instantaneously rises after time t4, the gate voltage Vga does not exceed the gate threshold voltage Vth. Thus, self-turn-on of the semiconductor element 1a can be prevented.

[0137] In the gate drive circuit 10a, the freewheeling operation determination circuit 19 compares the gate charge amount Qga with the threshold value Qb. Since Qga (=0) < Qb, the freewheeling operation determination circuit 19 determines that the semiconductor element 1a has completed the freewheeling operation. In response to the determination that the semiconductor element 1a has completed the freewheeling operation, the cut-off bias switching circuit 16 turns off the switch 16l and turns on the switch 16h. As a result, the gate voltage Vga of the semiconductor element 1a is switched from the cut-off bias voltage Vnl to the cut-off bias voltage Vnh.

[0138] That is, the gate drive circuit 10a temporarily reduces the gate voltage Vga of the semiconductor element 1a from the cut-off bias voltage Vnh to the cut-off bias voltage Vnl in synchronization with the timing of the recovery operation of the diode of the semiconductor element 1a. Thereby, it is possible to suppress the gate voltage Vga from instantaneously rising and exceeding the gate threshold voltage Vth in response to the recovery operation of the diode.

[0139] Here, in the oxide film of the gate of the semiconductor element 1, there is a lifetime corresponding to the magnitude of the voltage applied between the gate and the source (i.e., the gate voltage Vg). In particular, when the magnitude of the gate voltage Vg exceeds the maximum voltage applied between the gate and the source, there is a possibility that the oxide film is damaged or undergoes aging changes due to an increase in ions inside the oxide film. In order to suppress the progression of deterioration of the oxide film, it is necessary to reduce the magnitude of the gate voltage Vg to relax the electric field applied to the oxide film or shorten the application time of the gate voltage Vg.

[0140] Therefore, when the cut-off bias voltage is fixed at Vnl (for example, -10 to -20 V), it is possible to prevent self-turn-on of the semiconductor element 1a. On the other hand, deterioration of the oxide film of the gate of the semiconductor element 1a may progress. The gate drive circuit 10a according to Embodiment 1 makes the cut-off bias voltage temporarily become Vnl only at the timing of the recovery operation of the diode of the semiconductor element 1a, and makes the cut-off bias voltage become Vnh (for example, 0 to -5 V) having a magnitude smaller than Vnl otherwise. Therefore, it is possible to reduce the magnitude of the gate voltage Vga during the period when the diode of the semiconductor element 1a does not perform the recovery operation. Therefore, it is possible to prevent self-turn-on of the semiconductor element 1a and suppress the progression of deterioration of the oxide film of the gate.

[0141] Above, the operation waveforms when the semiconductor element 1b performs the SW operation and the semiconductor element 1a performs the freewheeling operation in the case where the phase current IL < 0 have been described. In the case where the phase current IL > 0, the semiconductor element 1a performs the SW operation and the semiconductor element 1b performs the freewheeling operation, but their operation waveforms can be considered Figure 8 similarly.

[0142] Figure 9 is a flowchart showing the operation of the gate drive circuit 10 according to Embodiment 1. InFigure 9 In the figure, the operation of the gate drive circuit 10 when the corresponding semiconductor element 1 is turned off by the gate command signal GSW (cut-off command) of L level from the control device 130 is shown. The determination of whether the semiconductor element 1 is performing a freewheeling operation when receiving the gate command signal GSW (conducting command) of H level does not affect the switching of the cut-off bias voltage, so the description is omitted.

[0143] When the semiconductor element 1 is in the conducting state, a conducting bias voltage Vp is applied to the gate of the semiconductor element 1. In this state, when the gate drive circuit 10 receives the gate command signal GSW (cut-off command) of L level from the control device 130 (in step S01), the control circuit 11 turns off the switch 15 and turns on the cut-off bias switching circuit 16. The cut-off bias switching circuit 16 turns on the switch 16h and turns off the switch 16l (step S02). As a result, the cut-off bias voltage Vnh is applied to the gate of the semiconductor element 1. The gate voltage Vg of the semiconductor element 1 becomes the cut-off bias voltage Vnh, so that the charges stored in the gate parasitic capacitances Cgs and Cgd of the semiconductor element 1 are discharged, and the gate charge amount Qg gradually decreases from Qh. The gate voltage Vga gradually decreases toward the cut-off bias voltage Vnh, and when it is less than the gate threshold voltage Vth, the semiconductor element 1 starts to turn off.

[0144] The freewheeling operation determination circuit 19 compares the gate charge amount Qg detected by the gate charge amount detection circuit 18 with the threshold value Qb (step S03). When the gate charge amount Qg is less than the threshold value Qb (when the determination in S03 is "no"), the freewheeling operation determination circuit 19 determines that the diode of the semiconductor element 1 is not in the freewheeling operation (step S10).

[0145] On the other hand, when the gate charge amount Qg is equal to or greater than the threshold value Qb (when the determination in S03 is "yes"), the freewheeling operation determination circuit 19 then determines whether the current timing is within the dead time Td after the turn-off period of the semiconductor element 1 (step S04). The turn-off period can be obtained based on the time constant of the gate parasitic capacitances Cgd and Cgs of the semiconductor element 1 and the gate resistance 17. Alternatively, it can be obtained based on the fall time Tf of the semiconductor element 1a described in a data sheet or the like.

[0146] When the current timing is within the turn-off period of the semiconductor element 1, the determination in S04 is "no". In this case, the freewheeling operation determination circuit 19 determines that the diode of the semiconductor element 1 is not in the freewheeling operation (step S10).

[0147] In contrast, when the current timing is within the dead time Td after the turn-off period of the semiconductor element 1 (when the determination in S04 is "Yes"), the freewheeling operation determination circuit 19 determines that the diode of the semiconductor element 1 is in the freewheeling operation (step S05). In this case, the cut-off bias switching circuit 16 turns off the switch 16h and turns on the switch 16l (step S06). Thereby, the gate voltage Vg of the semiconductor element 1 is switched from the cut-off bias voltage Vnh to the cut-off bias voltage Vnl.

[0148] During the dead time Td, when another semiconductor element 1 connected in series with the semiconductor element 1 is turned on, the diode of the semiconductor element 1 performs a recovery operation, so the drain voltage Vds of the semiconductor element 1 changes sharply. During the period when the change dv / dt of the drain voltage Vds with respect to time occurs, a displacement current (Cgd×dv / dt) flows through the gate-drain capacitance Cgd of the semiconductor element 1. Therefore, the gate voltage Vg rises, and the gate charge Qg decreases from Qa to 0.

[0149] The freewheeling operation determination circuit 19 compares the gate charge Qb detected by the gate charge detection circuit 18 with the threshold value Qb (step S07). When the gate charge Qg is equal to or greater than the threshold value Qb (when the determination in S07 is "No"), the freewheeling operation determination circuit 19 determines that the diode of the semiconductor element 1 is in the freewheeling operation (step S05). Therefore, the cut-off bias switching circuit 16 keeps the switch 16l turned on (step S06), thereby maintaining the gate voltage Vg of the semiconductor element 1 at the cut-off bias voltage Vnl.

[0150] On the other hand, when the gate charge Qg is less than the threshold value Qb (when the determination in S07 is "Yes"), the freewheeling operation determination circuit 19 determines that the freewheeling operation of the semiconductor element 1 has ended (step S08). In response to the determination that the freewheeling operation of the semiconductor element 1 has ended, the cut-off bias switching circuit 16 turns off the switch 16l and turns on the switch 16h (step S09). Thereby, the gate voltage Vg of the semiconductor element 1 is switched from the cut-off bias voltage Vnl to the cut-off bias voltage Vnh.

[0151] In addition, in Figure 9In the flowchart, the threshold Qb is used for both the process of determining whether the semiconductor element 1 is in the freewheeling operation (step S03) and the process of determining whether the semiconductor element 1 has completed the freewheeling operation (step S07). However, it is also possible to adopt a structure in which different thresholds are used for these two processes according to the characteristics of the semiconductor element 1. In order to reliably prevent self-turn-on of the semiconductor element 1, it is preferable to determine by fully studying the timing of the recovery operation of the diode of the semiconductor element 1 and the timing of switching from the cut-off bias voltage Vnl to the cut-off bias voltage Vnh. Therefore, when determining the threshold for each process in consideration of the characteristics of the semiconductor element 1, the effect of preventing self-turn-on is better.

[0152] <Effect of Embodiment 1>

[0153] As described above, the gate drive circuit 10 according to Embodiment 1 is configured to determine whether the diode of the corresponding semiconductor element 1 is in the freewheeling operation based on the detected value of the gate charge Qg of the semiconductor element 1. Therefore, there is no need to provide a sensing terminal for detecting the flow direction of the current in each semiconductor element 1, and it is possible to determine whether the diode of the semiconductor element is in the freewheeling operation with a simple structure.

[0154] Furthermore, when it is determined that the diode of the semiconductor element 1 is in the freewheeling operation, the gate drive circuit 10 can temporarily reduce the cut-off bias voltage in accordance with the detected value of the gate charge Qg so as to coincide with the timing of the recovery operation of the diode of the semiconductor element 1 in response to the turn-on of other semiconductor elements 1 connected in series with the semiconductor element 1. Thereby, it is possible to reduce the cut-off bias voltage without excessive shortage with respect to the time required to turn on other semiconductor elements 1. In addition, signals for detecting the timing of turning on other semiconductor elements 1 and the like become unnecessary. Therefore, the cut-off bias switching circuit 16, which is a circuit for suppressing self-turn-on of the semiconductor element 1, can be started at an appropriate timing with a simple structure. As a result, self-turn-on of the semiconductor element 1 can be prevented and deterioration of the gate oxide film can be suppressed from progressing.

[0155] Embodiment 2.

[0156] In Embodiment 2, a circuit structure example of the gate drive circuit 10 according to Embodiment 1 will be described.

[0157] Figure 10 It shows Figure 7 A circuit structure example of the shown gate drive circuit 10a. As Figure 10As shown, the switch 15 is composed of an NPN transistor. The collector of the NPN transistor is connected to the power supply node 12, the emitter is connected to the output node 14, and the base is connected to the input terminal T1. The NPN transistor conducts when a gate command signal GSWa (conducting command) of H level is received at the base, and cuts off when a gate command signal GSWa (cut-off command) of L level is received at the base.

[0158] The gate charge detection circuit 18 includes a differential amplifier 30 and a gate charge calculator 32. The differential amplifier 30 functions as a voltage detector for detecting the voltage between the terminals of the gate resistor 17. The gate charge calculator 32 detects the gate current Ig based on the voltage between the terminals of the gate resistor 17 and the resistance value of the gate resistor 17, and integrates the detected gate current Ig to obtain the gate charge Qg.

[0159] The freewheeling operation determination circuit 19 includes a NOT circuit 40, a delay circuit 42, a one-shot circuit 44, a comparator 46, and an AND circuit 48.

[0160] The comparator 46 compares the gate charge Qga obtained by the gate charge calculator 32 with a reference voltage Vref. The reference voltage Vref is a voltage value corresponding to the threshold Qb. When the gate charge Qga is greater than the reference voltage Vref (i.e., the threshold Qb), the comparator 46 outputs a signal of H level. When the gate charge Qga is less than the reference voltage Vref (threshold Qb), the comparator 46 outputs a signal of L level.

[0161] The NOT circuit 40 outputs an inverted signal of the gate command signal GSWa input to the input terminal T1.

[0162] The delay circuit 42 receives the output signal of the NOT circuit 40, delays the output signal by a predetermined delay time, and generates a delayed signal. Immediately after the gate command signal GSWa migrates from H level to L level, the gate charge Qga is Qh, which is greater than the threshold Qb, so it may be erroneously determined that the diode of the semiconductor element 1a is performing a freewheeling operation. Therefore, the delay time in the delay circuit 42 is set according to the turn-off time of the semiconductor element 1. In addition, when the semiconductor element 1a is performing a SW operation, in response to the turn-off of the semiconductor element 1a, the gate charge Qga decreases from Qh to 0, so the delay time is also set to wait for the gate charge Qga to become less than the threshold Qb.

[0163] The single-shot circuit 44 generates a single-shot pulse signal in response to the output signal of the NOT circuit 40 migrating from the L level to the H level. That is, the single-shot circuit 44 generates a single-shot pulse signal with a delay in the turn-off time of the semiconductor element 1 when receiving a cut-off instruction from the control device 130. According to the dead time Td, the pulse width of the pulse signal is set. The pulse width of the pulse signal can be adjusted by the CR constant in the single-shot circuit 44 in a manner that maintains the dead time Td.

[0164] The AND circuit 48 receives the pulse signal of the single-shot circuit 44 at the first input terminal and the output signal of the comparator 46 at the second input terminal. The AND circuit 48 performs an OR operation on the two input signals and outputs the operation result. The output signal of the AND circuit 48 delays the turn-off time of the semiconductor element 1 from the timing when receiving a cut-off instruction from the control device 130 and becomes the H level only during a period corresponding to the dead time Td when the gate charge Qga is greater than the threshold Qb. The output signal of the AND circuit 48 is input to the cut-off bias switching circuit 16 and functions as a signal for switching the gate voltage Vg of the semiconductor element 1 from the cut-off bias voltage Vh to the cut-off bias voltage Vnl.

[0165] The cut-off bias switching circuit 16 includes switches 16l and 16h composed of PNP transistors, a NOT circuit 50, and an AND circuit 52.

[0166] The emitter of the PNP transistor constituting the switch 16h is connected to the output node 14, the collector is connected to the negative terminal of the cut-off bias power supply Vnh, and the base is connected to the output terminal of the AND circuit 52.

[0167] The emitter of the PNP transistor constituting the switch 16l is connected to the output node 14, the collector is connected to the negative terminal of the cut-off bias power supply Vnl, and the base is connected to the output terminal of the NOT circuit 50.

[0168] The NOT circuit 50 generates an inverted signal of the output signal of the AND circuit 48 included in the freewheeling operation determination circuit 19 and inputs the generated inverted signal to the base of the switch 16l.

[0169] The AND circuit 52 receives the output signal of the AND circuit 48 at the first input terminal and the gate command signal GSWa at the second input terminal. The AND circuit 52 performs an AND operation on these two input signals and inputs the operation result to the base of the switch 16h.

[0170] Switch 16l conducts during the period when the output signal of the NOT circuit 50 is at the L level, that is, during the period when the output signal of the AND circuit 48 is at the H level. That is, when the gate charge amount Qga is greater than the threshold value Qb, the turn-off time of the semiconductor element 1 that receives the turn-off command from the control device 130 is delayed, and switch 16l conducts only during the period corresponding to the dead time Td. In response to the conduction of switch 16l, the cut-off bias voltage Vnl is applied to the gate of the semiconductor element 1a.

[0171] Switch 16h conducts when the gate command signal SWa is at the L level and switch 16l is cut off. In response to the conduction of switch 16h, the cut-off bias voltage Vnh is applied to the gate of the semiconductor element 1a.

[0172] In Figure 10 an example of the structure of the push-pull circuit in which switches 16l and 16l use bipolar transistors is illustrated, but switches 16l and 16h are not limited thereto. For example, a push-pull circuit using MOSFETs can also be used as switches 16l and 16h.

[0173] Embodiment 3.

[0174] In Embodiment 1, it was described that the gate drive circuit 10 has two types of cut-off bias power supplies Vnh and Vnl, and according to the determination result of the freewheeling operation determination circuit 19, the gate voltage Vg of the semiconductor element 1 is switched between the cut-off bias voltage Vnh and the cut-off bias voltage Vnl.

[0175] In Embodiment 3, a structure in which one type of cut-off bias power supply Vn is used to switch the cut-off bias voltage is described.

[0176] Figure 11 is a block diagram showing a structural example of the gate drive circuit 10a according to Embodiment 3. The gate drive circuit 10a drives the P-side semiconductor element 1a. Since the gate drive circuit 10a that drives the P-side semiconductor element 1a and the gate drive circuit 10b that drives the N-side semiconductor element 1b have substantially the same structure, the structure of the gate drive circuit 10a will be representatively described below.

[0177] As Figure 11 shown, the gate drive circuit 10a according to Embodiment 3 includes an input terminal T1, output terminals T2 and T3, a control circuit 11, a switch 15, a cut-off bias switching circuit 16, a gate charge amount detection circuit 18, and a freewheeling operation determination circuit 19.

[0178] The gate drive circuit 10a according to Embodiment 3 and Figure 7Compared with the gate drive circuit 10a related to the shown Embodiment 1, the structure of the control circuit 11 is different. The control circuit 11 has a conduction bias power supply Vp for generating a conduction bias voltage Vp applied to the gate of the semiconductor element 1a and a cut-off bias power supply Vn for generating a cut-off bias voltage Vn applied to the gate of the semiconductor element 1a. The control circuit 11 is connected to Figure 7 Compared with the shown control circuit 11, it is different in that it has one cut-off bias power supply Vn.

[0179] The positive terminal of the conduction bias power supply Vp is connected to the power supply node 12, and the negative terminal is connected to the reference node 13. The positive terminal of the cut-off bias power supply Vn is connected to the reference node 13, and the negative terminal is electrically connected to the output node 14.

[0180] The switch 16h of the cut-off bias switching circuit 16 is connected between the output node 14 and the reference node 13. The switch 16l is connected between the output node 14 and the negative terminal of the cut-off bias power supply Vn.

[0181] In response to the gate command signal GSWa, the control circuit 11 selectively turns on and off the switch 15 and the cut-off bias switching circuit 16. Specifically, when the gate command signal GSWa is at the H level, the control circuit 11 turns on the switch 15 and turns off the cut-off bias switching circuit 16. As a result, the output node 14 is connected to the power supply node 12, so the conduction bias power supply Vp is connected between the output terminals T2 and T3. As a result, a conduction bias voltage Vp is applied between the gate and source of the semiconductor element 1a.

[0182] On the other hand, when the gate command signal GSWa is at the L level, the control circuit 11 turns off the switch 15 and turns on the cut-off bias switching circuit 16. The cut-off bias switching circuit 16 selectively turns on the switches 16h and 16l according to the determination result provided by the freewheeling operation determination circuit 19. When the switch 16h is turned on, the output node 14 is connected to the reference node 13, so the gate and source of the semiconductor element 1a become the same potential. That is, 0V is applied between the gate and source of the semiconductor element 1a.

[0183] When the switch 16l is turned on, the output node 14 is connected to the negative terminal of the cut-off bias power supply Vn, so the cut-off bias power supply Vn is connected between the output terminals T2 and T3. As a result, a cut-off bias voltage Vn is applied between the gate and source of the semiconductor element 1a. The cut-off bias voltage Vn is a voltage less than 0V.

[0184] That is, in Embodiment 3, the cut-off bias switching circuit 16 is configured to be able to switch the gate voltage Vga of the semiconductor element 1a between 0 V and the cut-off bias voltage Vn according to the determination result of the freewheeling operation determination circuit 19. By making the cut-off bias voltage Vnh 0 V in this way, only one type of cut-off bias power supply is sufficient, so miniaturization and cost reduction of the gate drive circuit 10a can be achieved.

[0185] In addition, the operation of the gate drive circuit 10 according to Embodiment 3 is the same as Figure 8 and Figure 9 the operation of the gate drive circuit 10 according to Embodiment 1 shown. That is, only at the timing when the diode of the semiconductor element 1 performs a recovery operation, the cut-off bias voltage is temporarily made a voltage Vn less than 0, and except for this, the cut-off bias voltage is made 0 V, so self-turn-on of the semiconductor element 1 can be prevented and deterioration development of the gate oxide film can be suppressed. Therefore, the same effects as in Embodiment 1 can also be obtained in Embodiment 3.

[0186] Furthermore, according to Embodiment 3, compared with Embodiment 1, the magnitude of the cut-off bias voltage can be reduced, so damage to the gate oxide film can be reduced.

[0187] Embodiment 4.

[0188] In Embodiment 1, a structure in which the cut-off bias switching circuit 16 switches the gate voltage Vg of the semiconductor element 1 between the cut-off bias voltage Vnh and the cut-off bias voltage Vnl according to the determination result of the freewheeling operation determination circuit 19 has been described.

[0189] In Embodiment 4, a structure in which the resistance value of the gate resistor of the semiconductor element 1 is switched according to the determination result of the freewheeling operation determination circuit 19 will be described. As described below, this structure focuses on the fact that the gate voltage Vg instantaneously rises according to the displacement current flowing through the gate resistor during the recovery operation of the diode of the semiconductor element 1. The gate drive circuit 10 is configured to suppress the rise of the gate voltage Vg by temporarily reducing the resistance value of the gate resistor in coincidence with the timing of the recovery operation.

[0190] (Structural example of the gate drive circuit according to Embodiment 4)

[0191] Figure 12 is a block diagram showing a structural example of the gate drive circuit 10a according to Embodiment 4. The gate drive circuit 10a drives the P-side semiconductor element 1a. Since the gate drive circuit 10a that drives the P-side semiconductor element 1a and the gate drive circuit 10b that drives the N-side semiconductor element 1b have substantially the same structure, the structure of the gate drive circuit 10a will be representatively described below.

[0192] AsFigure 12 As shown, the gate drive circuit 10a is configured to include an input terminal T1, output terminals T2, T3, a control circuit 11, switches 15a, 15b, a gate resistor 17, a gate charge detection circuit 18, a freewheeling operation determination circuit 19, and a gate resistor switching circuit 20.

[0193] The gate drive circuit 10a according to Embodiment 3 Figure 7 differs from the gate drive circuit 10a according to Embodiment 1 shown in that it has switches 15a, 15b and a gate resistor switching circuit 20 instead of switches 15 and a cut-off bias switching circuit 16.

[0194] The control circuit 11 has a conduction bias power supply Vp for generating a conduction bias voltage Vp applied to the gate of the semiconductor element 1a and a cut-off bias power supply Vn for generating a cut-off bias voltage Vn applied to the gate of the semiconductor element 1a. The positive terminal of the conduction bias power supply Vp is connected to the power supply node 12, and the negative terminal is connected to the reference node 13. The positive terminal of the cut-off bias power supply Vn is connected to the reference node 13, and the negative terminal is electrically connected to the output node 14.

[0195] The switch 15a is connected between the power supply node 12 and the output node 14. The switch 15b is connected between the output node 14 and the negative terminal of the cut-off bias power supply Vn. A gate resistor 17 and a gate resistor switching circuit 20 are connected between the output node 14 and the output terminal T2.

[0196] In response to the gate command signal GSWa, the control circuit 11 selectively turns on and off the switches 15a, 15b. Specifically, when the gate command signal GSWa is at the H level, the control circuit 11 turns on the switch 15a and turns off the switch 15b. As a result, the output node 14 is connected to the power supply node 12, so that the conduction bias power supply Vp is connected between the output terminals T2 and T3. As a result, a conduction bias voltage Vp is applied between the gate and source of the semiconductor element 1a.

[0197] On the other hand, when the gate command signal GSWa is at the L level, the control circuit 11 turns off the switch 15a and turns on the switch 15b. As a result, the output node 14 is connected to the negative terminal of the cut-off bias power supply Vn, so that the cut-off bias power supply Vn is connected between the output terminals T2 and T3. As a result, a cut-off bias voltage Vn is applied between the gate and source of the semiconductor element 1a.

[0198] A gate charge detection circuit 18 is connected across the gate resistor 17. The gate charge detection circuit 18 calculates the gate current Iga based on the voltage across the terminals of the gate resistor 17, and performs time integration on it to detect the gate charge Qga. In order to calculate the gate current Iga, the resistance value of the gate resistor 17 is set to a fixed value Rg0.

[0199] The freewheeling operation determination circuit 19 determines whether the diode of the semiconductor element 1a is performing a freewheeling operation based on the detected value of the gate charge Qga. As described above, the freewheeling operation determination circuit 19 determines whether the diode of the semiconductor element 1a is performing a freewheeling operation by comparing the threshold value Qb with the detected value of the gate charge Qg.

[0200] The gate resistor switching circuit 20 has a variable resistor and is configured to be able to change the resistance value according to the determination result provided by the freewheeling operation determination circuit 19. As will be described later, the gate resistor switching circuit 20 switches the resistance value of the gate resistor Rga of the semiconductor element 1a between two resistance values according to the determination result of the freewheeling operation determination circuit 19.

[0201] Figure 13 is a diagram showing Figure 12 an example of the circuit structure of the gate drive circuit 10a shown. The circuit structures of the gate charge detection circuit 18 and the freewheeling operation determination circuit 19 are the same as those of the Figure 10 circuit structure shown, so the description is omitted.

[0202] The switch 15a is composed of an NPN transistor. The collector of the NPN transistor is connected to the power supply node 12, the emitter is connected to the output node 14, and the base is connected to the input terminal T1. The NPN transistor conducts when it receives a high-level gate command signal GSWa (conducting command) at the base and cuts off when it receives a low-level gate command signal GSWa (cut-off command) at the base.

[0203] The switch 15b is composed of a PNP transistor. The emitter of the PNP transistor is connected to the output node 14, the collector is connected to the negative terminal of the cut-off bias power supply Vn, and the base is connected to the input terminal T1. The PNP transistor cuts off when it receives a high-level gate command signal GSWa (conducting command) at the base and conducts when it receives a low-level gate command signal GSWa (cut-off command) at the base.

[0204] The gate resistor switching circuit 20 includes a gate resistor Rgon for turning on the semiconductor element 1a, a gate resistor Rgoff for turning off the semiconductor element 1a, diodes D1 and D2 for preventing reverse current, and a switch 60.

[0205] The diode D1 and the gate resistor Rgon are connected in series between the output node 14 and the gate resistor 17. The diode D1 allows the gate current Ig in the positive direction (the direction for charging the gate parasitic capacitances Cgd and Cgs) to flow through the gate resistor Rgon, while blocking the gate current Ig in the negative direction (the direction for discharging the gate parasitic capacitances Cgd and Cgs) from flowing through the gate resistor Rgon.

[0206] The diode D2 and the gate resistor Rgoff are connected in series between the output node 14 and the gate resistor 17. The diode D2 allows the gate current Ig in the negative direction to flow through the gate resistor Rgoff, while blocking the gate current Ig in the positive direction from flowing through the gate resistor Rgoff.

[0207] The switch 60 is connected in parallel with the gate resistor Rgoff. By turning on the switch 60, the gate resistor Rgoff is short-circuited and its resistance value becomes 0. The conduction and cutoff of the switch 60 are controlled by the freewheeling operation determination circuit 19.

[0208] Specifically, when the freewheeling operation determination circuit 19 determines that the diode of the semiconductor element 1a is in the freewheeling operation, it turns on the switch 60. When the switch 60 is turned on, the gate resistor Rga of the semiconductor element 1a in the freewheeling operation becomes the resistance value Rg0 of the gate resistor 17.

[0209] On the other hand, when the diode of the semiconductor element 1a is not in the freewheeling operation or when it is determined that the freewheeling operation of the diode of the semiconductor element 1a has ended, the freewheeling operation determination circuit 19 turns off the switch 60. When the switch 60 is turned off, the gate resistor Rga of the semiconductor element 1a becomes the sum of the resistance value Rg0 of the gate resistor 17 and the resistance value of the gate resistor Rgon or the gate resistor Rgoff.

[0210] That is, when turning on the semiconductor element 1a, the switch 15a is turned on to apply a conduction bias voltage Vp to the gate of the semiconductor element 1a. As a result, a gate current Ig temporarily flows in the positive direction from the power supply node 12 through the switch 15a, the output node 14, the diode D1, the gate resistor Rgon, and the gate resistor 17. The resistance value of the gate resistor Rga of the semiconductor element 1a becomes Rg0 + Rgon.

[0211] On the other hand, when turning off the semiconductor element 1a, the switch 15b is turned on to apply a cutoff bias voltage Vn to the gate of the semiconductor element 1a. As a result, a gate current Ig temporarily flows in the negative direction from the gate of the semiconductor element 1a through the gate resistor 17, the gate resistor Rgoff, the diode D2, the output node 14, and the switch 15b. The resistance value of the gate resistor Rga of the semiconductor element 1a becomes Rg0 + Rgoff.

[0212] As described above, during the period when the semiconductor element 1a is turned off and the diode of the semiconductor element 1a is performing a freewheeling operation, the switch 60 is temporarily turned on. As a result, the gate resistor Rgoff is bypassed, and thus the resistance value of the gate resistor Rga decreases from Rg0 + Rgoff to Rg0.

[0213] During the period when the drain voltage Vds changes rapidly by dv / dt due to the recovery operation of the diode of the semiconductor element 1a, a displacement current (Cgd × dv / dt) flows through the gate-drain capacitance Cgd of the semiconductor element 1. This displacement current flows through the gate resistor Rga, causing the gate voltage Vga to rise. The amount of increase ΔVga of the gate voltage Vga can be expressed as the product of the displacement current and the resistance value of the gate resistor Rga (ΔVgs = (Cgd × dv / dt) × Rga). In the fourth embodiment, by temporarily reducing the resistance value of the gate resistor Rga during the period when the displacement current flows, the amount of increase ΔVga can be reduced. As a result, the rise of the gate voltage Vga can be suppressed, and thus the self-turn-on of the semiconductor element 1a can be prevented.

[0214] In addition, when the gate charge Qg decreases from Qa to 0 due to the recovery operation of the diode of the semiconductor element 1a, the freewheeling operation determination circuit 19 determines that the freewheeling operation of the diode of the semiconductor element 1a has ended, and turns off the switch 60. As a result, the resistance value of the gate resistor Rga is switched from Rg0 to Rg0 + Rgoff.

[0215] Here, when the resistance value of the gate resistor Rga is small, the rise of the gate voltage Vga can be suppressed to prevent the self-turn-on of the semiconductor element 1a. On the other hand, there is a possibility that vibration is generated due to the floating inductance component of the gate wiring, which may cause gate misfire. In addition, since it is easily affected by electromagnetic noise, there is also a possibility of becoming an inducement for gate misfiring. The gate drive circuit 10a according to the fourth embodiment temporarily reduces the resistance value of the gate resistor Rga to Rg0 only at the timing when the diode of the semiconductor element 1a performs a recovery operation, and otherwise sets the resistance value of the gate resistor Rga to Rgoff + Rg. Therefore, the self-turn-on of the semiconductor element 1a can be prevented and the vibration of the gate can be eliminated. As a result, the gate misfiring of the semiconductor element 1a can be prevented.

[0216] (Operation of the gate drive circuit according to the fourth embodiment)

[0217] Next, the operation of the gate drive circuit 10a according to the fourth embodiment will be described.

[0218] Figure 14 is a timing chart showing the operations of the semiconductor elements 1a and 1b. InFigure 14 shows the waveforms of the drain voltage Vds, drain current Id, gate voltage Vg, gate charge Qg, switch 60 of the gate resistance switching circuit 20, and gate command signal GSW of semiconductor elements 1a and 1b. In each waveform, the solid line represents the waveform of the P-side semiconductor element 1a, and the dashed line represents the waveform of the N-side semiconductor element 1b.

[0219] Figure 14 The shown timing diagram and Figure 5 compared with the shown timing diagram, the waveform of the gate voltage Vga of the semiconductor element 1a is different. The other waveforms are the same as Figure 5 the shown waveforms, so detailed descriptions are omitted.

[0220] As Figure 14 shown, at time t0, the gate command signal GSWa is at the L level, and the gate command signal GSWb becomes the H level. In the gate drive circuit 10a, the control circuit 11 responds to the L-level gate command signal GSWa, turns off the switch 15a, and turns on the switch 15b. The gate voltage Vga of the semiconductor element 1a becomes the cut-off bias voltage Vn, and the semiconductor element 1a becomes the cut-off state. Therefore, the drain current Ida = 0, and the drain voltage Vdsa = VDC. The gate parasitic capacitances Cgd and Cgs of the semiconductor element 1b are discharged, so the gate charge Qga becomes 0.

[0221] The freewheeling operation determination circuit 19 compares the gate charge Qga with the threshold Qb. Since Qga < Qb, the freewheeling operation determination circuit 19 determines that the diode of the semiconductor element 1a is not in the freewheeling operation and turns off the switch 60 of the gate resistance switching circuit 20. Therefore, the resistance value of the gate resistance Rga of the semiconductor element 1a becomes Rg0 + Rgoff.

[0222] At time t1, when the gate command signal GSWb migrates from the H level to the L level, the semiconductor element 1b turns off. In the gate drive circuit 10b, the control circuit 11 responds to the L-level gate command signal GSWb, turns off the switch 15a, and turns on the switch 15b, thereby applying the cut-off bias voltage Vn to the gate of the semiconductor element 1b. The gate voltage Vgb of the semiconductor element 1b becomes the cut-off bias voltage Vn, and thus the gate charge Qgb of the semiconductor element 1b gradually decreases from Qh. In response to the completion of the discharge of the gate parasitic capacitances Cgs and Cgd, the gate charge Qgb becomes 0.

[0223] The freewheeling operation determination circuit 19 compares the gate charge amount Qgb with the threshold value Qb. Since Qgb < Qb, the freewheeling operation determination circuit 19 determines that the diode of the semiconductor element 1b is not in the freewheeling operation, and maintains the switch 60 of the gate resistance switching circuit 20 in the cut-off state. Therefore, the resistance value of the gate resistance RGB of the semiconductor element 1b becomes Rg0 + Rgoff.

[0224] In response to the cut-off of the semiconductor element 1b, a freewheeling current flows through the diode of the semiconductor element 1a. During the transition period in which the drain voltage Vdsa changes rapidly in response to the start of the freewheeling current flowing through the diode, a displacement current (Cgd × dv / dt) flows through the gate-drain capacitance Cgd of the semiconductor element 1a. This displacement current flows through the gate resistance 17 and the gate resistance Rga of the gate resistance switching circuit 20, thereby reducing the gate voltage Vga. In addition, since the gate parasitic capacitances Cgd and Cgs are charged by the displacement current, the gate charge amount Qga increases from 0 to Qa.

[0225] The period from time t1 to t2 corresponds to the dead time Td. During the dead time Td, the freewheeling current continues to flow through the diode of the semiconductor element 1a.

[0226] At time t2, when the gate command signal GSWa transitions from the L level to the H level, the semiconductor element 1a is turned on. Specifically, in response to the H-level gate command signal GSWa, the gate drive circuit 10a turns on the switch 15a and turns off the switch 15b, thereby switching the voltage applied to the gate of the semiconductor element 1a from the cut-off bias voltage Vn to the cut-off bias voltage Vp. The gate current Iga flows from the power supply node 12 through the gate resistance Rgon of the gate resistance switching circuit 20 and the gate resistance 17 to the gate of the semiconductor element 1a. Since the gate parasitic capacitances Cgs and Cgd are charged, the gate charge amount Qga gradually increases from Qa to Qh. A freewheeling current flows between the drain and source of the semiconductor element 1a, and the semiconductor element 1a is performing a freewheeling operation.

[0227] At time t3, when the gate command signal GSWa transitions from the H level to the L level, the semiconductor element 1a is turned off. In the gate drive circuit 10a, the control circuit 11 turns off the switch 15a and turns on the switch 15b in response to the L-level gate command signal GSWa, thereby applying the cut-off bias voltage Vn to the gate of the semiconductor element 1a.

[0228] The gate voltage Vga of the semiconductor element 1a becomes the cut-off bias voltage Vn, so that the gate charge Qgb gradually decreases from Qh. The gate voltage Vga gradually decreases from the on-bias voltage Vp towards the cut-off bias voltage Vn. When the gate voltage Vga is less than the gate threshold voltage Vth, the semiconductor element 1a starts to cut off. When the semiconductor element 1a becomes cut off, a freewheeling current starts to flow in the diode of the semiconductor element 1a. Therefore, the drain voltage Vdsa and the drain current Ida are maintained at constant values without change even when the semiconductor element 1a is turned off.

[0229] During the dead time Td from time t3 to t4, since the diode of the semiconductor element 1a performs a freewheeling operation, the gate charge Qga does not decrease to 0 but remains at Qa. The freewheeling operation determination circuit 19 compares the gate charge Qga and the threshold Qb during the dead time Td immediately after the semiconductor element 1a is turned off. Since Qga (=Qa)>Qb, the freewheeling operation determination circuit 19 determines that the diode of the semiconductor element 1a is in the freewheeling operation. In response to determining that the diode of the semiconductor element 1a is in the freewheeling operation, the freewheeling operation determination circuit 19 turns on the switch 60 at time t5 after the semiconductor element 1a is turned off. As a result, the resistance value of the gate resistance Rga of the semiconductor element 1a is switched from Rgoff+Rg0 to Rg0.

[0230] In addition, the timing for switching the gate resistance Rga from Rgoff+Rg0 to Rg0 is preferably set to the timing after the flow of the gate current Iga ends in response to the turning off of the semiconductor element 1a (time t3). This timing can be obtained based on the time constants of the gate parasitic capacitances Cgd, Cgs of the semiconductor element 1a and the gate resistance 17. Alternatively, the timing for switching the gate voltage Vga can be obtained based on the fall time Tf, etc. of the semiconductor element 1a recorded in a data sheet or the like.

[0231] When the gate command signal GSWb migrates from the L level to the H level at time t4, the semiconductor element 1b is turned on. Specifically, in response to the gate command signal GSWb at the H level, the gate drive circuit 10b turns on the switch 15a and turns off the switch 15b, thereby switching the voltage applied to the gate of the semiconductor element 1b from the cut-off bias voltage Vn to the on-bias voltage Vp.

[0232] When the drain current Idb starts to flow in the semiconductor element 1b in response to the turn-on of the semiconductor element 1b, the drain voltage Vdsa of the semiconductor element 1a changes sharply via the recovery operation of the diode of the semiconductor element 1a. During the period when the change dv / dt of the drain voltage Vdsa with respect to time occurs, a displacement current (Cgd×dv / dt) flows in the gate-drain capacitance Cgd of the semiconductor element 1a. This displacement current flows through the gate resistor 17 and the switch 60, so that the gate charge Qga decreases from Qa to 0.

[0233] However, during the dead time Td from time t3 to t4, the resistance value of the gate resistor Rga of the semiconductor element 1a decreases from Rgoff+Rg0 to Rg0. Therefore, even if a displacement current flows through the gate resistor 17 and the gate resistor switching circuit 20 after time t4, the rising amount ΔVga of the gate voltage Vga is suppressed and the gate voltage Vga does not exceed the gate threshold voltage Vth. Therefore, it is possible to prevent the semiconductor element 1a from turning on by itself. Therefore, it is possible to avoid the semiconductor elements 1a and 1b being damaged due to an excessive short-circuit current flowing through the semiconductor elements 1a and 1b.

[0234] In the gate drive circuit 10a, the freewheeling operation determination circuit 19 compares the gate charge Qga with the threshold Qb. Since Qga<Qb, the freewheeling operation determination circuit 19 determines that the freewheeling operation of the semiconductor element 1a has ended. In response to determining that the freewheeling operation of the semiconductor element 1a has ended, the freewheeling operation determination circuit 19 turns off the switch 60 at time t6. As a result, the resistance value of the gate resistor Rga of the semiconductor element 1a is switched from Rg0 to Rgoff+Rg0.

[0235] That is, the gate drive circuit 10a temporarily reduces the resistance value of the gate resistor Rga of the semiconductor element 1a from Rgoff+Rg0 to Rg0 in timing that coincides with the recovery operation of the diode of the semiconductor element 1a. Thereby, it is possible to suppress the gate voltage Vga from instantaneously rising and exceeding the gate threshold voltage Vth in response to the recovery operation.

[0236] Furthermore, the gate drive circuit 10a makes the resistance value of the gate resistor Rga be Rgoff+Rg except at the timing when the diode of the semiconductor element 1a performs the recovery operation. Therefore, it is possible to eliminate the vibration of the gate of the semiconductor element 1a, and as a result, it is possible to prevent misfiring of the semiconductor element 1a.

[0237] As described above, the operation waveforms when the semiconductor element 1b performs the SW operation and the semiconductor element 1a performs the freewheeling operation in the case where the phase current IL<0 have been described. In the case where the phase current IL>0, the semiconductor element 1a performs the SW operation and the semiconductor element 1b performs the freewheeling operation, but it is possible to Figure 14Similarly, consider its operation waveform.

[0238] Figure 15 is a flowchart showing the operation of the gate drive circuit 10 according to Embodiment 4. In Figure 15 it shows the operation of the gate drive circuit 10 when the corresponding semiconductor element 1 is turned off in accordance with the L-level gate command signal GSW (cut-off command) from the control device 130. The determination of whether the semiconductor element 1 is performing a freewheeling operation when receiving the H-level gate command signal GSW (conducting command) does not affect the switching of the gate resistor Rg, so the description is omitted.

[0239] Figure 15 The flowchart shown is different from Figure 9 the flowchart shown in that steps S02, S06, and S09 are replaced with steps S11 to S14.

[0240] As Figure 15 shown, when the semiconductor element 1 is in the conducting state, a conducting bias voltage Vp is applied to the gate of the semiconductor element 1. In this state, when receiving the L-level gate command signal GSW (cut-off command) from the control device 130 (at step S01), the control circuit 11 of the gate drive circuit 10 turns off the switch 15a and also turns off the switch 15b (step S11). As a result, the cut-off bias voltage Vn is applied to the gate of the semiconductor element 1. The gate resistor switching circuit 20 maintains the switch 60 in the cut-off state (step S13). Therefore, the resistance value of the gate resistor Rg of the semiconductor element 1 becomes Rgoff + Rg.

[0241] The gate voltage Vg of the semiconductor element 1 becomes the cut-off bias voltage Vn, and thus the gate charge Qg gradually decreases from Qh. When the gate voltage Vga gradually decreases toward the cut-off bias voltage Vn and becomes less than the gate threshold voltage Vth, the semiconductor element 1 starts to turn off. The freewheeling operation determination circuit 19 compares the gate charge Qg detected by the gate charge detection circuit 18 with the threshold value Qb (step S03). When the gate charge Qg is less than the threshold value Qb (when the determination in S03 is "no"), the freewheeling operation determination circuit 19 determines that the diode of the semiconductor element 1 is not in the freewheeling operation (step S10).

[0242] On the other hand, when the gate charge Qg is equal to or greater than the threshold value Qb (when the determination in S03 is "yes"), the freewheeling operation determination circuit 19 next determines whether the current timing is within the dead time Td after the turn-off period of the semiconductor element 1 (step S04). The turn-off period can be obtained based on the time constant of the gate parasitic capacitances Cgd, Cgs of the semiconductor element 1 and the gate resistor 17. Or it can be obtained based on the fall time Tf, etc. of the semiconductor element 1a described in the data sheet, etc.

[0243] When the current timing is during the off period of semiconductor element 1, S04 determines "No". In this case, the freewheeling operation determination circuit 19 determines that the diode of semiconductor element 1 is not in the freewheeling operation (step S10).

[0244] In contrast, when the current timing is during the dead time Td after the off period of semiconductor element 1 (when the determination in S04 is "Yes"), the freewheeling operation determination circuit 19 determines that the diode of semiconductor element 1 is in the freewheeling operation (step S05). In this case, the gate resistance switching circuit 20 turns on the switch 60 (step S13). As a result, the resistance value of the gate resistance Rg of semiconductor element 1 is switched from Rgoff + Rg to Rg.

[0245] During the dead time Td, when another semiconductor element 1 connected in series with semiconductor element 1 is turned on, the diode of semiconductor element 1 performs a recovery operation, so the drain voltage Vds of semiconductor element 1 changes rapidly. During the period when the change dv / dt of the drain voltage Vds with respect to time occurs, a displacement current (Cgd × dv / dt) flows through the gate-drain capacitance Cgd of semiconductor element 1. Therefore, the gate voltage Vg rises, and the gate charge Qg decreases from Qa to 0.

[0246] The freewheeling operation determination circuit 19 compares the gate charge Qb detected by the gate charge detection circuit 18 with the threshold value Qb (step S07). When the gate charge Qg is equal to or greater than the threshold value Qb (when the determination in S07 is "No"), the freewheeling operation determination circuit 19 determines that semiconductor element 1 is in the freewheeling operation (step S05). Therefore, the gate resistance switching circuit 20 maintains the resistance value of the gate resistance Rg of semiconductor element 1 at Rg by keeping the switch 60 turned on (step S13).

[0247] On the other hand, when the gate charge Qg is less than the threshold value Qb (when the determination in S07 is "Yes"), the freewheeling operation determination circuit 19 determines that the freewheeling operation of semiconductor element 1 has ended (step S08). In response to the determination that the freewheeling operation of semiconductor element 1 has ended, the gate resistance switching circuit 20 turns off the switch 60 (step S14). As a result, the resistance value of the gate resistance Rg of semiconductor element 1 is switched from Rg to Rgoff + Rg.

[0248] In addition, in the Figure 15 flowchart, it is also the same as Figure 9Similarly, the threshold Qb is used for both determining whether the semiconductor element 1 is in the freewheeling operation (step S03) and determining whether the semiconductor element 1 has completed the freewheeling operation (step S07). However, it is also possible to adopt a structure in which different thresholds are used in these two processes according to the characteristics of the semiconductor element 1.

[0249] <Effects of Embodiment 4>

[0250] As described above, the gate drive circuit 10 according to Embodiment 4 is configured to determine whether the diode of the semiconductor element 1 is in the freewheeling operation based on the detected value of the gate charge Qg of the corresponding semiconductor element 1. Therefore, there is no need to provide a sensing terminal for detecting the current flow direction in each semiconductor element 1, and it is possible to simply determine whether the diode of the semiconductor element is in the freewheeling operation.

[0251] Furthermore, when it is determined that the diode of the semiconductor element 1 is in the freewheeling operation, the gate drive circuit 10 can temporarily reduce the resistance value of the gate resistor of the semiconductor element 1 in accordance with the detected value of the gate charge Qg, in synchronization with the timing of the recovery operation of the diode of the semiconductor element 1 in response to the turn-on of other semiconductor elements 1 connected in series with the semiconductor element 1. As a result, it is possible to reduce the resistance value of the gate resistor without excessive shortage with respect to the time required to turn on other semiconductor elements 1. Therefore, it is possible to suppress the rise of the gate voltage Vg of the semiconductor element 1 and prevent self-turn-on. In addition, a signal for detecting the timing of turning on other semiconductor elements 1 becomes unnecessary. Therefore, it is possible to start the gate resistor switching circuit 20, which is a circuit for suppressing the self-turn-on of the semiconductor element 1, at an appropriate timing with a simple structure. As a result, it is possible to prevent the self-turn-on of the semiconductor element 1 and suppress the vibration of the gate.

[0252] It should be considered that the embodiments disclosed herein are illustrative only and not restrictive in all respects. The scope of the present disclosure is shown not by the above description but by the claims, and is intended to include all modifications within the meaning and scope equivalent to the claims.

[0253] (Reference Signs)

[0254] 1, 1a to 1f: semiconductor elements for electric power; 10, 10a to 10f: gate drive circuits; 11, 21: control circuits; 12: power supply node; 12U, 12V, 12W: branches; 13: reference node; 14: output node; 15, 15a, 15b, 16l, 16h, 25a, 25b, 60: switches; 16: cut-off bias switching circuit; 17, 26, Rgon, Rgoff: gate resistors; 18: gate charge detection circuit; 19: freewheeling operation determination circuit; 20: gate resistor switching circuit; 30: differential amplifier; 32: gate charge calculator; 40, 50: NOT circuits; 42: delay circuit; 44: one-shot circuit; 46: comparator; 48, 52: AND circuits; 100: power conversion device; 110: DC power supply; 120: motor; 130: control device; D1, D2: diodes; PL: DC positive busbar; NL: DC negative busbar; Vp: conduction bias power supply (conduction bias voltage); Vn, Vnh, Vnl: cut-off bias power supply (cut-off bias voltage); T1: input terminal; T2, T3: output terminals.

Claims

1. A drive circuit for a semiconductor element for electric power, which drives the semiconductor element for electric power, wherein, the semiconductor element for electric power has a first main electrode on the high potential side, a second main electrode on the low potential side, a gate as a control electrode, and a diode anti-parallel connected between the first main electrode and the second main electrode; the drive circuit of the semiconductor element for electric power includes: a control circuit that selectively applies a conduction bias voltage and a cut-off bias voltage to the gate of the semiconductor element for electric power in accordance with a control signal input from the outside; a detection circuit that detects the gate charge amount of the semiconductor element for electric power; and a determination circuit that determines whether the diode of the semiconductor element for electric power is performing a freewheeling operation based on the gate charge amount detected by the detection circuit.

2. The drive circuit of the conductor element for electric power according to claim 1, wherein, it further includes a cut-off bias switching circuit that switches the cut-off bias voltage applied to the gate between a first voltage and a second voltage lower than the first voltage, when disconnecting the semiconductor element for electric power in accordance with the control signal, the control circuit applies the cut-off bias voltage having the first voltage to the gate, the determination circuit determines that the diode of the semiconductor element for electric power is performing the freewheeling operation when the gate charge amount after the disconnection of the semiconductor element for electric power is greater than a first threshold value, the cut-off bias switching circuit switches the cut-off bias voltage from the first voltage to the second voltage in response to determining that the diode of the semiconductor element for electric power is performing the freewheeling operation.

3. The drive circuit of the semiconductor element for electric power according to claim 2, wherein, the determination circuit determines that the freewheeling operation has ended when the gate charge amount after the disconnection of the semiconductor element for electric power is greater than the first threshold value and the gate charge amount decreases to less than a second threshold value, the cut-off bias switching circuit switches the cut-off bias voltage from the second voltage to the first voltage in response to determining that the freewheeling operation has ended.

4. The drive circuit of the semiconductor element for electric power according to claim 2, wherein, the determination circuit determines that the semiconductor element for electric power is not performing the freewheeling operation when the gate charge amount after the disconnection of the semiconductor element for electric power is less than the first threshold value, the cut-off bias switching circuit maintains the cut-off bias voltage at the first voltage in response to determining that the semiconductor element for electric power is not performing the freewheeling operation.

5. The drive circuit of the semiconductor element for electric power according to any one of claims 2 to 4, wherein, the first voltage is 0V.

6. The drive circuit of the semiconductor element for electric power according to claim 1, wherein, it further includes a gate resistance switching circuit that switches the gate resistance of the semiconductor element for electric power between a first resistance value and a second resistance value smaller than the first resistance value, When the power semiconductor device is turned off according to the control signal, the control circuit applies the cut-off bias voltage to the gate via the gate resistor having the first resistance value. When the gate charge after the disconnection of the power semiconductor device is greater than a first threshold value, the determination circuit determines that the diode of the power semiconductor device is performing the freewheeling operation. In response to determining that the diode of the power semiconductor device is performing the freewheeling operation, the gate resistor switching circuit switches the gate resistor from the first resistance value to the second resistance value.

7. The drive circuit for a power semiconductor device according to claim 6, wherein, when the gate charge after the disconnection of the power semiconductor device is greater than the first threshold value, the determination circuit determines that the freewheeling operation has ended when the gate charge decreases to be less than a second threshold value. In response to determining that the freewheeling operation has ended, the gate resistor switching circuit switches the gate resistor from the second resistance value to the first resistance value.

8. The drive circuit for a power semiconductor device according to claim 6, wherein, when the gate charge after the disconnection of the power semiconductor device is less than the first threshold value, the determination circuit determines that the power semiconductor device is not performing the freewheeling operation. In response to determining that the power semiconductor device is not performing the freewheeling operation, the gate resistor switching circuit maintains the gate resistor at the first resistance value.

9. A power conversion device, comprising: a DC positive bus and a DC negative bus; a first power semiconductor device and a second power semiconductor device, which are connected in series between the DC positive bus and the DC negative bus; and the drive circuit according to any one of claims 1 to 8, which drives each of the power semiconductor devices of the first power semiconductor device and the second power semiconductor device.

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