Flat panel detector and detection device
Patent Information
- Application Number
- CN202380010792.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-09-21
- Publication Date
- 2025-06-10
AI Technical Summary
The thin film transistors of existing detectors are prone to leakage current when they are disconnected, which affects the performance of the detector.
A new type of detection substrate is designed to reduce the area of the first overlap region and the second overlap region by optimizing the structure of the thin film transistor and reduce leakage current. Specific measures include a smaller area of the first overlap region in the semiconductor layer than the second overlap region area, a larger area of the second overlap region than the first overlap region, reducing the channel region width of the thin film transistor and increasing its length, and reducing the carriers activated by the coupling electric field through an asymmetric design.
It effectively reduces the leakage current of the thin film transistor in the off state, improves the filling rate and response speed of the detection substrate, and improves the performance of the flat panel detector.
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Figure CN120130144A_ABST
Abstract
Description
Flat panel detector and detection device Technical Field
[0001] The present invention relates to the field of detection technology, and in particular to a flat panel detector and a detection device. Background Art
[0002] X-ray inspection technology is widely used in industrial nondestructive testing, container scanning, circuit board inspection, healthcare, security, and industry, and holds broad application prospects. Traditional X-ray imaging technology relies on analog signals, resulting in low resolution and poor image quality. Digital radiography (DR), a technology that emerged in the late 1990s, uses flat-panel X-ray detectors to directly convert X-ray images into digital images. This digital image, characterized by its clarity, high resolution, and ease of storage and transmission, has become a hot topic of research. Based on their structure, flat-panel X-ray detectors are categorized as direct (DR) and indirect (DR). Indirect X-ray flat-panel detectors have been widely developed and applied due to their mature technology, relatively low cost, high detective quantum efficiency (DQE), and excellent reliability.
[0003] Generally speaking, a flat-panel detector (FPD) consists of a scintillator, a detection substrate, a control module, a signal processing module, and a communication module. The scintillator absorbs X-rays and converts them into visible light. The detection substrate consists of a pixel array composed of photodiodes and thin-film transistors (TFTs). Driven by a control circuit, the photodiodes convert the visible light generated by the scintillator into electrical signals, which are then transmitted to the scan lines via the TFT switches. The signal processing module amplifies the electrical signals and converts them into digital signals via an analog-to-digital converter. Correction and compensation are then performed to produce an image.
[0004] However, the thin film transistors of current detectors are prone to leakage current when in an off state. Therefore, the current detection substrate, its manufacturing method, and detector still need to be improved.
[0005] Summary of the Invention
[0006] The present invention aims to solve one of the technical problems in the related art at least to a certain extent.
[0007] A detection substrate, comprising:
[0008] substrate;
[0009] a gate line, the gate line being disposed on the first side of the base substrate and extending along a first direction;
[0010] a scan line disposed on a first side of the base substrate and extending along a second direction, wherein the first direction intersects the second direction; and
[0011] At least one pixel unit is defined by the intersection of the gate line and the scan line,
[0012] The at least one pixel unit comprises:
[0013] a thin film transistor, disposed on a first side of the base substrate, the thin film transistor comprising: a semiconductor layer; a first electrode, the first electrode being electrically connected to the semiconductor layer in a first overlapping region; a second electrode, the second electrode being electrically connected to the semiconductor layer in a second overlapping region, an orthographic projection area of the second overlapping region on the base substrate being larger than an orthographic projection area of the first overlapping region on the base substrate; and,
[0014] A photoelectric converter is provided on a side of the thin film transistor away from the substrate; the photoelectric converter comprises: a bottom electrode, the bottom electrode being electrically connected to the first electrode through a first via hole; a photoelectric conversion layer, the photoelectric conversion layer being provided on a side of the bottom electrode away from the substrate; and a top electrode being provided on a side of the photoelectric conversion layer away from the substrate.
[0015] In which, in the at least one pixel unit, the minimum distance between the orthographic projection of the first via on the substrate and the orthographic projection of the scan line closest to the first via on the substrate is a first distance, and the maximum distance between the orthographic projection of the semiconductor layer on the substrate and the orthographic projection of the scan line closest to the first via on the substrate is a second distance, and the second distance is greater than or equal to the first distance.
[0016] in,
[0017] The orthographic projection of the first electrode on the substrate has symmetry axes, and the number of the symmetry axes is greater than or equal to 3;
[0018] The orthographic projection of the first via hole on the base substrate covers at least two intersection points of the symmetry axes.
[0019] The orthographic projection of the first electrode on the substrate has a center point, and the orthographic projection of the bottom electrode on the substrate covers the center point.
[0020] The orthographic projection of the first electrode on the substrate is at least partially conformal to the orthographic projection of the first via on the substrate.
[0021] The orthographic projection of the semiconductor layer on the base substrate partially overlaps with the orthographic projection of the bottom electrode on the base substrate.
[0022] It also includes a second insulating layer, which is arranged on the side of the first electrode away from the substrate, and the second insulating layer is arranged on the side of the bottom electrode close to the substrate; the orthographic projection of the second insulating layer on the substrate partially overlaps with the first overlapping area.
[0023] The orthographic projection of the semiconductor layer on the substrate and the orthographic projection of the bottom electrode on the substrate are spaced apart from each other.
[0024] The orthographic projection of the first via hole on the base substrate partially overlaps with the orthographic projection of the semiconductor layer on the base substrate.
[0025] The semiconductor layer is provided with a first recess near the first via hole.
[0026] Wherein, the semiconductor layer partially surrounds the first via hole.
[0027] The maximum dimension of the first overlapping area in the second direction is greater than or equal to the maximum dimension of the first via hole in the second direction.
[0028] The projection of the semiconductor layer in the first direction overlaps with the projection of the first via hole in the first direction.
[0029] The semiconductor layer includes a channel region, and the orthographic projection of the bottom electrode on the substrate does not overlap with the orthographic projection of the channel region on the substrate.
[0030] The orthographic projection of the bottom electrode on the base substrate is at least partially flush with the orthographic projection of the first electrode on the base substrate.
[0031] The first electrode is an N-gon, where N is greater than or equal to 5.
[0032] Wherein, a second recess is provided on at least one side in the second direction where the second electrode is connected to the scan line.
[0033] The orthographic projection of the semiconductor layer on the base substrate does not overlap with the orthographic projection of the second recess on the base substrate.
[0034] Wherein, a bias line is also included, and the bias line is electrically connected to the photoelectric converter through a second via hole.
[0035] The orthographic projection of the bias line on the base substrate covers the orthographic projection of the first via hole on the base substrate.
[0036] The thin film transistor further includes a gate, and a fourth recess is formed on a side of the gate close to the first via hole in the first direction.
[0037] An interlayer insulating layer is provided between the thin film transistor and the bias line, the interlayer insulating layer has a third via hole, and the scan line is electrically connected to the second electrode through the third via hole. BRIEF DESCRIPTION OF THE DRAWINGS
[0038] FIG1 is a schematic diagram of a pixel structure of a flat panel detector provided in the related art.
[0039] FIG2A is a schematic diagram of a pixel structure of a flat panel detector provided by the present disclosure.
[0040] FIG. 2B is a partially enlarged view of FIG. 2A .
[0041] FIG3 is a cross-sectional view taken along the AA′ line of FIG2B .
[0042] FIG4A is a schematic diagram of a pixel structure of a flat panel detector provided by the present disclosure.
[0043] FIG4B is a partially enlarged view of FIG4A .
[0044] FIG4C is a partially enlarged view of FIG4A .
[0045] FIG. 5 is a cross-sectional view taken along line AA′ of FIG. 4B .
[0046] FIG6A is a schematic diagram of a pixel structure of a flat panel detector provided by the present disclosure.
[0047] FIG6B is a partially enlarged view of FIG6A .
[0048] FIG. 7 is a cross-sectional view taken along line AA′ of FIG. 6B .
[0049] FIG8 is a schematic diagram of the first electrode structure provided by the present disclosure.
[0050] FIG9 is a schematic diagram of a pixel structure of a flat panel detector provided by the present disclosure.
[0051] FIG10A is a schematic diagram of a pixel structure of a flat panel detector provided by the present disclosure.
[0052] FIG10B is a cross-sectional view taken along line A′-A of FIG10A .
[0053] FIG11 is a schematic diagram of a flat panel detector provided by the present disclosure.
[0054] FIG12A is a schematic diagram of an intermediate product formed in step S1 of a process flow for preparing a flat panel detector provided by the present disclosure.
[0055] FIG12B is a schematic diagram of an intermediate product formed in step S2 of a process flow for preparing a flat panel detector provided by the present disclosure.
[0056] FIG12C is a schematic diagram of an intermediate product formed in step S4 of a process flow for preparing a flat panel detector provided by the present disclosure.
[0057] FIG12D is a schematic diagram of an intermediate product formed in step S5 of a process flow for preparing a flat panel detector provided by the present disclosure.
[0058] FIG13 is a schematic block diagram of an electronic device provided by an embodiment of the present disclosure. DETAILED DESCRIPTION
[0059] In order to make the purpose, technical solutions and advantages of the present disclosure clearer, the embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. The embodiments can be implemented in a variety of different forms. A person of ordinary skill in the art can easily understand the fact that the method and content can be transformed into one or more forms without departing from the purpose and scope of the present disclosure. Therefore, the present disclosure should not be interpreted as being limited to the contents described in the following embodiments. In the absence of conflict, the embodiments in the present disclosure and the features in the embodiments can be combined with each other in any way.
[0060] The scales of the figures in this disclosure can be used as a reference for actual processes, but are not limited to this. For example, the width-to-length ratio of the channel region, the thickness and spacing of each film layer, and the width and spacing of each scan line can be adjusted according to actual needs. The number of pixels in the optoelectronic substrate and the number of sub-pixels in each pixel are not limited to the numbers shown in the figures. The figures described in this disclosure are only schematic structural diagrams, and one embodiment of the present disclosure is not limited to the shapes or values shown in the figures.
[0061] The ordinal numbers such as "first," "second," and "third" in this disclosure are provided to avoid confusion among constituent elements, and are not intended to limit the number. The "plurality" in this disclosure includes two or more.
[0062] The words "equal", "approximately equal", "equal to" and the like in this disclosure are for convenience of writing and are not intended to be limiting in terms of numerical values. "Equal" in this disclosure includes that the difference between two numerical values does not exceed 10% to 20%.
[0063] In this disclosure, for convenience, words and phrases indicating orientation or positional relationships, such as "middle," "upper," "lower," "front," "back," "vertical," "horizontal," "top," "bottom," "inside," and "outside," are used to illustrate the positional relationships of constituent elements with reference to the accompanying drawings. This is merely for the convenience of describing this specification and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operate in a specific orientation. Therefore, it should not be understood as a limitation of this disclosure. The positional relationships of constituent elements are appropriately changed according to the direction in which the constituent elements are described. Therefore, the words and phrases are not limited to those described in the specification and can be appropriately replaced according to the circumstances.
[0064] In this disclosure, unless otherwise expressly specified or limited, the terms "mounted," "connected," and "connected" should be interpreted broadly. For example, they can refer to fixed, removable, or integral connections; mechanical or electrical connections; direct connections, indirect connections through intermediaries, or internal communication between two components. Those skilled in the art will understand the meaning of these terms in this disclosure based on the specific circumstances.
[0065] In this disclosure, a transistor refers to a device comprising at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between a drain electrode (drain electrode terminal, drain region, or drain) and a source electrode (source electrode terminal, source region, or source), and current can flow through the drain electrode, the channel region, and the source electrode. In this disclosure, the channel region refers to the region through which current primarily flows.
[0066] In the present disclosure, the first electrode may be a drain electrode and the second electrode may be a source electrode, or vice versa. The functions of the "source electrode" and "drain electrode" may be interchanged when using transistors with opposite polarities or when the direction of current changes during circuit operation. Therefore, in the present disclosure, the terms "source electrode" and "drain electrode" may be interchanged.
[0067] In this disclosure, "electrically connected" includes components connected together via an element having some electrical function. There are no particular limitations on the "element having some electrical function" as long as it enables the transfer of electrical signals between the connected components. Examples of "element having some electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements having one or more functions.
[0068] As shown in Figure 1, the flat panel detector sensor of the related art includes a detection substrate, which includes a base substrate 10, at least one thin film transistor 3 (TFT), at least one scan line 2 and at least one gate line 1 arranged on the base substrate 10; the at least one thin film transistor 3 includes a gate 31, a semiconductor layer 32 and a first electrode 33 and a second electrode 34 connected to the semiconductor layer 32, the gate 31 is arranged on the base substrate 10, the semiconductor layer 32 is arranged on the gate 31 insulating layer covering the gate 31, an end of the first electrode 33 close to the second electrode 34 is arranged on the semiconductor layer 32, the other end of the first electrode 33 away from the second electrode 34 is electrically connected to the scan line 2, and an end of the second electrode 34 close to the first electrode 33 is arranged on the semiconductor layer 32; an end of the second electrode 34 away from the first electrode 33 is electrically connected to the bottom electrode 6 of the photoelectric conversion layer 5; a top electrode 7 is provided on the side of the photoelectric conversion layer 5 away from the base substrate 10, and the top electrode 7 is electrically connected to the bias line 8.
[0069] Under X-ray irradiation, the scintillator layer or phosphor layer in the photoconversion layer converts X-ray photons into visible light, which is then incident on the detection substrate. The bias line 8 and top electrode 7 in the detection substrate apply a bias voltage to the photoelectric conversion layer 5, causing the photoelectric conversion layer 5 to convert the visible light photons into carriers (electrons) and integrate them. The integrated electrons are transported by the bottom electrode 6 to the first electrode 33, and the electrical signal is output to the scan line 2 through the thin film transistor 3. Combined with subsequent analog-to-digital conversion and image processing, a digital image is formed. The thin film transistor 3 reads the electrical signal to the scan line 2 and outputs the electrical signal to obtain the displayed image.
[0070] In the related art, the overlapping area between the first electrode 33 of the thin film transistor 3 and the semiconductor layer 32 is large. Therefore, when the potential on the side of the first electrode 33 is high, when the thin film transistor 3 is turned off (when the gate voltage Vg applied to the gate 31 is less than the threshold voltage Vth), leakage current may flow between the first electrode 33 / the second electrode 34.
[0071] It can be considered that when the detection substrate is working, a voltage is applied to the first electrode 33 side during the cut-off period of the thin film transistor 3, and electrostatic capacitance coupling is generated between the semiconductor layer 32 and the first electrode 33, thereby activating the semiconductor layer 32. As a result, the leakage current increases, causing the integrated electrical signal in the photosensitive unit to be lost, affecting the integrated signal finally read, and ultimately reducing the photoelectric characteristics of the flat-panel detector.
[0072] In order to reduce the leakage current of the thin film transistor 3 in the flat panel detector sensor when it is turned off, it is possible to consider narrowing the width and length of the channel region 321 of the thin film transistor 3; or reducing the overlapping area between the first electrode 33 and the semiconductor layer 32, that is, the first overlapping area 331, or the overlapping area between the second electrode 34 and the semiconductor layer 32, that is, the second overlapping area 341.
[0073] In order to solve the above technical problems, the present disclosure proposes a novel detection substrate for a flat panel detector.
[0074] In some embodiments, as shown in Figures 2-3 (the photoelectric conversion layer 5 is not shown for the convenience of illustrating the structure of the thin film transistor 3), a detection substrate is provided, which includes a base substrate 10, a gate line 1 extending along a first direction, and a scan line 2 extending along a second direction; the gate line 1 and the scan line 2 divide a plurality of pixel units distributed in an array; the pixel unit includes: a thin film transistor 3, which is arranged on a first side of the base substrate 10; a photoelectric converter, which is arranged on a side of the thin film transistor away from the base substrate; the photoelectric converter includes: a bottom electrode 6, which is electrically connected to the first electrode through a first via hole; and a photoelectric conversion layer 5, which is arranged on a side of the bottom electrode 6 away from the base substrate. The top electrode 7 is arranged on the side of the photoelectric conversion layer away from the base substrate; the thin film transistor 3 includes a first electrode 33, a second electrode 34, and a semiconductor layer 32; the first electrode 33 is connected to the semiconductor layer 32 in a first overlapping region 331, and the second electrode 34 is connected to the semiconductor layer 32 in a second overlapping region 341, and the orthographic projection area of the second overlapping region 341 on the base substrate 10 is larger than the orthographic projection area of the first overlapping region 331 on the base substrate 10; the photoelectric conversion layer 5 includes a bottom electrode 6, and the bottom electrode 6 is electrically connected to the first electrode 33 through a first via 9.
[0075] It should be noted that in the present disclosure, the area of the first overlapping region 331 of the semiconductor layer 32 of the thin-film transistor 3 is smaller than the area of the second overlapping region 341. When the gate 311 is energized, because the area of the second overlapping region 341 is larger than the area of the first overlapping region 331, more carriers accumulate in the semiconductor layer 32 in the second overlapping region 341, while less carriers accumulate in the semiconductor layer 32 in the first overlapping region 331. As a result, when the thin-film transistor 3 is turned off, the leakage current is reduced.
[0076] Furthermore, in some embodiments, the area of the semiconductor layer 32 at the first overlapping region 331 is simultaneously reduced, that is, the orthographic projection of the semiconductor layer 32 on the substrate 10 is a trapezoid or a pattern of two trapezoids spliced along the bottom edge. Due to the coupling electric field between the first electrode 33 or the second electrode 34 and the gate 31, the semiconductor layer 32 near the first overlapping region 331 or the second overlapping region 341 may be activated, increasing the leakage current. Therefore, in these embodiments, the asymmetric design of the semiconductor layer 32 is used to reduce or weaken or even eliminate the carriers activated by the coupling electric field, thereby achieving a different number of activated carriers on both sides of the thin film transistor 3, thereby reducing the leakage current.
[0077] In a flat-panel detector, the larger the area occupied by the photoelectric conversion layer 5 in the detector substrate, that is, the higher the fill factor, the higher the flat-panel detector's photoelectric conversion efficiency, and the lower the required X-ray dose. In the field of medical imaging, this reduces the amount of X-ray radiation received by patients. Therefore, the fill factor of a flat-panel detector is a parameter that needs to be improved urgently.
[0078] Continuing with reference to Figures 2-3, when only the structure of the channel region 321 is changed, the increased size of the thin-film transistor 3 will result in a reduction in the orthographic projection area of the photoelectric conversion layer 5 on the base substrate 100 in the photosensitive pixel, thereby affecting the effective response area of the detection substrate, affecting the quantum detection efficiency and modulation transfer function of the radiation detector, and degrading the performance of the detection substrate. It should be noted that the effective corresponding area of the detection substrate mentioned above can be the area where the photoelectric conversion layer 5 and the scintillator are arranged relative to each other, that is, the area of the surface used to respond to or receive light converted by the scintillator.
[0079] Therefore, in some examples, as shown in Figure 2B (the photoelectric conversion layer 5 is not shown in the figure. Since the photoelectric conversion layer 5 is arranged on the bottom electrode 6, when the area of the bottom electrode 6 increases, the area of the photoelectric conversion layer 5 that can be set increases), in the first direction, the shortest distance between the orthographic projection of the first via 9 on the substrate 10 and the orthographic projection of the scanning line 2 on the substrate 10 is L1, and the maximum distance between the orthographic projection of the semiconductor layer 32 on the substrate 10 and the orthographic projection of the scanning line 2 on the substrate 10 is L2, and L2 is greater than or equal to L1.
[0080] It should be noted that when L2 is greater than or equal to L1, the distance between the first via 9 and the scanning line 2 will decrease. In the photosensitive unit, the positive projection area of the bottom electrode 6 on the base substrate 10 increases, so the area of the photoelectric conversion layer 5 arranged on the side of the bottom electrode 6 away from the base substrate 10 increases, and the filling rate will increase accordingly, improving or enhancing the performance of the detection substrate. Furthermore, when L2 is greater than or equal to L1, the shortest distance between the first via 9 and the thin film transistor 3 will decrease, so this embodiment can reduce the transmission distance of the signal and the resistance on the transmission path, thereby improving the response speed of the detection substrate.
[0081] Continuing with FIG. 2B , in some embodiments, the orthographic projection of the first via 9 on the base substrate 10 partially overlaps with the orthographic projection of the semiconductor layer 32 on the base substrate 10. In this case, during the fabrication process of the semiconductor layer 32, the pattern complexity of the patterning process is low, the resulting morphology of the semiconductor layer 32 is good, and the patterning requirements of the semiconductor layer 32 during the fabrication process are relatively low, resulting in a relatively simple fabrication process.
[0082] It is worth noting that in these embodiments, since the semiconductor layer 32 is partially disposed in the first via hole 9 , this may cause a decrease in the flatness in the first via hole, which may result in macroscopic defects in the appearance of the final flat panel detector.
[0083] In some embodiments, as shown in Figures 4A-4B, the semiconductor layer 32 is provided with a first recess 13 near the first via hole 9; that is, the projection of the semiconductor layer 32 in the first direction overlaps with the projection of the first via hole 9 in the first direction; that is, the semiconductor layer 32 partially surrounds the first via hole 9 near the first via hole 9. Alternatively, the maximum dimension L3 of the first overlapping region 331 in the second direction is greater than the maximum dimension L4 of the first via hole 9 in the second direction.
[0084] As shown in Figure 4C , the first overlapping region 331 has a first side 3311, a second side 3312, a third side 3313, and a fourth side 3314. The second and fourth sides extend along the second direction. Partially surrounding means that, in the first direction, the first side 3311 and the third side 3313 are disposed on both sides of the first via 9, and an orthographic projection 9' of the first via in the first direction overlaps with an orthographic projection 331' of the first overlapping region 331 in the first direction.
[0085] In these embodiments, referring to FIG. 5 , since the semiconductor layer 32 is not provided in the first via hole 9 , the flatness inside the first via hole 9 is improved, which is helpful in solving the macroscopic defects caused by unevenness.
[0086] Furthermore, this design can reduce the overlapping area between the semiconductor layer 32 and the first electrode 33 , further reducing the leakage current when the thin film transistor 3 is turned off.
[0087] Furthermore, under such a design, the first via hole 9 can be brought closer to the thin film transistor 3 while reducing the area of the semiconductor layer 32 and the first overlapping region 331 , thereby further improving the filling rate of the photosensitive unit.
[0088] In the thin film transistor 3, if there is a large overlap between the metal layers, a large parasitic capacitance will be introduced, which may affect the performance of the thin film transistor 3. Therefore, this problem should also be considered when designing the thin film transistor 3.
[0089] In the above embodiment, as shown in FIG4A , since the first recess 13 is provided in the semiconductor layer 32 , the overlapping area between the semiconductor layer 32 and the bottom electrode 6 is reduced. Therefore, in addition to reducing leakage current and increasing the filling rate, the design of providing the first recess 13 in the semiconductor layer 32 can also reduce the overlapping area between the semiconductor layer 32 and the bottom electrode 6 , thereby reducing interference to the thin film transistor 3 .
[0090] In addition to the semiconductor layer 32, the bottom electrode 6 can also be designed to reduce parasitic capacitance. In some embodiments, as shown in Figures 2A and 4A, the orthographic projection of the bottom electrode 6 on the substrate 10 is flush with the orthographic projection of the first electrode 33 on the substrate 10 at least partially. That is, the orthographic projection of the bottom electrode 6 on the substrate 10 does not overlap with the orthographic projection of the channel region 321 on the substrate 10. At this time, the bottom electrode 6 and the channel region 321 of the thin film transistor 3 have no orthographic projection overlap or the orthographic projection overlap is small, so the coupling effect of the bottom electrode 6 on the channel region 321 of the thin film transistor 3 can be reduced or prevented, thereby improving the accuracy of the signal transmission of the thin film transistor 3.
[0091] It should be noted that the flushing means that at least part of the contour lines of the orthographic projection of the bottom electrode 6 on the base substrate 10 and the orthographic projection of the first electrode 33 on the base substrate 10 overlap.
[0092] In some embodiments, as shown in FIG3 and FIG5 , the orthographic projection of the semiconductor layer 32 on the base substrate 10 partially overlaps with the orthographic projection of the bottom electrode 6 on the base substrate 10. The detection substrate further includes a second insulating layer 42, which is arranged on the side of the first electrode 33 facing away from the base substrate 10, and the second insulating layer 42 is arranged on the side of the bottom electrode 6 close to the base substrate 10; the orthographic projection of the second insulating layer 42 on the base substrate 10 overlaps with the first overlapping region 331. That is, in the first overlapping region 331, from the base substrate 10 to the direction of the photoelectric conversion layer 5, the semiconductor layer 32, the first electrode 33, the second insulating layer 42, and the bottom electrode 6 are designed in sequence; the orthographic projection of the bottom electrode 6 on the base substrate 10 does not completely cover the orthographic projection of the first electrode 33 on the base substrate 10.
[0093] If the second insulating layer 42 is not provided and the orthographic projection of the bottom electrode 6 on the base substrate 10 overlaps with the orthographic projection of the channel region 321 on the base substrate 10, coupling or an electric field may be generated, interfering with the signal transmission of the thin film transistor 3 or increasing the leakage current of the thin film transistor 3. Therefore, adding a second insulating layer 42 increases the distance between the bottom electrode 6 and the semiconductor layer 32, reducing or avoiding the interference of the bottom electrode 6 on the thin film transistor 3.
[0094] In addition, due to the thickness of the second insulating layer 42 itself, a boss 12 of a certain thickness will be formed on the surface of the first interlayer insulating layer 161, which can increase the surface roughness of the first interlayer insulating layer 101, increase the contact force of the interlayer insulating layer 10, reduce the probability of the flat layer falling off or prevent the occurrence of such defects, and improve the yield of the detection substrate.
[0095] To further reduce the overlapping area between the bottom electrode 6 and the semiconductor layer 32, the area of the bottom electrode 6 can be further reduced. In some embodiments, as shown in Figures 6-7, the bottom electrode 6 does not extend to completely cover the first electrode 33. The orthographic projection of the semiconductor layer 32 on the base substrate 10 is spaced apart from the orthographic projection of the bottom electrode 6 on the base substrate 10, and the orthographic projection of the bottom electrode 6 on the base substrate 10 completely covers the orthographic projection of the first via 9 on the base substrate 10. In this embodiment, the bottom electrode 6 can achieve a good electrical connection with the first via 9. Furthermore, because the bottom electrode 6 and the semiconductor layer 32 do not overlap, the parasitic capacitance between them is reduced, thereby improving the performance of the flat-panel detector.
[0096] In some embodiments, as shown in FIG8 , the orthographic projection of the first electrode 33 on the base substrate 10 has a symmetry axis, and the number of the symmetry axes is greater than or equal to 3, thereby making the first electrode 33 have a contour morphology similar to a regular polygon, thereby ensuring the area of the first via 9, making the electrical connection between the first electrode 33 and the bottom electrode 6 more sufficient, and reducing the loss of the scan line readout signal.
[0097] Furthermore, the orthographic projection of the first via 9 on the base substrate 10 covers the intersection of at least two of the symmetry axes, that is, the orthographic projection of the bottom electrode 6 on the base substrate 10 covers the center point of the first electrode 33. In some embodiments, the orthographic projection of the first electrode 33 on the base substrate 10 and the orthographic projection of the first via 9 on the base substrate 10 are at least partially conformal. This allows the electrical connection position to be close to the centroid of the first electrode 33, resulting in more uniform signal transmission.
[0098] As shown in Figure 8, the axis of symmetry refers to the axis of symmetry of the axial symmetry or rotational symmetry of the figure, which is a straight line that makes the geometric figure form axial symmetry or rotational symmetry. The axis of symmetry can be an axis of symmetry or a centrosymmetry.
[0099] The center point of the first electrode 33 may be one of the centroid of the first electrode 33 , the centroid of the orthographic projection on the substrate 10 , and the geometric center of the orthographic projection on the substrate 10 .
[0100] Conformal means that two or more graphics are identical in whole or in part. In the embodiment of the present disclosure, at least partially conformal means that at least a portion of the contour line of the orthographic projection of the first electrode 33 on the base substrate 10 is similar to at least a portion of the contour line of the orthographic projection of the first via 9 on the base substrate 10, that is, the extension direction and bending angle are the same, or the two contour lines are parallel to each other.
[0101] Furthermore, the first electrode 33 can be an N-gon with N greater than or equal to 5. Near the thin film transistor 3 of the detection substrate, the pattern of the photoelectric conversion layer 5 is conformal to the pattern of the first electrode 33. When the curvature of the pattern of the first electrode 33 increases, the photoelectric conversion layer 5 can have a nonlinear continuous side wall, which optimizes and improves the surface quality and morphology of the side wall, and can effectively reduce or avoid the occurrence of leakage current in the photoelectric conversion layer 5. When N is greater than or equal to 5, as shown in Figure 9, the first electrode 33 can be adaptively rotated in a certain direction to make the corresponding photoelectric conversion layer 5 side wall quality and morphology better, which will not be repeated here.
[0102] In some embodiments, referring again to FIG. 9 , at least one second recess 14 is provided at the connection point between the second electrode 34 and the scan line 2. The provision of the second recess 14 on the scan line 2 results in an overlap capacitance between the second electrode 34 and the gate 31, reducing noise in the thin-film transistor 3, thereby improving the signal-to-noise ratio of the product and enhancing image quality. Furthermore, a conformal portion exists between the semiconductor layer 32 and the second electrode 34. In this embodiment, the orthographic projection of the semiconductor layer 32 on the substrate 10 does not overlap with the orthographic projection of the second recess 14 on the substrate 10. That is, the semiconductor layer 32 has third recesses 15 at both ends in the second direction near the adjacent scan line 2. This reduces the perimeter of the semiconductor layer 32, thereby reducing the lateral area of the semiconductor layer 32. Since performance defects in the semiconductor layer 32 of the thin-film transistor 3 are primarily concentrated on the lateral surfaces, reducing the lateral area also reduces defects in the thin-film transistor 3, facilitating overall performance reduction of the flat-panel detector.
[0103] Continuing with Figure 10 , a third via 17 is defined in the interlayer insulating layer, electrically connecting the scan line 2 and the second electrode 34 via the third via 17 . The scan line 2 and the bias line 8 are located on the same layer. In this embodiment, due to the presence of the interlayer insulating layer 10 between the scan line 2 and the gate line 1, the scan line 2 in the detection substrate is further away from the gate line 1, reducing the coupling capacitance in the overlapping region 21 between the scan line 2 and the gate line 1. This reduces interference during signal transmission, ensuring image quality.
[0104] The term "same layer" means that the bias line 8 and the scan line 2 are manufactured at the same step in the manufacturing process, that is, the bias line 8 and the scan line 2 are made of the same material. Alternatively, the term "same layer" may also mean that the bias line 8 and the scan line 2 are made of different materials but are disposed in the same layer, that is, the main portions of the bias line 8 and the scan line 2 are equidistant from the base substrate 100 in a direction perpendicular to the base substrate 100.
[0105] In addition, referring to Figure 10, in this embodiment, in the detection substrate, whether it is the connecting part of the third via 17 or the extended part of the scanning line 2, the distance between the scanning line 2 and the bottom electrode 6 is increased, so the coupling capacitance of the scanning line 2 to the bottom electrode 6 is also reduced, thereby ensuring the accuracy of the electrical signal generated by the photoelectric conversion layer 5, thereby ensuring the quality of the generated image.
[0106] In some embodiments, the detection substrate further includes a bias line 8. As shown in FIG11 , the bias line 8 is electrically connected to the photoelectric conversion layer 5 through the second via 11, providing a bias voltage for the photoelectric conversion layer 5. In addition, the bias line 8 can also serve as a light shielding layer. In the embodiment of the present disclosure, the distance between the first via 9 and the thin-film transistor 3 is small. When the bias line 8 serves as a light shielding layer for the thin-film transistor 3, the bias line 8 can only shield a portion of the first via 9. Since the flatness of the inside of the via varies, the reflection intensity varies. Therefore, in this case, the detection substrate may have macroscopic defects.
[0107] To address the above problem, in an embodiment of the present disclosure, the orthographic projection of the bias line 8 on the base substrate 10 covers the orthographic projection of the first via 9 on the base substrate 10. This allows the bias line 8 to completely shield the first via 9, thereby reducing or even resolving the macroscopic defect.
[0108] Furthermore, the thin film transistor 3 further includes a gate 31, and a fourth recess 16 is formed on a side of the gate 31 in the first direction close to the first via 9. This reduces the overlapping area between the second electrode 34 and the gate 31, thereby reducing the parasitic capacitance between the gate 31 and the second electrode 34.
[0109] Based on the same inventive concept, as shown in FIG12 , an embodiment of the present invention further provides a method for preparing a detection substrate as described in any one of the above items, comprising:
[0110] S1: As shown in FIG12A , the gate electrode 31 , the first insulating layer 41 , the semiconductor layer 32 , the first electrode 33 and the second electrode 34 of the thin film transistor 3 are sequentially formed on the base substrate 10 through a patterning process.
[0111] In this embodiment, the base substrate 10 can be made of a transparent material such as glass and is pre-cleaned. Specifically, first, a gate metal film layer is formed on the base substrate 10 by sputtering, thermal evaporation, plasma enhanced chemical vapor deposition (PECVD), low pressure chemical vapor deposition (LPCVD), atmospheric pressure chemical vapor deposition (APCVD), or electron cyclotron resonance chemical vapor deposition (ECR-CVD). Then, a halftone mask (HTM) or a gray tone mask (GTM) is used to form the pattern of the gate 31 through a patterning process (film formation, exposure, development, wet etching, or dry etching). The gate 31 may be formed of metal, metal alloy, such as molybdenum, molybdenum-niobium alloy, aluminum, aluminum-neodymium alloy, titanium, copper or other conductive materials.
[0112] Next, a first insulating layer 41 is formed on the gate 31 by plasma enhanced chemical vapor deposition, low pressure chemical vapor deposition, atmospheric pressure chemical vapor deposition, electron cyclotron resonance chemical vapor deposition, or sputtering.
[0113] Then, an amorphous silicon film is deposited by plasma enhanced chemical vapor deposition, low pressure chemical vapor deposition, etc., and after being crystallized, a pattern of the semiconductor layer 32 is formed by a patterning process.
[0114] Finally, a source / drain metal film layer is formed by plasma enhanced chemical vapor deposition, low pressure chemical vapor deposition, atmospheric pressure chemical vapor deposition, electron cyclotron resonance chemical vapor deposition or sputtering, and a pattern including the first electrode 33 and the second electrode 34 is simultaneously formed by a single patterning process.
[0115] S2: As shown in FIG. 12B , a second insulating layer 42 is formed by a patterning process, and a first via hole 9 is formed at a position of the second insulating layer 42 corresponding to the first electrode 33 .
[0116] Specifically, in this step, a passivation film layer may be deposited by plasma-enhanced chemical vapor deposition, low-pressure chemical vapor deposition, atmospheric pressure chemical vapor deposition, or electron cyclotron resonance chemical vapor deposition, and then patterned by masking, dry etching, or other processes to form the first via hole 9. The passivation film layer may be made of materials such as silicon nitride and silicon oxide.
[0117] A pattern of the bottom electrode 6 including the photoelectric conversion layer 5 is formed by a patterning process, and is connected to the first electrode 33 of the thin film transistor 3 through the first via hole 9 .
[0118] Similar to the process of forming the first electrode 33 and the second electrode 34 of the thin film transistor 3, in this step, a first metal film layer can be deposited on the passivation layer 3 by plasma enhanced chemical vapor deposition, low pressure chemical vapor deposition, atmospheric pressure chemical vapor deposition, electron cyclotron resonance chemical vapor deposition or sputtering, and the pattern of the bottom electrode 6 of the photoelectric conversion layer 5 can be formed through masking, wet etching and other composition processes.
[0119] The first metal film layer may be made of metal or metal alloy, such as molybdenum, molybdenum-niobium alloy, aluminum, aluminum-neodymium alloy, titanium or copper or other conductive materials.
[0120] In some examples, the bottom electrode 6 of the photoelectric conversion layer 5 is electrically connected to the first electrode 33 through the first via 9. This is because, during the fabrication of the detector substrate, the first electrode 33 is typically deposited and patterned first, followed by the fabrication of the second insulating layer 42. The second insulating layer 42 protects the channel region 321 of the thin-film transistor 3, minimizing or preventing interference or damage to the channel region 321 of the thin-film transistor 3 in subsequent processes. At this point, the first electrode 33 is completely covered by the second insulating layer 42. If this electrode 33 is to be used as the bottom electrode 6 of the photoelectric conversion layer 5, the second insulating layer 42 must be etched to expose the first electrode 33. However, this etching process can reduce the surface flatness of the first electrode 33 or leave residues in the second insulating layer 42, affecting the electrical connection between the photoelectric conversion layer 5 and the first electrode 33 in subsequent processes and reducing the photoelectric conversion performance of the flat-panel detector. Therefore, depositing and patterning the bottom electrode 6 on the second insulating layer 42 and depositing the photoelectric conversion layer 5 on the bottom electrode 6 with low or no defects can improve the performance of the flat-panel detector.
[0121] S4: As shown in FIG12C , a photoelectric conversion layer 5 is deposited on the base substrate 10 and a pattern is formed by a patterning process.
[0122] In this embodiment, the detection substrate includes a photoelectric conversion layer 5 region. The thickness of the photoelectric conversion layer 5 may be 10000 Å, and it may specifically include an N-type semiconductor material layer, an I-type semiconductor material layer, and a P-type semiconductor material layer.
[0123] Specifically, step S4 may include the following steps:
[0124] S41 , depositing semiconductor material on the base substrate 10 having the bottom electrode 6 formed thereon by sputtering, thermal evaporation, plasma enhanced chemical vapor deposition, low pressure chemical vapor deposition, atmospheric pressure chemical vapor deposition or electron cyclotron resonance chemical vapor deposition.
[0125] S42 , forming the photoelectric conversion layer 5 by dry etching processes such as plasma etching (PE), reactive ion etching (RIE), enhanced capacitive coupled plasma etching (ECCP), and inductively coupled plasma etching (ICP).
[0126] In order to ensure good ohmic contact between the photoelectric conversion layer 5 and the bias line 8 to be formed, a transparent conductive layer can be formed on the semiconductor material after forming the semiconductor material in S41; then, the transparent conductive layer is etched to form the bias line 8. The material of the bias line 8 can be ITO, IGZO, etc.
[0127] S5 . As shown in FIG. 12D , an interlayer insulating layer 10 is formed on the base substrate 10 on which the semiconductor layer 32 of the photoelectric conversion layer 5 is formed, and a second via hole 11 is formed in the interlayer insulating layer 10 .
[0128] The interlayer insulating layer 10 is made of resin and is relatively thick, thereby flattening the flat panel detector substrate. Specifically, in this step, the interlayer insulating material film can be deposited layer by layer using plasma-enhanced chemical vapor deposition, low-pressure chemical vapor deposition, atmospheric pressure chemical vapor deposition, or electron cyclotron resonance chemical vapor deposition. Then, through patterning processes such as masking and etching, second vias 11 are formed at locations corresponding to the photoelectric conversion layer 5.
[0129] Furthermore, since a single-layer interlayer insulating layer 10 made of resin material is relatively thick and easily peeled off, to further ensure product performance, the interlayer insulating layer 10 preferably includes a first interlayer insulating layer 101, a second interlayer insulating layer 102, and a third interlayer insulating layer 103, which are sequentially arranged. The materials of the first interlayer insulating layer 101 and the third interlayer insulating layer 103 may include silicon nitride or silicon oxide, while the material of the second interlayer insulating layer 102 may include resin. Furthermore, the thickness of the second interlayer insulating layer 102 is greater than that of the first interlayer insulating layer 101 and the third interlayer insulating layer 103.
[0130] A pattern including a bias line 8 is formed by a patterning process, and the bias line 8 is connected to the photoelectric conversion layer 5 through the second via hole 11 .
[0131] In this step, a second metal film layer can be deposited on the interlayer insulating layer 10 by plasma-enhanced chemical vapor deposition, low-pressure chemical vapor deposition, atmospheric pressure chemical vapor deposition, electron cyclotron resonance chemical vapor deposition, or sputtering, and then patterned by masking, wet etching, or other patterning processes to form the pattern of the bias line 8. The second metal film layer can be made of a metal or metal alloy, such as molybdenum, molybdenum-niobium alloy, aluminum, aluminum-neodymium alloy, titanium, or copper, or other conductive materials.
[0132] That is, the connection between the photoelectric conversion layer 5 and the thin film transistor 3 is achieved by connecting the bottom electrode 6 of the photoelectric conversion layer 5 to the first electrode 33 of the thin film transistor 3, thereby controlling the conduction state of the thin film transistor 3 to detect the light signal collected by the photoelectric conversion layer 5.
[0133] At this point, the preparation of the thin film transistor 3 and the photodiode in the flat panel detector substrate is completed.
[0134] It should be noted that the bottom electrode 6 in this embodiment may be directly connected to the first electrode 33 of the thin film transistor 3, so the above step S21 may specifically include:
[0135] The gate electrode 31 of the thin film transistor 3 , the first insulating layer 41 , the semiconductor layer 32 , the first electrode 33 , the second electrode 34 and the bottom electrode 6 of the photoelectric conversion layer 5 are sequentially formed on the base substrate 10 through a patterning process.
[0136] The gate electrode 31, gate electrode 31 insulating layer, and semiconductor layer 32 of the thin-film transistor 3 are fabricated in the same manner as described above and are not further described here. When forming the first electrode 33 and the second electrode 34, the patterns of the first electrode 33, the second electrode 34, and the bottom electrode 6 are simultaneously formed through a single patterning process. The first electrode 33 and the bottom electrode 6 are integrally formed, meaning that the extended portion of the first electrode 33 can serve as the bottom electrode 6.
[0137] After step S1 , the photoelectric conversion layer 5 , the interlayer insulating layer 10 , the bias line 8 and other structures are formed in sequence according to steps S3 , S4 and S5 , which will not be described in detail here.
[0138] In this embodiment, the first electrode 33 of the thin film transistor 3 is used as the bottom electrode 6 , which can further increase the filling rate and improve the performance of the flat panel detector.
[0139] Schematic block diagram 13 of an electronic device 200 provided in an embodiment of the present disclosure. The electronic device 200 includes the radiation detector described in any of the previous embodiments. Examples of the electronic device 200 include medical diagnostic equipment, industrial testing equipment, geological exploration equipment, and the like. The electronic device 200 has the same advantages as the radiation detector embodiments.
[0140] The present disclosure also includes a flat panel detector, which includes the above-mentioned detection substrate and a non-visible light conversion layer covering the array substrate, wherein the non-visible light conversion layer is configured to convert non-visible light into visible light.
[0141] It will be understood that the above embodiments are merely exemplary embodiments for illustrating the principles of the present invention, and the present invention is not limited thereto. Those skilled in the art will appreciate that various modifications and improvements can be made without departing from the spirit and substance of the present invention, and such modifications and improvements are also considered to be within the scope of protection of the present invention.
Claims
1. A detection substrate, comprising: substrate substrate; A gate line, the gate line is arranged on the first side of the base substrate and extends along a first direction; A scan line, the scan line is disposed on the first side of the base substrate and extends along a second direction, the first direction intersecting the second direction; and, At least one pixel unit is defined by the intersection of the gate line and the scan line, The at least one pixel unit comprises: A thin film transistor is arranged on the first side of the substrate, the thin film transistor comprising: a semiconductor layer; a first electrode, the first electrode is electrically connected to the semiconductor layer in a first overlapping region; a second electrode, the second electrode is electrically connected to the semiconductor layer in a second overlapping region, and an orthographic projection area of the second overlapping region on the substrate is larger than an orthographic projection area of the first overlapping region on the substrate; and, A photoelectric converter is arranged on a side of the thin film transistor away from the substrate; the photoelectric converter comprises: a bottom electrode, the bottom electrode is electrically connected to the first electrode through a first via hole; a photoelectric conversion layer, the photoelectric conversion layer is arranged on a side of the bottom electrode away from the substrate; and a top electrode is arranged on a side of the photoelectric conversion layer away from the substrate. Among them, in the at least one pixel unit, the minimum distance between the orthographic projection of the first via on the substrate and the orthographic projection of the scan line closest to the first via on the substrate is a first distance, the maximum distance between the orthographic projection of the semiconductor layer on the substrate and the orthographic projection of the scan line closest to the first via on the substrate is a second distance, and the second distance is greater than or equal to the first distance.
2. The detection substrate according to claim 1, wherein The orthographic projection of the first electrode on the substrate has symmetry axes, and the number of the symmetry axes is greater than or equal to 3; The orthographic projection of the first via hole on the base substrate covers at least two intersection points of the symmetry axes.
3. The detection substrate according to claim 1, wherein: The orthographic projection of the first electrode on the substrate has a center point, and the orthographic projection of the bottom electrode on the substrate covers the center point.
4. The detection substrate according to claim 1, wherein The orthographic projection of the first electrode on the substrate is at least partially conformal to the orthographic projection of the first via on the substrate.
5. The detection substrate according to any one of claims 1 to 4, wherein: The orthographic projection of the semiconductor layer on the substrate overlaps partially with the orthographic projection of the bottom electrode on the substrate.
6. The detection substrate according to any one of claims 1 to 4, wherein: It also includes a second insulating layer, which is arranged on the side of the first electrode away from the substrate and on the side of the bottom electrode close to the substrate; the orthographic projection of the second insulating layer on the substrate partially overlaps with the first overlapping area.
7. The detection substrate according to any one of claims 1 to 4, wherein: The orthographic projection of the semiconductor layer on the substrate and the orthographic projection of the bottom electrode on the substrate are spaced apart from each other.
8. The detection substrate according to any one of claims 1 to 4, wherein: An orthographic projection of the first via hole on the base substrate partially overlaps with an orthographic projection of the semiconductor layer on the base substrate.
9. The detection substrate according to any one of claims 1 to 4, wherein: The semiconductor layer is provided with a first recess near the first via hole.
10. The detection substrate according to claim 9, wherein: The semiconductor layer partially surrounds the first via hole.
11. The detection substrate according to claim 9, wherein: The maximum dimension of the first overlapping area in the second direction is greater than or equal to the maximum dimension of the first via hole in the second direction.
12. The detection substrate according to claim 11, wherein: A projection of the semiconductor layer in the first direction overlaps with a projection of the first via hole in the first direction.
13. The detection substrate according to claim 12, wherein: The semiconductor layer includes a channel region, and an orthographic projection of the bottom electrode on the substrate does not overlap with an orthographic projection of the channel region on the substrate.
14. The detection substrate according to any one of claims 1 to 4, wherein: The orthographic projection of the bottom electrode on the substrate is flush with at least a portion of the boundary of the orthographic projection of the first electrode on the substrate.
15. The detection substrate according to any one of claims 1 to 14, wherein: The first electrode is an N-gon, where N is greater than or equal to 5.
16. The detection substrate according to any one of claims 1 to 14, wherein: A second recess is provided on at least one side of the second electrode in the second direction where the second electrode is connected to the scan line.
17. The detection substrate according to claim 16, wherein: The orthographic projection of the semiconductor layer on the substrate does not overlap with the orthographic projection of the second recess on the substrate.
18. The detection substrate according to any one of claims 1 to 14, wherein: Also includes a bias line, the bias line is electrically connected to the photoelectric converter through a second via hole, The orthographic projection of the bias line on the base substrate covers the orthographic projection of the first via hole on the base substrate.
19. The detection substrate according to any one of claims 1 to 4, wherein: The thin film transistor further comprises a gate, and a fourth recess is formed on a side of the gate close to the first via hole in the first direction.
20. The detection substrate according to any one of claims 1 to 4, wherein: An interlayer insulating layer is provided between the thin film transistor and the bias line, the interlayer insulating layer has a third via hole, and the scan line is electrically connected to the second electrode through the third via hole.
21. The detection substrate of claim 20, wherein the scan line and the bias line are in the same layer.
22. A flat panel detector, wherein: It comprises a detection substrate as described in any one of claims 1 to 21 and a non-visible light conversion layer covering the array substrate, wherein the non-visible light conversion layer is configured to convert non-visible light into visible light.