Chip test method and test system suitable for SMT (Surface Mount Technology) processing

Abstract

The invention discloses a chip test method suitable for SMT processing and a corresponding test system, and belongs to the technical field of chip test methods suitable for SMT processing, the method comprises the following steps: collecting test data of each pin on a chip; identifying an area with the most concentrated problems through a spatial analysis method; identifying defect modes such as linearity, aggregation and periodicity by utilizing a mode identification algorithm, and calculating characteristic parameters such as direction angle, center coordinate, coverage radius, period and direction of the defect; according to the defect types and the characteristic parameters, targeted AOI scanning strategy adjustment suggestions and technological parameter optimization suggestions are generated; the method can be widely applied to defect detection and analysis in the fields of integrated circuits, LEDs, PCBs and the like.

Description

Technical Field

[0001] The present invention belongs to the technical field of chip testing methods applicable to SMT processing, and particularly relates to a chip testing method and a testing system applicable to SMT processing. Background Art

[0002] In the field of SMT manufacturing, with the continuous improvement of the integration degree of integrated circuits, the chip size is continuously reduced, the number of pins is continuously increased, and the requirements for manufacturing processes are also getting higher and higher. Due to the influence of equipment precision, process parameter fluctuations, environmental factors, etc., various defects will inevitably occur, such as open circuits, short circuits, bridging, etc. These defects will cause abnormal chip functions or even failures, seriously affecting the yield and reliability of products.

[0003] For traditional detection of chip defects, the chip is paired with a matching peripheral circuit, and after the chip works, the dynamic output data of its circuit is measured; This method results in a complex matching peripheral circuit due to different chip types and numbers of functions, and a large number of output data types to be measured, leading to a high cost of measuring instruments; At the same time, for existing detection methods, the power supply and signal input of the peripheral circuit are made to work normally, and then the dynamic output data is detected. This not only has low efficiency, but also there is a risk of power-on damage to the chip. At the same time, the testing of pin feet is slow. For chips with a large number of pin feet, the testing efficiency is low; the speed of data storage, reading, and processing is not fast enough. Summary of the Invention

[0004] The purpose of the present invention is to provide a chip testing method applicable to SMT processing to solve several problems raised in the above background art.

[0005] To achieve the above purpose, the present invention provides the following technical solution: A chip testing method applicable to SMT processing; including the following steps: a) Collect test data of each pin on the chip; b) Identify the area where problems are most concentrated; c) Identify and classify defect modes; d) Calculate characteristic parameters of various defects; e) Feedback to the front end of the SMT processing process for process adjustment according to the defect type and characteristic parameters.

[0006] As a preferred implementation manner, step b) includes: Traverse all problem pin pairs (pi, pj); Calculate the circle with each pair of pins as the diameter, where the center coordinates are ((xi + xj) / 2, (yi + yj) / 2) and the radius is √[(xi - xj)² + (yi - yj)²] / 2; Calculate the number of problem pins contained within each circle; Select the circle containing the most problem pins as the area with the most concentrated problems.

[0007] As a preferred implementation, when identifying defect patterns in step c), analyze and identify linear defects, clustering defects, and periodic defects; Among them, use the least squares method to fit a straight line to the problem pins; calculate the distance from all points to the fitted straight line; when the distance of more than a preset proportion or preset number of problem pins is less than the preset distance threshold, it is determined as a linear defect; Use the DBSCAN algorithm to cluster the problem pins; if at least one dense cluster is formed, it is determined as a clustering defect; Calculate the distance between adjacent problem pins; calculate the average value of these distances; if the difference between all distances and the average value is less than the preset threshold, it is determined as a periodic defect.

[0008] As a preferred implementation, step d) includes: Calculate the direction angle of the linear defect: θ = arctan(m) × 180° / π, where m is the slope of the fitted straight line; Calculate the center coordinates of the clustering defect: (xc, yc) = (Σxi / n, Σyi / n) and the coverage radius: R = max{√[(xi - xc)² + (yi - yc)²]}; Calculate the period length of the periodic defect: P = the average value of the spacing between adjacent problem pins and the direction: φ = arctan(Δy / Δx) × 180° / π, where Δx and Δy are the average displacements of adjacent pins.

[0009] As a preferred implementation, step e) includes the following steps: For linear defects, increase the AOI scan density in the defect direction θ and check the device alignment in the same direction as θ; For clustering defects, increase the AOI scan density in the area with a radius of R around the defect center (xc, yc) and check the process parameter distribution in this area; For periodic defects, adjust the AOI scan interval to an integer multiple of the period P and check the device components related to the period P.

[0010] As a preferred implementation, for linear defects, if a linear defect parallel to the scraper movement direction appears, that is, the angle between θ and the scraper movement direction is less than 15°; if a linear defect perpendicular to the scraper movement direction appears, that is, the angle between θ and the scraper movement direction is greater than 75°, the scraper pressure is reduced by 5%-10%; excessive pressure will cause the solder paste to be squeezed to the edge of the screen opening, forming a thin line perpendicular to the scraper direction; at the same time, check for local wear or deformation of the scraper; The component is systematically offset in the θ direction, and the XY axis compensation parameters of the placement machine are corrected according to the offset; In the θ direction, the reflow temperature rise rate or peak temperature deviation exceeds 5°C; the temperature curve test results are required to adjust the temperature setting value of the corresponding temperature zone or the fan speed in a targeted manner; after adjustment, re-test the temperature curve until the deviation is less than 3°C.

[0011] As a preferred embodiment, for periodic defects, the solder paste thickness or width presents periodic changes along the φ direction, with a period of P; the printing speed is adjusted to (1 ± 1 / n) * V, where V is the original printing speed and n is an integer greater than 1; the resonance with the defect period P is staggered; The component placement position shows a periodic shift along the φ direction, with a period of P; the placement speed is adjusted to (1 ± 1 / n) * V, where V is the original placement speed and n is an integer greater than 1; the resonance with the defect period P is staggered; The weld spot presents periodic defects of different sizes or shapes along the φ direction, with a period of P; the chain speed is adjusted to (1± 1 / n) * V, where V is the original chain speed and n is an integer greater than 1; the resonance with the defect period P is staggered.

[0012] As a preferred embodiment, for clustering defects, within the R range near (xc, yc), the solder paste printing thickness is 20% higher than other areas; the screen opening size within the R range near (xc, yc) is reduced by 5%-10%; If the reflow soldering heating rate exceeds 3°C / s within the radius R of the coordinate (xc, yc), the heating slope of the corresponding temperature zone in this position range will be reduced.

[0013] The present invention also provides a testing system for implementing the above method. Including test machine; The test machine comprises: Data acquisition module: Located inside the test machine, it includes test probes and a signal acquisition unit; the test probes are in contact with the pins on the chip to obtain electrical characteristic data of the pins, including voltage, current, and resistance; the signal acquisition unit converts analog signals into digital signals and transmits them to the host computer; Chip fixing device: Used to fix the chip to be tested to ensure good contact between the chip and the test probes.

[0014] The host computer includes: A data processing module, which includes a processor and a memory, and is used to process data from the test machine; the memory stores test data, defect information, analysis results, and a process parameter database; A spatial analysis module, based on the test data, by calculating the number of problematic pins within the circle with the pin pair as the diameter, identifies the area where the problems are most concentrated; A pattern recognition module, according to the results of the spatial analysis module, uses algorithms to identify defect patterns such as linearity, aggregation, and periodicity; A feature calculation module, which calculates the characteristic parameters of various types of defects, such as the direction angle of linear defects, the center coordinates and coverage radius of aggregation defects, and the period and direction of periodic defects; An optimization suggestion module, according to the defect type, characteristic parameters, and the process parameter database, generates adjustment suggestions for the AOI scanning strategy and process optimization suggestions, and can output the optimization suggestions to the control systems of related equipment such as AOI equipment, screen printers, pick-and-place machines, reflow ovens, etc.

[0015] It also includes a communication interface: Connects the host computer and the test machine, as well as AOI equipment, production execution system (MES), etc., to achieve high-speed data transmission. It can be Ethernet, RS232, GPIB, etc.

[0016] It also includes a user interface: Located on the host computer, it provides a graphical interface for displaying test data, defect distribution maps, analysis results, and optimization suggestions, and allows users to perform operations such as parameter setting and viewing historical data.

[0017] Compared with the prior art, the beneficial effects of the present invention are: This method not only focuses on the problems of individual pins, but also searches for the areas where problems are concentrated; it helps to identify problems that may be caused by systematic factors (such as uneven temperature distribution or inappropriate pressure in a certain area). Simply recording each pin may ignore the spatial distribution characteristics of the problems.

[0018] By identifying the areas with the most concentrated problems, the production process can be adjusted more specifically. For example, the accuracy of AOI detection can be increased in specific areas, or the reflow soldering parameters in that area can be adjusted; in contrast, analyzing the problems of individual pins alone may be difficult to provide such regional insights.

[0019] This solution reduces the impact of data noise. In actual production, the problems of individual pins may be random or occasional. By analyzing multiple pins within an area, the true systematic problems can be better identified; this method can better filter out the random failures of individual pins and focus on the areas that really need attention.

[0020] This solution can greatly improve the analysis efficiency: For large chips with hundreds or thousands of pins, analyzing the problems of each pin one by one may be very time-consuming and inefficient; by finding the areas with the most concentrated problems, the parts that most need attention can be quickly located, improving the analysis efficiency; the traditional method needs to traverse all combinations of pin coordinates, with a time complexity of O(n^4); step b) of this solution adopts a new method to reduce the complexity to O(n^3). For chips with a large number of pins, the calculation speed is greatly increased. At the same time, the traditional method can only find the problems of individual pins, while this solution can identify linear defects (possibly printing direction problems); clustered defects (possibly local temperature anomalies); periodic defects (possibly equipment vibration problems). This solution can predict potential problem areas through pattern recognition: if linear defects are found, it can be predicted that the pins on the extension line of the straight line may also have problems; if periodic defects are found, the risk of pins at the next periodic position can be predicted for AOI optimization guidance; In the prior art, the complete information of each pin needs to be stored, resulting in a huge storage volume and slow reading efficiency. However, this solution can store only the pattern features instead of the complete information, which can greatly reduce the data storage requirements. At the same time, this storage method is also convenient for the rapid transmission and sharing of data. Brief Description of the Drawings

[0022] Figure 1 It is a schematic flowchart of the method of the present invention; Figure 2 It is a system architecture diagram of the present invention. Detailed Embodiment Embodiment

[0023] Please refer to Figure 1-2 , the present invention provides a chip testing method applicable to SMT processing, including the following steps: including the following steps: a) Collect the test data of each pin on the chip; b) Identify the area where problems are most concentrated; c) Identify and classify defect patterns; d) Calculate the characteristic parameters of various types of defects; e) Feed back according to the defect type and characteristic parameters to the front end of the SMT processing process for process adjustment.

[0024] Specifically: a) Collect the test data of each pin on the chip, that is, test the open state of any pin combination, where the open determination condition is that the resistance value is greater than the preset threshold; - Test the short - circuit state of any pin combination, where the short - circuit determination condition is that the resistance value is less than the preset threshold; - Test the resistance value between any two pins and determine whether it is within the preset range; - Test the capacitance value between any two pins and determine whether it is within the preset range; - Test the diode value between any two pins and determine whether it is within the preset range.

[0025] b) Identify the area where problems are most concentrated, Traverse all problem pin pairs (pi, pj); Calculate the circle with each pair of pins as the diameter, the center coordinates are ((xi + xj) / 2, (yi + yj) / 2), and the radius is √[(xi - xj)² + (yi - yj)²] / 2; For each circle, calculate the number of problem pins it contains: Judgment condition: (x - xc)² + (y - yc)² ≤ r².

[0026] Select the circle containing the most problem pins as the optimal problem area.

[0027] c) When identifying defect patterns, analyze and identify linear defects, clustering defects, and periodic defects; use the least - squares method to fit a straight line to the problem pins; calculate the distance from all points to the fitted straight line; when the distance introduced by more than the preset proportion or preset number of problems is less than the preset distance threshold, it is determined as a linear defect; set the straight - line equation as y = mx + b For n points (xi, yi), minimize the sum of squared errors: E = Σ(yi - (mxi + b))² Solve ∂E / ∂m = 0 and ∂E / ∂b = 0, and get: m = (n·Σ(xiyi) - Σxi·Σyi) / (n·Σ(xi²) - (Σxi)²) b = (Σyi - m·Σxi) / n Judgment criterion: Calculate the distance from all points to the fitted line: d = |yi - (mxi + b)| / √(m² + 1). If the distances of more than a preset number of points (such as 80%) are less than the preset threshold, it is considered a linear defect; Linear defect direction angle: Use the slope m obtained by the least squares method to calculate the angle: θ = arctan(m) × 180° / π.

[0028] For clustering defect identification: Use the DBSCAN (Density-Based Spatial Clustering of Applications with Noise) algorithm. 1. Select an unvisited point P. 2. Find all points within the ε-neighborhood of P.

[0029] If the number of points in the neighborhood ≥ MinPts, form a new cluster. Otherwise, mark P as a noise point. 4. Repeat steps 2 - 3 for each point in the new cluster to expand the cluster. 5. Repeat 1 - 4 until all points are visited. If at least one dense cluster (the number of points is greater than the threshold) is formed, it is considered that there is a clustering defect; Clustering defect center and radius: Center coordinates: (xc, yc) = (Σxi / n, Σyi / n); Coverage radius: R = max{√[(xi - xc)² + (yi - yc)²]}.

[0030] For periodic defect identification: Calculate the distance between adjacent points: di = √[(xi+1 - xi)² + (yi+1 - yi)²]; Calculate the average value of these distances: davg = (Σdi) / (n - 1); Calculate the difference between each distance and the average value: Δi = |di - davg|; If all Δi are less than the preset threshold, it is considered that there is a periodic defect; Periodic defect period and direction: Period: P = davg; Direction: Calculate the average displacement vector of adjacent points: Δx = Σ(xi+1 - xi) / (n - 1) Δy = Σ(yi+1 - yi) / (n - 1) Direction angle: φ = arctan(Δy / Δx) × 180° / π.

[0031] For linear defects, if a linear defect parallel to the scraper movement direction appears, that is, the angle between θ and the scraper movement direction is less than 15°; adjust the scraper angle by 15°-30°; if a linear defect perpendicular to the scraper movement direction appears, that is, the angle between θ and the scraper movement direction is greater than 75°; reduce the scraper pressure by 5%-10%; excessive pressure will cause the solder paste to be squeezed to the edge of the screen opening, forming a thin line perpendicular to the scraper direction; at the same time, check for local wear or deformation of the scraper; The component is systematically offset in the θ direction, and the XY axis compensation parameters of the placement machine are corrected according to the offset; In the θ direction, the reflow temperature rise rate or peak temperature deviation exceeds 5°C; the temperature curve test results are required to adjust the temperature setting value of the corresponding temperature zone or the fan speed in a targeted manner; after adjustment, re-test the temperature curve until the deviation is less than 3°C.

[0032] For periodic defects, the solder paste thickness or width changes periodically along the φ direction, with a period of P. The printing speed is adjusted to (1 ± 1 / n) * V, where V is the original printing speed and n is an integer greater than 1. The resonance with the defect period P is staggered. The component placement position shows a periodic shift along the φ direction, with a period of P; the placement speed is adjusted to (1 ±1 / n) * V, where V is the original placement speed and n is an integer greater than 1; the resonance with the defect period P is staggered; The weld spot presents periodic defects of different sizes or shapes along the φ direction, with a period of P; the chain speed is adjusted to (1± 1 / n) * V, where V is the original chain speed and n is an integer greater than 1; the resonance with the defect period P is staggered.

[0033] For clustered defects, the solder paste printing thickness in the R range near (xc, yc) is 20% higher than that in other areas; reduce the screen opening size in the R range near (xc, yc) by 5%-10%; If the reflow soldering heating rate exceeds 3°C / s within the radius R of the coordinate (xc, yc), the heating slope of the corresponding temperature zone in this position range will be reduced.

[0034] As a preferred embodiment, the present solution also relates to a test system for implementing the above method. Including test machine; The test machine comprises: Data acquisition module: Located inside the test machine, it includes test probes and a signal acquisition unit; the test probes are in contact with the pins on the chip to obtain electrical characteristic data of the pins, including voltage, current, and resistance; the signal acquisition unit converts analog signals into digital signals and transmits them to the host computer; Chip fixing device: Used to fix the chip to be tested to ensure good contact between the chip and the test probes.

[0035] The host computer includes: A data processing module, which includes a processor and a memory, and is used to process data from the test machine; the memory stores test data, defect information, analysis results, and a process parameter database; A spatial analysis module, based on the test data, by calculating the number of problem pins within the circle with the pin pair as the diameter, identifies the area where the problems are most concentrated; A pattern recognition module, according to the results of the spatial analysis module, uses algorithms to identify defect patterns such as linearity, aggregation, and periodicity; A feature calculation module, which calculates the characteristic parameters of various types of defects, such as the direction angle of linear defects, the center coordinates and coverage radius of aggregation defects, and the period and direction of periodic defects; An optimization suggestion module, according to the defect type, characteristic parameters, and the process parameter database, generates adjustment suggestions for the AOI scanning strategy and process optimization suggestions, and outputs the optimization suggestions to the control systems of relevant devices; It also includes a communication interface: Connects the host computer with the test machine, as well as the AOI device and the MES system to achieve high-speed data transmission; It also includes a user interface: Located on the host computer, it provides a graphical interface for displaying test data, defect distribution maps, analysis results, and optimization suggestions.

[0036] This solution quickly locates the problem area through spatial analysis, uses pattern recognition technology to accurately identify the defect type and calculate the key characteristic parameters. Based on this, it can deeply trace the root cause of the defect and provide specific and refined process optimization and AOI scanning strategy adjustment suggestions. This method realizes the closed-loop control of detection, analysis, and improvement. Finally, it can significantly improve the defect detection rate, increase the product yield, reduce the production cost, and enhance the competitiveness of the enterprise.

[0037] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and not to limit them. Although the present invention has been described in detail with reference to the preferred embodiments, those of ordinary skill in the art should understand that the technical solutions of the present invention can be modified or equivalently replaced without departing from the purpose and scope of the technical solutions of the present invention, and they should all be covered within the scope of the claims of the present invention.

Claims

1. A chip testing method suitable for SMT processing, characterized in that: The following steps are involved: a) Collect test data of each pin on the chip; b) identify the areas where problems are most concentrated; c) identify and classify defect patterns; d) Calculate the characteristic parameters of various defects; e) Feedback the defect type and characteristic parameters to the front end of the SMT processing step for process adjustment.

2. The chip testing method suitable for SMT processing according to claim 1, characterized in that: Step b) comprises: Traverse all problematic pin pairs (pi, pj); Calculate the circle with each pair of pins as the diameter, the center coordinates are ((xi+ xj) / 2, (yi+ yj) / 2), and the radius is √[(xi - xj)² + (yi - yj)²] / 2; Count the number of problematic pins contained in each circle; The circle containing the most problematic pins is selected as the area where the problems are most concentrated.

3. The chip testing method suitable for SMT processing according to claim 2, characterized in that: Step c) When identifying defect modes, linear defects, clustered defects, and periodic defects are analyzed and identified; The least square method is used to fit a straight line to the problem pin; the distances from all points to the fitted straight line are calculated; When the distance introduced by the problems exceeding the preset ratio or the preset number is less than the preset distance threshold, it is determined as a linear defect; Use the DBSCAN algorithm to cluster the problem pins; if at least one dense cluster is formed, it is determined to be a cluster defect; Calculate the distances between adjacent problematic pins; calculate the average of these distances; if the difference between all distances and the average is less than a preset threshold, it is determined to be a periodic defect.

4. The chip testing method suitable for SMT processing according to claim 3, characterized in that: Step d) comprises: Calculate the direction angle of the linear defect: θ = arctan(m)180° / π, where m is the slope of the fitting line; Calculate the center coordinates of the clustered defect: (xc, yc) = (Σxi / n, Σyi / n) and the coverage radius: R = max{√[(xi-xc)² + (yi-yc)²]}; Calculate the period length of a periodic defect: P = the average distance between adjacent problematic pins, and direction: φ = arctan(Δy / Δx) 180° / π, where Δx and Δy are the average displacements between adjacent pins.

5. The chip testing method suitable for SMT processing according to claim 4, characterized in that: Step e) comprises the following steps: For linear defects, increase the AOI scan density in the defect direction θ and check the device alignment consistent with the θ direction; For clustered defects, increase the AOI scanning density in the area with a radius R around the defect center (xc, yc) and check the process parameter distribution in this area; For periodic defects, adjust the AOI scanning interval to an integer multiple of the period P, and inspect the equipment parts related to the period P.

6. The chip testing method suitable for SMT processing according to claim 5, characterized in that: For linear defects, if a linear defect parallel to the scraper movement direction appears, that is, the angle between θ and the scraper movement direction is less than 15°; adjust the scraper angle by 15°-30°; if a linear defect perpendicular to the scraper movement direction appears, that is, the angle between θ and the scraper movement direction is greater than 75°; reduce the scraper pressure by 5%-10%; excessive pressure will cause the solder paste to be squeezed to the edge of the screen opening, forming a thin line perpendicular to the scraper direction; at the same time, check for local wear or deformation of the scraper; The component is systematically offset in the θ direction, and the XY axis compensation parameters of the placement machine are corrected according to the offset; In the θ direction, the reflow temperature rise rate or peak temperature deviation exceeds 5°C; the temperature curve test results are required to adjust the temperature setting value of the corresponding temperature zone or the fan speed in a targeted manner; after adjustment, re-test the temperature curve until the deviation is less than 3°C.

7. The chip testing method suitable for SMT processing according to claim 6, characterized in that: For periodic defects, the solder paste thickness or width changes periodically along the φ direction, with a period of P; the printing speed is adjusted to (1 ± 1 / n)* V, where V is the original printing speed and n is an integer greater than 1; Stagger the resonance with the defect period P; The component placement position shows a periodic shift along the φ direction, with a period of P. The placement speed is adjusted to (1 ± 1 / n)* V, where V is the original placement speed and n is an integer greater than 1. Stagger the resonance with the defect period P; The weld spot presents periodic defects of different sizes or shapes along the φ direction, with a period of P; the chain speed is adjusted to (1 ± 1 / n) * V, where V is the original chain speed and n is an integer greater than 1; the resonance with the defect period P is staggered.

8. The chip testing method suitable for SMT processing according to claim 7, characterized in that: For clustered defects, the solder paste printing thickness in the R range near (xc, yc) is 20% higher than that in other areas; reduce the screen opening size in the R range near (xc, yc) by 5%-10%; If the reflow soldering heating rate exceeds 3°C / s within the radius R of the coordinate (xc, yc), the heating slope of the corresponding temperature zone in this position range will be reduced.

9. A chip defect testing system for implementing the method according to any one of claims 1 to 8, characterized in that: Including test machine; The test machine comprises: Data acquisition module: located inside the test machine, including a test probe and a signal acquisition unit; the test probe contacts the pins on the chip to obtain the electrical characteristic data of the pins including voltage, current, and resistance; the signal acquisition unit converts the analog signal into a digital signal and transmits it to the host computer; Chip fixture: used to fix the chip to be tested to ensure good contact between the chip and the test probe; The host computer comprises: The data processing module includes a processor and a memory for processing data from the test machine; the memory stores test data, defect information, analysis results and a process parameter database; The spatial analysis module, based on the test data, identifies the area where the problem is most concentrated by counting the number of problematic pins within a circle with the pin pair as the diameter; The pattern recognition module uses algorithms to identify linear, clustered, and periodic defect patterns based on the results of the spatial analysis module; Feature calculation module, which calculates the characteristic parameters of various defects, such as the direction angle of linear defects, the center coordinates and coverage radius of clustered defects, and the period and direction of periodic defects; The optimization suggestion module generates adjustment suggestions for AOI scanning strategies and process optimization suggestions based on defect types, characteristic parameters and process parameter databases, and outputs the optimization suggestions to the control system of related equipment; Also includes communication interfaces: Connect the host computer and test machine, as well as AOI equipment and MES system to achieve high-speed data transmission; Also includes the user interface: Located on the host computer, it provides a graphical interface for displaying test data, defect distribution diagrams, analysis results, and optimization suggestions.

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