A parameter optimization method and computer equipment for chip electromagnetic fault injection testing

Abstract

The present invention discloses a parameter optimization method for chip electromagnetic fault injection testing, comprising: collecting electromagnetic fault injection test data from a large number of training chips to construct a training dataset; using the constructed training dataset to train multiple models and establish a mapping relationship between electromagnetic fault injection parameters and attack success rates; collecting a small amount of electromagnetic fault injection test data from a new model of chip to be tested; using the new model of chip to be tested data to perform transfer learning on the trained models, and selecting the optimal model from the transfer-learned models; determining the value range of the electromagnetic fault injection parameters for the new model of chip to be tested, constructing a multidimensional parameter space, and using the Latin hypercube sampling method to generate uniformly distributed parameter combinations; inputting the parameter combinations into the optimal model, predicting the attack success rate of each parameter combination, and selecting the optimal parameter combination for the electromagnetic fault injection test. The present invention can automatically optimize electromagnetic fault injection parameter combinations, reducing manual tuning costs.

Description

Technical Field

[0001] The invention belongs to the field of electromagnetic fault injection testing, and in particular relates to a parameter optimization method and computer equipment for chip electromagnetic fault injection testing. Background Art

[0002] Electromagnetic fault injection testing is an important means of evaluating the functional safety of chips. Its core is to trigger chip faults by adjusting electromagnetic parameters (such as frequency, intensity, coordinate position, etc.) to verify its anti-interference ability. During the test process, there are multiple test conditions and parameters that need to be reasonably selected, otherwise the test efficiency and accuracy will be affected. Traditional methods rely on manual experience for parameter selection and optimization, but they have the following problems: (1) High cost: a large number of repeated experiments are required to explore effective parameter combinations, which is time-consuming and wastes resources seriously; (2) Low efficiency: manual tuning is difficult to cover the multi-dimensional electromagnetic fault injection parameter space, it is difficult to grasp the optimal parameter combination, and it is easy to fall into the local optimal result; (3) Poor portability: for new models of tested chips, due to differences in physical properties, traditional models cannot be directly migrated, and test parameters need to be readjusted and optimized. When performing electromagnetic fault injection testing on chips of the same series, parameter tuning still relies on independent testing of each model. This method fails to fully utilize the similarities between chips of the same series and historical test data, resulting in a time-consuming and costly detection process. Summary of the Invention

[0003] The purpose of the present invention is to provide a parameter optimization method, computer equipment, computer-readable storage medium and computer program product for chip electromagnetic fault injection testing, which can automatically optimize the electromagnetic fault injection parameter combination, reduce the cost of manual tuning, realize the rapid migration of parameter optimization models between different types of chips, reduce the demand for new types of tested chip data, and improve the efficiency and accuracy of parameter tuning in small sample scenarios.

[0004] To achieve the above objectives, one aspect of the present invention provides a parameter optimization method for a chip electromagnetic fault injection test, comprising:

[0005] Step S1, collecting electromagnetic fault injection test data of a large number of training chips to construct a training data set;

[0006] Step S2: using the constructed training data set to train multiple models and establish a mapping relationship between electromagnetic fault injection parameters and attack success rate;

[0007] Step S3, collecting a small amount of electromagnetic fault injection test data of the new model chip to be tested, and integrating it into a data set input format that is the same as the training data set;

[0008] Step S4, using the new model chip data to be tested to perform transfer learning on the trained model, so that the model adapts to the new model chip data to be tested, and selecting the optimal model from the transfer learning models;

[0009] Step S5, determining the value range of the electromagnetic fault injection parameter of the new model chip to be tested, constructing a multidimensional parameter space of the electromagnetic fault injection parameter, and using the Latin hypercube sampling method to generate uniformly distributed parameter combinations;

[0010] Step S6: input the generated parameter combination into the optimal model after transfer learning, predict the attack success rate of each parameter combination, and select the optimal parameter combination for electromagnetic fault injection test based on the predicted attack success rate.

[0011] Preferably, in step S2, the plurality of models include a random forest model, a gradient boosting model, a gradient enhancement model and a neural network model;

[0012] In step S4, the transfer learning strategy includes:

[0013] For the random forest model, the number of trees is dynamically adjusted and a category weight balancing strategy is adopted to adapt to the data of the new model chip to be tested;

[0014] For the gradient boosting model and the gradient enhancement model, the learning rate is reduced to 50% of the original value and the number of weak learners is dynamically set according to the data size of the new chip to be tested;

[0015] For the neural network model, the original network structure is retained, the learning rate is reduced to 50% and the number of iterations is increased to fully adapt to the data of the new model chip to be tested.

[0016] Preferably, in step S4, the model after transfer learning is comprehensively evaluated using two indicators, F1 score and area under the ROC curve, and the model with the highest score is determined as the optimal model.

[0017] Preferably, in step S2, the electromagnetic fault injection parameters include X-axis coordinates, Y-axis coordinates, power and delay; in step S5, the multi-dimensional parameter space is a four-dimensional parameter space.

[0018] Preferably, in step S6, all parameter combinations are sorted according to the predicted attack success rates, and the top 10 parameter combinations in terms of attack success rates are selected as the optimal parameter combinations for the electromagnetic fault injection test.

[0019] Another aspect of the present invention provides a computer device, comprising a memory, a processor, and a computer program stored in the memory, wherein the processor executes the computer program to implement the steps of the above method.

[0020] Another aspect of the present invention provides a computer-readable storage medium having a computer program stored thereon, which implements the steps of the above method when executed by a processor.

[0021] Yet another aspect of the present invention provides a computer program product, comprising a computer program, which implements the steps of the above method when executed by a processor.

[0022] According to the parameter optimization method, computer equipment, computer-readable storage medium and computer program product for chip electromagnetic fault injection testing of the above aspects of the present invention, it is possible to automatically optimize the electromagnetic fault injection parameter combination, reduce the cost of manual tuning, realize the rapid migration of parameter optimization models between different types of chips, reduce the demand for data of new models of tested chips, and improve the efficiency and accuracy of parameter tuning in small sample scenarios. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] In order to more clearly illustrate the technical solutions of the present invention, the following briefly introduces the drawings used in the description of the embodiments of the present invention. Obviously, the drawings described below are only some embodiments of the present invention. Those skilled in the art can also derive other drawings based on these drawings without inventive efforts.

[0024] Figure 1 is a flow chart of a chip electromagnetic fault injection parameter optimization method according to an embodiment of the present invention;

[0025] Figure 2 It is a structural diagram of a computer device according to an embodiment of the present invention. DETAILED DESCRIPTION

[0026] To make the objectives, technical solutions, and advantages of the present invention more clear, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the embodiments described are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts shall fall within the scope of protection of the present invention.

[0027] An embodiment of the present invention provides a chip electromagnetic fault injection parameter optimization method, such as Figure 1 As shown, the chip electromagnetic fault injection parameter optimization method according to the embodiment of the present invention includes steps S1 to S6.

[0028] In step S1, electromagnetic fault injection test data of a large number of training chips are collected to provide training data for the model in step S2.

[0029] A large number of electromagnetic fault injection tests are performed on the training chip. The result of each fault injection is a sampling point. The test results are processed and integrated into a dataset input format allowed by the model in step S2. The allowed dataset input format is as follows, where the attack success is marked as 0 / 1, where 0 indicates that the attack was unsuccessful and 1 indicates that the attack successfully caused a fault (the attack was successful):

[0030] X-axis coordinate of the sampling point;

[0031] (2) Y-axis coordinate of the sampling point;

[0032] (3) Sampling point power;

[0033] (4) Sampling point delay;

[0034] (5) Sampling point attack success mark.

[0035] In step S2, the constructed training dataset is used to train multiple models in the model library. In one embodiment, the multiple models include four models: a gradient boosting model (GBM), a random forest model (RF), an XGBoost model, and a neural network model (CNN).

[0036] The trained model establishes a nonlinear mapping relationship between fault injection parameters (feature variables) and attack success rate (target variable) through a supervised learning framework, and is capable of undertaking the prediction task of predicting the probability of attack success for a set of fault injection parameters.

[0037] In step S3, a small amount of electromagnetic fault injection test data of the new model chip to be tested is collected: a small amount of electromagnetic fault injection test is performed on the new model chip to be tested, and the test results are processed and integrated into a data set input format that is the same as the training data set in step S1.

[0038] In step S4, transfer learning is applied to adapt the model to the new chip model. Specifically, transfer learning is performed on the four models trained in step S2 using a small amount of data from the chip under test in step S3, resulting in four models adapted to the data from step S3. These four models are then subjected to an optimal model selection mechanism to determine the optimal model used to predict the optimal parameter combination in step S6.

[0039] In one embodiment, a transfer learning technique called parameter fine-tuning is employed. This approach preserves the fundamental knowledge structure of the original model while efficiently adapting the model to the electromagnetic fault response characteristics of the new chip under test by precisely adjusting specific parameters (such as the learning rate, number of trees, and class weights). The core goal of this invention is to leverage the abundant electromagnetic fault injection data from the training chips (the source domain) to enhance the model's predictive capabilities for the new chip under test (the target domain), significantly reducing the amount of test data required for the new chip under test. In this invention, given the high similarity between the source and target domains, this simple transfer learning framework is sufficiently effective.

[0040] The transfer learning of the embodiment of the present invention includes an adaptation strategy for different models and an optimal model selection mechanism, including the following steps:

[0041] (a) Data preprocessing and standardization: The data here comes from the electromagnetic fault injection test data of the new model chip under test collected in step S3.

[0042] (b) Different transfer learning strategies are adopted for different models: (i) The random forest model adapts to the data of the new model chip under test by dynamically adjusting the number of trees and adopting a category weight balancing strategy; (ii) The gradient boosting model reduces the learning rate to 50% of the original value and dynamically sets the number of weak learners according to the scale of the new data; (iii) The gradient boosting model also adopts the method of halving the learning rate and dynamically adjusting the number of weak learners to improve the adaptability of the model on the new model chip under test; (iv) The neural network model retains the original network structure, reduces the learning rate to 50% and increases the number of iterations to fully adapt to the characteristics of the new model chip under test.

[0043] (c) Model Performance Evaluation: The performance of the transferred learning model is comprehensively evaluated using the F1 score and the area under the receiver operating characteristic (ROC) curve (AUC). The model with the highest F1 and AUC scores is determined to be the optimal model. This optimal model selection mechanism comprehensively evaluates the performance of different transferred learning models and selects the prediction model that best suits the characteristics of the new chip model.

[0044] In step S5, the numerical range of the electromagnetic fault injection parameters of the new chip model is determined and sampled. In one embodiment, the value ranges of the four parameters in the fault injection test data of the new chip model under test in step S3 are determined, for example, the power range is (0%-100%), thus obtaining a four-dimensional parameter space of the electromagnetic fault injection parameters.

[0045] For the four-dimensional parameter space obtained above, Latin hypercube sampling was used to generate 10,000 sets of evenly distributed sample points, ensuring uniform distribution of edges in each dimension and no clustering in the multidimensional space. Each parameter combination is represented by the following: (X-axis coordinate, Y-axis coordinate, power, delay).

[0046] The Latin hypercube sampling method for electromagnetic fault injection parameter space ensures uniform distribution of sampling points in the multidimensional parameter space, effectively covering the parameter space and improving sampling efficiency. Efficient parameter space exploration is achieved with 10,000 sets of sampling points.

[0047] In step S6, the optimal parameter combination for electromagnetic fault injection testing of the new chip under test is predicted. Specifically, the 10,000 uniformly distributed parameter combinations generated in step S5 are input into the optimal model obtained in step S4, and the attack success rate of each parameter combination is predicted. These 10,000 parameter combinations are ranked based on the predicted attack success rates, and the top 10 parameter combinations with the highest attack success rates are selected as the optimal parameter combinations for electromagnetic fault injection testing.

[0048] In summary, the parameter optimization method for chip electromagnetic fault injection testing according to an embodiment of the present invention is an electromagnetic fault injection parameter optimization method based on multi-model integration and transfer learning. This method combines the predictive capabilities of multiple models (gradient boosting, random forest, gradient boosting, and neural network models) and uses transfer learning techniques to achieve knowledge transfer from training chip data to the new model of chip under test. Specifically, the method according to an embodiment of the present invention thoroughly analyzes historical chip electromagnetic fault injection test data and utilizes an artificial intelligence algorithm to learn and obtain the relationship between the attack success probability of a sample point and various electromagnetic fault injection parameters (including X-axis coordinates, Y-axis coordinates, power, and delay). Based on this, transfer learning is performed by leveraging the similarities between the current new model of chip under test and historical data to predict the optimal parameter combination for electromagnetic fault injection testing of the current chip under test. This enables rapid and efficient completion of electromagnetic fault injection testing, significantly improving testing efficiency.

[0049] The method of the embodiment of the present invention has the following beneficial effects:

[0050] (1) Automated optimization of parameter combinations: By introducing automated optimization methods, the parameter combination can be automatically adjusted during the electromagnetic fault injection process, thereby reducing the cost of manual intervention and tuning. The optimization process is more efficient and can significantly improve experimental efficiency.

[0051] (2) Rapid cross-chip model migration: This enables rapid cross-chip model migration, enabling rapid adaptation and tuning of electromagnetic fault injection parameters in the testing of new chip models, reducing the need for large amounts of data. This is particularly effective in small sample scenarios, improving the efficiency and accuracy of parameter tuning for new chip models.

[0052] (3) Reduced experimental costs: By reducing the reliance on manual tuning and large amounts of labeled data, the overall cost of electromagnetic fault injection experiments is significantly reduced. The optimized automation process reduces the investment in manpower and time, and improves the economic benefits of the overall experiment.

[0053] The embodiment of the present invention further provides a computer device, which may be a server, and its internal structure diagram may be as shown in FIG. Figure 2 As shown. The computer device includes a processor, a memory and a network interface connected via a system bus. The processor of the computer device is used to provide computing and control capabilities. The memory of the computer device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system, a computer program and a database. The internal memory provides an environment for the operation of the operating system and computer program in the non-volatile storage medium. The database of the computer device is used to store operating parameter data of each framework. The network interface of the computer device is used to communicate with an external terminal via a network connection. When the computer program is executed by the processor, the steps of the method of the embodiment of the present invention are implemented.

[0054] Those skilled in the art will understand that Figure 2 The structure shown in the figure is only a block diagram of a part of the structure related to the solution of the present application, and does not constitute a limitation on the computer device to which the solution of the present application is applied. The specific computer device may include more or fewer components than shown in the figure, or combine certain components, or have a different component arrangement.

[0055] An embodiment of the present invention further provides a computer-readable storage medium having a computer program stored thereon, and when the computer program is executed by a processor, the steps of the method of the embodiment of the present invention are implemented.

[0056] An embodiment of the present invention further provides a computer program product, including a computer program, which implements the steps of the method of the embodiment of the present invention when executed by a processor.

[0057] The above description is merely illustrative of certain exemplary embodiments of the present invention. It goes without saying that those skilled in the art will be able to modify the described embodiments in various ways without departing from the spirit and scope of the present invention. Therefore, the above drawings and description are illustrative in nature and should not be construed as limiting the scope of protection of the claims.

Claims

1. A parameter optimization method for chip electromagnetic fault injection testing, characterized in that: include: Step S1, collecting electromagnetic fault injection test data of a large number of training chips to construct a training data set; Step S2: using the constructed training data set to train multiple models and establish a mapping relationship between electromagnetic fault injection parameters and attack success rate; Step S3, collecting a small amount of electromagnetic fault injection test data of the new model chip to be tested, and integrating it into a data set input format that is the same as the training data set; Step S4, using the new model chip data to be tested to perform transfer learning on the trained model, so that the model adapts to the new model chip data to be tested, and selecting the optimal model from the transfer learning models; Step S5, determining the value range of the electromagnetic fault injection parameter of the new model chip to be tested, constructing a multidimensional parameter space of the electromagnetic fault injection parameter, and using the Latin hypercube sampling method to generate uniformly distributed parameter combinations; Step S6: input the generated parameter combination into the optimal model after transfer learning, predict the attack success rate of each parameter combination, and select the optimal parameter combination for electromagnetic fault injection test based on the predicted attack success rate. In step S2, the electromagnetic fault injection parameters include X-axis coordinates, Y-axis coordinates, power and delay; in step S5, the multi-dimensional parameter space is a four-dimensional parameter space; In step S6, all parameter combinations are sorted according to the predicted attack success rates, and the top 10 parameter combinations in terms of attack success rates are selected as the optimal parameter combinations for the electromagnetic fault injection test.

2. The method according to claim 1, wherein In step S2, the plurality of models include a random forest model, a gradient boosting model, a gradient enhancement model, and a neural network model; In step S4, the transfer learning strategy includes: For the random forest model, the number of trees is dynamically adjusted and a category weight balancing strategy is adopted to adapt to the data of the new model chip to be tested; For the gradient boosting model and the gradient enhancement model, the learning rate is reduced to 50% of the original value and the number of weak learners is dynamically set according to the data size of the new chip to be tested; For the neural network model, the original network structure is retained, the learning rate is reduced to 50% and the number of iterations is increased to fully adapt to the data of the new model chip to be tested.

3. The method according to claim 1 or 2, wherein: In step S4, the model after transfer learning is comprehensively evaluated using the F1 score and the area under the ROC curve, and the model with the highest score is determined as the optimal model.

4. A computer device comprising a memory, a processor, and a computer program stored in the memory, characterized in that: The processor executes the computer program to implement the steps of the method according to any one of claims 1 to 3.

5. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the steps of the method according to any one of claims 1 to 3 are implemented.

6. A computer program product comprising a computer program, characterized in that When the computer program is executed by a processor, the steps of the method according to any one of claims 1 to 3 are implemented.

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