Burr testing method, device, system and computer equipment

Abstract

The present application relates to a glitch testing method, device, system and computer equipment. The method includes: determining scenario information, and determining each current target channel information based on the scenario information; controlling the unit under test to connect or disconnect the link of each current target channel based on each current target channel information, and controlling the load network of the load unit to connect to the unit under test; controlling the unit under test to output signals to the load network of the load unit through the link of each current target channel based on the scenario information, and each time the unit under test stops outputting signals, collecting the waveform information of the unit under test corresponding to the current target channel through an oscilloscope; and obtaining glitch information based on the collected waveform information. The use of this method can improve test efficiency.

Description

Technical Field

[0001] The present application relates to the field of testing technology, and in particular to a glitch testing method, device, system and computer equipment. Background Art

[0002] Currently, there are several main causes of circuit glitches: Circuit design factors: In digital circuits, signal glitches often arise from the race condition of combinational logic circuits. The impact of the switching process: When a transistor or other switching element transitions from the on state to the off state or vice versa, parasitic capacitance and inductance produce significant voltage and current change rates, leading to high voltage glitches on the stray inductance of the line. Noise coupling and voltage ripple: External electromagnetic interference, power supply ripple, and crosstalk between internal circuits can also cause signal glitches. The impacts of glitches on circuits include: Circuit reliability: Glitches can cause logic gates to falsely trigger, leading to circuit logic errors, and thus affecting the functionality and performance of the entire system. Electromagnetic compatibility (EMC): Severe glitches can exceed regulatory limits, radiate additional electromagnetic interference, and fail to meet EMC standards. Equipment lifespan: Frequent glitches can cause increased stress on semiconductor devices, accelerating aging and reducing equipment lifespan.

[0003] Traditionally, glitches have been detected manually using an oscilloscope to observe and capture signal glitches. However, in the test environment, circuit glitches are more likely to occur due to complex circuitry, numerous relay switches, high number of channels, and a variety of different test head types.

[0004] Traditionally, measuring glitches on test machines still relies on manually adjusting the oscilloscope trigger mode to capture glitches in different scenarios on the test machine board. This testing method is inefficient. Summary of the Invention

[0005] Based on this, it is necessary to provide a glitch testing method, device, system and computer equipment that can improve testing efficiency in response to the above technical problems.

[0006] In a first aspect, the present application provides a burr testing method, the method comprising:

[0007] Determine scene information, and determine each current target channel information based on the scene information;

[0008] sequentially controlling the unit under test to connect or disconnect the link of each current target channel based on the information of each current target channel, and controlling the load network of the load unit to connect to the unit under test;

[0009] Based on the scenario information, the unit under test is controlled to output signals to the load network of the load unit through the links of the current target channels respectively, and each time the unit under test stops outputting signals, waveform information of the unit under test corresponding to the current target channel is collected through an oscilloscope;

[0010] Glitch information is obtained based on the acquired waveform information.

[0011] In one embodiment, after determining the scene information, the method further includes:

[0012] Initializing a load type variable, where the load type variable is used to indicate the type of the load network;

[0013] Initialize the gear position variable and output signal variable of the unit to be tested;

[0014] The group pin is parsed to obtain channel configuration information, which includes the initial pin information, the initial slot information bound to each pin, and the initial channel information. The gear variable of the unit under test, the output signal variable, and the channel configuration information are used as initialization loop variables. The number of times each variable in the initialization loop variable is traversed is the number of changes of the current target channel.

[0015] In one embodiment, determining the information of each current target channel includes:

[0016] The current target channel information is determined based on the value of the initialization loop variable and the scene information, and after the waveform information of the target channel corresponding to the unit under test is collected by an oscilloscope, the value of the initialization loop variable is updated, and the current target channel information is continued to be determined based on the value of the initialization loop variable until all the values ​​corresponding to the initialization loop variables are traversed.

[0017] In one embodiment, determining the current target channel information based on the value of the initialization loop variable and the scene information includes:

[0018] Determine the current target channel information based on the value corresponding to the gear position variable of the unit under test, the value corresponding to the output signal variable of the unit under test at each gear position, the initial pin information, and the initial channel information bound to each pin; wherein the relationship between the value corresponding to the output signal variable of the unit under test and the value corresponding to the gear position variable of the unit under test is determined by the output mode of the unit under test in the scenario information;

[0019] The updating of the value of the initialization loop variable comprises:

[0020] The initial channel information, the initial pin information, the value corresponding to the output signal variable of the unit to be tested and the value of the gear variable of the unit to be tested are cycled in sequence.

[0021] In one embodiment, after determining the scene information, the method further includes:

[0022] Initialize the configuration of the load unit and the communication unit communication.

[0023] In one embodiment, before sequentially controlling the unit under test to connect to or disconnect from the links of each current target channel based on the information of each current target channel, the method further includes:

[0024] The oscilloscope, the load unit and the unit under test are initialized and configured based on the scenario information, the current target channel information and the value of the load type variable.

[0025] In one embodiment, the initializing and configuring the oscilloscope, the load unit, and the unit under test based on the scenario information, the current target channel information, and the value of the load type variable includes:

[0026] Initializing the connection between the industrial computer and the oscilloscope, resetting the oscilloscope and configuring the probe channels of the oscilloscope and the load unit;

[0027] updating display scale information of the oscilloscope based on the load type;

[0028] Resetting the relay of the load unit and connecting the unit under test and the load unit according to the current target channel information;

[0029] Configure the horizontal and vertical position values ​​of the oscilloscope;

[0030] configuring a trigger mode and a trigger level of the oscilloscope based on the scenario information;

[0031] Initialize the attribute information of the output voltage and current circuit in the unit under test.

[0032] In one embodiment, the method further comprises:

[0033] Initialize the oscilloscope's single waveform acquisition threshold and number variables;

[0034] Setting the oscilloscope acquisition mode and display waveform retention mode based on the threshold of the number of times the oscilloscope acquires waveforms in a single shot;

[0035] The controlling the unit under test to output a signal to the load network of the load unit through the link of the current target channel based on the scenario information, and collecting waveform information of the current target channel corresponding to the unit under test through an oscilloscope each time the unit under test stops outputting a signal, includes:

[0036] Detecting whether the value of the number variable is less than the threshold value of the number of times the oscilloscope acquires a waveform in a single shot;

[0037] When the value of the number variable is less than the threshold value of the number of waveform acquisitions by the oscilloscope in a single time, the output signal of the unit under test is controlled based on the value of the load type variable and the scenario information, and each time the unit under test stops outputting a signal, the waveform information corresponding to the load unit is acquired through the oscilloscope, the delay time of the unit under test is updated based on the value of the load type variable, the value of the waveform number variable is updated, and the step of detecting whether the value of the number variable is less than the threshold value of the number of waveform acquisitions by the oscilloscope in a single time is continued, until it is detected that the value of the number variable is greater than or equal to the threshold value of the number of waveform acquisitions by the oscilloscope in a single time, and the step of updating the value of the initialization loop variable is continued.

[0038] In one embodiment, controlling the unit under test to output a signal to the load network of the load unit through the link of the current target channel based on the scenario information, and collecting waveform information of the target channel corresponding to the unit under test through an oscilloscope each time the unit under test stops outputting a signal, includes:

[0039] Determining an output target value for each output mode of the unit under test based on the scenario information;

[0040] Outputting the current output mode output target value to the link of the target channel;

[0041] Determining a delay time of an output signal of the unit under test based on a value of the load type variable;

[0042] Determine whether there is a next output mode output target value;

[0043] If there is no next output mode output target value and the output time of the output target value of the unit under test reaches the delay time, disconnecting the unit under test from the target channel link and collecting waveform information corresponding to the load unit through an oscilloscope;

[0044] If there is a next output mode output target value, the next output mode output target value is used as the current output mode output target value, and the step of outputting the current output mode output target value to the target channel link is continued until all the output mode output target values ​​are traversed.

[0045] In one embodiment, the scenario information includes different output modes of the unit under test and different scenario types corresponding to each output mode, and the different scenario types include at least one of no step change, step change, positive and negative step change, and switching between different output modes;

[0046] The step-free change includes: after the unit under test outputs an output signal with a negative value or a positive value for a first period of time, the output signal returns to 0;

[0047] The step change includes: the unit under test outputting an output signal of a negative value or a positive value in a first time period; then outputting an output signal of a negative value or a positive value half of the first time period, and then returning the output signal to 0;

[0048] The positive and negative step changes include: the unit under test outputting an output signal of a negative value or a positive value in a first time period; then outputting an output signal of an output value of an inverted signal in the first time period, and then returning the output signal to 0;

[0049] The switching of different output modes includes: first, the unit under test outputs a negative value or a positive value of an initial mode signal, which lasts for a first time period, and then the output signal returns to 0; second, the output of different mode signs takes the inverted signal value, which lasts for a first time period; finally, the output signal returns to 0.

[0050] In one embodiment, determining the scene information includes:

[0051] Get the current test case, each test case corresponds to a test scenario;

[0052] Determining scenario information based on the current test case;

[0053] The method further comprises:

[0054] After the corresponding waveform information is obtained based on the current test case, the next test case is obtained, and the step of determining the scenario information based on the current test case is continued until the execution of each test case is completed.

[0055] In a second aspect, the present application further provides a burr testing device, comprising:

[0056] A target channel determination module is used to determine scene information and determine each current target channel information based on the scene information;

[0057] A first control module is used to control the unit under test to connect or disconnect the link of each current target channel based on the information of each current target channel, and to control the load network of the load unit to connect to the unit under test;

[0058] a second control module, configured to control the unit under test to output signals to the load network of the load unit through the links of the current target channels based on the scenario information, and to collect waveform information of the target channel corresponding to the unit under test through an oscilloscope each time the unit under test stops outputting signals;

[0059] The glitch information acquisition module is used to obtain glitch information based on the collected waveform information.

[0060] In a third aspect, the present application further provides a glitch testing system, comprising:

[0061] An industrial computer, configured to execute the glitch testing method described in any one of the above embodiments to obtain glitch information;

[0062] Communication unit, used to establish communication between the industrial computer and the load unit and the unit under test;

[0063] A load unit communicates with the industrial computer via a communication unit, the load unit being configured to be initialized based on the control of the industrial computer and to enable a link from the unit under test to the load unit;

[0064] The unit under test communicates with the industrial computer through the communication unit, and the unit under test is used to establish or disconnect the connection with the target channel link based on the control output signal of the industrial computer;

[0065] An oscilloscope is connected to the industrial computer and the load unit respectively, and is used for initialization and configuration based on the control of the industrial computer, and for collecting waveform information output by the load unit.

[0066] In a fourth aspect, the present application further provides a computer device comprising a memory and a processor, wherein the memory stores a computer program, and wherein the processor implements the steps of the method described in any one of the above embodiments when executing the computer program.

[0067] The glitch test method, apparatus, system and computer equipment described above determine scenario information and determine information of each current target channel based on the scenario information; sequentially control the unit under test to connect or disconnect the link of each current target channel based on the information of each current target channel, and control the load network of the load unit to connect to the unit under test; control the unit under test to output signals to the load network of the load unit through the link of each current target channel based on the scenario information, and each time the unit under test stops outputting signals, collects waveform information of the target channel corresponding to the unit under test through an oscilloscope; obtains glitch information based on the collected waveform information. The entire test process does not require manual intervention, and the oscilloscope collects signals for each scenario, which can greatly improve test efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0068] In order to more clearly illustrate the technical solutions in the embodiments of the present application or related technologies, the following briefly introduces the drawings required for use in the embodiments of the present application or related technical descriptions. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without paying any creative work.

[0069] Figure 1 A diagram showing an application environment of a burr testing method according to an embodiment;

[0070] Figure 2 1 is a flow chart of a burr testing method according to an embodiment;

[0071] Figure 3 is a flow chart of a burr testing method according to another embodiment;

[0072] Figure 4 1. A flow chart of a multi-channel, multi-scenario glitch test process for a PMU FIMV mode without step changes in one embodiment;

[0073] Figure 5 A flowchart of a multi-channel, multi-scenario glitch test process for a PMU FVMI mode without step changes in one embodiment is provided;

[0074] Figure 6 is a structural block diagram of a burr testing device in one embodiment;

[0075] Figure 7 FIG. 1 is a diagram showing the internal structure of a computer device in one embodiment. DETAILED DESCRIPTION

[0076] In order to make the purpose, technical solutions and advantages of this application more clear, the following further describes this application in detail with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain this application and are not intended to limit this application.

[0077] The burr testing method provided in the embodiment of the present application can be applied to Figure 1 In the application environment shown, the industrial computer is connected to the oscilloscope in communication, and is also connected to the communication unit in communication, the communication unit is connected to the load unit and the unit to be tested in communication, the unit to be tested is also electrically connected to the load unit, and the oscilloscope is also electrically connected to the load unit.

[0078] In the present application, the unit to be tested is an AD board (mixed signal board), the load unit is a check board, including a channel selection and a load board, and the communication unit is a communication board, such as a CTI board. One point that needs to be explained is that the pogo is on the unit to be tested, and the pogo is a radio frequency port component. There is a relay between the output voltage and current circuit of the unit to be tested and the pogo, which is used to select the corresponding current target channel; the pogo is electrically connected to the radio frequency terminal of the load unit, and the pogo and the radio frequency terminal are both metal connectors. In the present application, the unit to be tested includes a chip, a constructed analog circuit, or a circuit with a controller and an output voltage and current, etc., which are not specifically limited here. In other embodiments, the load unit and the unit to be tested can be on one board, or they can be two separate independent boards, which are not specifically limited here.

[0079] In some optional embodiments, the output voltage and current circuit of the present application is a PMU module. In other embodiments, it can also be other circuits. No specific limitation is made here. In this application, the output voltage and current circuit is taken as a PMU module as an example for explanation. The PMU module can be an integrated chip or a constructed analog circuit.

[0080] The industrial computer in this application includes test software, which includes three parts of control, namely: the test software controls the relay in the load unit CHECK to select the link from the PMU output to the load end by controlling the I2C bus of the communication unit CTI; the test software controls the PMU module of the unit under test to perform FI or FV mode function output and the pogo link relay connection of the unit under test by controlling the DBUS communication of the communication unit CTI; the test software triggers the acquisition and storage of waveforms through the network threaded oscilloscope.

[0081] Specifically, the industrial computer (IPC) runs the test software and controls the communication interface (CTI) to control the output voltage or current of the AD unit under test (UUT). It also controls the load unit CHECK relay connection via the I2C interface, thereby establishing a Pogo link between the PMU of the UUT and the load unit CHECK board's load pressure measurement link. The oscilloscope probe is connected to the load unit CHECK's pressure measurement banana probes (HF and LF terminals). The RF terminals connect the UUT's AD channel to the load unit CHECK. The IPC can configure the oscilloscope's trigger mode, trigger level, horizontal position, vertical position, time adjustment, voltage adjustment, and screenshot saving functions through the network port. This allows waveforms to be captured and saved for different PMU output scenarios. A human can then observe the captured images for glitches.

[0082] In an exemplary embodiment, Figure 2 As shown, a glitch test method is provided, which is applied to Figure 1The industrial computer in the example is used to illustrate, including the following steps S202 to S208.

[0083] S202: Determine scene information, and determine each current target channel information based on the scene information.

[0084] In one optional embodiment, the scene information includes different output modes of the unit to be tested and different scene types corresponding to each output mode, and the different scene types include at least one of no step change, step change, positive and negative step change, and switching between different output modes; no step change includes: after the unit to be tested outputs an output signal with a negative value or a positive value for a first time period, the output signal returns to 0; step change includes: after the unit to be tested outputs an output signal with a negative value or a positive value for a first time period; and then outputs an output signal with a negative value or a positive value half of the first time period, the output signal returns to 0; positive and negative step change includes: after the unit to be tested outputs an output signal with a negative value or a positive value for a first time period; and then outputs an output signal with an output sign inverted for the first time period, the output signal returns to 0; switching between different output modes includes: first, the unit to be tested outputs a negative value or a positive value of the initial mode signal, and after the first time period, the output signal returns to 0; second, outputs a signal value with a different mode sign inverted for the first time period; and finally, the output signal returns to 0.

[0085] The unit under test includes multiple channels. In each scenario, it is necessary to test the waveform information of each channel when connected to the load network of the load unit. The load network is composed of resistors and capacitors. When no capacitor is connected, there is only resistance or resistance and other loads coexist (i.e., non-capacitive load). When capacitor is connected, there is resistance in parallel with capacitance (i.e., capacitive load). In some optional embodiments, the unit under test includes 8 channels, namely CH0, CH6, CH9, CH15, CH17, CH23, CH24, and CH30. In other embodiments, other numbers of channels may be included, and no specific limitation is given here.

[0086] Optionally, the output mode includes a FIMV mode and a FVMI mode, wherein in the FIMV mode, the output signal type is FI, and in the FVMI mode, the output signal type is FV.

[0087] Therefore, the scenarios involved in this application include at least the following 8 major scenarios, and each scenario also includes 4 small scenarios, specifically:

[0088] The first scenario: PMU FIMV mode non-step change multi-channel multi-scenario glitch test includes four scenarios:

[0089] Scenario 1: FIMV mode cycles through five levels (5uA, 20uA, 200uA, 2mA, and 50mA) and switches to the corresponding link resistors (1MR, 100K, 10K, 1K, and 100R) of the load unit CHECK. The load network is non-capacitive, for example, not a capacitor. The UUT outputs the FI signal at -1.8uA, -18.0uA, -180.0uA, -1.8mA, and -18.0mA, respectively. This means the voltage switches from 0V to a negative voltage of approximately -1.8V. The UUT's PMU is then operated to disconnect the link output, switching the voltage from -1.8V to 0V. This scenario cycles through eight channels (CH0, CH6, CH9, CH15, CH17, CH23, CH24, and CH30) of the UUT's AD.

[0090] The difference between scenario 2 and scenario 1 is that the load network is a capacitive load. For example, if a 10nF capacitor is connected in parallel with the load network, the FI outputs are -1.8uA, -18.0uA, -180.0uA, -1.8mA, and -18.0mA, respectively. That is, the voltage switches from 0V to a negative voltage of approximately -1.8V. Then, the PMU is operated to disconnect the link output, and the voltage switches from -1.8V to 0V.

[0091] The difference between scenario 3 and scenario 1 is that the FI outputs 1.8uA, 18.0uA, 180.0uA, 1.8mA, and 18.0mA, respectively. That is, the voltage switches from 0V to a positive voltage of approximately 1.8V. Then, the PMU is operated to disconnect the link output, and the voltage switches from 1.8V to 0V.

[0092] The difference between scenario 4 and scenario 1 is that the load network is a capacitive load. For example, if a 10nF capacitor is connected in parallel to the load network, the FI outputs are 1.8uA, 18.0uA, 180.0uA, 1.8mA, and 18.0mA, respectively. That is, the voltage is switched from 0V to a positive voltage of approximately 1.8V. Then, the PMU is operated to disconnect the link output, and the voltage switches from 1.8V to 0V.

[0093] The second scenario: PMU FIMV mode with step change multi-channel multi-scenario glitch test includes four scenarios:

[0094] Scenario 1: FIMV mode cycles through five settings (5uA, 20uA, 200uA, 2mA, 50mA) and switches to the corresponding link resistors (1MR, 100K, 10K, 1K, 100R) of the load unit CHECK. No load capacitor is connected. The FI outputs -1.8uA, -18.0uA, -180.0uA, -1.8mA, and -18.0mA, switching the load voltage from 0V to approximately -1.8V. The FI output is then halved, switching the load voltage from -1.8V to -0.9V. The PMU is then operated to disconnect the link output, switching the voltage from -0.9V to 0V. This scenario cycles through eight AD channels of the unit under test (CH0, CH6, CH9, CH15, CH17, CH23, CH24, and CH30).

[0095] The difference between scenario 2 and scenario 1 is that the load network is capacitive. For example, if a 10nF capacitor is connected in parallel with the load network, the FI outputs are -1.8uA, -18.0uA, -180.0uA, -1.8mA, and -18.0mA, respectively. That is, the load voltage is cut from 0V to a negative voltage of approximately -1.8V. The FI output is then halved according to the gear level, that is, the load voltage is cut from -1.8V to -0.9V. The PMU is then operated to disconnect the link output, and the voltage switches from -0.9V to 0V.

[0096] The difference between scenario 3 and scenario 1 is that the FI outputs 1.8uA, 18.0uA, 180.0uA, 1.8mA, and 18.0mA, respectively. That is, the voltage is cut from 0V to a positive voltage of approximately 1.8V. Then, the FI output is halved according to the gear level. That is, the load voltage is cut from 1.8V to 0.9V. Then, the PMU is operated to disconnect the link output, and the voltage switches from 0.9V to 0V.

[0097] The difference between scenario 4 and scenario 1 is that the load network is capacitive. For example, if a 10nF capacitor is connected in parallel with the load network, the FI outputs are 1.8uA, 18.0uA, 180.0uA, 1.8mA, and 18.0mA, respectively. That is, the voltage is cut from 0V to a positive voltage of approximately 1.8V. The FI then reduces the output by half, cutting the load voltage from 1.8V to 0.9V. The PMU is then operated to disconnect the link output, causing the voltage to switch from 0.9V to 0V.

[0098] The third scenario: PMU FIMV mode positive and negative step change multi-channel multi-scenario glitch test can include four scenarios:

[0099] Scenario 1: FIMV mode cycles through five settings (5uA, 20uA, 200uA, 2mA, and 50mA) and switches to the corresponding link resistors (1MR, 100K, 10K, 1K, and 100R) of the load unit CHECK. No load capacitor is connected. First, the FI outputs -1.8uA, -18.0uA, -180.0uA, -1.8mA, and -18.0mA, switching the load voltage from 0V to a negative voltage of approximately -1.8V. Then, the current is output at the -FI setting, switching the load voltage from -1.8V to 1.8V. The PMU then disconnects the link output, switching the voltage from 1.8V to 0V. This scenario cycles through eight AD channels of the unit under test (CH0, CH6, CH9, CH15, CH17, CH23, CH24, and CH30).

[0100] The difference between scenario 2 and scenario 1 is that the load network is a capacitive load. For example, if a 10nF capacitor is connected in parallel to the load network, the FI outputs are -1.8uA, -18.0uA, -180.0uA, -1.8mA, and -18.0mA, respectively. That is, the load voltage is switched from 0V to a negative voltage of approximately -1.8V. Then, the current is output according to the gear position -FI, that is, the load voltage is switched from -1.8V to 1.8V. Then, the PMU is operated to disconnect the link output, and the voltage switches from 1.8V to 0V.

[0101] The difference between scenario 3 and scenario 1 is that the FI outputs are 1.8uA, 18.0uA, 180.0uA, 1.8mA, and 18.0mA, respectively. That is, the voltage is switched from 0V to a positive voltage of approximately 1.8V. Then, the current is output according to the gear position -FI. That is, the load voltage is switched from 1.8V to -1.8V. Then, the PMU is operated to disconnect the link output, and the voltage switches from -1.8V to 0V.

[0102] The difference between scenario 4 and scenario 1 is that the load network is a capacitive load. For example, if a 10nF capacitor is connected in parallel to the load network, the FI outputs are 1.8uA, 18.0uA, 180.0uA, 1.8mA, and 18.0mA, respectively. That is, the voltage is switched from 0V to a positive voltage of approximately 1.8V. The current is then output according to the -FI level, that is, the load voltage is switched from 1.8V to -1.8V. The PMU is then operated to disconnect the link output, and the voltage switches from -1.8V to 0V.

[0103] The fourth scenario: PMU FIMV mode switching FVMI multi-channel multi-scenario glitch testing can include four scenarios:

[0104] Scenario 1: FIMV mode cycles through five settings (5uA, 20uA, 200uA, 2mA, 50mA) and switches to the corresponding link resistor (1MR, 100K, 10K, 1K, 100R) of the load unit CHECK, without any load capacitor. First, the FI outputs -1.8uA, -18.0uA, -180.0uA, -1.8mA, and -18.0mA, switching the load voltage from 0V to approximately -1.8V. Then, in FVMI mode, the voltage output is set to 1.8V, switching the load voltage from -1.8V to 1.8V. The PMU then disconnects the link output, switching the voltage from 1.8V to 0V. This scenario cycles through eight AD channels of the unit under test (CH0, CH6, CH9, CH15, CH17, CH23, CH24, and CH30).

[0105] The difference between scenario 2 and scenario 1 is that the load network is a capacitive load. For example, if a 10nF capacitor is connected in parallel to the load network, the FI outputs are -1.8uA, -18.0uA, -180.0uA, -1.8mA, and -18.0mA, respectively. That is, the load voltage is switched from 0V to a negative voltage of approximately -1.8V. Then, in FVMI mode, the voltage is output at 1.8V, that is, the load voltage is switched from -1.8V to 1.8V. Then, the PMU is operated to disconnect the link output, and the voltage switches from 1.8V to 0V.

[0106] The difference between scenario 3 and scenario 1 is that the FI outputs 1.8uA, 18.0uA, 180.0uA, 1.8mA, and 18.0mA, respectively. That is, the voltage is cut from 0V to a positive voltage of approximately 1.8V. Then, in FVMI mode, the voltage is output at the -1.8V level. That is, the load voltage is cut from 1.8V to -1.8V. Then, the PMU is operated to disconnect the link output, and the voltage switches from -1.8V to 0V.

[0107] The difference between scenario 4 and scenario 1 is that the load network is a capacitive load. For example, if a 10nF capacitor is connected in parallel to the load network, the FI outputs are 1.8uA, 18.0uA, 180.0uA, 1.8mA, and 18.0mA, respectively. That is, the voltage is switched from 0V to a positive voltage of approximately 1.8V. Then, in FVMI mode, the voltage is output at -1.8V, that is, the load voltage is switched from 1.8V to -1.8V. Then, the PMU is operated to disconnect the link output, and the voltage switches from -1.8V to 0V.

[0108] The fifth scenario: PMU FVMI mode non-step change multi-channel multi-scenario glitch testing can include four scenarios:

[0109] Scenario 1: The FVMI mode switches through five settings (5uA, 20uA, 200uA, 2mA, and 50mA) and switches to the corresponding load unit CHECK link resistor (1MR, 100K, 10K, 1K, and 100R) without connecting a load capacitor. The initial FV output voltage is set to -1.8V, meaning the load voltage switches from 0V to a negative voltage of approximately -1.8V. The PMU is then operated to disconnect the link output, switching the voltage from -1.8V to 0V. This scenario switches across all eight AD channels of the unit under test (CH0, CH6, CH9, CH15, CH17, CH23, CH24, and CH30).

[0110] The difference between Scenario 2 and Scenario 1 is that the load network is a capacitive load. For example, a 10nF capacitor is connected in parallel to the load network. The initial value of the FV output voltage is set to -1.8V, that is, the voltage is switched from 0V to a negative voltage of approximately -1.8V. Then, the PMU is operated to disconnect the link output, and the voltage switches from -1.8V to 0V.

[0111] The difference between scenario 3 and scenario 1 is that the initial value of the FV output voltage is set to 1.8V, that is, the voltage is switched from 0V to a positive voltage of approximately 1.8V. Then, the PMU is operated to disconnect the link output, and the voltage switches from 1.8V to 0V.

[0112] The difference between scenario 4 and scenario 1 is that the load network is a capacitive load. For example, a 10nF capacitor is connected in parallel to the load network. The initial value of the FV output voltage is set to 1.8V, that is, the voltage is switched from 0V to a positive voltage of approximately 1.8V. Then, the PMU is operated to disconnect the link output, and the voltage switches from 1.8V to 0V.

[0113] The sixth scenario: PMU FVMI mode with step change multi-channel multi-scenario glitch testing can include four scenarios:

[0114] Scenario 1: The FVMI mode cycles through five settings (5uA, 20uA, 200uA, 2mA, and 50mA) and switches to the corresponding load unit CHECK link resistor (1MR, 100K, 10K, 1K, and 100R) without connecting a load capacitor. First, the FV output voltage is initially set to -1.8V, reducing the load voltage from 0V to a negative voltage of approximately -1.8V. The FV output is then halved according to the setting, reducing the load voltage from -1.8V to -0.9V. The PMU is then operated to disconnect the link output, switching the voltage from -0.9V to 0V. This scenario cycles through eight AD channels of the unit under test (CH0, CH6, CH9, CH15, CH17, CH23, CH24, and CH30).

[0115] The difference between scenario 2 and scenario 1 is that the load network is a capacitive load, for example, a 10nF capacitor is connected in parallel to the load network, and the initial FV output voltage is set to -1.8V. That is, the load voltage is cut from 0V to a negative voltage of approximately -1.8V. Then, the FV output is halved according to the gear level, that is, the load voltage is cut from -1.8V to -0.9V. Then, the PMU is operated to disconnect the link output, and the voltage switches from -0.9V to 0V.

[0116] The difference between scenario 3 and scenario 1 is that the initial value of the FV output voltage is set to 1.8V, that is, the load voltage is cut from 0V to a positive voltage of approximately 1.8V. Then, the FV output is halved according to the gear level, that is, the load voltage is cut from 1.8V to 0.9V. Then, the PMU is operated to disconnect the link output, and the voltage switches from 0.9V to 0V.

[0117] The difference between Scenario 4 and Scenario 1 is that the load network is a capacitive load, for example, a 10nF capacitor is connected in parallel to the load network, and the initial value of the FV output voltage is set to 1.8V. That is, the load voltage is cut from 0V to a positive voltage of approximately 1.8V. Then, the FV output is halved according to the gear level, that is, the load voltage is cut from 1.8V to 0.9V. Then, the PMU is operated to disconnect the link output, and the voltage switches from 0.9V to 0V.

[0118] The seventh scenario: PMU FVMI mode positive and negative step change multi-channel multi-scenario glitch test includes four scenarios:

[0119] Scenario 1: In FVMI mode, the five settings (5uA, 20uA, 200uA, 2mA, and 50mA) are switched to the corresponding load unit CHECK link resistor (1MR, 100K, 10K, 1K, and 100R) without any load capacitors. First, the FV output voltage is initially set to -1.8V, switching the load voltage from 0V to a negative voltage of approximately -1.8V. The voltage is then output according to the -FV setting, switching the load voltage from -1.8V to 1.8V. The PMU is then operated to disconnect the link output, switching the voltage from 1.8V to 0V. This scenario involves eight AD channels of the unit under test (CH0, CH6, CH9, CH15, CH17, CH23, CH24, and CH30).

[0120] The difference between scenario 2 and scenario 1 is that the load network is a capacitive load, for example, a 10nF capacitor is connected in parallel to the load network. First, the initial value of the FV output voltage is set to -1.8V, that is, the load voltage is switched from 0V to a negative voltage of approximately -1.8V. Then, the voltage is output according to the gear position -FV, that is, the load voltage is switched from -1.8V to 1.8V. Then, the PMU is operated to disconnect the link output, and the voltage switches from 1.8V to 0V.

[0121] The difference between scenario 3 and scenario 1 is that: first, the initial value of the FV output voltage is set to 1.8V, that is, the voltage is switched from 0V to a positive voltage of approximately 1.8V. Then, the voltage is output according to the gear position -FV, that is, the load voltage is switched from 1.8V to -1.8V. Then, the PMU is operated to disconnect the link output, and the voltage switches from -1.8V to 0V.

[0122] The difference between scenario 4 and scenario 1 is that the load network is a capacitive load, for example, a 10nF capacitor is connected in parallel to the load network. First, the initial value of the FV output voltage is set to 1.8V, that is, the voltage is switched from 0V to a positive voltage of approximately 1.8V. Then, the voltage is output according to the gear position -FV, that is, the load voltage is switched from 1.8V to -1.8V. Then, the PMU is operated to disconnect the link output, and the voltage switches from -1.8V to 0V.

[0123] The eighth scenario: PMU FVMI mode switching FIMV multi-channel multi-scenario glitch test includes four scenarios:

[0124] Scenario 1: In FVMI mode, the calibrator switches between five settings (5uA, 20uA, 200uA, 2mA, and 50mA) and the corresponding link resistor (1MR, 100K, 10K, 1K, and 100R) of the load unit CHECK. No load capacitor is connected. First, the FV output voltage changes from -1.8V according to the setting, switching the load voltage from 0V to a negative voltage of approximately -1.8V. Then, in FIMV mode, the calibrator outputs 1.8uA, 18.0uA, 180.0uA, 1.8mA, and 18.0mA, switching the load voltage from -1.8V to 1.8V. The PMU then disconnects the link output, switching the voltage from 1.8V to 0V. This scenario traverses eight AD channels of the unit under test (CH0, CH6, CH9, CH15, CH17, CH23, CH24, and CH30).

[0125] The difference between scenario 2 and scenario 1 is that the load network is a capacitive load, for example, a 10nF capacitor is connected in parallel to the load network. First, the FV outputs a voltage of -1.8V according to the gear ratio, that is, the load voltage is switched from 0V to a negative voltage of about -1.8V. Then, in FIMV mode, the FI outputs 1.8uA, 18.0uA, 180.0uA, 1.8mA, and 18.0mA according to the gear ratio, that is, the load voltage is switched from -1.8V to 1.8V. Then, the PMU is operated to disconnect the link output, and the voltage switches from 1.8V to 0V.

[0126] The difference between scenario 3 and scenario 1 is that: first, FV outputs a voltage of 1.8V according to the gear level, that is, the voltage is switched from 0V to a positive voltage of about 1.8V. Then, in FIMV mode, FI outputs -1.8uA, -18.0uA, -180.0uA, -1.8mA, and -18.0mA according to the gear level, that is, the load voltage is switched from 1.8V to -1.8V. Then, the PMU is operated to disconnect the link output, and the voltage switches from -1.8V to 0V.

[0127] The difference between scenario 4 and scenario 1 is that the load network is a capacitive load, for example, a 10nF capacitor is connected in parallel to the load network. First, the FV outputs a voltage of 1.8V according to the gear ratio, that is, the voltage is switched from 0V to a positive voltage of approximately 1.8V. Then, in FIMV mode, the FI outputs -1.8uA, -18.0uA, -180.0uA, -1.8mA, and -18.0mA according to the gear ratio, that is, the load voltage is switched from 1.8V to -1.8V. Then, the PMU is operated to disconnect the link output, and the voltage switches from -1.8V to 0V.

[0128] Each of the eight major scenarios mentioned above is divided into two minor scenarios. For example, the PMU FIMV mode is divided into two minor scenarios: capacitive load and non-capacitive load. The output signal can traverse these two minor scenarios (positive and negative voltage values ​​are traversed together). A total of 16 minor scenarios can be regarded as 16 test cases. These 16 test cases are independent of each other. After waveform acquisition is completed in one test case, you can randomly switch to any other test case.

[0129] In another embodiment, each of the above-mentioned eight major scenarios has four minor scenarios. For example, the PMU FIMV mode is divided into two minor scenarios: capacitive load and non-capacitive load. The positive and negative values ​​of the output voltage are separated independently, for a total of 32 scenarios, which can be regarded as 32 test cases. These 32 test cases are independent of each other. After a test case completes waveform acquisition, it can randomly switch to any other test case.

[0130] S204: sequentially controlling the unit under test to connect or disconnect the links of each current target channel based on the information of each current target channel, and controlling the load network of the load unit to connect to the unit under test.

[0131] After the current target channel information is determined based on the scenario information, the unit under test can be controlled to connect or disconnect the link of the current target channel, so that the current target channel of this test is connected to the unit under test. The load network of the load unit is controlled to connect to the unit under test.

[0132] One point that needs to be explained is that in this application, the connection or disconnection of the link of each current target channel of the unit to be tested is controlled in sequence based on the information of each current target channel, and the connection of the load network of the load unit with the unit to be tested is controlled. In this way, each time a current target channel is connected to the unit to be tested, and the load network of the load unit is connected to the unit to be tested, the connection between the current target channel of the unit to be tested and the load network of the load unit is realized. When the current target channel is subsequently disconnected, the waveform information is collected, and then the next current target channel is connected to the unit to be tested, and the load network of the load unit is connected to the unit to be tested, until the test is completed. And one point that needs to be explained is that after each waveform information is collected, after the current target channel is determined in the new test scenario, the oscilloscope and the unit to be tested need to be initialized to avoid test errors caused by inadequate parameter settings of the oscilloscope and the unit to be tested.

[0133] S206: Based on the scenario information, the UUT is controlled to output signals to the load network of the load unit through the links of each current target channel respectively, and each time the UUT stops outputting signals, waveform information of the UUT corresponding to the current target channel is collected through an oscilloscope.

[0134] There is a relay between the PMU chip of the unit under test and the link pogo, which is used to select the current target channel. The link pogo is electrically connected to the RF terminal of the load unit. The link pogo and the RF terminal are both metal connectors. In this way, the link of the current target channel of the unit under test can be connected to the corresponding load network of the load unit, so as to configure the corresponding mode output to the link, and determine the time for the PMU to generate voltage according to the type of load network. When the channel connection where the PMU is located is disconnected, each time the unit under test stops outputting the signal, that is, when the output signal is 0, the waveform information of the current target channel of the unit under test corresponding to the current target channel is collected through the oscilloscope.

[0135] S208: Obtain burr information based on the collected waveform information.

[0136] After obtaining each waveform information, the waveform information and the corresponding scene information can be associated and stored, and then manual observation can be made to determine whether burr information exists, or identification can be performed through a model to determine whether burr information exists.

[0137] The waveform information may be a screenshot of an oscilloscope interface, and the screenshot may be manually observed to determine whether there are glitches, or the screenshot may be identified using a pre-trained neural network model to determine whether there are glitches.

[0138] In some optional embodiments, a screenshot with glitches and scene information corresponding to the screenshot may also be output to facilitate subsequent processing by the user.

[0139] The above-mentioned glitch test method determines scenario information and determines the information of each current target channel based on the scenario information; controls the unit under test to connect or disconnect the link of each current target channel based on the information of each current target channel, and controls the load network of the load unit to be connected to the unit under test; controls the unit under test to output signals to the load network of the load unit through the link of each current target channel based on the scenario information, and collects the waveform information of the unit under test corresponding to the current target channel through the oscilloscope each time the unit under test stops outputting the signal; obtains the glitch information based on the collected waveform information. The entire test process does not require manual intervention, and the oscilloscope collects data for each scenario, which can greatly improve the test efficiency.

[0140] In one optional embodiment, after determining the scenario information, the method further includes: initializing a load type variable, which is used to indicate the type of the load network; initializing a gear variable and an output signal variable of the unit under test; parsing the group pins to obtain channel configuration information, wherein the channel configuration information includes each initial pin information, each initial slot information bound to each pin, and each initial channel information; using the gear variable, output signal variable, and channel configuration information of the unit under test as initialization loop variables, and traversing each variable in the initialization loop variable the number of times the current target channel changes. Each variable in the initialization loop variable is traversed once, and the current target channel changes once.

[0141] The load type variable bRorC indicates the type of load network, including capacitive and non-capacitive loads. This variable indicates the PMU voltage delay time in the UUT. For example, in one embodiment, if the load network is non-capacitive, the delay time vecDelayTimeR is {2.0ms, 2.0ms, 2.0ms, 2.0ms}; if the load network is capacitive, the delay time vecDelayTimeC is {45.0ms, 4.0ms, 2.0ms, 2.0ms, 2.0ms}. In other embodiments, this delay time can also be set to other values. After the PMU output voltage is delayed by the corresponding delay time, the connection to the current target channel of the PMU is disconnected, indicating that the UUT output signal is 0. Optionally, if a capacitive load is connected, bRorC is initialized to true; otherwise, it is set to false.

[0142] The number of times each variable in the initialization loop is traversed represents the number of changes in the current target channel. The initialization loop variables include the UUT gear variable, output signal variable, and channel configuration information. The UUT gear variable is the current gear variable. For example, the five gears (5uA, 20uA, 200uA, 2mA, 50mA) are switched to the corresponding load unit CHECK link resistance (1MR, 100K, 10K, 1K, 100R). The output signal variable vecForceI is the output signal of the corresponding mode. For example, the output signal of the FIMV mode is the output current FI, and the output signal of the FVMI mode is the output voltage FV. Different output signals and different small scenarios have different value ranges. For example, the output current FI can include -1.8uA, -18.0uA, -180.0uA, -1.8mA, and -18.0mA, that is, the voltage is cut from 0V to a negative voltage of approximately -1.8V. It can also include 1.8uA, 18.0uA, 180.0uA, 1.8mA, and 18.0mA, that is, the voltage is cut from 0V to a positive voltage of approximately 1.8V. The initial value of the output voltage FV is set to -1.8V, that is, the load voltage is cut from 0V to a negative voltage of approximately -1.8V. It can also include the initial value of the output voltage FV being set to 1.8V, that is, the voltage is cut from 0V to a positive voltage of approximately 1.8V. In other embodiments, the value range of the output signal variable may also be other values. The values ​​given in this embodiment are empirical values ​​and are not specifically limited here.

[0143] In one of the optional embodiments, determining each current target channel information includes: determining the current target channel information based on the value of the initialization loop variable and the scene information, and after collecting the waveform information of the unit under test corresponding to the current target channel through the oscilloscope, updating the value of the initialization loop variable, and continuing to determine the current target channel information based on the value of the initialization loop variable until all the values ​​corresponding to the initialization loop variables are traversed.

[0144] Among them, in this application, a loop is performed based on the information of each current target channel to realize automatic testing to obtain the waveform information corresponding to each scene information. After the waveform information of the unit under test corresponding to the current target channel is collected by the oscilloscope, the initialization loop variable is updated, and then the above steps are executed again.

[0145] In one of the optional embodiments, the current target channel information is determined based on the value of the initialization loop variable and the current target channel of the scene information, including: based on the value corresponding to the gear variable of the unit to be tested, the value corresponding to the output signal variable of the unit to be tested under each gear, each initial pin information and the initial channel information bound to each pin, the current target channel determines the current target channel information; wherein, the relationship between the value corresponding to the output signal variable of the unit to be tested and the value corresponding to the gear variable of the unit to be tested is determined by the output mode of the unit to be tested in the scene information; updating the value of the initialization loop variable includes: looping through each initial channel information, each initial pin information, the value corresponding to the output signal variable of the unit to be tested and the value of the gear variable of the unit to be tested in turn.

[0146] Optionally, since the initialization loop variables include the gear variable of the unit under test, the output signal variable, and the channel configuration information, the gear variable of the unit under test, the output signal variable, and the channel configuration information can be updated in sequence during the update. After the value traversal of one variable is completed, the subsequent update traverses the value of the next variable until the values ​​of the gear variable, the output signal variable, and the channel configuration information of the unit under test are all traversed. Optionally, in this application, the gear variable of the unit under test is first traversed, and then the output signal variable is traversed according to the current gear variable. Then, the channel configuration information is traversed according to the current output signal variable. After the variable values ​​of the channel configuration information are completed, the output signal variable values ​​and the gear variable values ​​are traversed in sequence until all the initialization loop variables are traversed. The update step size of the initialization loop variable is determined based on the type of the variable currently traversed, for example, directly obtaining the next one within the value range. For the output signal variable, when the output mode is FIMV output mode, the output current is updated, and when the output mode is FVMI output mode, the output voltage is updated.

[0147] In the above embodiment, by introducing the initialization loop variable, the gear variable, output signal variable, and channel configuration information of the unit to be tested can be traversed, thereby realizing the loop of the gear variable, output signal variable, and channel configuration information of each unit to be tested in any small scene in the above eight scenes. The loop is fully automatic without the need for manual intervention, thereby improving test efficiency.

[0148] In one optional embodiment, after determining the scenario information, the method further includes: initializing and configuring communication between the load unit and the communication unit.

[0149] In one output mode, the load unit is initialized and configured only once, establishing a communication connection between the load unit and the communication unit (CTI board). If you switch to another output mode, the communication connection between the load unit and the communication unit is reinitialized.

[0150] If all output modes are in one test case, the output mode loop can be realized by introducing a variable representing the output mode, and whether to initialize the communication between the load unit and the communication unit can be determined by judging whether the output mode variable changes.

[0151] In one of the optional embodiments, before controlling the unit to be tested to connect or disconnect the link of each current target channel based on the information of each current target channel in turn, it also includes: initializing and configuring the oscilloscope, the load unit and the unit to be tested based on the scene information, the current target channel information and the value of the load type variable.

[0152] Before each test of the oscilloscope, the oscilloscope and the unit under test need to be initialized and configured based on the scenario information, the current target channel information, and the value of the load type variable to avoid test errors caused by parameter errors.

[0153] In one of the optional embodiments, the oscilloscope and the unit to be tested are initialized and configured based on the scene information, the current target channel information and the value of the load type variable, including: initializing the connection between the industrial computer and the oscilloscope, resetting the oscilloscope and configuring the probe channels of the oscilloscope and the load unit; updating the display scale information of the oscilloscope based on the load type; resetting the relay of the load unit, and connecting the unit to be tested and the load unit according to the current target channel information; configuring the horizontal position value and the vertical position value of the oscilloscope; configuring the trigger mode and trigger level of the oscilloscope based on the scene information; and initializing the attribute information of the output voltage and current circuit in the unit to be tested.

[0154] The oscilloscope configuration includes the oscilloscope's connection mode, display scale information, position information, and trigger mode information. The oscilloscope connection mode initializes the connection between the industrial computer and the oscilloscope, resets the oscilloscope, and configures the probe channels between the oscilloscope and the load unit. The display scale information includes a time scale and a voltage scale. The display scale information is configured based on a load type variable. Optionally, the load type variable represents a non-capacitive load, with a time scale of vecTimeScaleR = {2ms, 2ms, 2ms, 2ms, 2ms} and a voltage scale of vecVoltageScaleR = {0.5V, 0.5V, 0.5V, 0.5V, 0.5V}. The load type variable represents a capacitive load, with a time scale of vecTimeScaleC = {20ms, 4.0ms, 2ms, 2ms, 2ms} and a voltage scale of vecVoltageScaleC = {0.5V, 0.5V, 0.5V, 0.5V, 0.5V}. Other values ​​may also be selected in other embodiments. Only empirical values ​​are given in this application and they are not to be construed as limitations on this application. The position information includes the horizontal position and vertical position of the oscilloscope. This position information is set to allow the waveform to be displayed in the interface of the oscilloscope, so that the screenshot and saved interface include waveform information. Optionally, the horizontal position of the oscilloscope is set to 70 and the vertical position is set to 0; 70 and 0 are empirical values. The trigger mode information includes an edge trigger mode and a trigger level, wherein the delay trigger mode and trigger level of the oscilloscope are set according to the positive or negative value of the traversed PMU output signal. If the current value is negative, a rising edge trigger and a trigger level of -0.5V are used. If the current value is positive, a falling edge trigger and a trigger level of 0.5V are used. Other settings may also be made in other embodiments.

[0155] It should be noted that initializing the load cell includes connecting and disconnecting the load cell from the load network. This also includes resetting the disconnected state of the load cell relay before setting the oscilloscope's position information, and then connecting the load cell's pressure measurement link based on the current target channel information.

[0156] The initialization of the unit under test includes the attribute information of the output voltage and current circuit. The attribute information of the output voltage and current circuit PMU of the unit under test may include the connection of the corresponding current target channel and the configuration mode output to the pogo link.

[0157] In one optional embodiment, the method further includes: initializing a threshold value and a number variable for the number of waveforms acquired in a single shot by the oscilloscope; setting an oscilloscope acquisition mode and a display waveform retention mode based on the threshold value for the number of waveforms acquired in a single shot by the oscilloscope; controlling the unit under test to output a signal to a load network of a load unit through a link of a current target channel based on scenario information, and acquiring waveform information of the current target channel corresponding to the unit under test through an oscilloscope each time the unit under test stops outputting a signal, including: detecting whether the value of the number variable is less than the threshold value for the number of waveforms acquired in a single shot by the oscilloscope; if the value of the number variable is less than the threshold value for the number of waveforms acquired in a single shot by the oscilloscope, controlling the unit under test to output a signal based on a value of a load type variable and scenario information, and acquiring waveform information corresponding to the load unit through an oscilloscope each time the unit under test stops outputting a signal, updating a delay time of the unit under test based on the value of the load type variable, updating the value of the waveform number variable, and continuing to execute the step of detecting whether the value of the number variable is less than the threshold value for the number of waveforms acquired in a single shot by the oscilloscope, until the value of the number variable is greater than or equal to the threshold value for the number of waveforms acquired in a single shot by the oscilloscope, and continuing to execute the step of updating the value of the initialization loop variable.

[0158] Among them, initializing the oscilloscope also includes initializing the oscilloscope's single waveform acquisition threshold uiCaptureCnt and the number variable uiCapIdx. Among them, if the oscilloscope's single waveform acquisition threshold uiCaptureCnt is greater than 1, the oscilloscope needs to be set to continuous acquisition and display waveform retention mode, otherwise no setting is made. Optionally, in this application, uiCaptureCnt is the number of times the oscilloscope single-shot waveform acquisition is performed, and the default value is 1.

[0159] In addition, only when the value of the number variable uiCapIdx is less than the single waveform acquisition number threshold uiCaptureCnt, the attribute information of the output voltage and current circuit PMU of the unit under test is set, and the mode output to the pogo link is configured. For example, if the mode is FVMI, the FVMI mode is configured to output FV to the pogo link. If the mode is FIMV, the FIMV mode is configured to output FI to the pogo link.

[0160] Furthermore, if the value of the count variable uiCapIdx (an index representing the number of waveform captures) is less than the single waveform capture count threshold uiCaptureCnt, the output signal of the UUT is controlled based on the value of the load type variable and scenario information. The load type variable is used to control the voltage delay of the UUT's output voltage and current circuit (PMU). For example, in one embodiment, if the load network is non-capacitive, the delay time vecDelayTimeR = {2.0ms, 2.0ms, 2.0ms, 2.0ms}; if the load network is capacitive, the delay time vecDelayTimeC = {45.0ms, 4.0ms, 2.0ms, 2.0ms, 2.0ms}. In other embodiments, this delay time can also be set to other values. After the PMU output voltage is delayed for the corresponding delay time, the current target channel where the PMU is located is disconnected, and the UUT output signal is reset to 0. Optionally, if a capacitive load is connected, bRorC is initialized to true; otherwise, it is set to false. And after the voltage delay time is arrived, the unit to be tested stops outputting the signal. Each time the unit to be tested stops outputting the signal, it is determined whether the single waveform acquisition number threshold uiCaptureCnt is greater than 1. If it is not greater than 1, the number variable uiCapIdx changes according to the preset step size, and continues to judge whether the value of the number variable uiCapIdx is less than the single waveform acquisition number threshold uiCaptureCnt. Since the single waveform acquisition number threshold uiCaptureCnt is set to 1 in this application, in this embodiment, after a measurement is performed, the number variable uiCapIdx is greater than or equal to the single waveform acquisition number threshold uiCaptureCnt, so that the waveform information corresponding to the load unit is directly acquired through the oscilloscope.

[0161] Among them, if the single waveform acquisition number threshold uiCaptureCnt is greater than 1, that is, the acquisition number is greater than 1, the delay is controlled according to the load type variable bRorC to ensure that the oscilloscope acquires waveforms multiple times without confusion. For example, if the load network is a non-capacitive load, the delay time is vecTimeScaleR[uiIrange]x10-vecDelayTimeR[uiIrange]; if the load network is a capacitive load, the delay time is vecTimeScaleC[uiIrange]x10-vecDelayTimeC[uiIrange]; and after the delay time, the number variable uiCapIdx changes according to the preset step size, and continues to judge whether the value of the number variable uiCapIdx is less than the single waveform acquisition number threshold uiCaptureCnt, until the number variable uiCapIdx is greater than or equal to the single waveform acquisition number threshold uiCaptureCnt, thereby directly acquiring the waveform information corresponding to the load unit through the oscilloscope.

[0162] In addition, it should be noted that the above embodiment is illustrated by way of example without step changes. If there are step changes, such as positive and negative step changes, the output of the unit under test needs to be set, that is, the output signal of the unit under test is controlled based on the value of the load type variable and the scenario information, including: first outputting the corresponding delay time with the first step of the first mode, then resetting the PMU attribute information of the unit under test, and configuring the corresponding second mode to output the second step to the pogo link, disconnecting after outputting the corresponding delay time with the second step, and then collecting waveform information based on the single waveform collection number threshold uiCaptureCnt and the number variable uiCapIdx.

[0163] The second step can be half the length of the first step, or a negative number of the first step. When the mode remains unchanged, the first and second modes are the same. When the mode changes, the first and second modes are different. The second step corresponds to a different type of output signal than the first step. For example, one step corresponds to an output signal of type FV, while the other step corresponds to an output signal of type FI.

[0164] In one of the optional embodiments, the unit under test is controlled to output a signal to the load network of the load unit through the link of the current target channel based on the scenario information, and each time the unit under test stops outputting a signal, the waveform information of the current target channel corresponding to the unit under test is collected through an oscilloscope, including: determining the output target value of each output mode of the unit under test based on the scenario information; outputting the current output mode output target value to the link of the current target channel; determining the delay time of the output signal of the unit under test based on the value of the load type variable; determining whether there is a next output mode output target value; if there is no next output mode output target value and the output time of the output target value of the unit under test reaches the delay time, disconnecting the unit under test from the current target channel link, and collecting the waveform information corresponding to the load unit through an oscilloscope; if there is a next output mode output target value, using the next output mode output target value as the current output mode output target value, and continuing to execute the step of outputting the current output mode output target value to the current target channel link until all output mode output target values ​​are traversed.

[0165] The output mode output target value in this embodiment includes two when there is a step change or a mode change. For example, in the PMU FIMV mode with step change multi-channel multi-scenario glitch test, the output mode output target value includes two steps of the same output mode, namely FI and FI / 2. In other embodiments, the second step FI / 2 can take other values. In the PMU FIMV mode positive and negative step change multi-channel multi-scenario glitch test, the output mode output target value includes two steps of the same output mode, namely FI and -FI. In the PMU FIMV mode switching FVMI multi-channel multi-scenario glitch test, two modes are included, namely, the output mode output target value includes FI and FV. For the multiple steps, positive and negative steps involved in the PMU FVMI mode, and the scenario where the FVMI mode switches to the FIMV mode, the output mode output target value has similar changes and will not be repeated here.

[0166] The output target values ​​of each output mode of the unit under test are determined based on the scenario information; the output target value of the current output mode is output to the link of the current target channel; the delay time of the output signal of the unit under test is determined based on the value of the load type variable, that is, the first step outputs a certain delay time. If there are other output mode output target values, the next output mode output target value is used as the current output mode output target value, and the current output mode output target value is output to the link of the current target channel; the delay time of the output signal of the unit under test is determined based on the value of the load type variable, so that the second step or the second mode also outputs a certain delay time, and then the connection between the unit under test and the current target channel link is disconnected, and the waveform information corresponding to the load unit is collected through an oscilloscope.

[0167] In one of the optional embodiments, determining the scenario information includes: obtaining the current test case, each test case corresponding to a test scenario; determining the scenario information based on the current test case; the method also includes: after obtaining the corresponding waveform information based on the current test case, obtaining the next test case, and continuing to execute the step of determining the scenario information based on the current test case until each test case is executed.

[0168] Among them, the test scenarios correspond to the eight large scenarios mentioned above, each large scenario includes 2 small scenarios or 4 small scenarios, and 16 small scenarios or 32 small scenarios correspond to a test case. The scenario information can be determined based on the test case. For example, the scenario information can be stored in the name of the test case. In other embodiments, it can also be stored in other ways, such as associated storage, etc. In order to improve the test efficiency, in this application, after each test case is completed and the corresponding waveform information is obtained, the next test case is executed until the execution of each test case is completed. Then, the waveform information corresponding to each small scenario in the eight large scenarios can be obtained to facilitate the subsequent glitch information extraction.

[0169] Among them, combined Figure 3 As shown, Figure 3 This is a flowchart of a glitch testing method in another embodiment. In this embodiment, the scenario information is first determined, and then the load type variable, the gear variable of the unit to be tested, and the output signal variable are initialized based on the scenario information, and the threshold value and the number variable of the single waveform acquisition of the oscilloscope are initialized; the group pin is parsed to obtain the channel configuration information, and the gear variable of the unit to be tested, the output signal variable, and the channel configuration information are used as initialization loop variables to complete the software initialization.

[0170] Then initialize and configure the load unit to communicate with the communication unit.

[0171] The current target channel information is determined based on the value corresponding to the gear variable of the unit to be tested in the initialization loop variable, the value corresponding to the output signal variable of the unit to be tested under each gear, the initial pin information and the initial channel information bound to each pin.

[0172] The oscilloscope, the load unit and the unit under test are initialized and configured based on the scenario information, the current target channel information and the value of the load type variable. For the specific process, please refer to the above definition.

[0173] The oscilloscope acquisition mode and the display waveform retention mode are set based on the threshold value of the number of times the oscilloscope acquires waveforms in a single time.

[0174] Check whether the value of the number variable is less than the threshold value of the number of waveform acquisitions of the oscilloscope in a single time; when the value of the number variable is less than the threshold value of the number of waveform acquisitions of the oscilloscope in a single time, control the output signal of the unit to be tested based on the value of the load type variable and the scenario information, and each time the unit to be tested stops outputting the signal, collect the waveform information corresponding to the load unit through the oscilloscope, update the delay time of the unit to be tested based on the value of the load type variable, update the value of the waveform number variable, and continue to execute the step of checking whether the value of the number variable is less than the threshold value of the number of waveform acquisitions of the oscilloscope in a single time, until the value of the number variable is greater than or equal to the threshold value of the number of waveform acquisitions of the oscilloscope in a single time, save the waveform information, and continue to execute the step of updating the value of the initialization loop variable.

[0175] The above embodiment only provides a process for a large scenario. The differences between the processes of different large scenarios can be specifically combined with the following to modify the above process.

[0176] In some optional embodiments, for the first to fourth scenarios, or the fifth to eighth scenarios mentioned above, loop control can also be performed, that is, when the value of the number variable is less than the threshold value of the number of waveforms acquired by the oscilloscope in a single time, the output target values ​​of each output mode of the unit to be tested are determined based on the scenario information; the current output mode output target value is output to the link of the target channel; the delay time of the output signal of the unit to be tested is determined based on the value of the load type variable; it is determined whether there is a next output mode output target value; if there is no next output mode output target value and the output time of the output target value of the unit to be tested reaches the delay time, the connection between the unit to be tested and the target channel link is disconnected, and the waveform information corresponding to the load unit is acquired through the oscilloscope; if there is a next output mode output target value, the next output mode output target value is used as the current output mode output target value, and the step of outputting the current output mode output target value to the target channel link is continued until all output mode output target values ​​are traversed.

[0177] For the sake of ease of understanding, the PMU FIMV mode non-step change multi-channel multi-scenario glitch test process is used as an example to illustrate. Figure 4 As shown, it mainly includes the following steps:

[0178] 1. Initialize the load type variable bRorC and the oscilloscope's single waveform acquisition threshold uiCaptureCnt. The load type variable bRorC is initialized to true if a capacitive load is connected, otherwise it is set to false. The oscilloscope's single waveform acquisition threshold uiCaptureCnt is the number of times the oscilloscope acquires a waveform in a single shot, with a default value of 1. The output signal variable vecForceI = {1.8uA, 18.0uA, 180.0uA, 1.8mA, 18.0mA}; the gear variable Irange of the unit under test is the current gear, FI is the current output by the PMU chip, and the acquisition count uiCapIdx is the index of the number of waveform acquisitions.

[0179] 2. By parsing the group pin, we can get the slot number and channel number information bound to the pin. Phoenix defines the group pin and PinMap information. Group pin = "PMU_CH32_GRP". The parsed single pin vector vecPin = {"AWG_P0", "AWG_N0", "AWG_P1", "AWG_N1", "DGT_P0", "DGT_N0", "DGT_P1", "DGT_N1"}. These 8 are the initialization values ​​of the vector vecPin. The channel mapping of each single pin is mapSlotsChs. Taking a single pin as an example, mapSlotsChs["AWG_P0"] = {{15, 0}, {15, 4}, {15, 8}, {15, 12}}; the initialization iterator PinIter can obtain the initial address of vecPin; there are 8 pins, each of which contains slot and channel information;

[0180] 3. The load unit Check is initialized so that the relay on the check board is disconnected.

[0181] 4. Traverse the output voltage and current circuit PMU gear variable IRange (0-4), traverse the output current value FI (-vecForceI[IRange]~vecForceI[IRange]), traverse the bound channel Pin (vecPin), and traverse the channel information under Pin (mapSlotsChs).

[0182] Initialize the iterator PinIter=vecPin.end() to indicate whether the vector vecPin has been traversed to the end, that is, whether it has traversed to the very end of the vector vecPin.

[0183] The channel mapping iterator SlotsChIter=mapSlotsChs[PinIter].end() indicates whether the channel mapping iterator SlotsChIter traverses to the end of the mapSlotsChs variable.

[0184] 5. Initialize the connection to the oscilloscope, reset the oscilloscope, and configure the probe channel connected to the oscilloscope.

[0185] 6. Set the oscilloscope's time and voltage scales based on the load type variable bRorC. Without capacitors, set vecTimeScaleR to {2ms, 2ms, 2ms, 2ms} and vecVoltageScaleR to {0.5V, 0.5V, 0.5V, 0.5V, 0.5V}. With capacitors, set vecTimeScaleC to {20ms, 4.0ms, 2ms, 2ms} and vecVoltageScaleC to {0.5V, 0.5V, 0.5V, 0.5V, 0.5V}.

[0186] 7. Reset the load unit Check relay to the disconnected state, and then connect the load unit Check pressure measurement link according to the traversed channel information; the channel information includes [SoltChIter.uiSlot, SoltChIter.uiChannel].

[0187] 8. Set the oscilloscope horizontal position to 70 and vertical position to 0; 70 and 0 are empirical values.

[0188] 9. Set the oscilloscope's delayed trigger mode and trigger level based on the positive or negative output current value. If the current value is negative, use rising edge triggering and a trigger level of -0.5V. If the current value is positive, use falling edge triggering and a trigger level of 0.5V.

[0189] 10. If the oscilloscope's single waveform acquisition threshold uiCaptureCnt is greater than 1, you need to set the oscilloscope to continuous acquisition and display waveform retention mode.

[0190] 11. Loop through the oscilloscope acquisition times.

[0191] 12. Set the output voltage and current circuit PMU attribute information of the unit AD under test, and configure the FIMV mode output to pogo.

[0192] 13. Set the time for the output voltage and current circuit PMU to generate voltage according to the load type variable bRorC; when no capacitor is connected, vecDelayTimeR={2.0ms, 2.0ms, 2.0ms, 2.0ms}; when capacitor is connected, vecDelayTimeC={45.0ms, 4.0ms, 2.0ms, 2.0ms, 2.0ms}.

[0193] 14. Disconnect the channel where the output voltage and current circuit PMU is located, and the output is 0; collect the waveform at this moment.

[0194] 15. When the number of acquisitions is greater than 1, the delay is controlled according to the load type variable bRorC to ensure that the oscilloscope acquires waveforms multiple times without confusion; if no capacitor is connected, vecTimeScaleR[uiIrange]x10-vecDelayTimeR[uiIrange] is used; if capacitor is connected, vecTimeScaleC[uiIrange]x10-vecDelayTimeC[uiIrange] is used.

[0195] 16. After waveform acquisition is completed, control the oscilloscope to save the image and reset the oscilloscope.

[0196] The process for multi-channel, multi-scenario glitch testing in PMU FIMV mode with step changes differs from the process for multi-channel, multi-scenario glitch testing in PMU FIMV mode without step changes in that, after step 13, the process also includes setting the PMU attribute information for the output voltage and current circuit of the unit under test (AD) and configuring the FIMV mode output FI / 2 to pogo. The time required for the PMU to generate the voltage is set based on the load type variable bRorC. When no capacitor is connected, vecDelayTimeR = {2.0ms, 2.0ms, 2.0ms, 2.0ms}; when capacitor is connected, vecDelayTimeC = {45.0ms, 4.0ms, 2.0ms, 2.0ms, 2.0ms}. Then, the process proceeds to step 14.

[0197] The process for testing multi-channel, multi-scenario glitch signals in PMU FIMV mode with positive and negative step changes differs from the process for testing multi-channel, multi-scenario glitch signals in PMU FIMV mode without step changes in that, after step 13, the following steps are performed: The PMU attribute information for the output voltage and current circuit of the unit under test (AD) is set, and the FIMV mode output -FI is configured to output to pogo; the time for the PMU to generate voltage is set based on the load type variable bRorC; vecDelayTimeR is set to {2.0ms, 2.0ms, 2.0ms, 2.0ms} when no capacitor is connected, and vecDelayTimeC is set to {45.0ms, 4.0ms, 2.0ms, 2.0ms, 2.0ms} when capacitor is connected. The process then proceeds to step 14.

[0198] The difference between the FVMI multi-channel, multi-scenario glitch test process for switching PMU FIMV mode to FVMI and the non-step-change multi-channel, multi-scenario glitch test process for PMU FIMV mode is that, after step 13, the following steps are performed: The PMU attribute information for the output voltage and current circuit of the unit under test (AD) is set, and the FVMI mode output FV is configured to output the FV to the pogo pin; the time for the PMU to generate the voltage is set based on the load type variable bRorC; vecDelayTimeR is set to {2.0ms, 2.0ms, 2.0ms, 2.0ms} when no capacitor is connected, and vecDelayTimeC is set to {45.0ms, 4.0ms, 2.0ms, 2.0ms, 2.0ms} when capacitor is connected. Then, the process continues with step 14.

[0199] For the sake of ease of understanding, the PMU FVMI mode non-step change multi-channel multi-scenario glitch test process is used as an example to illustrate. Figure 5 As shown, it mainly includes the following steps:

[0200] 1. Initialize the load type variable bRorC and the oscilloscope's single waveform acquisition threshold uiCaptureCnt. The load type variable bRorC is initialized to true if a capacitive load is connected, otherwise it is set to false. The oscilloscope's single waveform acquisition threshold uiCaptureCnt is the number of times the oscilloscope acquires a waveform in a single shot. The default value is 1. The output signal variable FV = -1.8V.

[0201] 2. By parsing the group pin, we can get the slot number and channel number information bound to the pin. Phoenix defines the group pin and PinMap information. The group pin = "PMU_CH32_GRP". The parsed single pin vector vecPin = {"AWG_P0", "AWG_N0", "AWG_P1", "AWG_N1", "DGT_P0", "DGT_N0", "DGT_P1", "DGT_N1"}. These 8 are the initialization values ​​of the vector vecPin. The channel mapping of each single pin is mapSlotsChs. Taking a single pin as an example, mapSlotsChs["AWG_P0"] = {{15, 0}, {15, 4}, {15, 8}, {15, 12}}; the initialization iterator PinIter can obtain the initial address of vecPin; there are 8 pins, each of which contains slot and channel information.

[0202] 3. The load unit Check is initialized so that the relay on the check board is disconnected.

[0203] 4. Traverse the output voltage and current circuit PMU gear variable IRange (0~4), traverse the output voltage value (-1.8V~1.8V), traverse the pin of the bound channel (vecPin), and traverse the channel mapping information (mapSlotsChs) under the pin.

[0204] 5. Initialize the connection to the oscilloscope, reset the oscilloscope, and configure the probe channel connected to the oscilloscope.

[0205] 6. Set the oscilloscope's time and voltage scales based on the load type variable bRorC. Without capacitors, set vecTimeScaleR to {2ms, 2ms, 2ms, 2ms} and vecVoltageScaleR to {0.5V, 0.5V, 0.5V, 0.5V, 0.5V}. With capacitors, set vecTimeScaleC to {20ms, 4.0ms, 2ms, 2ms} and vecVoltageScaleC to {0.5V, 0.5V, 0.5V, 0.5V, 0.5V}.

[0206] 7. Reset the load unit Check relay to the disconnected state, and then connect the load unit Check pressure measurement link according to the traversed channel information; the channel information includes [SoltChIter.uiSlot, SoltChIter.uiChannel].

[0207] 8. Set the oscilloscope horizontal position to 70 and vertical position to 0; 70 and 0 are empirical values.

[0208] 9. Set the oscilloscope's delayed trigger mode and trigger level based on the positive or negative output voltage value. If the voltage value is negative, use rising edge triggering and a trigger level of -0.5V. If the voltage value is positive, use falling edge triggering and a trigger level of 0.5V.

[0209] 10. If the oscilloscope's single waveform acquisition threshold uiCaptureCnt is greater than 1, you need to set the oscilloscope to continuous acquisition and display waveform retention mode.

[0210] 11. Loop through the oscilloscope acquisition times.

[0211] 12. Each time the oscilloscope is used for acquisition, the PMU attribute information of the AD board output voltage and current circuit of the unit under test is set, and the FVMI mode is configured to be output to the pogo;

[0212] 13. Each time the oscilloscope acquires data, the time it takes for the output voltage and current circuit PMU to generate voltage is set according to the load type variable bRorC. When no capacitor is connected, vecDelayTimeR = {2.0ms, 2.0ms, 2.0ms, 2.0ms}; when capacitor is connected, vecDelayTimeC = {45.0ms, 4.0ms, 2.0ms, 2.0ms, 2.0ms}.

[0213] 14. Each time the oscilloscope collects data, disconnect the channel where the PMU of the output voltage and current circuit is located, and the output is 0.

[0214] 15. When the number of acquisitions is greater than 1, the delay is controlled according to the load type variable bRorC to ensure that the oscilloscope acquires waveforms multiple times without confusion; if no capacitor is connected, vecTimeScaleR[uiIrange]x10-vecDelayTimeR[uiIrange] is used; if capacitor is connected, vecTimeScaleC[uiIrange]x10-vecDelayTimeC[uiIrange] is used.

[0215] 16. After waveform acquisition is completed, control the oscilloscope to save the image and reset the oscilloscope.

[0216] Among them, the difference between the PMU FVMI mode multi-channel multi-scenario glitch test process with step change and the PMU FVMI mode multi-channel multi-scenario glitch test process without step change is that: after step 13, it also includes setting the output voltage and current circuit PMU attribute information of the unit under test AD, and configuring the FVMI mode to output FV / 2 to pogo; setting the time for the PMU to generate voltage according to the load type variable bRorC; when no capacitor is connected, vecDelayTimeR={2.0ms, 2.0ms, 2.0ms, 2.0ms}, and when capacitor is connected, vecDelayTimeC={45.0ms, 4.0ms, 2.0ms, 2.0ms, 2.0ms}.

[0217] Among them, the difference between the PMU FVMI mode positive and negative step change multi-channel multi-scenario glitch test process and the PMU FVMI mode non-step change multi-channel multi-scenario glitch test process is that: after step 13, it also includes setting the output voltage and current circuit PMU attribute information of the unit under test AD, and configuring the FVMI mode output -FV to pogo; setting the time for the voltage generated by the PMU according to the load type variable bRorC; when no capacitor is connected, vecDelayTimeR={2.0ms, 2.0ms, 2.0ms, 2.0ms}, and when capacitor is connected, vecDelayTimeC={45.0ms, 4.0ms, 2.0ms, 2.0ms, 2.0ms}.

[0218] Among them, the difference between the PMU FVMI mode switching FIMV multi-channel multi-scenario glitch test and the PMU FVMI mode non-step change multi-channel multi-scenario glitch test process is that: after step 13, it also includes setting the output voltage and current circuit PMU attribute information of the unit AD under test, and configuring the FIMV mode output FI to pogo; setting the time for the voltage generated by the PMU according to the load type variable bRorC; when no capacitor is connected, vecDelayTimeR={2.0ms, 2.0ms, 2.0ms, 2.0ms}, and when the capacitor is connected, vecDelayTimeC={45.0ms, 4.0ms, 2.0ms, 2.0ms, 2.0ms}.

[0219] The above two embodiments provide test flow charts for each test case. These test cases can automatically traverse conditional test glitches, greatly saving manpower, time and cost. Moreover, these test cases cover all scenarios and detect problems in a timely manner, helping developers to solve glitches in a targeted manner.

[0220] It should be understood that, although the steps in the flowcharts of the above embodiments are shown in sequence as indicated by the arrows, these steps are not necessarily performed in the order indicated by the arrows. Unless otherwise specified herein, there is no strict order restriction on the execution of these steps, and these steps can be performed in other orders. Moreover, at least a portion of the steps in the flowcharts of the above embodiments may include multiple steps or multiple stages, and these steps or stages are not necessarily performed at the same time, but can be performed at different times. The execution order of these steps or stages is not necessarily to be performed in sequence, but can be performed in turn or alternately with other steps or at least a portion of steps or stages in other steps.

[0221] Based on the same inventive concept, embodiments of the present application further provide a glitch testing device for implementing the aforementioned glitch testing method. The solution provided by this device is similar to the solution described in the aforementioned method. Therefore, the specific limitations of one or more glitch testing device embodiments provided below can be found in the above-described limitations of the glitch testing method and will not be further elaborated here.

[0222] In an exemplary embodiment, Figure 6 As shown, a glitch testing device is provided, comprising: a target channel determination module 501, a first control module 502, a second control module 503 and a glitch information acquisition module 504, wherein:

[0223] The target channel determination module 501 is used to determine scene information and determine each current target channel information based on the scene information;

[0224] A first control module 502 is configured to control the unit under test to connect or disconnect the link of each current target channel based on the information of each current target channel, and to control the load network of the load unit to connect to the unit under test;

[0225] The second control module 503 is configured to control the UUT to output signals to the load network of the load unit through the links of each current target channel based on the scenario information, and to collect waveform information of the corresponding target channel of the UUT through an oscilloscope each time the UUT stops outputting signals;

[0226] The glitch information acquisition module 504 is configured to obtain glitch information based on the collected waveform information.

[0227] In one of the optional embodiments, the above-mentioned device also includes: a software initialization module, used to initialize the load type variable, the load type variable is used to indicate the type of the load network; initialize the gear variable and output signal variable of the unit to be tested; parse the group pin to obtain channel configuration information, the channel configuration information includes each initial pin information, each initial slot information bound to each pin and each initial channel information, and use the gear variable, output signal variable and channel configuration information of the unit to be tested as initialization loop variables, and the number of times each variable in the initialization loop variable is traversed is the number of changes of the current target channel.

[0228] In one of the optional embodiments, the above-mentioned target channel information determination module is specifically used to determine the current target channel information based on the value of the initialization loop variable and the scene information, and after collecting the waveform information of the target channel corresponding to the unit under test through the oscilloscope, update the value of the initialization loop variable, and continue to determine the current target channel information based on the value of the initialization loop variable until the values ​​corresponding to each initialization loop variable are traversed.

[0229] In one of the optional embodiments, the above-mentioned target channel information determination module is specifically used to determine the current target channel information based on the value corresponding to the gear variable of the unit to be tested, the value corresponding to the output signal variable of the unit to be tested under each gear, each initial pin information and the initial channel information bound to each pin; wherein, the relationship between the value corresponding to the output signal variable of the unit to be tested and the value corresponding to the gear variable of the unit to be tested is determined by the output mode of the unit to be tested in the scene information; and the initial channel information, each initial pin information, the value corresponding to the output signal variable of the unit to be tested and the value of the gear variable of the unit to be tested are cycled in sequence.

[0230] In one of the optional embodiments, the above-mentioned device further includes: a load unit initialization module, which is used to initialize and configure the communication between the load unit and the communication unit.

[0231] In one optional embodiment, the apparatus further includes: an oscilloscope initialization module for initializing and configuring the oscilloscope, the load unit, and the unit under test based on the scenario information, the current target channel information, and the value of the load type variable.

[0232] In one of the optional embodiments, the above-mentioned oscilloscope initialization module is specifically used to initialize the connection between the industrial computer and the oscilloscope, reset the oscilloscope and configure the probe channels of the oscilloscope and the load unit; update the display scale information of the oscilloscope based on the load type; reset the relay of the load unit, and connect the unit to be tested and the load unit according to the current target channel information; configure the horizontal position value and the vertical position value of the oscilloscope; configure the trigger mode and trigger level of the oscilloscope based on the scene information; initialize the attribute information of the output voltage and current circuit in the unit to be tested.

[0233] In one optional embodiment, the oscilloscope initialization module is specifically used to initialize the threshold value and the number variable of the number of waveforms acquired by the oscilloscope in a single time; based on the threshold value of the number of waveforms acquired by the oscilloscope in a single time, set the oscilloscope acquisition mode and the display waveform retention mode;

[0234] The above-mentioned second control module 503 is also used to detect whether the value of the number variable is less than the threshold value of the number of waveform acquisitions of the oscilloscope in a single time; when the value of the number variable is less than the threshold value of the number of waveform acquisitions of the oscilloscope in a single time, the output signal of the unit under test is controlled based on the value of the load type variable and the scene information, and each time the unit under test stops outputting a signal, the waveform information corresponding to the load unit is collected by the oscilloscope, the delay time of the unit under test is updated based on the value of the load type variable, the value of the waveform number variable is updated, and the step of detecting whether the value of the number variable is less than the threshold value of the number of waveform acquisitions of the oscilloscope in a single time is continued, until the value of the number variable is greater than or equal to the threshold value of the number of waveform acquisitions of the oscilloscope in a single time, and the step of updating the value of the initialization loop variable is continued.

[0235] In one of the optional embodiments, the above-mentioned second control module 503 is specifically used to determine the output target value of each output mode of the unit to be tested based on the scenario information; output the current output mode output target value to the link of the target channel; determine the delay time of the output signal of the unit to be tested based on the value of the load type variable; determine whether there is a next output mode output target value; if there is no next output mode output target value and the output time of the output target value of the unit to be tested reaches the delay time, disconnect the unit to be tested from the target channel link, and collect the waveform information corresponding to the load unit through an oscilloscope; if there is a next output mode output target value, use the next output mode output target value as the current output mode output target value, and continue to execute the step of outputting the current output mode output target value to the target channel link until all output mode output target values ​​are traversed.

[0236] In one optional embodiment, the scene information includes different output modes of the unit under test and different scene types corresponding to each output mode, and the different scene types include at least one of no step change, step change, positive and negative step change, and switching between different output modes;

[0237] The step-free change includes: after the unit under test outputs an output signal with a negative value or a positive value for a first period of time, the output signal returns to 0;

[0238] The step change includes: the unit under test outputs an output signal of a negative value or a positive value in a first time period; then outputs an output signal of a negative value or a positive value half of the first time period, and then the output signal returns to 0;

[0239] The positive and negative step changes include: the unit under test outputs an output signal of a negative value or a positive value in a first time period; then outputs an output signal of an output value of an inverted signal in the first time period, and then the output signal returns to 0;

[0240] Switching between different output modes includes: first, the unit under test outputs a negative or positive value of the initial mode signal, which lasts for a first time period and then the output signal returns to 0; second, outputting a signal value with the inverted sign of different modes, which lasts for a first time period; finally, the output signal returns to 0.

[0241] In one optional embodiment, the target scenario information determination module is specifically used to obtain a current test case, each test case corresponds to a test scenario; determine scenario information based on the current test case;

[0242] The above-mentioned device also includes: a loop module for obtaining the next test case after obtaining the corresponding waveform information based on the current test case, and continuing to execute the step of determining the scenario information based on the current test case until each test case is executed.

[0243] Each module in the glitch test device can be implemented in whole or in part through software, hardware, or a combination thereof. Each module can be embedded in or independent of a processor in a computer device in hardware form, or can be stored in a memory in the computer device in software form, so that the processor can call and execute the corresponding operations of each module.

[0244] In an exemplary embodiment, a computer device is provided. The computer device may be an industrial computer, and its internal structure diagram may be as follows: Figure 7 As shown. The computer device includes a processor, memory, an input / output interface, a communication interface, a display unit, and an input device. The processor, memory, and input / output interface are connected via a system bus, and the communication interface, display unit, and input device are connected to the system bus via the input / output interface. The processor of the computer device is used to provide computing and control capabilities. The memory of the computer device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system and a computer program. The internal memory provides an environment for the operation of the operating system and computer program in the non-volatile storage medium. The input / output interface of the computer device is used to exchange information between the processor and an external device. The communication interface of the computer device is used to communicate with an external terminal via wired or wireless communication, and the wireless communication can be achieved via Wi-Fi, a mobile cellular network, near-field communication (NFC), or other technologies. When executed by the processor, the computer program implements a glitch testing method. The display unit of the computer device is used to form a visually visible image, and can be a display screen, a projection device, or a virtual reality imaging device. The display screen can be a liquid crystal display screen or an electronic ink display screen, and the input device of the computer device can be a touch layer covering the display screen, or a button, trackball or touchpad set on the computer device casing, or an external keyboard, touchpad or mouse.

[0245] Those skilled in the art will understand that Figure 7 The structure shown in the figure is only a block diagram of a part of the structure related to the solution of the present application, and does not constitute a limitation on the computer device to which the solution of the present application is applied. The specific computer device may include more or fewer components than shown in the figure, or combine certain components, or have a different component arrangement.

[0246] In one embodiment, a computer device is further provided, including a memory and a processor. The memory stores a computer program, and the processor implements the steps in the above method embodiments when executing the computer program.

[0247] In one embodiment, a computer-readable storage medium is provided, on which a computer program is stored. When the computer program is executed by a processor, the steps in the above-mentioned method embodiments are implemented.

[0248] In one embodiment, a computer program product is provided, including a computer program, which implements the steps in the above method embodiments when executed by a processor.

[0249] Those skilled in the art will understand that all or part of the processes in the above-mentioned embodiments can be implemented by instructing the relevant hardware through a computer program. The computer program can be stored in a non-volatile computer-readable storage medium. When the computer program is executed, it can include the processes of the embodiments of the above-mentioned methods. In particular, any reference to memory, database, or other media used in the embodiments provided in this application can include at least one of non-volatile memory and volatile memory. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical memory, high-density embedded non-volatile memory, resistive random access memory (ReRAM), magnetic random access memory (MRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), graphene memory, etc. Volatile memory can include random access memory (RAM) or external cache memory, etc. By way of illustration and not limitation, RAM can take various forms, such as static random access memory (SRAM) or dynamic random access memory (DRAM). The databases involved in the various embodiments provided herein may include at least one of a relational database and a non-relational database. Non-relational databases may include, but are not limited to, blockchain-based distributed databases. The processors involved in the various embodiments provided herein may be, but are not limited to, general-purpose processors, central processing units (CPUs), graphics processing units (GPUs), digital signal processors (DSPs), programmable logic devices (PLDs), quantum computing-based data processing logic devices, artificial intelligence (AI) processors, and the like.

[0250] The technical features of the above embodiments can be combined arbitrarily. In order to make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this application.

[0251] The above-described embodiments merely represent several implementation methods of the present application. While the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the present application. It should be noted that a person of ordinary skill in the art may make various modifications and improvements without departing from the spirit of the present application, and these modifications and improvements fall within the scope of protection of the present application. Therefore, the scope of protection of the present application shall be determined by the appended claims.

Claims

1. A burr testing method, characterized in that: The method comprises: Determining scene information, and determining information of each current target channel based on the scene information, wherein the scene information includes different output modes of the unit under test and different scene types corresponding to each output mode, and the different scene types include at least one of no step change, step change, positive and negative step change, and switching between different output modes; sequentially controlling the unit under test to connect or disconnect the link of each current target channel based on the information of each current target channel, and controlling the load network of the load unit to connect to the unit under test; Based on the scenario information, the unit under test is controlled to output signals to the load network of the load unit through the links of each current target channel, and each time the unit under test stops outputting signals, the waveform information of the unit under test corresponding to the current target channel is collected through an oscilloscope, including: determining the output target value of each output mode of the unit under test based on the scenario information; outputting the current output mode output target value to the link of the target channel; determining the delay time of the output signal of the unit under test based on the value of a load type variable, the load type variable being used to represent the type of the load network; if there is no next output mode output target value and the output time of the output target value of the unit under test reaches the delay time, disconnecting the unit under test from the target channel link, and collecting the waveform information corresponding to the load unit through an oscilloscope; or, if there is a next output mode output target value, using the next output mode output target value as the current output mode output target value, and continuing to execute the step of outputting the current output mode output target value to the target channel link until all the output mode output target values ​​are traversed; Glitch information is obtained based on the acquired waveform information.

2. The method according to claim 1, characterized in that After determining the scene information, the method further includes: Initialize payload type variables; Initialize the gear position variable and output signal variable of the unit to be tested; The group pin is parsed to obtain channel configuration information, which includes the initial pin information, the initial slot information bound to each pin, and the initial channel information. The gear variable of the unit under test, the output signal variable, and the channel configuration information are used as initialization loop variables. The number of times each variable in the initialization loop variable is traversed is the number of changes in the current target channel.

3. The method according to claim 2, characterized in that Determining the information of each current target channel includes: The current target channel information is determined based on the value of the initialization loop variable and the scene information, and after the waveform information of the target channel corresponding to the unit under test is collected by an oscilloscope, the value of the initialization loop variable is updated, and the current target channel information is continued to be determined based on the value of the initialization loop variable until all the values ​​corresponding to the initialization loop variables are traversed.

4. The method according to claim 3, characterized in that The determining the current target channel information based on the value of the initialization loop variable and the scene information includes: Determine the current target channel information based on the value corresponding to the gear position variable of the unit under test, the value corresponding to the output signal variable of the unit under test at each gear position, the initial pin information, and the initial channel information bound to each pin; wherein the relationship between the value corresponding to the output signal variable of the unit under test and the value corresponding to the gear position variable of the unit under test is determined by the output mode of the unit under test in the scenario information; The updating of the value of the initialization loop variable comprises: The initial channel information, the initial pin information, the value corresponding to the output signal variable of the unit to be tested and the value of the gear variable of the unit to be tested are cycled in sequence.

5. The method according to claim 2, characterized in that After determining the scene information, the method further includes: Initialize the configuration of the load unit and the communication unit communication.

6. The method according to claim 2, characterized in that Before sequentially controlling the unit under test to connect to or disconnect from the links of the current target channels based on the information of the current target channels, the method further includes: The oscilloscope, the load unit and the unit under test are initialized and configured based on the scenario information, the current target channel information and the value of the load type variable.

7. The method according to claim 6, characterized in that The initializing and configuring the oscilloscope, the load unit, and the unit under test based on the scenario information, the current target channel information, and the value of the load type variable includes: Initializing the connection between the industrial computer and the oscilloscope, resetting the oscilloscope and configuring the probe channels of the oscilloscope and the load unit; updating display scale information of the oscilloscope based on the load type; Resetting the relay of the load unit and connecting the unit under test and the load unit according to the current target channel information; Configure the horizontal and vertical position values ​​of the oscilloscope; configuring a trigger mode and a trigger level of the oscilloscope based on the scenario information; Initialize the attribute information of the output voltage and current circuit in the unit under test.

8. The method according to claim 2, characterized in that The method further comprises: Initialize the oscilloscope's single waveform acquisition threshold and number variables; Setting the oscilloscope acquisition mode and display waveform retention mode based on the threshold of the number of times the oscilloscope acquires waveforms in a single shot; The controlling the unit under test to output signals to the load network of the load unit through the link of the current target channel based on the scenario information, and collecting waveform information of the unit under test corresponding to the current target channel through an oscilloscope each time the unit under test stops outputting signals, includes: Detecting whether the value of the number variable is less than the threshold value of the number of times the oscilloscope acquires a waveform in a single shot; When the value of the number variable is less than the threshold value of the number of waveform acquisitions by the oscilloscope in a single time, the output signal of the unit under test is controlled based on the value of the load type variable and the scenario information, and each time the unit under test stops outputting a signal, the waveform information corresponding to the load unit is acquired through the oscilloscope, the delay time of the unit under test is updated based on the value of the load type variable, the value of the waveform number variable is updated, and the step of detecting whether the value of the number variable is less than the threshold value of the number of waveform acquisitions by the oscilloscope in a single time is continued, until it is detected that the value of the number variable is greater than or equal to the threshold value of the number of waveform acquisitions by the oscilloscope in a single time, and the step of updating the value of the initialization loop variable is continued.

9. The method according to claim 1, characterized in that The step-free change includes: after the unit under test outputs an output signal with a negative value or a positive value for a first period of time, the output signal returns to 0; The step change includes: the unit under test outputting an output signal of a negative value or a positive value in a first time period; then outputting an output signal of a negative value or a positive value half of the first time period, and then returning the output signal to 0; The positive and negative step changes include: the unit under test outputting an output signal of a negative value or a positive value in a first time period; then outputting an output signal of an output value of an inverted signal in the first time period, and then returning the output signal to 0; The switching of different output modes includes: first, the unit under test outputs a negative value or a positive value of an initial mode signal, which lasts for a first time period, and then the output signal returns to 0; second, the output of different mode signs takes the inverted signal value, which lasts for a first time period; finally, the output signal returns to 0.

10. The method according to claim 1, characterized in that The determining of the scene information includes: Get the current test case, each test case corresponds to a test scenario; Determining scenario information based on the current test case; The method further comprises: After the corresponding waveform information is obtained based on the current test case, the next test case is obtained, and the step of determining the scenario information based on the current test case is continued until the execution of each test case is completed.

11. A burr testing device, characterized in that: The device comprises: a target channel determination module, configured to determine scenario information and determine information of each current target channel based on the scenario information, wherein the scenario information includes different output modes of the unit under test and different scenario types corresponding to each output mode, wherein the different scenario types include at least one of no step change, step change, positive or negative step change, and switching between different output modes; A first control module is used to control the unit under test to connect or disconnect the link of each current target channel based on the information of each current target channel, and to control the load network of the load unit to connect to the unit under test; a second control module, configured to control the unit under test to output signals to the load network of the load unit through the links of the current target channels based on the scenario information, and to collect waveform information of the target channel corresponding to the unit under test through an oscilloscope each time the unit under test stops outputting signals; A glitch information acquisition module, used to obtain glitch information based on the collected waveform information; The second control module is specifically used to determine the output target value of each output mode of the unit under test based on the scenario information; output the current output mode output target value to the link of the target channel; determine the delay time of the output signal of the unit under test based on the value of the load type variable, and the load type variable is used to represent the type of the load network; if there is no next output mode output target value and the output time of the output target value of the unit under test reaches the delay time, disconnect the unit under test from the target channel link and collect the waveform information corresponding to the load unit through an oscilloscope; or, if there is a next output mode output target value, use the next output mode output target value as the current output mode output target value, and continue to execute the step of outputting the current output mode output target value to the target channel link until all the output mode output target values ​​are traversed.

12. A burr testing system, characterized in that: The system comprises: An industrial computer, configured to execute the glitch testing method according to any one of claims 1 to 10 to obtain glitch information; Communication unit, used to establish communication between the industrial computer and the load unit and the unit under test; A load unit communicates with the industrial computer via a communication unit, the load unit being configured to be initialized based on the control of the industrial computer and to enable a link from the unit under test to the load unit; The unit under test communicates with the industrial computer through the communication unit, and the unit under test is used to establish or disconnect the connection with the target channel link based on the control output signal of the industrial computer; An oscilloscope is connected to the industrial computer and the load unit respectively, and is used for initialization and configuration based on the control of the industrial computer, and for collecting waveform information output by the load unit.

13. A computer device comprising a memory and a processor, wherein the memory stores a computer program, wherein: When the processor executes the computer program, the steps of the method according to any one of claims 1 to 10 are implemented.

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