Driving circuit and distance measuring sensor

Abstract

The invention provides a driving circuit and a distance measuring sensor which can enable a light emitting element to stably emit light pulses with short pulse widths. The drive circuit includes: an n-channel field effect transistor including a gate, a drain, and a source, a current constituting a drive current for driving a light emitting element flowing into the drain; a capacitor that AC-grounds the gate electrode; and a source driving circuit that drives the source with a signal corresponding to the inputted pulse signal.

Description

Technical Field

[0001] The present disclosure relates to a drive circuit and a distance measurement sensor. Background Art

[0002] International Publication No. 2017 / 209206 discloses a distance measurement sensor using the time-of-flight (ToF) method. In this distance measurement sensor, a vertical cavity surface emitting laser (VCSEL) driver drives a VCSEL.

[0003] Thereby, the VCSEL emits light pulses. A single photon avalanche diode (SPAD) array receives the light reflected by the object to be detected. Thereby, the SPAD array outputs a pulse signal (paragraphs 0017 - 0020 and 0022). Summary of the Invention

[0004] In the distance measurement sensor disclosed in International Publication No. 2017 / 209206, the shorter the pulse width of the light pulse emitted by the VCSEL, the higher the accuracy of distance measurement. However, in this distance measurement sensor, it is difficult to stably emit a light pulse with a short pulse width from the VCSEL.

[0005] One aspect of the present disclosure has been completed in view of the above problems. An object of one aspect of the present disclosure is to provide a drive circuit and a distance measurement sensor capable of stably emitting a light pulse having, for example, a short pulse width from a light emitting element.

[0006] A drive circuit according to one aspect of the present disclosure includes: an n-channel field effect transistor including a gate, a drain, and a source, and a drive current for driving a light emitting element flows into the drain; a capacitor that AC grounds the gate; and a source drive circuit that drives the source with a signal corresponding to an input pulse signal. Brief Description of the Drawings

[0007] Figure 1 It is a cross-sectional view schematically showing a distance measurement sensor of the first embodiment and an object to be measured for distance measurement by the distance measurement sensor. Figure 2 It is a block diagram of a light receiving integrated circuit (IC) and a light emitting element included in the distance measurement sensor of the first embodiment. Figure 3 It is a diagram showing an example of a histogram of a first time difference and a histogram of a second time difference produced by a histogram generation / distance calculation unit included in the distance measurement sensor of the first embodiment. Figure 4 It is a circuit diagram of a drive circuit and a light emitting element included in the distance measurement sensor of the first embodiment. Figure 5This is a diagram showing the drive signal input to the drive circuit of the distance measurement sensor according to the first embodiment and the waveform of the drive current output by this drive circuit. Figure 6 This is a diagram showing the drive signal input to the input terminals of the first inverter and the second inverter of the drive circuit of the distance measurement sensor according to the first embodiment, and the waveform of the inverted pulse signal output from the output terminals of this first inverter and this second inverter. Figure 7 This is a circuit diagram showing the equivalent circuit of the light-emitting element, the anode-side gold wire, the cathode-side gold wire, and the buffer circuit of the distance measurement sensor according to the first embodiment. Figure 8 This is a graph showing an example of the waveform of the drive current output by the drive circuit of the distance measurement sensor according to the first embodiment and the waveform of the drive current output by this drive circuit when the buffer circuit is omitted from this drive circuit. Figure 9 This is a circuit diagram of the drive circuit of the distance measurement sensor according to the second embodiment. Figure 10 This is a circuit diagram of the drive circuit of the distance measurement sensor according to the third embodiment. Detailed Embodiments

[0008] Hereinafter, embodiments of the present disclosure will be described with reference to the drawings. In addition, for the drawings, the same or equivalent elements are given the same reference numerals, and repeated descriptions are omitted.

[0009] 1. First Embodiment 1.1 Distance Measurement Sensor Figure 1 This is a cross-sectional view schematically showing the distance measurement sensor according to the first embodiment and the object to be measured by this distance measurement sensor.

[0010] Figure 1 The shown distance measurement sensor 1 according to the first embodiment is a time-of-flight (ToF) type distance measurement sensor. Therefore, the distance measurement sensor 1 emits the second pulsed light 12, receives the reflected pulsed light 13 generated by reflecting the emitted second pulsed light 12 by the object 2, and measures the distance to the object 2 based on the time from when the second pulsed light 12 is emitted to when the reflected pulsed light 13 is received.

[0011] As Figure 1 shown, the distance measurement sensor 1 includes a package 21, a light-emitting element 22, a first optical filter 23, a condenser lens 24, a second optical filter 25, a light-receiving integrated circuit (IC) 26, and a light-shielding wall 27. The light-receiving IC 26 includes a first light-receiving element 31 and a second light-receiving element 32.

[0012] An internal space 21a, a first hole 21b, and a second hole 21c are formed in the package 21. The internal space 21a houses a light-emitting element 22, a first optical filter 23, a second optical filter 25, a light-receiving IC 26, and a light-shielding wall 27. The first hole 21b reaches the outside of the package 21 from the internal space 21a. The second hole 21c reaches the outside of the package 21 from the internal space 21a. The second hole 21c houses a condenser lens 24.

[0013] The light-emitting element 22 emits pulsed light including first pulsed light 11 and second pulsed light 12. The first pulsed light 11 does not exit to the outside of the package 21 but advances into the internal space 21a of the package 21 and reaches a first light-receiving element 31 via the first optical filter 23. The second pulsed light 12 is emitted from the internal space 21a to the outside of the package 21 via the first hole 21b and reaches an object 2. The reflected pulsed light 13 generated by reflecting the second pulsed light 12 by the object 2 reaches a second light-receiving element 32 from the outside of the package 21 via the condenser lens 24 and the second optical filter 25. The light-emitting element 22 is a vertical-cavity surface-emitting laser (VCSEL). The light-emitting element 22 may also be a light-emitting element other than a VCSEL.

[0014] The first optical filter 23 transmits the first pulsed light 11. The first optical filter 23 selectively transmits light having the wavelength of the first pulsed light 11 and wavelengths close to the wavelength.

[0015] The first light-receiving element 31 receives the first pulsed light 11 that has passed through the first optical filter 23 and outputs a first pulse signal corresponding to the received first pulsed light 11. The first light-receiving element 31 is a single-photon avalanche diode (SPAD) array. The first light-receiving element 31 may also be a light-receiving element other than a SPAD array.

[0016] The condenser lens 24 transmits the reflected pulsed light 13. The condenser lens 24 condenses the reflected pulsed light 13 onto the second light-receiving element 32.

[0017] The second optical filter 25 transmits the reflected pulsed light 13 that has passed through the condenser lens 24. The second optical filter 25 selectively transmits light having the wavelength of the second pulsed light 12 and wavelengths close to the wavelength.

[0018] The second light-receiving element 32 receives the reflected pulsed light 13 that has passed through the second optical filter 25 and outputs a second pulse signal corresponding to the received reflected pulsed light 13. The second light-receiving element 32 is a SPAD array. The second light-receiving element 32 may also be a light-receiving element other than a SPAD array.

[0019] The light-shielding wall 27 separates the region where the second light-receiving element 32 is disposed from the region where the light-emitting element 22 and the first light-receiving element 31 are disposed. The light-shielding wall 27 blocks light. Thus, the light-shielding wall 27 prevents the first pulsed light 11 from reaching the second light-receiving element 32.

[0020] The light-receiving IC 26 obtains the distance between the distance measurement sensor 1 and the object 2 based on the output first pulsed signal and second pulsed signal.

[0021] The first optical filter 23 and the first light-receiving element 31 are respectively referred to as the optical filter and the light-receiving element on the reference side. The second optical filter 25 and the second light-receiving element 32 are respectively referred to as the optical filter and the light-receiving element on the return side.

[0022] 1.2 Light-receiving IC Figure 2 is a block diagram of the light-receiving IC and the light-emitting element included in the distance measurement sensor of the first embodiment.

[0023] As Figure 2 shown, the light-receiving IC 26 includes a drive circuit 41, a first front-end circuit 42, a high-voltage generation circuit 43, a second front-end circuit 44, a third front-end circuit 45, a time measurement circuit 46, a time difference calculation unit 47, and a histogram generation / distance calculation unit 48.

[0024] A drive signal 51 is input to the drive circuit 41. The drive circuit 41 drives the light-emitting element 22 with a drive current 61 corresponding to the input drive signal 51. Thus, the light-emitting element 22 emits light corresponding to the drive signal 51. The drive signal 51 includes a pulsed signal. Therefore, the emitted light includes pulsed light emitted synchronously with the pulsed signal. The pulsed light includes the first pulsed light 11 and the second pulsed light 12. The drive circuit 41 outputs a drive signal 52 corresponding to the drive current 61.

[0025] The output drive signal 52 is input to the first front-end circuit 42. The first front-end circuit 42 shapes the waveform of the input drive signal 52 and outputs a drive signal having the shaped waveform.

[0026] The high-voltage generation circuit 43 generates a high voltage and outputs the generated high voltage. The output high voltage has a voltage value of, for example, 10 to 20V.

[0027] The output high voltage is applied to the first light-receiving element 31. The first light-receiving element 31 operates by the applied high voltage. The first light-receiving element 31 receives the first pulsed light 11 and outputs a first pulsed signal corresponding to the received first pulsed light 11.

[0028] The first output pulse signal is input to the second front-end circuit 44. The second front-end circuit 44 shapes the waveform of the input first pulse signal and outputs a first pulse signal having the shaped waveform.

[0029] The output high voltage is applied to the second light-receiving element 32. The second light-receiving element 32 operates by the applied high voltage. The second light-receiving element 32 receives the second pulsed light 12 and outputs a second pulse signal corresponding to the received second pulsed light 12.

[0030] The output second pulse signal is input to the third front-end circuit 45. The third front-end circuit 45 shapes the waveform of the input second pulse signal and outputs a second pulse signal having the shaped waveform.

[0031] The drive signal, the first pulse signal, and the second pulse signal having the shaped waveforms are input to the time measurement circuit 46. The time measurement circuit 46 measures, based on the input drive signal, first pulse signal, and second pulse signal, the absolute values of the light emission time when the light-emitting element 22 emits the first pulsed light 11, the first light-receiving time when the first light-receiving element 31 receives the first pulsed light 11, and the second light-receiving time when the second light-receiving element 32 receives the second pulsed light 12, respectively. The time measurement circuit 46 outputs the measured absolute values of the light emission time, the first light-receiving time, and the second light-receiving time. The time measurement circuit 46 includes three time-to-digital converters (TDCs) for measuring the absolute values of the light emission time, the first light-receiving time, and the second light-receiving time. The time measurement circuit 46 outputs the drive signal 51.

[0032] The output absolute values of the light emission time, the first light-receiving time, and the second light-receiving time are input to the time difference calculation unit 47. The time difference calculation unit 47 calculates a first time difference from when the light-emitting element 22 emits the first pulsed light 11 until the first light-receiving element 31 receives the first pulsed light 11, based on the input absolute values of the light emission time and the first light-receiving time. Further, the time difference calculation unit 47 calculates a second time difference from when the light-emitting element 22 emits the first pulsed light 11 until the second light-receiving element 32 receives the second pulsed light 12, based on the input absolute values of the light emission time and the second light-receiving time. The time difference calculation unit 47 outputs the calculated first time difference and second time difference.

[0033] Figure 3 FIG. is a diagram showing an example of a histogram of the first time difference and a histogram of the second time difference created by the histogram generation / distance calculation unit included in the distance measurement sensor according to the first embodiment.

[0034] The output first time difference and second time difference are input to the histogram generation / distance calculation unit 48. The histogram generation / distance calculation unit 48 generatesFigure 3 Histogram 71 of the first time difference shown. The histogram generation / distance calculation unit calculates the first centroid time 81, which is the centroid of the histogram 71 of the first time difference created. In addition, the histogram generation / distance calculation unit 48 generates Figure 3 Histogram 72 of the second time difference shown. The histogram generation / distance calculation unit calculates the second centroid time 82, which is the centroid of the histogram 72 of the second time difference created. The histogram generation / distance calculation unit 48 calculates the time difference 91 between the calculated first centroid time 81 and the calculated second centroid time 82. The histogram generation / distance calculation unit 48 calculates the distance between the distance measurement sensor 1 and the object 2 based on the calculated time difference 91.

[0035] The histogram 71 of the first time difference is also referred to as the reference-side histogram. The histogram 72 of the second time difference is also referred to as the return-side histogram.

[0036] The time difference calculation unit 47 and the histogram generation / distance calculation unit 48 may be constituted by an electronic circuit or may be constituted by a processor that executes a program stored in a memory.

[0037] 1.3 Driving Circuit Figure 4 It is a circuit diagram of the driving circuit and the light-emitting element included in the distance measurement sensor of the first embodiment.

[0038] As Figure 4 shown, the driving circuit 41 includes an anode connection terminal 101, a cathode connection terminal 102, a power supply 103, a ground 104, an anode-side circuit 105, and a cathode-side circuit 106. The light-emitting element 22 includes an anode 22a and a cathode 22b.

[0039] The anode 22a and the cathode 22b of the light-emitting element 22 are electrically connected to the anode connection terminal 101 and the cathode connection terminal 102, respectively.

[0040] The power supply 103 and the ground 104 have a power supply potential and a ground potential, respectively.

[0041] The anode-side circuit 105 is electrically connected to the power supply 103 and the anode connection terminal 101. The anode-side circuit 105 causes the driving current 61 flowing out from the anode connection terminal 101 to flow from the power supply 103 to the anode connection terminal 101.

[0042] The cathode-side circuit 106 is electrically connected to the cathode connection terminal 102 and the ground 104. The cathode-side circuit 106 causes the driving current 61 flowing into the cathode connection terminal 102 to flow from the cathode connection terminal 102 to the ground 104.

[0043] Accordingly, the drive current 61 flows out from the anode connection terminal 101, passes through the light-emitting element 22, and flows into the cathode connection terminal 102.

[0044] 1.4 Connection between the drive circuit and the light-emitting element The anode 22a and the cathode 22b of the light-emitting element 22 are electrically connected to the anode connection terminal 101 and the cathode connection terminal 102 via an anode-side bonding wire and a cathode-side bonding wire, respectively.

[0045] The anode-side bonding wire and the cathode-side bonding wire each have a parasitic resistance and a parasitic inductance. The light-emitting element 22 has a parasitic capacitance. The parasitic resistance, the parasitic inductance, and the parasitic capacitance cause ringing of the drive current 61.

[0046] Countermeasures for suppressing ringing of the drive current 61 are implemented for the cathode-side circuit 106.

[0047] 1.5 Anode-side circuit As Figure 4 shown, the anode-side circuit 105 includes a p-channel field-effect transistor (FET) 111, a buffer 112, and a capacitor 113. The p-channel FET 111 includes a gate 111a, a source 111b, and a drain 111c. The buffer 112 includes an input terminal 112a and an output terminal 112b. The capacitor 113 includes a first terminal 113a and a second terminal 113b.

[0048] The source 111b of the p-channel FET 111 is electrically connected to the power supply 103. The drain 111c of the p-channel FET 111 is electrically connected to the anode connection terminal 101. Accordingly, a conduction path from the power supply 103 to the anode connection terminal 101 is formed. The source 111b and the drain 111c are inserted into the formed conduction path. Accordingly, when the drain 111c and the source 111b are conducting, the anode-side circuit 105 causes the drive current 61 to flow through the conduction path and causes the drive current 61 to flow out from the anode connection terminal 101. In addition, when the drain 111c and the source 111b are not conducting, the anode-side circuit 105 does not cause the drive current 61 to flow through the conduction path and does not cause the drive current 61 to flow out from the anode connection terminal 101.

[0049] When a conduction potential is applied to the gate 111a of the p-channel FET 111, the drain 111c of the p-channel FET 111 is made conductive with the source 111b of the p-channel FET 111, and the drive current 61 flows out from the drain 111c. When a cut-off potential is applied to the gate 111a of the p-channel FET 111, the drain 111c is not made conductive with the source 111b, and the drive current 61 does not flow out from the drain 111c. The conduction potential is a potential lower than the potential obtained by subtracting the threshold voltage of the p-channel FET 111 from the power supply potential, for example, the ground potential. The cut-off potential is a potential higher than the potential obtained by subtracting the threshold voltage of the p-channel FET 111 from the power supply potential, for example, the power supply potential.

[0050] The p-channel FET 111 is a metal oxide semiconductor (MOS) FET or the like.

[0051] The input terminal 112a of the buffer 112 is electrically connected to a control circuit that applies the conduction potential and the cut-off potential. The output terminal 112b of the buffer 112 is electrically connected to the gate 111a of the p-channel FET 111.

[0052] When a conduction potential is applied to the input terminal 112a of the buffer 112, the buffer 112 applies a conduction potential to the output terminal 112b and applies a conduction potential to the gate 111a of the p-channel FET 111. Further, when a cut-off potential is applied to the input terminal 112a, the buffer 112 applies a cut-off potential to the output terminal 112b and applies a cut-off potential to the gate 111a. The input terminal 112a of the buffer 112 has a high input impedance.

[0053] The first terminal 113a of the capacitor 113 is electrically connected to the drain 111c of the p-channel FET 111 and the anode connection terminal 101, and is electrically connected to the anode 22a of the light-emitting element 22 via the anode connection terminal 101. The second terminal 113b of the capacitor 113 is electrically connected to the ground 104. Thus, the capacitor 113 is inserted between the drain 111c and the ground 104. Thus, when the drive current 61 rises sharply, the capacitor 113 can supply at least a part of the drive current 61. Thus, the influence of the sharp rise of the drive current 61 can be suppressed from reaching the power supply 103. Thus, electromagnetic interference (EMI) caused by the sharp rise of the drive current 61 can be suppressed.

[0054] 1.6 Cathode-side circuit As Figure 4 shown, the cathode-side circuit 106 includes a bias current circuit 121, a reference current circuit 122, a mirror current circuit 123, a plurality of driver units 124, a feedback circuit 125, and a buffer circuit 126.

[0055] The bias current circuit 121 is electrically connected to the cathode connection terminal 102 and the ground 104. The bias current circuit 121 causes a bias current 131 to flow from the cathode connection terminal 102 to the ground 104. The flowing bias current 131 has a constant current value.

[0056] The reference current circuit 122 is electrically connected to the power supply 103 and the ground 104. The reference current circuit 122 causes a reference current 132 to flow from the power supply 103 to the ground 104. The flowing reference current 132 has a constant current value.

[0057] The mirror current circuit 123 is electrically connected to the cathode connection terminal 102 and the ground 104. The mirror current circuit 123 causes a mirror current 133 to flow from the cathode connection terminal 102 to the ground 104. The flowing mirror current 133 has the same current value as the current value of the reference current 132.

[0058] Each of the driver units 124 included in the plurality of driver units 124 is electrically connected to the cathode connection terminal 102 and is electrically connected to the ground 104 when turned on. Each driver unit 124 causes a mirror current 134 to flow from the cathode connection terminal 102 to the ground 104. The mirror current 134 has a current value that is 4 times the current value of the reference current 132. The mirror current 134 may also have a current value different from this current value. Each driver unit 124 is configured such that the current value of the mirror current 134 becomes 4 times the current value of the mirror current 133, and thus, is configured such that the current value of the mirror current 134 becomes 4 times the current value of the reference current 132.

[0059] The drive signal 51 is input to each driver unit 124. Each driver unit 124 allows the mirror current 134 to flow when the potential of the input drive signal 51 is at the H potential, and does not allow the mirror current 134 to flow when the potential of the input drive signal 51 is at the L potential. The H potential is a potential higher than the potential obtained by adding the threshold voltage of the n-channel FET 171 described later to the ground potential, and is, for example, the power supply potential. The L potential is a potential lower than the potential obtained by adding the threshold voltage of the n-channel FET 171 described later to the ground potential, and is, for example, the ground potential.

[0060] When the current value of the mirror current 133 is greater than the current value of the reference current 132, the feedback circuit 125 controls the mirror current circuit 123 to reduce the current value of the mirror current 133, and controls each driver unit 124 to reduce the current value of the mirror current 134. When the current value of the mirror current 133 is less than the current value of the reference current 132, the feedback circuit 125 controls the mirror current circuit 123 to increase the current value of the mirror current 133, and controls each driver unit 124 to increase the current value of the mirror current 134. Thus, the feedback circuit 125 mirrors the reference current 132 to the mirror current 133 such that the current value of the mirror current 133 becomes the same as the current value of the reference current 132, and mirrors the reference current 132 to the mirror current 134 such that the current value of the mirror current 134 becomes four times the current value of the reference current 132.

[0061] The reference current circuit 122, the mirror current circuit 123, and the feedback circuit 125 form a circuit that passes the reference current 132 and mirrors the reference current 132 to the mirror current 134, and together with each driver unit 124, form a current mirror circuit. The circuit that passes the reference current 132 and mirrors the reference current 132 to the mirror current 134 can be a circuit different from the Figure 4 circuit shown.

[0062] The bias current circuit 121, the mirror current circuit 123, and the plurality of driver units 124 are inserted between the cathode connection terminal 102 and the ground 104 and are electrically connected in parallel. Thus, the drive current 61 flowing into the cathode connection terminal 102 is shunted to the bias current circuit 121, the mirror current circuit 123, and the plurality of driver units 124. Therefore, the drive current 61 is composed of the bias current 131, the mirror current 133, and the plurality of mirror currents 134.

[0063] By electrically connecting the plurality of driver units 124 in parallel, the light-emitting element 22 can be driven by the drive current 61, which has a current value larger than the current value of the mirror current 134 that can flow through each driver unit 124.

[0064] The buffer circuit 126 is electrically connected to the cathode connection terminal 102 and the ground 104. The buffer circuit 126 suppresses ringing in the drive current 61.

[0065] 1.7 Waveforms of the drive signal and the drive current Figure 5 is a diagram showing the waveforms of the drive signal input to the drive circuit included in the distance measurement sensor of the first embodiment and the drive current output from the drive circuit.

[0066] As Figure 5As shown, the drive signal 51 includes a pulse signal 51a. In addition, the drive current 61 includes a pulse current 61a.

[0067] The drive circuit 41 outputs a pulse current 61a in response to the input of the pulse signal 51a.

[0068] During the period when the pulse signal 51a is not input, the drive circuit 41 outputs a drive current 61 having a current value equal to the sum of the current value of the bias current 131 and the current value of the mirror current 133, i.e., IBAIS. During the period when the pulse signal 51a is input, the drive circuit 41 outputs a drive current 61 having a current value equal to the sum of the current value IBAIS and the sum of the current values of a plurality of mirror currents 134, i.e., DRV.

[0069] 1.8 Bias current circuit As Figure 4 shown, the bias current circuit 121 includes a current source 141. The current source 141 includes a first terminal 141a and a second terminal 141b.

[0070] The first terminal 141a of the current source 141 is electrically connected to the cathode connection terminal 102. The second terminal 141b of the current source 141 is connected to the ground 104. Thus, a conduction path from the cathode connection terminal 102 to the ground 104 is formed. The current source 141 is inserted into the formed conduction path.

[0071] The current source 141 causes the bias current 131 to flow from the first terminal 141a of the current source 141 to the second terminal 141b of the current source 141. Thus, the bias current circuit 121 causes the bias current 131 to flow from the cathode connection terminal 102 to the ground 104.

[0072] 1.9 Reference current circuit As Figure 4 shown, the reference current circuit 122 includes a constant current source 151 and a resistor 152. The constant current source 151 includes a first terminal 151a and a second terminal 151b. The resistor 152 includes a first terminal 152a and a second terminal 152b.

[0073] The first terminal 151a of the constant current source 151 is electrically connected to the power supply 103. The second terminal 151b of the constant current source 151 is electrically connected to the first terminal 152a of the resistor 152. The second terminal 152b of the resistor 152 is electrically connected to the ground 104. Thus, a conduction path from the power supply 103 to the ground 104 is formed. The inserted constant current source 151 and resistor 152 are electrically connected in series.

[0074] The constant current source 151 causes the reference current 132 to flow from the first terminal 151a of the constant current source 151 to the second terminal 151b of the constant current source 151. Thereby, the reference current circuit 122 causes the reference current 132 to flow from the power supply 103 to the ground 104. The second terminal 151b of the constant current source 151 and the first terminal 152a of the resistor 152 are applied with a potential corresponding to the current value of the flowing reference current 132. The applied potential is the product of the current value of the reference current 132 and the resistance value of the resistor 152.

[0075] 1.10 Mirror current circuit As Figure 4 shown, the mirror current circuit 123 includes an n-channel FET 161 and a resistor 162. The n-channel FET 161 includes a gate 161a, a drain 161b, and a source 161c. The resistor 162 includes a first terminal 162a and a second terminal 162b.

[0076] The drain 161b of the n-channel FET 161 is electrically connected to the cathode connection terminal 102. Thus, the mirror current 133 that constitutes the drive current 61 flows into the drain 161b. The source 161c of the n-channel FET 161 is electrically connected to the first terminal 162a of the resistor 162. The second terminal 162b of the resistor 162 is electrically connected to the ground 104. Thereby, a conduction path from the cathode connection terminal 102 to the ground 104 is formed. The drain 161b, the source 161c, and the resistor 162 are inserted into the formed conduction path. The inserted drain 161b, source 161c, and resistor 162 are electrically connected in series.

[0077] The n-channel FET 161 causes the mirror current 133 corresponding to the potential applied to the gate 161a of the n-channel FET 161 to flow from the drain 161b of the n-channel FET 161 to the source 161c of the n-channel FET 161. Thereby, the mirror current circuit 123 causes the mirror current 133 corresponding to the potential applied to the gate 161a to flow from the cathode connection terminal 102 to the ground wire 104. The higher this potential, the larger the current value of the flowing mirror current 133. The source 161c of the n-channel FET 161 and the first terminal 162a of the resistor 162 are applied with a potential corresponding to the current value of the flowing mirror current 133. The applied potential is the product of the current value of the mirror current 133 and the resistance value of the resistor 162.

[0078] The gate 161a of the n-channel FET 161 is electrically connected to the feedback circuit 125. Thereby, a potential at which the current value of the mirror current 133 applied to the gate 161a becomes the same as the current value of the reference current 132 is applied. Thereby, the mirror current circuit 123 is controlled so that the mirror current 133 having the same current value as the current value of the reference current 132 flows.

[0079] The source 161c of the n-channel FET 161 and the first terminal 162a of the resistor 162 are electrically connected to the feedback circuit 125. Thus, the mirror current circuit 123 can transfer the potential corresponding to the current value of the mirror current 133 to the feedback circuit 125.

[0080] The n-channel FET 161 is a MOSFET.

[0081] 1.11 Driver unit As Figure 4 As shown, each driver unit 124 includes an n-channel FET 171, a resistor 172, a capacitor 173, and a source driver circuit 174. The n-channel FET 171 includes a gate 171a, a drain 171b, and a source 171c. The resistor 172 includes a first terminal 172a and a second terminal 172b. The capacitor 173 includes a first terminal 173a and a second terminal 173b. The source driver circuit 174 includes a first terminal 174a and a second terminal 174b.

[0082] The drain 172b of the n-channel FET 171 is electrically connected to the cathode connection terminal 102. Thus, the mirror current 134 that constitutes the drive current 61 flows into the drain 171b. The source 171c of the n-channel FET 171 is electrically connected to the first terminal 172a of the resistor 172. The second terminal 172b of the resistor 172 is electrically connected to the first terminal 174a of the source driver circuit 174. Thus, a conduction path from the cathode connection terminal 102 to the first terminal 174a is formed. The drain 171b, the source 171c, and the resistor 172 are inserted in the formed conduction path. The inserted drain 171b, source 171c, and resistor 172 are electrically connected in series.

[0083] The n-channel FET 171 causes the mirror current 134 corresponding to the potential applied to the gate 171a of the n-channel FET 171 to flow from the drain 171b of the n-channel FET 171 to the source 171c of the n-channel FET 171. Thus, each driver unit 124 causes the mirror current 134 corresponding to the potential applied to the gate 171a to flow from the cathode connection terminal 102 to the first terminal 174a of the source driver circuit 174. The higher this potential, the larger the current value of the flowing mirror current 134.

[0084] The gate 171a of the n-channel FET 171 is electrically connected to the feedback circuit 125. Thus, the potential at which the current value of the mirror current 134 applied to the gate 171a becomes 4 times the current value of the reference current 132 is applied. Thus, the mirror current circuit 123 is controlled to flow a mirror current 133 having a current value 4 times the current value of the reference current 132.

[0085] The n-channel FET 171 is a MOSFET.

[0086] The resistance value of resistor 172 is 1 / 4 times that of resistor 162. Thus, the current value of mirror current 134 can be made 4 times that of mirror current 133.

[0087] The first terminal 173a of capacitor 173 is electrically connected to the gate 171a of n-channel FET 171. The second terminal 173b of capacitor 173 is electrically connected to ground 104. Thus, capacitor 173 is inserted between gate 171a and ground 104 to AC-ground gate 171a. The capacitance value of capacitor 173 is set to have a capacitive impedance small enough at the frequency that contains a large amount of the frequency components in drive signal 51.

[0088] Drive signal 51 is input to the second terminal 174b of source driver circuit 174. Source driver circuit 174 outputs a signal 181 corresponding to drive signal 51 input to the second terminal 174b from the first terminal 174a of source driver circuit 174. The first terminal 174a is electrically connected to the source 171c of n-channel FET 171 via resistor 172. Therefore, source driver circuit 174 drives source 171c with signal 181 to cause mirror current 134 to flow.

[0089] When the potential of drive signal 51 becomes the H potential, source driver circuit 174 sets the potential of signal 181 to the L potential to cause mirror current 134 to flow. When the potential of drive signal 51 becomes the L potential, source driver circuit 174 sets the potential of signal 181 to the H potential to prevent mirror current 134 from flowing.

[0090] When the gate 171a of n-channel FET 171 is AC-grounded and the source 171c of n-channel FET 171 is driven by signal 181, the modulation based on signal 181 is hardly affected by the mirror capacitance of n-channel FET 171. Thus, the modulation based on signal 181 can be performed at high speed, and the light-emitting element 22 can emit pulsed light with a short pulse width.

[0091] 1.12 Source driver circuit As Figure 4 shown, source driver circuit 174 includes a first inverter 201, a second inverter 202, a capacitor 203, and a constant voltage power supply 204. The first inverter 201 includes an input terminal 201a, an output terminal 201b, and a power supply terminal 201c. The second inverter 202 includes an input terminal 202a, an output terminal 202b, and a power supply terminal 202c. The capacitor 203 includes a first terminal 203a and a second terminal 203b.

[0092] The input terminal 201a of the first inverter 201 and the input terminal 202a of the second inverter 202 are electrically connected to the time measurement circuit 46. The output terminal 201b of the first inverter 201 is electrically connected to the second terminal 172b of the resistor 172. The output terminal 202b of the second inverter 202 is electrically connected to the first terminal 203a of the capacitor 203. The second terminal 203b of the capacitor 203 is electrically connected to the second terminal 172b of the resistor 172. Thus, the output terminal 201b of the first inverter 201 is directly connected to the second terminal 172b. The output terminal 202b of the second inverter 202 is connected to the second terminal 172b via the capacitor 203. The power supply terminals 201c of the first inverter 201 and 202c of the second inverter 202 are electrically connected to the constant voltage power supply 204.

[0093] The drive signal 51 is input to the input terminal 201a of the first inverter 201 and the input terminal 202a of the second inverter 202. The first inverter 201 and the second inverter 202 respectively output inverted pulse signals obtained by inverting the input drive signal 51 to the output terminal 201b of the first inverter 201 and the output terminal 202b of the second inverter 202. Thus, a potential corresponding to the inverted pulse signal is applied to the second terminal 172b of the resistor 172. Thus, the signal for driving the source 171c of the n-channel FET 171 becomes an inverted pulse signal obtained by inverting the drive signal 51.

[0094] The output terminal 202b of the second inverter 202 is connected to the second terminal 172b of the resistor 172 via the capacitor 203, thereby being AC-coupled to the second terminal 172b. Thus, the rise of the potential in the inverted pulse signal can be accelerated.

[0095] Figure 6 It is a diagram showing waveforms of drive signals input to input terminals of a first inverter and a second inverter of a drive circuit included in the distance measurement sensor according to the first embodiment, and inverted pulse signals output from output terminals of the first inverter and the second inverter.

[0096] As Figure 6 shown, the potential of the inverted pulse signal 211 output from the output terminal 201b of the first inverter 201 and the output terminal 202b of the second inverter 202 drops from the H potential to the L potential at the timing 231 when the potential of the drive signal 51 input to the input terminal 201a of the first inverter 201 and the input terminal 202a of the second inverter 202 rises and exceeds the threshold potential 221, and rises from the L potential to the H potential at the timing 232 when the potential of the drive signal 51 drops and exceeds the threshold potential 221.

[0097] The potential of the drive signal 51 takes time to rise from the L potential to the H potential, and also takes time to fall from the H potential to the L potential. Therefore, when the threshold potential 221 changes, the timings 231 and 232 change, and the waveform of the inversion pulse signal 211 also changes.

[0098] The threshold potential 221 changes when the potential applied to the power supply terminal 201c of the first inverter 201 and the power supply terminal 202c of the second inverter 202 changes. Therefore, the waveform of the inversion pulse signal 211 changes when the potential applied to the power supply terminal 201c and the power supply terminal 202c changes. However, when the power supply terminals 201c and 202c are electrically connected to the constant voltage power supply 204 and a stable potential is applied to the power supply terminals 201c and 202c, the waveform of the inversion pulse signal 211 can be made a stable waveform.

[0099] 1.13 Feedback Circuit As Figure 4 shown, the feedback circuit 125 includes an operational amplifier 241. The operational amplifier 241 includes a non-inverting input terminal 241a, an inverting input terminal 241b, and an output terminal 241c.

[0100] The non-inverting input terminal 241a is electrically connected to the second terminal 151b of the constant current source 151 and the first terminal 152a of the resistor 152. The inverting input terminal 241b is electrically connected to the source 161c of the n-channel FET 161 and the first terminal 162a of the resistor 162. The output terminal 241c is electrically connected to the gate 161a of the n-channel FET 161 and the gate 171a of the n-channel FET 171.

[0101] Accordingly, a potential consistent with the product of the current value of the reference current 132 and the resistance value of the resistor 152 is applied to the non-inverting input terminal 241a. A potential consistent with the product of the current value of the mirror current 133 and the resistance value of the resistor 162 is applied to the inverting input terminal 241b.

[0102] The operational amplifier 241 applies a potential obtained by multiplying the potential difference obtained by subtracting the potential applied to the inverting input terminal 241b of the operational amplifier 241 from the potential applied to the non-inverting input terminal 241a of the operational amplifier 241 by the gain to the output terminal 241c of the operational amplifier 241.

[0103] The resistance value of resistor 162 is the same as that of resistor 152. Therefore, the potential difference is proportional to the difference in current values obtained by subtracting the current value of mirror current 133 from the current value of reference current 132. Accordingly, the potential applied to the output terminal 241c of operational amplifier 241, the gate 161a of n-channel FET 161, and the gate 171a of n-channel FET 171 is proportional to the difference in current values. Thus, when the difference in current values is greater than 0, feedback circuit 125 raises the potential applied to the gate 161a of n-channel FET 161 and the gate 171a of n-channel FET 171, and increases the current values of mirror current 133 and mirror current 134. Further, when the difference in current values is less than 0, feedback circuit 125 lowers the potential applied to the gate 161a of n-channel FET 161 and the gate 171a of n-channel FET 171, and decreases the current values of mirror current 133 and mirror current 134. Thereby, feedback circuit 125 mirrors reference current 132 as mirror current 133 such that the current value of mirror current 133 becomes the same as the current value of reference current 132, and mirrors reference current 132 as mirror current 134 such that the current value of mirror current 134 becomes four times the current value of reference current 132.

[0104] 1.14 Buffer Circuit As Figure 4 shown, buffer circuit 126 includes resistor 251 and capacitor 252. Resistor 251 includes a first terminal 251a and a second terminal 251b. Capacitor 252 includes a first terminal 252a and a second terminal 252b.

[0105] The first terminal 251a of resistor 251 is electrically connected to cathode connection terminal 102. The second terminal 251b of resistor 251 is electrically connected to the first terminal 252a of capacitor 252. The second terminal 252b of capacitor 252 is electrically connected to ground 104. Thereby, a conduction path 261 from cathode connection terminal 102 to ground 104 is formed. Resistor 251 and capacitor 252 are inserted in the formed conduction path 261. The inserted resistor 251 and capacitor 252 are electrically connected in series and constitute buffer circuit 126.

[0106] Buffer circuit 126 functions as a ringing correction circuit that suppresses ringing in drive current 61.

[0107] 1.15 Suppression of Ringing Figure 7 is a circuit diagram showing an equivalent circuit of a light-emitting element, an anode-side gold wire, a cathode-side gold wire, and a buffer circuit included in the distance measurement sensor of the first embodiment. Figure 8It is a graph showing an example of the waveform of the drive current output by the drive circuit included in the distance measurement sensor of the first embodiment and the waveform of the drive current output by the drive circuit when the buffer circuit is omitted from the drive circuit.

[0108] As Figure 7 shown, the anode-side gold wire 271 that electrically connects the anode 22a of the light-emitting element 22 to the anode connection terminal 101 has a parasitic resistance 281 and a parasitic inductor 282. Figure 7 An example is given where the resistance value of the parasitic resistance 281 is 0.46 Ω and the inductance value of the parasitic inductor 282 is 1.07 nH.

[0109] The cathode-side gold wire 272 that electrically connects the cathode 22b of the light-emitting element 22 to the cathode connection terminal 102 has a parasitic resistance 291 and a parasitic inductor 292. Figure 7 An example is given where the resistance value of the parasitic resistance 291 is 0.21 Ω and the inductance value of the parasitic inductor 292 is 0.46 nH.

[0110] The light-emitting element 22 has a parasitic capacitor 300. Figure 7 An example is given where the capacitance value of the parasitic capacitor 300 is 15 pF.

[0111] In the case where the buffer circuit 126 is not provided despite the presence of the parasitic resistance 281, the parasitic inductor 282, the parasitic resistance 291, the parasitic inductor 292, and the parasitic capacitor 300, as Figure 8 shown by the waveform 312, large ringing occurs in the drive current 61. However, even in the presence of the parasitic resistance 281, the parasitic inductor 282, the parasitic resistance 291, the parasitic inductor 292, and the parasitic capacitor 300, when the buffer circuit 126 is provided, as Figure 8 shown by the waveform 311, large ringing does not occur in the drive current 61.

[0112] The resistance value of the resistor 251 and the capacitance value of the capacitor 252 are adjusted according to the resistance value of the parasitic resistance 281, the inductance value of the parasitic inductor 282, the resistance value of the parasitic resistance 291, the inductance value of the parasitic inductor 292, and the capacitance value of the parasitic capacitor 300. In Figure 7 it, an example is given where the resistance value of the resistor 251 is 10 Ω and the capacitance value of the capacitor 252 is 10 pF.

[0113] 2 Second Embodiment Hereinafter, the differences between the second embodiment and the first embodiment will be described. Regarding the points not described, the same configurations as those adopted in the first embodiment are also adopted in the second embodiment.

[0114] Figure 9This is a circuit diagram of the drive circuit included in the distance measurement sensor of the second embodiment.

[0115] In the second embodiment, as Figure 9 shown, each driver unit 124 includes a conduction path 261 and a buffer circuit 126.

[0116] The conduction path 261 extends from the cathode connection terminal 102 to the ground 104. The buffer circuit 126 is inserted into the conduction path 261.

[0117] By including the buffer circuit 126 in each driver unit 124, the multiple driver units 124 each include multiple buffer circuits 126. The multiple buffer circuits 126 are electrically connected in parallel with each other.

[0118] Thus, when the number of the multiple driver units 124 is N, the resistance value of the resistor 251 in the second embodiment can be made N times the resistance value of the resistor 251 in the first embodiment. In addition, the capacitance value of the capacitor 252 in the second embodiment can be made 1 / N times the capacitance value of the capacitor 252 in the first embodiment. Thus, it becomes easier to install the buffer circuit 126 in the light-receiving IC 26 in which it is difficult to install a resistor with a small resistance value and a capacitor with a large capacitance value.

[0119] 3 Third Embodiment Hereinafter, the differences between the third embodiment and the second embodiment will be described. Regarding the points not described, the same configurations as those adopted in the second embodiment are also adopted in the third embodiment.

[0120] Figure 10 This is a circuit diagram of the drive circuit included in the distance measurement sensor of the third embodiment.

[0121] In the third embodiment, as Figure 10 shown, each driver unit 124 includes multiple conduction paths 261, multiple buffer circuits 126, and multiple switches 253.

[0122] The multiple buffer circuits 126 are respectively inserted into the multiple conduction paths 261. The multiple switches 253 are respectively inserted into the multiple conduction paths 261.

[0123] The multiple switches 253 respectively switch between the state where the multiple conduction paths 261 are closed and the state where the multiple conduction paths 261 are open.

[0124] The buffer circuit 126 inserted into the closed conduction path 261 helps to suppress ringing in the drive current 61.

[0125] In the third embodiment, by selecting the number of closed conduction paths 261, it is possible to suppress ringing corresponding to parasitic resistance, parasitic capacitance, and parasitic inductance.

[0126] The present invention is not limited to the above embodiments, and can be replaced with configurations that are substantially the same as those shown in the above embodiments, configurations that achieve the same effects, or configurations that can achieve the same purpose.

Claims

1. A driving circuit, characterized in that: include: An n-channel field effect transistor including a gate, a drain and a source, wherein a current constituting a driving current for driving the light emitting element flows into the drain; A capacitor for connecting the gate to ground via alternating current; as well as The source driving circuit drives the source with a signal corresponding to the input pulse signal.

2. The driving circuit according to claim 1, characterized in that: The source driving circuit comprises: an inverter including an input terminal, an output terminal and a power supply terminal, the input terminal being input with the pulse signal, the output terminal outputting an inverted pulse signal obtained by inverting the pulse signal; and a constant voltage power supply, which is electrically connected to the power supply terminal, The signal is the inversion pulse signal.

3. The driving circuit according to claim 1, characterized in that: include: Grounding; a conduction path from the drain to the ground; as well as A buffer circuit is inserted into the conduction path.

4. The driving circuit according to claim 3, characterized in that: Comprising multiple drive units, Each of the plurality of driver units includes the n-channel field effect transistor, the capacitor, the source driving circuit, the conduction path, and the buffer circuit.

5. The driving circuit according to claim 1, characterized in that: include: A ground, a plurality of conduction paths from the drain to the ground, a plurality of buffer circuits respectively inserted into the plurality of conduction paths, and a plurality of switches respectively inserted into the plurality of conduction paths.

6. The driving circuit according to claim 1, characterized in that: The gate is a first gate, The drain is a first drain, The source is a first source, The driving circuit comprises: A p-channel field effect transistor, comprising a second gate, a second drain for allowing the driving current to flow out, and a second source; a power source electrically connected to the second source; grounding; and A capacitor is inserted between the second drain and the ground.

7. The driving circuit according to claim 1, characterized in that: A circuit is included which allows a reference current to flow and mirrors the reference current to the current.

8. The driving circuit according to claim 1, characterized in that: The light emitting element is a vertical cavity surface light emitting diode.

9. A distance measuring sensor, characterized in that: include: The driving circuit according to claim 1; the light emitting element; as well as Light receiving element.

Images