Mask pattern, semiconductor device and preparation method and equipment thereof
By identifying different pattern areas in semiconductor manufacturing and combining ILT and OPC methods to generate mask pattern, the problem of excessive etching or bridging caused by increasing the size of the lithography target during lithography is solved, and a larger lithography process window and higher design mask stability are achieved.
Patent Information
- Application Number
- CN202510441080.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-04-09
- Publication Date
- 2025-06-13
AI Technical Summary
In semiconductor manufacturing, the prior art increases the size of the lithography target during lithography may lead to problems such as excessive subsequent etching or bridge short circuits with the adjacent metal.
By identifying different graphic areas in the original design layout, using the inverse calculation lithography method (ILT) to solve the maximum lithography size window for connecting through holes in dense graphic areas, generate a suitable mask pattern, and optimize other areas with the optical proximity correction algorithm (OPC) to integrate and generate a complete mask pattern.
Without relying on increasing the size of the lithography target, the lithography process window is improved to effectively avoid defects such as over-etching or metal bridge, improve the stability and reliability of the design mask, and take into account both production efficiency and cost.
Smart Images
Figure CN120143544A_ABST
Abstract
Description
Technical Field
[0001] The present invention belongs to the field of semiconductor integrated circuit design and manufacturing, and particularly relates to a photomask pattern, a semiconductor device, a preparation method thereof, and a device. Background Art
[0002] In the process of semiconductor manufacturing, lithography is one of the key steps, and its accuracy directly affects the performance and yield of chips. Optical Proximity Correction (OPC) technology calculates the photomask pattern through a model to improve the process window of light, enabling accurate pattern transfer in a wider range of process parameters during the lithography process.
[0003] For low-density (ISO) metal via layers, conventionally, methods such as increasing the lithography target size (Target CD) and adding Sub-Resolution Assist Features (SRAF) are used in the OPC stage to improve the process window. However, when encountering a complex structure with a dense pattern of the minimum line width in the underlying metal layer and connecting vias on it, if the method of increasing the lithography target size of the connecting vias is still used, subsequent etching problems will be caused, such as etching through or forming a bridge with the adjacent metal, seriously affecting the chip quality and yield.
[0004] Inverse Lithography Technology (ILT), as a method currently known to be able to solve the optimal photomask pattern with the largest lithography process window, has unique advantages. However, due to its high computational complexity, if it is fully applied to all lithography structures, it will significantly increase the computational cost and time, lacking economy in actual production.
[0005] It should be noted that the above introduction of the technical background is only for the convenience of clearly and completely explaining the technical solutions of the present application and facilitating the understanding of those skilled in the art. It cannot be considered that the above technical solutions are well-known to those skilled in the art just because these solutions are described in the background art part of the present application. Summary of the Invention
[0006] In view of the above-mentioned disadvantages of the prior art, the purpose of the present invention is to provide a photomask pattern, a semiconductor device, a preparation method thereof, and a device, which are used to solve the problem that increasing the lithography target size in the prior art may cause excessive subsequent etching or short-circuit bridging with the adjacent metal.
[0007] To achieve the above and other related objectives, the present invention provides a method for preparing a mask pattern. The preparation method includes: identifying a first graphic area and a second graphic area in the original design layout, wherein the lower metal layer of the first graphic area is a dense graphic area with a line width smaller than the first line width, and the lower metal layer of the second graphic area is a graphic area with a line width greater than or equal to the first line width; calculating the maximum lithography size window of the connection vias in the first graphic area by inverse calculation using a lithography method, and generating a first mask pattern based on the maximum lithography size window; solving a second mask pattern adapted to the second graphic area through an optical proximity correction algorithm; integrating the first mask pattern and the second mask pattern to generate a complete mask pattern.
[0008] Optionally, the first line width is 1 to 1.2 times the minimum line width of the current manufacturing process.
[0009] Optionally, the first graphic area includes: a lower metal layer, the lower metal layer includes a plurality of metal lines arranged at intervals, the line width of the metal lines is smaller than the first line width, and the plurality of metal lines are arranged at intervals with a spacing smaller than the first line width; an interlayer dielectric layer covering the lower metal layer, and a plurality of connection vias are provided in the interlayer dielectric layer, the connection vias expose the metal lines, and metal plugs are provided in the connection vias to connect the metal lines.
[0010] Optionally, solving the second mask pattern adapted to the second connection via area through an optical proximity correction algorithm includes: optimizing the second connection via area by using a method of increasing the lithography target size or / and inserting auxiliary exposure patterns.
[0011] Optionally, the division rule of the first graphic area and the second graphic area is to select the area without connection vias as the dividing edge of the first graphic area and the second graphic area.
[0012] Optionally, integrating the first mask pattern and the second mask pattern includes aligning the edge patterns of the first mask pattern and the second mask pattern and then splicing them.
[0013] Optionally, the first graphic area accounts for 5% to 50% of the area of the original design layout.
[0014] The present invention also provides a mask pattern, which is prepared based on the method for preparing a mask pattern according to any one of the above solutions.
[0015] The present invention also provides a method for preparing a semiconductor device, and the method for preparing a semiconductor device includes the method for preparing a mask pattern according to any one of the above solutions.
[0016] The present invention also provides a semiconductor device, which is prepared based on the method for preparing a semiconductor device as described above.
[0017] The present invention also provides a semiconductor manufacturing apparatus for implementing the method for preparing a mask pattern according to any one of the above solutions. The manufacturing apparatus includes: a pattern recognition module configured to recognize a first pattern region and a second pattern region in an original design layout, wherein the lower metal layer of the first pattern region is a dense pattern region with a line width smaller than a first line width, and the lower metal layer of the second pattern region is a pattern region with a line width greater than or equal to the first line width; an inverse calculation module configured to solve the maximum lithography size window of the connection vias in the first pattern region through inverse calculation of lithography methods, and generate a first mask pattern based on the maximum lithography size window; an optical proximity correction module configured to solve a second mask pattern adapted to the second pattern region through an optical proximity correction algorithm; and a pattern integration module configured to integrate the first mask pattern and the second mask pattern to generate a complete mask pattern.
[0018] As described above, the mask pattern, semiconductor device, method for preparing the same, and apparatus of the present invention have the following beneficial effects:
[0019] The present invention performs ILT solution on the connection via regions on the lower metal layer with the minimum line width dense pattern to obtain a mask pattern with the optimal size. Without relying on increasing the lithography target size, the lithography process window is improved, and defects such as over-etching or metal bridging formed with the metal lines on both sides can be effectively avoided. However, ILT calculation is relatively complex. The present invention only uses the ILT method to solve for specific connection via regions, while maintaining the use of the OPC calculation method for other regions. Utilizing its relatively mature and computationally efficient characteristics, it can ensure the stability and reliability of the designed mask while not excessively increasing the computational amount. The present invention provides a method for hybrid computational lithography, which can effectively solve the lithography process window problem of specific complex structures while taking into account production efficiency and cost. BRIEF DESCRIPTION OF THE DRAWINGS
[0020] The included drawings are used to provide a further understanding of the embodiments of the present application, and they form a part of the specification, which is used to illustrate the embodiments of the present application and, together with the textual description, explain the principles of the present application. Obviously, the drawings in the following description are only some embodiments of the present application.
[0021] Figure 1 It shows a schematic flowchart of the steps of the method for preparing a mask pattern according to an embodiment of the present invention.
[0022] Figure 2 It shows a schematic diagram of the classification of pattern regions of the method for preparing a mask pattern according to an embodiment of the present invention.
[0023] Figure 3Schematic diagram comparing the connection via windows of the ILT algorithm and the OPC algorithm in the method for preparing a mask pattern according to an embodiment of the present invention.
[0024] Figure 4 Schematic diagram of the light intensity of the pattern, where the solid line represents the curve of the method for preparing the mask pattern of the present invention, and the dashed line represents the curve of the method for preparing the mask pattern of the prior art.
[0025] Description of component labels
[0026] 1 Original design layout
[0027] 11 First pattern region
[0028] 12 Second pattern region
[0029] 21 Metal wire
[0030] 22 Connection via
[0031] 23 ILT connection via
[0032] 24 OPC connection via
[0033] Steps S11 to S15 Detailed implementation manners
[0034] The following describes the embodiments of the present invention through specific specific examples. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific implementation manners. Various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.
[0035] It should be emphasized that the term "including / comprising" when used herein refers to the presence of features, whole parts, steps or components, but does not exclude the presence or addition of one or more other features, whole parts, steps or components.
[0036] Features described and / or illustrated for one embodiment can be used in the same or similar manner in one or more other embodiments, combined with the features in other embodiments, or replace the features in other embodiments.
[0037] When detailing the embodiments of the present invention, for the convenience of description, the cross-sectional views showing the device structure will be enlarged locally out of the general scale, and the schematic diagrams are only examples and should not limit the scope of protection of the present invention herein. In addition, in actual production, three-dimensional spatial dimensions including length, width and depth should be included.
[0038] For ease of description, spatial relationship terms such as "below", "beneath", "lower", "under", "above", "on" may be used herein to describe the relationship of one element or feature shown in the drawings to other elements or features. It will be understood that these spatial relationship terms are intended to encompass other orientations of the device in use or operation, in addition to the orientation depicted in the drawings. Further, when a layer is referred to as being "between" two layers, it can be the only layer between the two layers, or there can be one or more intervening layers.
[0039] In the context of the present application, the structure in which the first feature is "above" the second feature as described may include embodiments where the first and second features are formed in direct contact, and may also include embodiments where additional features are formed between the first and second features, such that the first and second features may not be in direct contact.
[0040] It should be noted that the diagrams provided in this embodiment only schematically illustrate the basic concept of the present invention. Therefore, only the components related to the present invention are shown in the diagrams, rather than being drawn according to the number, shape, and size of the components in actual implementation. The type, quantity, and proportion of each component in actual implementation can be arbitrarily changed, and the component layout type may also be more complex.
[0041] As Figures 1 to 4 shown, this embodiment provides a method for preparing a mask pattern, and the preparation method includes:
[0042] As Figure 1 and Figure 2 shown, first step S11 is performed to identify a first graphic area 11 and a second graphic area 12 in the original design plate Figure 1 . Among them, the lower metal layer of the first graphic area 11 is a dense graphic area smaller than the first line width, and the lower metal layer of the second graphic area 12 is a graphic area greater than or equal to the first line width.
[0043] In some embodiments, the first line width is 1 to 1.2 times the minimum line width of the current manufacturing process. For example, if the minimum line width is 7 nm, the first line width is 7 nm (1 time) or 8.4 nm (1.2 times), etc. If the minimum line width is 10 nm, the first line width is 10 nm to 12 nm. In this embodiment, the first line width is the minimum line width of the current manufacturing process.
[0044] In some embodiments, the first graphic region 11 includes: a lower metal layer including a plurality of metal lines arranged at intervals, the line width of the metal lines being less than the first line width, the plurality of metal lines being arranged at intervals with a spacing less than the first line width, and the material of the lower metal layer may be, for example, copper (Cu), aluminum (Al), gold (Au), etc.; an interlayer dielectric layer covering the lower metal layer, wherein a plurality of connection vias are provided in the interlayer dielectric layer, the connection vias exposing the metal lines, and metal plugs are provided in the connection vias to connect the metal lines, and the material of the interlayer dielectric layer may be, for example, silicon dioxide, silicon nitride, silicon oxynitride, etc.
[0045] In one embodiment, the original design version is identified Figure 1 The first graphic region 11 and the second graphic region 12 in
[0046] a) Receive the original design version Figure 1 , identify the line width and arrangement density of the lower metal layer, determine whether the metal lines in the lower metal layer are less than the first line width. If less than the first line width, proceed to step b). If greater than or equal to the first line width, determine that this region is the second graphic region 12;
[0047] b) Identify the interlayer dielectric layer, and determine whether there are connection vias above the region where the metal lines are less than the first line width. If so, determine that this region is the first graphic region 11. If not, still determine that this region is the second graphic region 12.
[0048] In some embodiments, the division rule for the first graphic region 11 and the second graphic region 12 is to select the region without connection vias as the dividing edge of the first graphic region 11 and the second graphic region 12, so as to effectively reduce the difficulty and precision of subsequent divided graphic integration.
[0049] In some embodiments, the first graphic region 11 preferably occupies Figure 1 5% - 50% of the area of the original design version. For example, the first graphic region 11 may occupy Figure 1 10%, 20%, 30%, 50%, etc. of the area of the original design version.
[0050] As Figure 1 and Figure 3 shown, then proceed to step S12, solve for the maximum lithography size window of the connection vias in the first graphic region 11 through inverse calculation lithography method, and generate the first mask pattern based on the maximum lithography size window. The inverse calculation lithography method (ILT) can take the target wafer design layout as input and inversely solve for the optimal mask pattern.
[0051] In some embodiments, solving the inverse calculation lithography method includes: for the identified first graphic region 11, calling the ILT algorithm module, inputting relevant parameters for lithography of the first graphic region 11, such as light source wavelength, numerical aperture, photoresist characteristics, lower layer metal layer graphic information, etc., performing inverse solution to obtain optimized reticle graphic data, ensuring a significant improvement in the process window of the first graphic region 11 during the lithography process, and at the same time avoiding the etching risk caused by size changes.
[0052] In a specific example, the inverse calculation lithography (ILT) may include the following steps:
[0053] Step 1), clarify the final design graphic to be implemented on the wafer. This design graphic is determined according to the requirements of chip design and includes the precise shapes and layouts of various tiny circuit elements, lines, etc. In this embodiment, the design graphic includes the first graphic region 11 and the second graphic region 12.
[0054] Step 2), based on the optical characteristics of the lithography system and the reaction characteristics of the photoresist, etc., establish a physical model that can describe the propagation, diffraction, interference of light during the lithography process, and the interaction with the photoresist. This physical model can integrate the light source characteristics of the lithography machine, such as wavelength, intensity distribution, etc., and the influence of optical elements in the lithography system, such as lenses, mirrors, etc. on light, and can also include parameters such as the sensitivity and contrast of the photoresist.
[0055] Step 3), generate an initial mask graphic based on the design graphic.
[0056] Step 4), use the established physical model to perform forward lithography simulation on the first graphic region 11 in the initial mask graphic, and calculate the lithography graphic formed on the wafer after passing through the lithography system under the first graphic region 11.
[0057] Step 5), according to the difference between the first graphic region 11 obtained from the forward simulation and the target graphic, calculate the error value and define an objective function to quantify this difference. The objective function is usually a certain measure of the error, such as mean square error, maximum error, etc., and find the optimal first graphic region 11 by minimizing the objective function.
[0058] Step 6), based on the calculated error and the objective function, use an optimization algorithm to adjust and optimize the first graphic region 11, such as adjusting and optimizing the connection vias. For example, by making slight changes to the shape and size of the first graphic region 11, and re-performing forward lithography simulation and error calculation, gradually find the mask graphic that minimizes the objective function.
[0059] Step 7), repeat Steps 4) to 6), continuously perform forward simulation, error calculation, and optimization of the mask pattern (the first pattern region 11) until the preset convergence condition is met. The convergence condition can be that the value of the objective function is less than a certain threshold, or the change in the objective function after consecutive iterations is less than a certain amount. Through multiple repetitions, the first pattern region 11 on the mask pattern gradually approaches the ideal shape that can generate the closest target pattern on the wafer.
[0060] As Figure 3 shown, for the first pattern region 11, which includes multiple metal lines 21 with the minimum line width, if the method of increasing the lithography target size of the connection vias 22 is still used, the formed OPC connection vias 24 are prone to over-etching or bridging with the adjacent metal, seriously affecting the chip quality and yield. However, the ILT connection vias 23 formed by the ILT method for the first pattern region 11 in the present invention can effectively avoid defects such as over-etching or metal bridging formed with the metal lines on both sides.
[0061] As Figure 1 shown, then perform Step S13, and solve the second mask pattern adapted to the second pattern region 12 through the optical proximity correction algorithm. The optical proximity correction algorithm (OPC) can compensate for the optical proximity effect during the lithography process by pre-distorting the mask pattern.
[0062] In some embodiments, solving the second mask pattern adapted to the second connection via region through the optical proximity correction algorithm includes: optimizing the second connection via region by using the method of increasing the lithography target size or / and inserting auxiliary exposure patterns. The size of the auxiliary pattern (SRAF) can be an auxiliary pattern below the resolution of the lithography machine, which is used to improve the imaging quality of the main pattern. The optical proximity correction algorithm (OPC) can efficiently complete the optimization of the mask pattern and quickly improve the process window by using existing mature models and empirical parameters. The present invention compensates for the optical distortion in the non-dense region (the second pattern region 12) through OPC, simplifies the calculation process, and improves the efficiency.
[0063] As Figure 1 shown, finally perform Steps S14 to S15, integrate the first mask pattern and the second mask pattern to generate a complete mask pattern.
[0064] In some embodiments, integrating the first mask pattern and the second mask pattern includes aligning the edge patterns of the first mask pattern and the second mask pattern and then splicing them to generate a complete mask pattern, which is transmitted to the mask manufacturing equipment to manufacture a high-precision mask for chip lithography manufacturing and is put into the subsequent semiconductor manufacturing process to effectively improve the lithography yield and product performance of chip manufacturing.
[0065] Figure 4It is shown as a schematic diagram of graphic light intensity. Among them, the solid line represents the curve of the method for preparing the mask pattern of the present invention, and the dotted line represents the curve of the method for preparing the mask pattern of the prior art. It can be seen from the figure that the implementation curve has a larger curvature, and the lateral dimension (CD) value is smaller at the tangent of the process window threshold, indicating that the process window of the method for preparing the mask pattern of the present invention is larger.
[0066] This embodiment also provides a mask pattern, which is prepared based on the method for preparing the mask pattern in the above embodiment.
[0067] This embodiment also provides a method for manufacturing a semiconductor device, and the method for manufacturing the semiconductor device includes the method for preparing the mask pattern in the above embodiment.
[0068] This embodiment also provides a semiconductor device, which is prepared based on the method for manufacturing the semiconductor device in the above embodiment.
[0069] This embodiment also provides a semiconductor manufacturing device for implementing the method for preparing the mask pattern in the above embodiment. The manufacturing device includes: a graphic recognition module configured to recognize a first graphic area 11 and a second graphic area 12 in the original design layout. Among them, the lower metal layer of the first graphic area 11 is a dense graphic area smaller than the first line width, and the lower metal layer of the second graphic area 12 is a graphic area greater than or equal to the first line width; an inverse calculation module configured to solve the maximum lithography size window of the connection vias in the first graphic area 11 through inverse calculation of the lithography method, and generate a first mask pattern based on the maximum lithography size window; an optical proximity correction module configured to solve a second mask pattern adapted to the second graphic area 12 through an optical proximity correction algorithm; and a graphic integration module configured to integrate the first mask pattern and the second mask pattern to generate a complete mask pattern.
[0070] As described above, the mask pattern, semiconductor device, its manufacturing method and device of the present invention have the following beneficial effects:
[0071] The present invention performs ILT solution on the connection via hole region of the minimum line width dense pattern on the lower metal layer to obtain a photomask pattern with the optimal size. Without relying on increasing the lithography target size, the lithography process window can be improved, and defects such as over-etching or metal bridging formed with the metal lines on both sides can be effectively avoided. However, the ILT calculation is relatively complex. The present invention only uses the ILT method to solve for specific connection via hole regions, while maintaining the use of the OPC calculation method for other regions. Utilizing its relatively mature and computationally efficient characteristics, it can ensure the stability and reliability of the designed photomask while not excessively increasing the computational amount. The present invention provides a method for hybrid computational lithography, which can effectively solve the lithography process window problem of specific complex structures while taking into account production efficiency and cost.
[0072] Therefore, the present invention effectively overcomes various disadvantages in the prior art and has high industrial utilization value.
[0073] The above embodiments are only illustrative of the principles and effects of the present invention and are not intended to limit the present invention. Any person familiar with this technology can modify or change the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or changes made by those with ordinary knowledge in the technical field without departing from the spirit and technical ideas disclosed by the present invention should still be covered by the claims of the present invention.
Claims
1. A method for preparing a mask pattern, characterized in that: The preparation method comprises: Identify a first graphic region and a second graphic region in the original design layout, wherein the lower metal layer of the first graphic region is a dense graphic region with a width smaller than the first line width, and the lower metal layer of the second graphic region is a graphic region with a width greater than or equal to the first line width; Solve the maximum photolithography size window of the connecting through hole in the first graphic area by using the inverse calculation photolithography method, and generate the first mask pattern according to the maximum photolithography size window; Solving a second mask pattern adapted to the second pattern area by an optical proximity correction algorithm; The first mask pattern and the second mask pattern are integrated to generate a complete mask pattern.
2. The method for preparing a mask pattern according to claim 1, characterized in that: The first line width is 1 to 1.2 times the minimum line width of the current process technology.
3. The method for preparing a mask pattern according to claim 1, characterized in that: The first graphic area includes: A lower metal layer, the lower metal layer comprising a plurality of metal lines arranged at intervals, the line width of the metal lines being smaller than the first line width, and the plurality of metal lines being arranged at intervals at intervals smaller than the first line width; The interlayer dielectric layer covers the lower metal layer, and a plurality of connecting through holes are arranged in the interlayer dielectric layer, wherein the connecting through holes expose the metal wires, and metal plugs are arranged in the connecting through holes to connect the metal wires.
4. The method for preparing a mask pattern according to claim 1, characterized in that: Solving the second mask pattern adapted to the second connecting through-hole region by an optical proximity correction algorithm includes: optimizing the second connecting through-hole region by increasing the photolithography target size or / and inserting an auxiliary exposure pattern.
5. The method for preparing a mask pattern according to claim 1, characterized in that: The division rule of the first graphic area and the second graphic area is to select the area without connecting through holes as the dividing edge of the first graphic area and the second graphic area.
6. The method for preparing a mask pattern according to claim 1, characterized in that: Integrating the first mask pattern and the second mask pattern includes aligning edge patterns of the first mask pattern and the second mask pattern and then splicing them.
7. The method for preparing a mask pattern according to claim 1, characterized in that: The first graphic region occupies 5% to 50% of the area of the original design layout.
8. A mask pattern, characterized in that: The mask pattern is prepared based on the method for preparing a mask pattern according to any one of claims 1 to 7.
9. A method for preparing a semiconductor device, characterized in that: The method for preparing the semiconductor device comprises the method for preparing the mask pattern according to any one of claims 1 to 7.
10. A semiconductor device, characterized in that: The semiconductor device is manufactured based on the method for manufacturing a semiconductor device according to claim 9.
11. A semiconductor manufacturing device, used to implement the method for preparing a mask pattern according to any one of claims 1 to 7, characterized in that: The semiconductor manufacturing equipment comprises: A graphic recognition module is configured to recognize a first graphic region and a second graphic region in an original design layout, wherein a lower metal layer of the first graphic region is a dense graphic region having a width smaller than a first line width, and a lower metal layer of the second graphic region is a graphic region having a width greater than or equal to the first line width; A reverse calculation module is configured to solve a maximum photolithography size window of the connecting through-holes in the first graphic area by a reverse calculation photolithography method, and generate a first mask graphic according to the maximum photolithography size window; An optical proximity correction module, configured to solve a second mask pattern adapted to the second pattern area through an optical proximity correction algorithm; The pattern integration module is configured to integrate the first mask pattern and the second mask pattern to generate a complete mask pattern.