Preparation method of semiconductor device and semiconductor device

Abstract

The invention discloses a preparation method of a semiconductor device and the semiconductor device. The preparation method comprises the following steps: providing a substrate; sequentially forming a channel layer and a barrier layer on one side of the substrate; forming a first doped III-V group semiconductor layer on one side, far away from the substrate, of the barrier layer; forming a second doped III-V group semiconductor layer on one side, far away from the substrate, of the first doped III-V group semiconductor layer; etching the first doped III-V group semiconductor layer on two sides of the second doped III-V group semiconductor layer to form a first through groove, a second through groove, a third through groove and a fourth through groove; forming a source electrode in the first through groove; and forming a drain electrode in the fourth through groove. According to the method, the technological process is simplified, the number of masks and the number of times of a photoetching process are reduced, and the preparation cost is effectively reduced.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and particularly to a method for manufacturing a semiconductor device and a semiconductor device. Background Art

[0002] For existing gallium nitride (GaN) high electron mobility transistors (HEMTs), a doped group III-V semiconductor layer is provided on a barrier layer, and the doped group III-V semiconductor layer can be a p-type gallium nitride layer (P-GaN). During the manufacturing process, the doped group III-V semiconductor layer between the source and the drain is disconnected by selectively etching the doped group III-V semiconductor layer, and then an ohmic contact window is formed by etching for subsequent formation of the source and the drain. The existing manufacturing process flow is complex, requires multiple mask plates, and has a high manufacturing cost. Summary of the Invention

[0003] The present invention provides a method for manufacturing a semiconductor device and a semiconductor device to solve the problems of complex existing manufacturing process flow and high manufacturing cost.

[0004] In a first aspect, the present invention provides a method for manufacturing a semiconductor device, the manufacturing method comprising:

[0005] Providing a substrate;

[0006] Successively forming a channel layer and a barrier layer on one side of the substrate;

[0007] Forming a first doped group III-V semiconductor layer on a side of the barrier layer away from the substrate; the vertical projection of the first doped group III-V semiconductor layer on the substrate coincides with the vertical projection of the barrier layer on the substrate;

[0008] Forming a second doped group III-V semiconductor layer on a side of the first doped group III-V semiconductor layer away from the substrate; the vertical projection of the second doped group III-V semiconductor layer on the substrate is within the vertical projection of the first doped group III-V semiconductor layer on the substrate;

[0009] Etching the first doped group III-V semiconductor layer on both sides of the second doped group III-V semiconductor layer to form a first through groove, a second through groove, a third through groove, and a fourth through groove; wherein, the first through groove and the second through groove are located on the same side of the second doped group III-V semiconductor layer, and the first through groove is located on a side of the second through groove away from the second doped group III-V semiconductor layer; the third through groove and the fourth through groove are located on the other side of the second doped group III-V semiconductor layer, and the fourth through groove is located on a side of the third through groove away from the second doped group III-V semiconductor layer;

[0010] Forming a source electrode in the first through groove;

[0011] Forming a drain electrode in the fourth through groove.

[0012] Optionally, before etching the first-doped group III-V semiconductor layers on both sides of the second-doped group III-V semiconductor layer to form the first through groove, the second through groove, the third through groove, and the fourth through groove, it further includes:

[0013] Forming a first protective layer on the side of the first-doped group III-V semiconductor layer away from the substrate and on the side of the second-doped group III-V semiconductor layer away from the substrate;

[0014] Etching the first protective layer on both sides of the second-doped group III-V semiconductor layer to form the fifth through groove, the sixth through groove, the seventh through groove, and the eighth through groove; wherein, the fifth through groove and the sixth through groove are located on the same side of the second-doped group III-V semiconductor layer, and the fifth through groove is located on the side away from the second-doped group III-V semiconductor layer of the sixth through groove; the seventh through groove and the eighth through groove are located on the other side of the second-doped group III-V semiconductor layer, and the eighth through groove is located on the side away from the second-doped group III-V semiconductor layer of the seventh through groove;

[0015] Etching the first-doped group III-V semiconductor layers on both sides of the second-doped group III-V semiconductor layer to form the first through groove, the second through groove, the third through groove, and the fourth through groove, including:

[0016] Etching the first-doped group III-V semiconductor layers on both sides of the second-doped group III-V semiconductor layer to form the first through groove communicating with the fifth through groove, the second through groove communicating with the sixth through groove, the third through groove communicating with the seventh through groove, and the fourth through groove communicating with the eighth through groove.

[0017] Optionally, forming the first protective layer on the side of the first-doped group III-V semiconductor layer away from the substrate and on the side of the second-doped group III-V semiconductor layer away from the substrate, including:

[0018] Forming a first sub-protective layer on the side of the first-doped group III-V semiconductor layer away from the substrate and on the side of the second-doped group III-V semiconductor layer away from the substrate;

[0019] Forming a second sub-protective layer on the side of the first sub-protective layer away from the substrate.

[0020] Optionally, forming a source electrode in the first through groove and forming a drain electrode in the fourth through groove, including:

[0021] Forming an electrode layer on the side of the first-doped group III-V semiconductor layer away from the substrate, on the side of the second-doped group III-V semiconductor layer away from the substrate, and in the first through groove, the second through groove, the third through groove, and the fourth through groove;

[0022] Remove the electrode layer outside the corresponding regions of the first through-groove and the fourth through-groove; the electrode layer in the corresponding region of the first through-groove serves as the source electrode, and the electrode layer in the corresponding region of the fourth through-groove serves as the drain electrode.

[0023] Optionally, after forming the drain electrode in the fourth through-groove, it further includes:

[0024] Form a second protective layer on the side of the first doped group III-V semiconductor layer away from the substrate, the side of the second doped group III-V semiconductor layer away from the substrate, the side of the source electrode away from the substrate, the side of the drain electrode away from the substrate, and inside the second through-groove and the third through-groove;

[0025] Etch the second protective layer on the side of the source electrode away from the substrate to form a first opening to expose the source electrode, and etch the second protective layer on the side of the drain electrode away from the substrate to form a second opening to expose the drain electrode.

[0026] Optionally, forming a second protective layer on the side of the first doped group III-V semiconductor layer away from the substrate, the side of the second doped group III-V semiconductor layer away from the substrate, the side of the source electrode away from the substrate, the side of the drain electrode away from the substrate, and inside the second through-groove and the third through-groove includes:

[0027] Form a third sub-protective layer on the side of the first doped group III-V semiconductor layer away from the substrate, the side of the second doped group III-V semiconductor layer away from the substrate, the side of the source electrode away from the substrate, the side of the drain electrode away from the substrate, and inside the second through-groove and the third through-groove;

[0028] Form a fourth sub-protective layer on the side of the third sub-protective layer away from the substrate.

[0029] Optionally, after forming the second doped group III-V semiconductor layer on the side of the first doped group III-V semiconductor layer away from the substrate, it further includes:

[0030] Form a Schottky contact region on the side of the second doped group III-V semiconductor layer away from the substrate.

[0031] In a second aspect, the present invention provides a semiconductor device, and the semiconductor device includes:

[0032] A substrate;

[0033] A channel layer and a barrier layer located on one side of the substrate;

[0034] A first doped group III-V semiconductor layer located on the side of the barrier layer away from the substrate; the vertical projection of the first doped group III-V semiconductor layer on the substrate coincides with the vertical projection of the barrier layer on the substrate;

[0035] A second doped group III-V semiconductor layer located on the side of the first doped group III-V semiconductor layer away from the substrate; the vertical projection of the second doped group III-V semiconductor layer on the substrate is within the vertical projection of the first doped group III-V semiconductor layer on the substrate; the first doped group III-V semiconductor layers on both sides of the second doped group III-V semiconductor layer include a first through groove, a second through groove, a third through groove, and a fourth through groove; wherein, the first through groove and the second through groove are located on the same side of the second doped group III-V semiconductor layer, and the first through groove is located on the side of the second through groove away from the second doped group III-V semiconductor layer; the third through groove and the fourth through groove are located on the other side of the second doped group III-V semiconductor layer, and the fourth through groove is located on the side of the third through groove away from the second doped group III-V semiconductor layer;

[0036] A source electrode located in the first through groove;

[0037] A drain electrode located in the fourth through groove.

[0038] Optionally, the semiconductor device further includes: a first protective layer;

[0039] The first protective layer is located on the side of the first doped group III-V semiconductor layer away from the substrate and on the side of the second doped group III-V semiconductor layer away from the substrate; the first protective layer includes a fifth through groove, a sixth through groove, a seventh through groove, and an eighth through groove; the vertical projection of the fifth through groove on the substrate coincides with the vertical projection of the first through groove on the substrate, the vertical projection of the sixth through groove on the substrate coincides with the vertical projection of the second through groove on the substrate, the vertical projection of the seventh through groove on the substrate coincides with the vertical projection of the third through groove on the substrate, and the vertical projection of the eighth through groove on the substrate coincides with the vertical projection of the fourth through groove on the substrate.

[0040] Optionally, the semiconductor device further includes: a second protective layer;

[0041] The second protective layer is located on the side of the first doped group III-V semiconductor layer away from the substrate, the side of the second doped group III-V semiconductor layer away from the substrate, the side of the source electrode away from the substrate, the side of the drain electrode away from the substrate, and within the second through groove and the third through groove; the second protective layer includes a first opening and a second opening, the first opening is located on the side of the source electrode away from the substrate, and the second opening is located on the side of the drain electrode away from the substrate.

[0042] Optionally, the semiconductor device further includes: a Schottky contact region;

[0043] The Schottky contact region is located on the side of the second doped group III-V semiconductor layer away from the substrate.

[0044] In the technical solution of the embodiment of the present invention, during the preparation process of a semiconductor device, selective enhancement treatment and ohmic contact opening treatment are simultaneously performed on the first-doped group III-V semiconductor layers on both sides of the second-doped group III-V semiconductor layer. By performing the SAE treatment, a second through groove and a third through groove are formed, which can achieve insulating isolation between the source electrode and the gate electrode, insulating isolation between the drain electrode and the gate electrode, and insulating isolation between the source electrode and the drain electrode. By performing the OHO treatment, a first through groove and a fourth through groove are formed for subsequent deposition of metal to form the source electrode and the drain electrode. The SAE treatment and the OHO treatment are performed simultaneously, that is, a single mask plate can be used to form the first through groove, the second through groove, the third through groove, and the fourth through groove. Through the above process optimization, the technical solution of the embodiment of the present invention simplifies the process flow, saves the number of mask plates and the number of photolithography processes, and effectively reduces the preparation cost.

[0045] It should be understood that the content described in this part is not intended to identify the key or important features of the embodiments of the present invention, nor is it used to limit the scope of the present invention. Other features of the present invention will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0046] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the drawings in the following description are only some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained based on these drawings.

[0047] Figure 1 is a flowchart of a method for preparing a semiconductor device provided by an embodiment of the present invention;

[0048] Figures 2 - 7 is a schematic structural diagram corresponding to each step in a method for preparing a semiconductor device provided by an embodiment of the present invention;

[0049] Figure 8 is a flowchart of another method for preparing a semiconductor device provided by an embodiment of the present invention;

[0050] Figures 9 - 11 is a schematic structural diagram corresponding to some steps in another method for preparing a semiconductor device provided by an embodiment of the present invention;

[0051] Figure 12 is a flowchart of yet another method for preparing a semiconductor device provided by an embodiment of the present invention;

[0052] Figure 13 is a schematic structural diagram corresponding to some steps in yet another method for preparing a semiconductor device provided by an embodiment of the present invention;

[0053] Figure 14It is a flowchart of another method for manufacturing a semiconductor device provided by an embodiment of the present invention;

[0054] Figures 15 - 16 It is a schematic structural diagram corresponding to some steps in another method for manufacturing a semiconductor device provided by an embodiment of the present invention;

[0055] Figure 17 It is a flowchart of another method for manufacturing a semiconductor device provided by an embodiment of the present invention;

[0056] Figures 18 - 20 It is a schematic structural diagram corresponding to some steps in another method for manufacturing a semiconductor device provided by an embodiment of the present invention;

[0057] Figure 21 It is a flowchart of another method for manufacturing a semiconductor device provided by an embodiment of the present invention;

[0058] Figure 22 It is a schematic structural diagram corresponding to some steps in another method for manufacturing a semiconductor device provided by an embodiment of the present invention;

[0059] Figure 23 It is a flowchart of another method for manufacturing a semiconductor device provided by an embodiment of the present invention;

[0060] Figures 24 - 30 It is a schematic structural diagram corresponding to some steps in another method for manufacturing a semiconductor device provided by an embodiment of the present invention. Detailed implementation manners

[0061] In order to enable those skilled in the art to better understand the solution of the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.

[0062] It should be noted that the terms "first", "second", etc. in the description, claims and the above-mentioned drawings of the present invention are used to distinguish similar objects, and do not necessarily describe a specific order or sequence. It should be understood that the data used in this way can be interchanged under appropriate circumstances, so that the embodiments of the present invention described here can be implemented in an order other than those illustrated or described here. In addition, the terms "comprising" and "having" and any variations thereof are intended to cover non-exclusive inclusion. For example, a process, method, system, product or device that includes a series of steps or units does not necessarily have to be limited to those steps or units clearly listed, but may include other steps or units not clearly listed or inherent to these processes, methods, products or devices.

[0063] Figure 1 is a flowchart of a method for manufacturing a semiconductor device provided by an embodiment of the present invention, Figures 2 - 7 is a schematic structural diagram corresponding to each step in a method for manufacturing a semiconductor device provided by an embodiment of the present invention, as Figure 1 shown, the manufacturing method includes:

[0064] S100: Provide a substrate.

[0065] Specifically, as Figure 2 shown, first provide a substrate 1, and the substrate 1 can be a Si substrate, a sapphire substrate or a GaN substrate.

[0066] S110: Sequentially form a channel layer and a barrier layer on one side of the substrate.

[0067] Specifically, as Figure 3 shown, first form a channel layer 2 on one side of the substrate 1, and form a barrier layer 3 on the side of the channel layer 2 away from the substrate 1. The channel layer 2 can use intrinsic GaN as the channel layer, and the barrier layer 3 can use an AlGaN material.

[0068] S120: Form a first-doped group III-V semiconductor layer on the side of the barrier layer away from the substrate; the vertical projection of the first-doped group III-V semiconductor layer on the substrate coincides with the vertical projection of the barrier layer on the substrate.

[0069] Specifically, as Figure 4 shown, form a first-doped group III-V semiconductor layer 4 on the side of the barrier layer 3 away from the substrate 1. Exemplarily, the first-doped group III-V semiconductor layer 4 can include a P-type gallium nitride layer.

[0070] S130: Form a second-doped group III-V semiconductor layer on the side of the first-doped group III-V semiconductor layer away from the substrate; the vertical projection of the second-doped group III-V semiconductor layer on the substrate is within the vertical projection of the first-doped group III-V semiconductor layer on the substrate.

[0071] Specifically, as Figure 5 shown, a second-doped group III-V semiconductor layer 5 is formed on the side of the first-doped group III-V semiconductor layer 4 away from the substrate 1. Exemplarily, the second-doped group III-V semiconductor layer 5 may also include a p-type gallium nitride layer. During the process of forming the second-doped group III-V semiconductor layer 5, the second-doped group III-V semiconductor layer 5 may be first formed on the entire surface of the side of the first-doped group III-V semiconductor layer 4 away from the substrate 1, and then the second-doped group III-V semiconductor layer 5 on both sides may be removed by processes such as photolithography and etching. The second-doped group III-V semiconductor layer 5 may serve as a gate and may be connected to a metal layer in subsequent processes.

[0072] S140: Etch the first-doped group III-V semiconductor layer on both sides of the second-doped group III-V semiconductor layer to form a first through groove, a second through groove, a third through groove, and a fourth through groove; wherein, the first through groove and the second through groove are located on the same side of the second-doped group III-V semiconductor layer, and the first through groove is located on the side of the second through groove away from the second-doped group III-V semiconductor layer; the third through groove and the fourth through groove are located on the other side of the second-doped group III-V semiconductor layer, and the fourth through groove is located on the side of the third through groove away from the second-doped group III-V semiconductor layer.

[0073] Specifically, as Figure 6 shown, a selective area enhancement (SAE) process and an ohmic hole opening (OHO) process are simultaneously performed on the first-doped group III-V semiconductor layer 4 on both sides of the second-doped group III-V semiconductor layer 5. Through the SAE process, that is, the first-doped group III-V semiconductor layer 4 on both sides of the second-doped group III-V semiconductor layer 5 is etched in a region to form a second through groove 42 and a third through groove 43, so as to disconnect the first-doped group III-V semiconductor layer 4 between the source electrode and the drain electrode. By forming the second through groove 42 and the third through groove 43 through the SAE process, insulation isolation between the source electrode and the gate, insulation isolation between the drain electrode and the gate, and insulation isolation between the source electrode and the drain electrode can be achieved. By forming the first through groove 41 and the fourth through groove 44 through the OHO process, it is used for subsequent deposition of metal to form the source electrode and the drain electrode. The SAE process and the OHO process are performed simultaneously, that is, a single mask can be used to form the first through groove 41, the second through groove 42, the third through groove 43, and the fourth through groove 44.

[0074] S150: Form a source electrode in the first through groove.

[0075] Specifically, as Figure 7 shown, a source electrode 6 is formed in the first through groove 41. The source electrode 6 may also extend outside the first through groove 41, and the source electrode 6 contacts the barrier layer 3 through the first through groove 41.

[0076] S160: Form a drain in the fourth through-groove.

[0077] Specifically, as Figure 7 shown, form a drain 7 in the fourth through-groove 44. The drain 7 can extend outside the fourth through-groove 44, and the drain 7 contacts the barrier layer 3 through the fourth through-groove 44.

[0078] In the technical solution of the embodiment of the present invention, during the preparation process of the semiconductor device, the first-doped group III-V semiconductor layers on both sides of the second-doped group III-V semiconductor layer are simultaneously subjected to selective enhancement treatment and ohmic hole opening treatment. By the SAE treatment, a second through-groove and a third through-groove are formed, which can realize the insulation isolation between the source and the gate, the insulation isolation between the drain and the gate, and the insulation isolation between the source and the drain. By the OHO treatment, a first through-groove and a fourth through-groove are formed for subsequent deposition of metal to form the source and the drain. The SAE treatment and the OHO treatment are carried out simultaneously, that is, using a single mask can realize the formation of the first through-groove, the second through-groove, the third through-groove, and the fourth through-groove. In the technical solution of the embodiment of the present invention, through the above process optimization, the process flow is simplified, the number of masks and the number of photolithography processes are saved, and the preparation cost is effectively reduced.

[0079] Optionally, on the basis of the above embodiments, Figure 8 is a flowchart of another method for preparing a semiconductor device provided by an embodiment of the present invention, Figures 9 - 11 is a schematic structural diagram corresponding to some steps in another method for preparing a semiconductor device provided by an embodiment of the present invention. As Figure 8 shown, the preparation method includes:

[0080] S200: Provide a substrate.

[0081] S210: Sequentially form a channel layer and a barrier layer on one side of the substrate.

[0082] S220: Form a first-doped group III-V semiconductor layer on the side of the barrier layer away from the substrate; the vertical projection of the first-doped group III-V semiconductor layer on the substrate coincides with the vertical projection of the barrier layer on the substrate.

[0083] S230: Form a second-doped group III-V semiconductor layer on the side of the first-doped group III-V semiconductor layer away from the substrate; the vertical projection of the second-doped group III-V semiconductor layer on the substrate is within the vertical projection of the first-doped group III-V semiconductor layer on the substrate.

[0084] S240: Form a first protective layer on the side of the first-doped group III-V semiconductor layer away from the substrate and on the side of the second-doped group III-V semiconductor layer away from the substrate.

[0085] Specifically, as Figure 9 shown, a first protective layer 10 is formed on the side of the first-doped group III-V semiconductor layer 4 away from the substrate 1 and on the side of the second-doped group III-V semiconductor layer 5 away from the substrate 1. The first protective layer 10 may include a first sub-protective layer 101 and a second sub-protective layer 102. The first protective layer 10 is mainly used to protect the second-doped group III-V semiconductor layer 5 from etching damage when etching the first protective layer 10 on both sides of the second-doped group III-V semiconductor layer 5 and the first-doped group III-V semiconductor layer 4 in subsequent processes.

[0086] S250: Etch the first protective layer on both sides of the second-doped group III-V semiconductor layer to form a fifth through groove, a sixth through groove, a seventh through groove, and an eighth through groove; wherein, the fifth through groove and the sixth through groove are located on the same side of the second-doped group III-V semiconductor layer, and the fifth through groove is located on the side of the sixth through groove away from the second-doped group III-V semiconductor layer; the seventh through groove and the eighth through groove are located on the other side of the second-doped group III-V semiconductor layer, and the eighth through groove is located on the side of the seventh through groove away from the second-doped group III-V semiconductor layer.

[0087] Specifically, as Figure 10 shown, etch partial regions of the first protective layer 10 on both sides of the second-doped group III-V semiconductor layer 5 to form a fifth through groove 103, a sixth through groove 104, a seventh through groove 105, and an eighth through groove 106.

[0088] S260: Etch the first-doped group III-V semiconductor layer on both sides of the second-doped group III-V semiconductor layer to form a first through groove communicating with the fifth through groove, a second through groove communicating with the sixth through groove, a third through groove communicating with the seventh through groove, and a fourth through groove communicating with the eighth through groove.

[0089] Specifically, as Figure 10 shown, etch the first-doped group III-V semiconductor layer 4 in the region corresponding to the fifth through groove 103 to form a first through groove 41, etch the first-doped group III-V semiconductor layer 4 in the region corresponding to the sixth through groove 104 to form a second through groove 42, etch the first-doped group III-V semiconductor layer 4 in the region corresponding to the seventh through groove 105 to form a third through groove 43, and etch the first-doped group III-V semiconductor layer 4 in the region corresponding to the eighth through groove 106 to form a fourth through groove 44. In the preparation process flow provided by the embodiments of the present invention, the fifth through groove 103, the first through groove 41, the sixth through groove 104, the second through groove 42, the seventh through groove 105, the third through groove 43, the eighth through groove 106, and the fourth through groove 44 can be simultaneously completed using a single mask plate in a single lithography process, simplifying the process flow, saving the number of mask plates and the number of lithography processes, and effectively reducing the preparation cost.

[0090] S270: Form a source electrode in the first through groove.

[0091] Specifically, as Figure 11 shown, a source electrode 6 is formed in the first through groove 41 and the fifth through groove 103, and the source electrode 6 can extend outside the fifth through groove 103.

[0092] S280: Form a drain electrode in the fourth through groove.

[0093] Specifically, as Figure 11 shown, a drain electrode 7 is formed in the fourth through groove 44 and the eighth through groove 106, and the drain electrode 7 can extend outside the eighth through groove 106.

[0094] Optionally, the first protective layer 10 on the side of the second-doped group III-V semiconductor layer 5 away from the substrate 1 can be etched to form a ninth through groove 107 to expose the second-doped group III-V semiconductor layer 5. Optionally, on the basis of the above embodiments, Figure 12 is a flowchart of another method for manufacturing a semiconductor device provided by an embodiment of the present invention, Figure 13 is a schematic structural diagram corresponding to some steps in another method for manufacturing a semiconductor device provided by an embodiment of the present invention. As Figure 12 shown, the manufacturing method includes:

[0095] S300: Provide a substrate.

[0096] S310: Sequentially form a channel layer and a barrier layer on one side of the substrate.

[0097] S320: Form a first-doped group III-V semiconductor layer on the side of the barrier layer away from the substrate; the vertical projection of the first-doped group III-V semiconductor layer on the substrate coincides with the vertical projection of the barrier layer on the substrate.

[0098] S330: Form a second-doped group III-V semiconductor layer on the side of the first-doped group III-V semiconductor layer away from the substrate; the vertical projection of the second-doped group III-V semiconductor layer on the substrate is within the vertical projection of the first-doped group III-V semiconductor layer on the substrate.

[0099] S340: Form a first sub-protective layer on the side of the first-doped group III-V semiconductor layer away from the substrate and on the side of the second-doped group III-V semiconductor layer away from the substrate.

[0100] Specifically, as Figure 13 shown, in the process of forming the first protective layer, first, a first sub-protective layer 101 is formed on the side of the first-doped group III-V semiconductor layer 4 away from the substrate 1 and on the side of the second-doped group III-V semiconductor layer 5 away from the substrate 1. Exemplarily, the first sub-protective layer 101 can include a silicon nitride protective layer.

[0101] S350: Form a second sub-protective layer on the side of the first sub-protective layer away from the substrate.

[0102] Specifically, as Figure 9 shown, form a second sub-protective layer 102 on the side of the first sub-protective layer 101 away from the substrate 1. Exemplarily, the second sub-protective layer 102 may include a silicon dioxide protective layer.

[0103] S360: Etch the first sub-protective layer and the second sub-protective layer on both sides of the second doped III-V semiconductor layer to form a fifth through groove, a sixth through groove, a seventh through groove, and an eighth through groove; wherein, the fifth through groove and the sixth through groove are located on the same side of the second doped III-V semiconductor layer, and the fifth through groove is located on the side of the sixth through groove away from the second doped III-V semiconductor layer; the seventh through groove and the eighth through groove are located on the other side of the second doped III-V semiconductor layer, and the eighth through groove is located on the side of the seventh through groove away from the second doped III-V semiconductor layer.

[0104] S370: Etch the first doped III-V semiconductor layer on both sides of the second doped III-V semiconductor layer to form a first through groove communicating with the fifth through groove, a second through groove communicating with the sixth through groove, a third through groove communicating with the seventh through groove, and a fourth through groove communicating with the eighth through groove.

[0105] S380: Form a source electrode in the first through groove.

[0106] S390: Form a drain electrode in the fourth through groove.

[0107] Optionally, based on the above embodiments, Figure 14 is a flowchart of another method for manufacturing a semiconductor device provided by an embodiment of the present invention, Figures 15 - 16 is a schematic structural diagram corresponding to some steps in another method for manufacturing a semiconductor device provided by an embodiment of the present invention. As Figure 14 shown, the manufacturing method includes:

[0108] S400: Provide a substrate.

[0109] S410: Sequentially form a channel layer and a barrier layer on one side of the substrate.

[0110] S420: Form a first doped III-V semiconductor layer on the side of the barrier layer away from the substrate; the vertical projection of the first doped III-V semiconductor layer on the substrate coincides with the vertical projection of the barrier layer on the substrate.

[0111] S430: Form a second doped III-V semiconductor layer on the side of the first doped III-V semiconductor layer away from the substrate; the vertical projection of the second doped III-V semiconductor layer on the substrate is within the vertical projection of the first doped III-V semiconductor layer on the substrate.

[0112] S440: A first protective layer is formed on the side of the first doped group III-V semiconductor layer away from the substrate and on the side of the second doped group III-V semiconductor layer away from the substrate.

[0113] S450: The first protective layer on both sides of the second doped group III-V semiconductor layer is etched to form a fifth through groove, a sixth through groove, a seventh through groove, and an eighth through groove; wherein, the fifth through groove and the sixth through groove are located on the same side of the second doped group III-V semiconductor layer, and the fifth through groove is located on the side away from the second doped group III-V semiconductor layer of the sixth through groove; the seventh through groove and the eighth through groove are located on the other side of the second doped group III-V semiconductor layer, and the eighth through groove is located on the side away from the second doped group III-V semiconductor layer of the seventh through groove.

[0114] S460: The first doped group III-V semiconductor layer on both sides of the second doped group III-V semiconductor layer is etched to form a first through groove communicating with the fifth through groove, a second through groove communicating with the sixth through groove, a third through groove communicating with the seventh through groove, and a fourth through groove communicating with the eighth through groove.

[0115] S470: An electrode layer is formed on the side of the first doped group III-V semiconductor layer away from the substrate, on the side of the second doped group III-V semiconductor layer away from the substrate, and inside the first through groove, the second through groove, the third through groove, and the fourth through groove.

[0116] Specifically, as Figure 15 shown, an electrode layer 9 is formed on the side of the first protective layer 10 away from the substrate 1, and an electrode layer 9 is formed inside the first through groove 41, the second through groove 42, the third through groove 43, the fourth through groove 44, the fifth through groove 103, the sixth through groove 104, the seventh through groove 105, and the eighth through groove 106. The electrode layer 9 can also extend to the outside of the first through groove 41, the second through groove 42, the third through groove 43, the fourth through groove 44, the fifth through groove 103, the sixth through groove 104, the seventh through groove 105, and the eighth through groove 106.

[0117] S480: The electrode layer outside the corresponding regions of the first through groove and the fourth through groove is removed; the electrode layer in the corresponding region of the first through groove serves as the source electrode, and the electrode layer in the corresponding region of the fourth through groove serves as the drain electrode.

[0118] Specifically, as Figure 16As shown, remove the electrode layer outside the corresponding regions of the first through groove 41 and the fifth through groove 103, the fourth through groove 44 and the eighth through groove 106. The electrode layer in the corresponding regions of the first through groove 41 and the fifth through groove 103 serves as the source electrode 6, and the electrode layer in the corresponding regions of the fourth through groove 44 and the eighth through groove 106 serves as the drain electrode 7. During the process of removing the electrode layer, a photoresist can be first formed on the side of the electrode layer away from the substrate 1, and the photoresist outside the corresponding regions of the first through groove 41 and the fifth through groove 103, the fourth through groove 44 and the eighth through groove 106 can be removed through processes such as exposure and development. Using the photoresist as a hard mask plate, the electrode layer is etched to retain the electrode layer in the corresponding regions of the first through groove 41 and the fifth through groove 103, the fourth through groove 44 and the eighth through groove 106. After the electrode layer is etched, the exposed barrier layer 3 can be subjected to an interface enhancement treatment to passivate interface defects and enhance the two-dimensional electron gas concentration.

[0119] Optionally, on the basis of the above embodiments, Figure 17 is a flowchart of another method for manufacturing a semiconductor device provided by an embodiment of the present invention, Figures 18 - 20 is a schematic structural diagram corresponding to some steps in another method for manufacturing a semiconductor device provided by an embodiment of the present invention. As Figure 17 shown, the manufacturing method includes:

[0120] S500: Provide a substrate.

[0121] S510: Sequentially form a channel layer and a barrier layer on one side of the substrate.

[0122] S520: Form a first doped III-V semiconductor layer on the side of the barrier layer away from the substrate; the vertical projection of the first doped III-V semiconductor layer on the substrate coincides with the vertical projection of the barrier layer on the substrate.

[0123] S530: Form a second doped III-V semiconductor layer on the side of the first doped III-V semiconductor layer away from the substrate; the vertical projection of the second doped III-V semiconductor layer on the substrate is within the vertical projection of the first doped III-V semiconductor layer on the substrate.

[0124] S540: Form a first protective layer on the side of the first doped III-V semiconductor layer away from the substrate and on the side of the second doped III-V semiconductor layer away from the substrate.

[0125] S550: Etch the first protective layer on both sides of the second-doped group III-V semiconductor layer to form a fifth through groove, a sixth through groove, a seventh through groove, and an eighth through groove; wherein, the fifth through groove and the sixth through groove are located on the same side of the second-doped group III-V semiconductor layer, and the fifth through groove is located on the side of the sixth through groove away from the second-doped group III-V semiconductor layer; the seventh through groove and the eighth through groove are located on the other side of the second-doped group III-V semiconductor layer, and the eighth through groove is located on the side of the seventh through groove away from the second-doped group III-V semiconductor layer.

[0126] S560: Etch the first-doped group III-V semiconductor layer on both sides of the second-doped group III-V semiconductor layer to form a first through groove communicating with the fifth through groove, a second through groove communicating with the sixth through groove, a third through groove communicating with the seventh through groove, and a fourth through groove communicating with the eighth through groove.

[0127] S570: Form an electrode layer on the side of the first-doped group III-V semiconductor layer away from the substrate, the side of the second-doped group III-V semiconductor layer away from the substrate, and inside the first through groove, the second through groove, the third through groove, and the fourth through groove.

[0128] S580: Remove the electrode layer outside the corresponding regions of the first through groove and the fourth through groove; the electrode layer in the corresponding region of the first through groove serves as the source electrode, and the electrode layer in the corresponding region of the fourth through groove serves as the drain electrode.

[0129] S590: Form a second protective layer on the side of the first-doped group III-V semiconductor layer away from the substrate, the side of the second-doped group III-V semiconductor layer away from the substrate, the side of the source electrode away from the substrate, the side of the drain electrode away from the substrate, and inside the second through groove and the third through groove.

[0130] Specifically, as Figure 18 shown, a second protective layer 11 is formed on the side of the first protective layer 10 away from the substrate 1, a second protective layer 11 is formed on the side of the source electrode 6 away from the substrate 1, a second protective layer 11 is formed on the side of the drain electrode 7 away from the substrate 1, and a second protective layer 11 is also formed inside the second through groove 42 and the sixth through groove 104 and inside the third through groove 43 and the seventh through groove 105. The second protective layer 11 can also extend outside the sixth through groove 104 and the seventh through groove 105. The second protective layer 11 can include a third sub-protective layer 111 and a fourth sub-protective layer 112. The second protective layer 11 is mainly used to protect the exposed barrier layer 3. Exemplarily, before forming the second protective layer 11, a layer of aluminum nitride layer (not shown in the figure) can be first formed on the side of the first protective layer 10 away from the substrate 1, the side of the source electrode 6 away from the substrate 1, the side of the drain electrode 7 away from the substrate 1, inside the second through groove 42 and the sixth through groove 104, and inside the third through groove 43 and the seventh through groove 105.

[0131] S591: Etch the second protective layer on the side of the source electrode away from the substrate to form a first opening to expose the source electrode, and etch the second protective layer on the side of the drain electrode away from the substrate to form a second opening to expose the drain electrode.

[0132] Specifically, as Figure 19 shown, etch the second protective layer 11 on the side of the source electrode 6 away from the substrate 1 to form a first opening 113 to expose the source electrode 6. Etch the second protective layer 11 on the side of the drain electrode 7 away from the substrate 1 to form a second opening 114 to expose the drain electrode 7.

[0133] Optionally, as Figure 20 shown, it is possible to etch the second protective layer 11 on the side of the second-doped III-V semiconductor layer 5 away from the substrate 1 to form a third opening 115, and then etch the first protective layer 10 corresponding to the third opening 15 to form a ninth through groove 107 to expose the second-doped III-V semiconductor layer 5.

[0134] Optionally, on the basis of the above embodiments, Figure 21 is a flowchart of yet another method for fabricating a semiconductor device provided by an embodiment of the present invention, Figure 22 is a schematic structural diagram corresponding to some steps in yet another method for fabricating a semiconductor device provided by an embodiment of the present invention. As Figure 21 shown, the fabrication method includes:

[0135] S600: Provide a substrate.

[0136] S610: Sequentially form a channel layer and a barrier layer on one side of the substrate.

[0137] S620: Form a first-doped III-V semiconductor layer on the side of the barrier layer away from the substrate; the vertical projection of the first-doped III-V semiconductor layer on the substrate coincides with the vertical projection of the barrier layer on the substrate.

[0138] S630: Form a second-doped III-V semiconductor layer on the side of the first-doped III-V semiconductor layer away from the substrate; the vertical projection of the second-doped III-V semiconductor layer on the substrate is within the vertical projection of the first-doped III-V semiconductor layer on the substrate.

[0139] S640: Form a first protective layer on the side of the first-doped III-V semiconductor layer away from the substrate and on the side of the second-doped III-V semiconductor layer away from the substrate.

[0140] S650: Etch the first protective layers on both sides of the second-doped group III-V semiconductor layer to form a fifth through-groove, a sixth through-groove, a seventh through-groove, and an eighth through-groove; wherein, the fifth through-groove and the sixth through-groove are located on the same side of the second-doped group III-V semiconductor layer, and the fifth through-groove is located on the side away from the second-doped group III-V semiconductor layer with respect to the sixth through-groove; the seventh through-groove and the eighth through-groove are located on the other side of the second-doped group III-V semiconductor layer, and the eighth through-groove is located on the side away from the second-doped group III-V semiconductor layer with respect to the seventh through-groove.

[0141] S660: Etch the first-doped group III-V semiconductor layers on both sides of the second-doped group III-V semiconductor layer to form a first through-groove communicating with the fifth through-groove, a second through-groove communicating with the sixth through-groove, a third through-groove communicating with the seventh through-groove, and a fourth through-groove communicating with the eighth through-groove.

[0142] S670: Form an electrode layer on the side of the first-doped group III-V semiconductor layer away from the substrate, on the side of the second-doped group III-V semiconductor layer away from the substrate, and inside the first through-groove, the second through-groove, the third through-groove, and the fourth through-groove.

[0143] S680: Remove the electrode layer outside the regions corresponding to the first through-groove and the fourth through-groove; the electrode layer in the region corresponding to the first through-groove serves as the source electrode, and the electrode layer in the region corresponding to the fourth through-groove serves as the drain electrode.

[0144] S690: Form a third sub-protective layer on the side of the first-doped group III-V semiconductor layer away from the substrate, on the side of the second-doped group III-V semiconductor layer away from the substrate, on the side of the source electrode away from the substrate, on the side of the drain electrode away from the substrate, and inside the second through-groove and the third through-groove.

[0145] Specifically, as Figure 22 shown, a third sub-protective layer 111 is formed on the side of the first protective layer 10 away from the substrate 1, a third sub-protective layer 111 is formed on the side of the source electrode 6 away from the substrate 1, a third sub-protective layer 111 is formed on the side of the drain electrode 7 away from the substrate 1, third sub-protective layers 111 are also formed inside the second through-groove 42 and the sixth through-groove 104, and inside the third through-groove 43 and the seventh through-groove 105. The third sub-protective layer 111 can also extend outside the sixth through-groove 104 and the seventh through-groove 105. Exemplarily, the third sub-protective layer 111 can include a silicon nitride protective layer.

[0146] S691: Form a fourth sub-protective layer on the side of the third sub-protective layer away from the substrate.

[0147] Specifically, as Figure 18 shown, a fourth sub-protective layer 112 is formed on the side of the third sub-protective layer 111 away from the substrate 1. Exemplarily, the fourth sub-protective layer 112 can include a silicon dioxide protective layer.

[0148] S692: Etch the second protective layer on the side of the source electrode away from the substrate to form a first opening to expose the source electrode, and etch the second protective layer on the side of the drain electrode away from the substrate to form a second opening to expose the drain electrode.

[0149] Optionally, based on the above embodiments, Figure 23 is a flowchart of another method for manufacturing a semiconductor device provided by an embodiment of the present invention, Figures 24 - 30 is a schematic structural diagram corresponding to some steps in another method for manufacturing a semiconductor device provided by an embodiment of the present invention. As Figure 23 shown, the manufacturing method includes:

[0150] S700: Provide a substrate.

[0151] S710: Sequentially form a channel layer and a barrier layer on one side of the substrate.

[0152] S720: Form a first doped group III-V semiconductor layer on the side of the barrier layer away from the substrate; the vertical projection of the first doped group III-V semiconductor layer on the substrate coincides with the vertical projection of the barrier layer on the substrate.

[0153] S730: Form a second doped group III-V semiconductor layer on the side of the first doped group III-V semiconductor layer away from the substrate; the vertical projection of the second doped group III-V semiconductor layer on the substrate is within the vertical projection of the first doped group III-V semiconductor layer on the substrate.

[0154] S740: Form a Schottky contact region on the side of the second doped group III-V semiconductor layer away from the substrate.

[0155] Specifically, as Figure 24 shown, a Schottky contact region 12 is formed in the middle region on the side of the second doped group III-V semiconductor layer 5 away from the substrate 1. Exemplarily, the material of the Schottky contact region 12 can be titanium nitride.

[0156] S750: Form a first protective layer on the side of the first doped group III-V semiconductor layer away from the substrate and on the side of the second doped group III-V semiconductor layer away from the substrate.

[0157] Specifically, as Figure 25 shown, a first protective layer 10 is formed on the side of the first doped group III-V semiconductor layer 4 away from the substrate 1, on the side of the second doped group III-V semiconductor layer 5 away from the substrate 1, and on the side of the Schottky contact region 12 away from the substrate 1. The first protective layer 10 is mainly used to protect film layers such as the second doped group III-V semiconductor layer 5 and the Schottky contact region 12 from etching damage when etching the first protective layer 10 on both sides of the second doped group III-V semiconductor layer 5 and the first doped group III-V semiconductor layer 4 in subsequent processes.

[0158] S760: Etch the first protective layers on both sides of the second-doped group III-V semiconductor layer to form a fifth through groove, a sixth through groove, a seventh through groove, and an eighth through groove; wherein, the fifth through groove and the sixth through groove are located on the same side of the second-doped group III-V semiconductor layer, and the fifth through groove is located on the side away from the second-doped group III-V semiconductor layer of the sixth through groove; the seventh through groove and the eighth through groove are located on the other side of the second-doped group III-V semiconductor layer, and the eighth through groove is located on the side away from the second-doped group III-V semiconductor layer of the seventh through groove.

[0159] Specifically, as Figure 26 shown, etch partial regions of the first protective layers 10 on both sides of the second-doped group III-V semiconductor layer 5 to form a fifth through groove 103, a sixth through groove 104, a seventh through groove 105, and an eighth through groove 106.

[0160] S770: Etch the first-doped group III-V semiconductor layers on both sides of the second-doped group III-V semiconductor layer to form a first through groove communicating with the fifth through groove, a second through groove communicating with the sixth through groove, a third through groove communicating with the seventh through groove, and a fourth through groove communicating with the eighth through groove.

[0161] Specifically, as Figure 26 shown, etch the first-doped group III-V semiconductor layer 4 in the region corresponding to the fifth through groove 103 to form a first through groove 41, etch the first-doped group III-V semiconductor layer 4 in the region corresponding to the sixth through groove 104 to form a second through groove 42, etch the first-doped group III-V semiconductor layer 4 in the region corresponding to the seventh through groove 105 to form a third through groove 43, and etch the first-doped group III-V semiconductor layer 4 in the region corresponding to the eighth through groove 106 to form a fourth through groove 44. In the preparation process flow provided by the embodiment of the present invention, the fifth through groove 103, the first through groove 41, the sixth through groove 104, the second through groove 42, the seventh through groove 105, the third through groove 43, the eighth through groove 106, and the fourth through groove 44 can be completed using a single mask plate in one photolithography process, simplifying the process flow, saving the number of mask plates and the number of photolithography processes, and effectively reducing the preparation cost.

[0162] S780: Form electrode layers on the side of the first-doped group III-V semiconductor layer away from the substrate, the side of the second-doped group III-V semiconductor layer away from the substrate, and inside the first through groove, the second through groove, the third through groove, and the fourth through groove.

[0163] Specifically, as Figure 27As shown, an electrode layer 9 is formed on the side of the first protective layer 10 away from the substrate 1, and the electrode layer 9 is also formed in the first through groove 41, the second through groove 42, the third through groove 43, the fourth through groove 44, the fifth through groove 103, the sixth through groove 104, the seventh through groove 105, and the eighth through groove 106. The electrode layer 9 can also extend outside the first through groove 41, the second through groove 42, the third through groove 43, the fourth through groove 44, the fifth through groove 103, the sixth through groove 104, the seventh through groove 105, and the eighth through groove 106.

[0164] S790: Remove the electrode layer outside the corresponding areas of the first through groove and the fourth through groove; the electrode layer in the corresponding area of the first through groove serves as the source electrode, and the electrode layer in the corresponding area of the fourth through groove serves as the drain electrode.

[0165] Specifically, as Figure 28 shown, remove the electrode layer outside the corresponding areas of the first through groove 41 and the fifth through groove 103, and the fourth through groove 44 and the eighth through groove 106. The electrode layers in the corresponding areas of the first through groove 41 and the fifth through groove 103 serve as the source electrode 6, and the electrode layers in the corresponding areas of the fourth through groove 44 and the eighth through groove 106 serve as the drain electrode 7.

[0166] S791: Form a second protective layer on the side of the first doped III-V semiconductor layer away from the substrate, the side of the second doped III-V semiconductor layer away from the substrate, the side of the source electrode away from the substrate, the side of the drain electrode away from the substrate, and inside the second through groove and the third through groove.

[0167] Specifically, as Figure 29 shown, a second protective layer 11 is formed on the side of the first protective layer 10 away from the substrate 1, a second protective layer 11 is formed on the side of the source electrode 6 away from the substrate 1, a second protective layer 11 is formed on the side of the drain electrode 7 away from the substrate 1, and the second protective layer 11 is also formed inside the second through groove 42 and the sixth through groove 104, and the third through groove 43 and the seventh through groove 105. The second protective layer 11 can also extend outside the sixth through groove 104 and the seventh through groove 105. The second protective layer 11 can include a third sub-protective layer 111 and a fourth sub-protective layer 112. The second protective layer 11 is mainly used to protect the exposed barrier layer 3.

[0168] S792: Etch the second protective layer on the side of the source electrode away from the substrate to form a first opening to expose the source electrode, and etch the second protective layer on the side of the drain electrode away from the substrate to form a second opening to expose the drain electrode.

[0169] Specifically, as Figure 30 shown, etch the second protective layer on the side of the source electrode 6 away from the substrate 1 to form a first opening 113 to expose the source electrode 6. Etch the second protective layer 11 on the side of the drain electrode 7 away from the substrate 1 to form a second opening 114 to expose the drain electrode 7.

[0170] Optionally, as Figure 30 shown, a third opening 115 is formed by etching the second protective layer 11 on the side of the Schottky contact region 12 away from the substrate 1, and then a ninth through groove 107 is formed by etching the first protective layer 10 corresponding to the third opening 115 to expose the Schottky contact region 12. The second-doped group III-V semiconductor layer 5 serves as a gate and can be connected to a metal layer in subsequent processes through the Schottky contact region 12.

[0171] Figure 30 is a schematic structural diagram of a semiconductor device provided by an embodiment of the present invention. The semiconductor device provided by an embodiment of the present invention is fabricated using the semiconductor device fabrication method provided in any of the above embodiments of the present invention. As Figure 30 shown, the semiconductor device includes: a substrate 1; a channel layer 2 and a barrier layer 3 located on one side of the substrate 1. A first-doped group III-V semiconductor layer 4 is located on the side of the barrier layer 3 away from the substrate 1, and the vertical projection of the first-doped group III-V semiconductor layer 4 on the substrate 1 coincides with the vertical projection of the barrier layer 3 on the substrate 1. A second-doped group III-V semiconductor layer 5 is located on the side of the first-doped group III-V semiconductor layer 4 away from the substrate 1, and the vertical projection of the second-doped group III-V semiconductor layer 5 on the substrate 1 is within the vertical projection of the first-doped group III-V semiconductor layer 4 on the substrate 1. The first-doped group III-V semiconductor layer 4 on both sides of the second-doped group III-V semiconductor layer 5 includes a first through groove 41, a second through groove 42, a third through groove 43, and a fourth through groove 44. Among them, the first through groove 41 and the second through groove 42 are located on the same side of the second-doped group III-V semiconductor layer 5, and the first through groove 41 is located on the side of the second through groove 42 away from the second-doped group III-V semiconductor layer 5. The third through groove 43 and the fourth through groove 44 are located on the other side of the second-doped group III-V semiconductor layer 5, and the fourth through groove 44 is located on the side of the third through groove 43 away from the second-doped group III-V semiconductor layer 5. A source electrode 6 is located in the first through groove 41. A drain electrode 7 is located in the fourth through groove 44.

[0172] Specifically, Figure 30 shows the structure of a GaN HEMT semiconductor device. The GaN HEMT semiconductor device includes a substrate 1, a channel layer 2, and a barrier layer 3 stacked. The substrate 1 can be a Si substrate, a sapphire substrate, or a GaN substrate. The channel layer 2 can use intrinsic GaN as the channel layer, and the barrier layer 3 can use an AlGaN material.

[0173] On the side of the barrier layer 3 away from the substrate 1, there is also a first doped group III-V semiconductor layer 4 and a second doped group III-V semiconductor layer 5 arranged in a stacked manner. Exemplarily, the first doped group III-V semiconductor layer 4 may include a P-type gallium nitride layer, and the second doped group III-V semiconductor layer 5 may also include a P-type gallium nitride layer. The first doped group III-V semiconductor layer 4 on both sides of the second doped group III-V semiconductor layer 5 includes a first through groove 41, a second through groove 42, a third through groove 43, and a fourth through groove 44. By performing SAE processing to form the second through groove 42 and the third through groove 43, insulation isolation between the source electrode and the gate electrode, insulation isolation between the drain electrode and the gate electrode, and insulation isolation between the source electrode and the drain electrode can be achieved. By performing OHO processing to form the first through groove 41 and the fourth through groove 44, it is used for subsequent deposition of metal to form the source electrode and the drain electrode. The SAE processing and the OHO processing are carried out simultaneously, that is, using one mask plate can simultaneously form the first through groove 41, the second through groove 42, the third through groove 43, and the fourth through groove 44.

[0174] A source electrode 6 is arranged in the first through groove 41, and the source electrode 6 can also extend outside the first through groove 41. The source electrode 6 contacts the barrier layer 3 through the first through groove 41. A drain electrode 7 is also arranged in the fourth through groove 44, and the drain electrode 7 can extend outside the fourth through groove 44. The drain electrode 7 contacts the barrier layer 3 through the fourth through groove 44.

[0175] The GaN HEMT semiconductor device may also include a Schottky contact region 12, and the Schottky contact region 12 is located on the side of the second doped group III-V semiconductor layer 5 away from the substrate 1. Exemplarily, the material of the Schottky contact region 12 may be titanium nitride. The second doped group III-V semiconductor layer 5 can serve as a gate electrode and can be connected to a metal layer through the Schottky contact region 12 in subsequent processes.

[0176] In the technical solution of the embodiment of the present invention, the first doped group III-V semiconductor layers on both sides of the second doped group III-V semiconductor layer include a first through groove, a second through groove, a third through groove, and a fourth through groove. During the preparation process of the semiconductor device, selective enhancement processing and ohmic hole opening processing are simultaneously performed on the first doped group III-V semiconductor layers on both sides of the second doped group III-V semiconductor layer. By performing SAE processing to form the second through groove and the third through groove, insulation isolation between the source electrode and the gate electrode, insulation isolation between the drain electrode and the gate electrode, and insulation isolation between the source electrode and the drain electrode can be achieved. By performing OHO processing to form the first through groove and the fourth through groove, it is used for subsequent deposition of metal to form the source electrode and the drain electrode. The SAE processing and the OHO processing are carried out simultaneously, that is, using one mask plate can form the first through groove, the second through groove, the third through groove, and the fourth through groove. In the technical solution of the embodiment of the present invention, through the above process optimization, the process flow is simplified, the number of mask plates and the number of photolithography processes are saved, and the preparation cost is effectively reduced.

[0177] Optionally, based on the above embodiments, continue to refer to Figure 30 , the semiconductor device further includes: a first protective layer 10. The first protective layer 10 is located on the side of the first doped group III-V semiconductor layer 4 away from the substrate 1 and on the side of the second doped group III-V semiconductor layer 5 away from the substrate 1. The first protective layer 10 includes a fifth through groove 103, a sixth through groove 104, a seventh through groove 105, and an eighth through groove 106. The vertical projection of the fifth through groove 103 on the substrate 1 coincides with the vertical projection of the first through groove 41 on the substrate 1, the vertical projection of the sixth through groove 104 on the substrate 1 coincides with the vertical projection of the second through groove 42 on the substrate 1, the vertical projection of the seventh through groove 105 on the substrate 1 coincides with the vertical projection of the third through groove 43 on the substrate 1, and the vertical projection of the eighth through groove 106 on the substrate 1 coincides with the vertical projection of the fourth through groove 44 on the substrate 1.

[0178] Specifically, the GaN HEMT semiconductor device may further include a first protective layer 10. The first protective layer 10 is disposed on the side of the first doped group III-V semiconductor layer 4 away from the substrate 1, on the side of the second doped group III-V semiconductor layer 5 away from the substrate 1, and on the side of the Schottky contact region 12 away from the substrate 1. The first protective layer 10 is mainly used to protect the second doped group III-V semiconductor layer 5 and the Schottky contact region 12 from etching damage when etching the first protective layer 10 on both sides of the second doped group III-V semiconductor layer 5 and the first doped group III-V semiconductor layer 4 in the manufacturing process. In the manufacturing process flow provided by the embodiments of the present invention, the fifth through groove 103, the first through groove 41, the sixth through groove 104, the second through groove 42, the seventh through groove 105, the third through groove 43, the eighth through groove 106, and the fourth through groove 44 can be completed using a single mask plate in a single photolithography process, simplifying the process flow, saving the number of mask plates and the number of photolithography processes, and effectively reducing the manufacturing cost.

[0179] Optionally, based on the above embodiments, continue to refer to Figure 30 , the semiconductor device further includes: a second protective layer 11. The second protective layer 11 is located on the side of the first doped group III-V semiconductor layer 4 away from the substrate 1, on the side of the second doped group III-V semiconductor layer 5 away from the substrate 1, on the side of the source electrode 6 away from the substrate 1, on the side of the drain electrode 7 away from the substrate 1, and inside the second through groove 42 and the third through groove 43. The second protective layer 11 includes a first opening 113 and a second opening 114. The first opening 113 is located on the side of the source electrode 6 away from the substrate 1, and the second opening 114 is located on the side of the drain electrode 7 away from the substrate 1.

[0180] Specifically, the GaN HEMT semiconductor device may further include a second protective layer 11, which is disposed on the side of the first protective layer 10 away from the substrate 1, the side of the source electrode 6 away from the substrate 1, the side of the drain electrode 7 away from the substrate 1, the second through groove 42 and the sixth through groove 104, and the third through groove 43 and the seventh through groove 105. The second protective layer 11 is mainly used to protect the exposed barrier layer 3.

[0181] Optionally, based on the above embodiments, continue to refer to Figure 30 , the semiconductor device further includes: a Schottky contact region 12. The Schottky contact region 12 is located on the side of the second-doped group III-V semiconductor layer 5 away from the substrate 1. Specifically, the GaN HEMT semiconductor device may further include a Schottky contact region 12, and the second-doped group III-V semiconductor layer 5 may serve as a gate and can be connected to a metal layer through the Schottky contact region 12 in subsequent processes.

[0182] Since the GaN HEMT semiconductor device provided by the technical solution of the embodiment of the present invention has a different manufacturing process from the existing GaN HEMT semiconductor device, the final GaN HEMT semiconductor device has two fewer insulating protective layers than the existing GaN HEMT semiconductor device, reducing the device size.

[0183] It should be understood that various forms of the processes shown above can be used, reordering, adding, or deleting steps. For example, the steps described in the present invention can be executed in parallel, sequentially, or in a different order, as long as the desired results of the technical solution of the present invention can be achieved, and no limitation is imposed herein.

[0184] The above specific embodiments do not constitute a limitation to the protection scope of the present invention. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principle of the present invention shall be included within the protection scope of the present invention.

Claims

1. A method for manufacturing a semiconductor device, characterized in that, Including: Providing a substrate; Successively forming a channel layer and a barrier layer on one side of the substrate; Forming a first doped group III-V semiconductor layer on the side of the barrier layer away from the substrate; the vertical projection of the first doped group III-V semiconductor layer on the substrate coincides with the vertical projection of the barrier layer on the substrate; Forming a second doped group III-V semiconductor layer on the side of the first doped group III-V semiconductor layer away from the substrate; the vertical projection of the second doped group III-V semiconductor layer on the substrate is within the vertical projection of the first doped group III-V semiconductor layer on the substrate; Etching the first doped group III-V semiconductor layer on both sides of the second doped group III-V semiconductor layer to form a first through groove, a second through groove, a third through groove, and a fourth through groove; wherein, the first through groove and the second through groove are located on the same side of the second doped group III-V semiconductor layer, and the first through groove is located on the side of the second through groove away from the second doped group III-V semiconductor layer; the third through groove and the fourth through groove are located on the other side of the second doped group III-V semiconductor layer, and the fourth through groove is located on the side of the third through groove away from the second doped group III-V semiconductor layer; Forming a source electrode in the first through groove; Forming a drain electrode in the fourth through groove.

2. The manufacturing method of the semiconductor device according to claim 1, characterized in that, Before etching the first doped group III-V semiconductor layer on both sides of the second doped group III-V semiconductor layer to form a first through groove, a second through groove, a third through groove, and a fourth through groove, further including: Forming a first protective layer on the side of the first doped group III-V semiconductor layer away from the substrate and on the side of the second doped group III-V semiconductor layer away from the substrate; Etching the first protective layer on both sides of the second doped group III-V semiconductor layer to form a fifth through groove, a sixth through groove, a seventh through groove, and an eighth through groove; wherein, the fifth through groove and the sixth through groove are located on the same side of the second doped group III-V semiconductor layer, and the fifth through groove is located on the side of the sixth through groove away from the second doped group III-V semiconductor layer; the seventh through groove and the eighth through groove are located on the other side of the second doped group III-V semiconductor layer, and the eighth through groove is located on the side of the seventh through groove away from the second doped group III-V semiconductor layer; Etching the first doped group III-V semiconductor layer on both sides of the second doped group III-V semiconductor layer to form a first through groove, a second through groove, a third through groove, and a fourth through groove, including: Etching the first doped group III-V semiconductor layer on both sides of the second doped group III-V semiconductor layer to form the first through groove communicating with the fifth through groove, the second through groove communicating with the sixth through groove, the third through groove communicating with the seventh through groove, and the fourth through groove communicating with the eighth through groove.

3. The manufacturing method of the semiconductor device according to claim 2, characterized in that, Forming a first protective layer on the side of the first doped group III-V semiconductor layer away from the substrate and on the side of the second doped group III-V semiconductor layer away from the substrate, including: A first sub-protective layer is formed on a side of the first doped group III-V semiconductor layer away from the substrate and on a side of the second doped group III-V semiconductor layer away from the substrate; A second sub-protective layer is formed on a side of the first sub-protective layer away from the substrate.

4. The manufacturing method of the semiconductor device according to claim 1, characterized in that, Forming a source electrode in the first through groove and forming a drain electrode in the fourth through groove includes: Forming an electrode layer on a side of the first doped group III-V semiconductor layer away from the substrate, on a side of the second doped group III-V semiconductor layer away from the substrate, and in the first through groove, the second through groove, the third through groove, and the fourth through groove; Removing the electrode layer outside the corresponding regions of the first through groove and the fourth through groove; the electrode layer in the corresponding region of the first through groove serves as the source electrode, and the electrode layer in the corresponding region of the fourth through groove serves as the drain electrode.

5. The method for manufacturing a semiconductor device according to claim 1, characterized in that, After forming the drain electrode in the fourth through groove, it further includes: Forming a second protective layer on a side of the first doped group III-V semiconductor layer away from the substrate, on a side of the second doped group III-V semiconductor layer away from the substrate, on a side of the source electrode away from the substrate, on a side of the drain electrode away from the substrate, and in the second through groove and the third through groove; Etching the second protective layer on a side of the source electrode away from the substrate to form a first opening to expose the source electrode, and etching the second protective layer on a side of the drain electrode away from the substrate to form a second opening to expose the drain electrode.

6. The manufacturing method of the semiconductor device according to claim 5, characterized in that, Forming a second protective layer on a side of the first doped group III-V semiconductor layer away from the substrate, on a side of the second doped group III-V semiconductor layer away from the substrate, on a side of the source electrode away from the substrate, on a side of the drain electrode away from the substrate, and in the second through groove and the third through groove includes: Forming a third sub-protective layer on a side of the first doped group III-V semiconductor layer away from the substrate, on a side of the second doped group III-V semiconductor layer away from the substrate, on a side of the source electrode away from the substrate, on a side of the drain electrode away from the substrate, and in the second through groove and the third through groove; Forming a fourth sub-protective layer on a side of the third sub-protective layer away from the substrate.

7. The method for manufacturing a semiconductor device according to claim 1, wherein, After forming the second doped group III-V semiconductor layer on a side of the first doped group III-V semiconductor layer away from the substrate, it further includes: Forming a Schottky contact region on a side of the second doped group III-V semiconductor layer away from the substrate.

8. A semiconductor device, characterized in that, Including: A substrate; A channel layer and a barrier layer located on one side of the substrate; A first doped group III-V semiconductor layer located on a side of the barrier layer away from the substrate; the vertical projection of the first doped group III-V semiconductor layer on the substrate coincides with the vertical projection of the barrier layer on the substrate; A second doped group III-V semiconductor layer located on a side of the first doped group III-V semiconductor layer away from the substrate; a vertical projection of the second doped group III-V semiconductor layer on the substrate is within a vertical projection of the first doped group III-V semiconductor layer on the substrate; the first doped group III-V semiconductor layers on both sides of the second doped group III-V semiconductor layer include a first through groove, a second through groove, a third through groove, and a fourth through groove; wherein, the first through groove and the second through groove are located on the same side of the second doped group III-V semiconductor layer, and the first through groove is located on a side of the second through groove away from the second doped group III-V semiconductor layer; the third through groove and the fourth through groove are located on the other side of the second doped group III-V semiconductor layer, and the fourth through groove is located on a side of the third through groove away from the second doped group III-V semiconductor layer; A source electrode located within the first through groove; A drain electrode located within the fourth through groove.

9. The semiconductor device according to claim 8, wherein Further comprising: A first protective layer; The first protective layer is located on a side of the first doped group III-V semiconductor layer away from the substrate and on a side of the second doped group III-V semiconductor layer away from the substrate; the first protective layer includes a fifth through groove, a sixth through groove, a seventh through groove, and an eighth through groove; a vertical projection of the fifth through groove on the substrate coincides with a vertical projection of the first through groove on the substrate, a vertical projection of the sixth through groove on the substrate coincides with a vertical projection of the second through groove on the substrate, a vertical projection of the seventh through groove on the substrate coincides with a vertical projection of the third through groove on the substrate, and a vertical projection of the eighth through groove on the substrate coincides with a vertical projection of the fourth through groove on the substrate.

10. The semiconductor device according to claim 8, wherein, Further comprising: A second protective layer; The second protective layer is located on a side of the first doped group III-V semiconductor layer away from the substrate, a side of the second doped group III-V semiconductor layer away from the substrate, a side of the source electrode away from the substrate, a side of the drain electrode away from the substrate, and within the second through groove and the third through groove; the second protective layer includes a first opening and a second opening, the first opening is located on a side of the source electrode away from the substrate, and the second opening is located on a side of the drain electrode away from the substrate.

11. The semiconductor device according to claim 8, wherein Further comprising: A Schottky contact region; The Schottky contact region is located on a side of the second doped group III-V semiconductor layer away from the substrate.

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