Photoresist development with halide chemicals

Abstract

Development of photoresist may be useful, for example, for forming patterned masks in the context of high resolution patterning. Developing may be accomplished using a halide-containing chemical, such as a hydrogen halide. A metal-containing resist film may be deposited on a semiconductor substrate using a dry or wet deposition technique. The photoresist film may be an EUV sensitive organic metal-containing oxide or organic metal-containing thin film resist. After exposure, the photo-patterned metal-containing resist is developed using wet or dry development.

Description

This application is a divisional application of the patent application for "Photoresist Development Using Halide Chemicals" with application number 202080046943.1, filing date June 25, 2020, and applicant Lam Research Corporation. Incorporated by reference

[0001] The PCT application form is filed simultaneously with this specification as part of this application. Each application for which this application claims the benefit or priority, as identified in the PCT application form filed simultaneously, is incorporated herein by reference in its entirety and for all purposes. Background Art

[0002] The processing of semiconductor devices such as integrated circuits is a multi-step process involving lithography. Generally, the process includes depositing a material on a wafer and patterning the material via lithographic techniques to form the structural features (e.g., transistors and circuitry) of the semiconductor device. Steps in a typical lithographic process known in the art include: preparing a substrate; applying a photoresist, e.g., by spin coating; exposing the photoresist to light of a desired pattern such that the exposed regions of the photoresist become more soluble or less soluble in a developer solution; developing by applying the developer solution to remove the exposed regions, or unexposed regions, of the photoresist; and subsequent processing, e.g., by etching or material deposition to create features on the substrate regions from which the photoresist has been removed.

[0003] The evolution of semiconductor design creates a need to create ever smaller features on semiconductor substrate materials, and the ability to create ever smaller features on semiconductor substrate materials drives the evolution of semiconductor design. In "Moore's Law", this technological progression is characterized by doubling the transistor density in dense integrated circuits every two years. Indeed, chip design and manufacturing have advanced such that advanced microprocessors can contain billions of transistors and other circuit features on a single chip. The individual features on such chips can be on the order of 22 nanometers (nm) or smaller, and in some cases less than 10 nm.

[0004] One challenge in manufacturing devices with such tiny features is the ability to reliably and reproducibly create a lithographic mask with sufficient resolution. Current lithographic processes typically use ultraviolet (UV) light at 193 nm to expose the photoresist. The fact that the wavelength of the light is significantly larger than the desired feature size to be fabricated on the semiconductor substrate creates an inherent problem. Achieving feature sizes smaller than the wavelength of the light requires the use of complex resolution enhancement techniques such as multiple patterning. Thus, there is significant interest and research effort in developing lithographic techniques that use light of shorter wavelengths, such as extreme ultraviolet (EUV) radiation, which has a wavelength of 10 nm to 15 nm (e.g., 13.5 nm).

[0005] However, EUV lithography processing can present challenges, including low power output and light loss during patterning. There can be potential drawbacks when using conventional chemically amplified resists (CARs) (similar to those used in 193 nm UV lithography) in EUV lithography, especially since they have low absorption coefficients in the EUV region and diffusion of photoactivated chemicals can cause blurring and line edge roughness. Additionally, to provide the etch resistance required to pattern underlying device layers, the patterned microfeatures in conventional CAR materials may risk pattern collapse to form high aspect ratios. Accordingly, there remains a need for improved EUV photoresist materials having properties such as lower thickness, higher absorption, and higher etch resistance.

[0006] The background description provided herein is for the purpose of generally presenting the background of the technology. The work of the currently named inventors, to the extent it is described in this background section of the application and in other parts of the specification that were not part of the prior art as of the filing date of the application, is neither expressly nor impliedly admitted to be prior art to the present technology. SUMMARY OF THE INVENTION

[0007] Development of a photoresist can be useful, for example, for forming a patterned mask in the context of high-resolution patterning. Using certain development chemicals, development can selectively remove either the exposed or unexposed portions of the resist. The development chemicals can include halides, such as hydrogen halides, or mixtures of hydrogen and halide gases. In some embodiments, the development is dry development. In some embodiments, the resist is a photo-patterned metal-containing EUV resist. In some embodiments, the dry development process is a plasma-free heat treatment.

[0008] Disclosed herein are methods and systems for processing a semiconductor substrate. A method of processing a semiconductor substrate includes providing, in a processing chamber, a photo-patterned metal-containing resist on a substrate layer of the semiconductor substrate; and developing the photo-patterned metal-containing resist by selectively removing a portion of the resist by exposing the resist to a development chemical that includes a halide to form a resist mask.

[0009] In some implementations, the optically patterned metal-containing resist is an optically patterned metal-containing EUV resist. In some implementations, developing the optically patterned metal-containing EUV resist includes selectively removing the non-EUV-exposed portions of the EUV resist relative to the EUV-exposed portions using the developer chemical to form the resist mask. In some implementations, the developer chemical includes hydrogen halide, hydrogen and halogen gas, organic halide, acyl halide, carbonyl halide, thionyl halide, or a mixture thereof. In some implementations, the developer chemical includes hydrogen fluoride, hydrogen chloride, hydrogen bromide, or hydrogen iodide. In some implementations, developing the optically patterned metal-containing resist by exposure to the developer chemical includes dry-developing the optically patterned metal-containing resist by exposure to a dry developer chemical. In some implementations, dry-developing the optically patterned metal-containing resist includes applying a remote plasma including radicals of the halide to the resist. In some implementations, dry-developing the optically patterned metal-containing resist is performed at a temperature between -60°C and 120°C, a chamber pressure between 0.1 mTorr and 500 Torr or between about 0.5 Torr and about 760 Torr, and a gas flow rate of the halide between 100 sccm and 2000 sccm, and the etch selectivity of the resist mask can be adjusted at least in part based on the temperature, the chamber pressure, the gas flow rate, or a combination thereof. In some implementations, the temperature is between -20°C and 20°C. In some implementations, the optically patterned metal-containing resist includes an element selected from the group consisting of tin, hafnium, tellurium, bismuth, indium, antimony, iodine, and germanium. In some implementations, the method further includes exposing the optically patterned metal-containing resist to an inert gas plasma after developing the optically patterned metal-containing resist. In some implementations, the method further includes depositing a metal-containing EUV resist film on the semiconductor substrate; and non-selectively removing the metal-containing EUV resist film from the semiconductor substrate without removing the substrate layer before providing the optically patterned metal-containing resist.

[0010] Disclosed herein is an apparatus for developing a resist. The apparatus includes a processing chamber having a substrate support; a vacuum line coupled to the processing chamber; and a developing chemical line coupled to the processing chamber. The apparatus further includes a controller configured with instructions for processing a semiconductor substrate, the instructions including code for: providing a photopatterned metal-containing resist on a substrate layer of the semiconductor substrate in the processing chamber; and developing the photopatterned metal-containing resist by selectively removing a portion of the resist by exposing the resist to a developing chemical including a halide to form a resist mask.

[0011] In some implementations, the photopatterned metal-containing resist is a photopatterned metal-containing EUV resist, and wherein the controller includes code for selectively removing an un-EUV-exposed portion of the EUV resist relative to an EUV-exposed portion using the developing chemical to form the resist mask, wherein the controller is configured with instructions. The instructions include code for developing the photopatterned metal-containing EUV resist. In some implementations, the apparatus further includes one or more heaters coupled to the substrate support, wherein the one or more heaters include a plurality of independently controllable temperature control zones. In some implementations, the interior of the processing chamber is coated with a corrosion inhibitor. In some implementations, the apparatus further includes a cold trap coupled to the processing chamber, wherein the cold trap is configured to remove water from the processing chamber. In some implementations, the apparatus further includes a UV lamp or an IR lamp coupled to the processing chamber, wherein the UV lamp or the IR lamp is configured to cure the photopatterned metal-containing resist or to remove excess halide from the processing chamber.

[0012] Disclosed herein is a method for processing a semiconductor substrate. The method includes providing a dry-deposited photopatterned metal oxide EUV resist on a substrate layer of a semiconductor substrate in a processing chamber; and dry-developing the photopatterned metal oxide EUV resist by selectively removing an un-EUV-exposed portion of the EUV resist by exposing the EUV resist to a dry-developing chemical including hydrogen halide to form a resist hard mask from the EUV-exposed portion.

[0013] In some implementations, the dry development is performed in a plasma-free heat treatment, wherein the exposure to the dry-developing chemical is performed at a temperature between about -20 °C and about 20 °C. In some implementations, the photopatterned metal oxide EUV resist includes organotin oxide.

[0014] These and other features of the disclosed embodiments will be described in detail below with reference to the associated drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 A flowchart presenting an exemplary method for depositing and developing a photoresist according to some embodiments.

[0016] Figures 2A - 2C A cross-sectional schematic diagram showing various processing stages of dry development according to some embodiments.

[0017] Figure 3 An exemplary dry development mechanism shown according to some embodiments for the chemical reaction of hydrogen bromide (HBr) with the exposed and unexposed portions of an EUV resist.

[0018] Figure 4A A cross-sectional schematic diagram showing dry development without applying an inert gas plasma according to some embodiments.

[0019] Figure 4B A cross-sectional schematic diagram showing dry development with an inert gas plasma recycled to remove residues according to some embodiments.

[0020] Figure 5 A graph is shown that compares the etching rates between the exposed and unexposed portions of an EUV photoresist using a helium plasma during dry development.

[0021] Figure 6A And 6B Scanning electron microscope (SEM) images are shown comparing wet development and dry development in terms of line collapse.

[0022] Figure 7A And 7B SEM images are shown comparing wet development and dry development in terms of controlling roughness and critical dimension (CD).

[0023] Figure 8 SEM images are shown comparing wet development and dry development in terms of residues after hard mask opening.

[0024] Figure 9A And 9B Multiple graphs are shown that illustrate the effect of the post-second-exposure bake operation on the selectivity of dry development at different pressures and temperatures.

[0025] Figure 10 Multiple SEM images are shown that illustrate the effect of pressure on the EUV resist profile.

[0026] Figure 11A And 11BShows SEM images of EUV resists at different pitches and different thicknesses for different lines / spacings.

[0027] Figure 12 Depicts a schematic diagram of an exemplary processing station for maintaining a low-pressure environment, which is suitable for performing development, cleaning, rework, residue removal, and smoothing operations.

[0028] Figure 13 Illustrates a schematic diagram of an exemplary multi-station processing tool, which is suitable for implementing the development, cleaning, rework, residue removal, and smoothing operations described herein.

[0029] Figure 14 Shows a cross-sectional schematic diagram of an exemplary inductively coupled plasma device, which is used to implement certain embodiments and operations described herein.

[0030] Figure 15 Depicts a semiconductor processing cluster tool architecture having a vacuum integrated deposition and patterning module docked with a vacuum transfer module, which is suitable for implementing the processing described herein. Detailed Description

[0031] The present disclosure generally relates to the field of semiconductor processing. In certain aspects, the present disclosure is directed to processes and apparatuses for developing photoresists (e.g., photoresists containing EUV-sensitive metals and / or metal oxides) using halide chemicals to form, for example, a patterned mask in the context of EUV patterning.

[0032] Specific embodiments of the present disclosure are referred to in detail herein. Examples of these specific embodiments are illustrated in the accompanying drawings. While the present disclosure will be described in conjunction with these specific embodiments, it is understood that this is not intended to limit the present disclosure to these specific embodiments. On the contrary, it is intended to cover modifications, variations, and equivalents that may be included within the spirit and scope of the present disclosure. In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present disclosure. The present disclosure may be practiced without some or all of these specific details. In other instances, well-known processing operations are not described in detail so as not to unnecessarily obscure the present disclosure. Introduction

[0033] In semiconductor processing, patterning of thin films is often an important step in semiconductor fabrication. Patterning involves lithography. In conventional lithography (e.g., 193 nm lithography), a pattern is printed by emitting photons from a photon source onto a mask and imprinting the pattern on a photosensitive photoresist, thereby causing a chemical reaction in the photoresist that results in the removal of certain portions of the photoresist after development to form a pattern.

[0034] Advanced technology nodes (as defined by the International Technology Roadmap for Semiconductors) include 22 nm, 16 nm, and lower nodes. For example, in a 16 nm node, the width of a typical via or line in a damascene structure is generally no greater than about 30 nm. Scaling the features on advanced semiconductor integrated circuits (ICs) and other devices drives lithography to improve resolution.

[0035] Extreme ultraviolet (EUV) lithography can extend lithography technology by moving to a smaller imaging source wavelength compared to what can be achieved by conventional lithography methods. An EUV light source located at a wavelength of about 10 - 20 nm, or 11 - 14 nm (e.g., 13.5 nm wavelength) can be used in a front-end lithography tool, which is also referred to as a scanner. The radiation of EUV is strongly absorbed by various solid and fluid materials (including quartz and water vapor), and thus it operates in a vacuum.

[0036] EUV lithography uses a patterned EUV resist to form a mask used in etching the underlying layer. The EUV resist can be a polymer-based chemically amplified resist (CAR) fabricated by a liquid-based spin coating technique. Alternatives to CAR are metal oxide-containing films that can be directly photo-patterned, such as those available from Inpria, Corvallis, OR; and those described, for example, in U.S. Patent Applications US2017 / 0102612, US2016 / 021660, and US2016 / 0116839, the disclosures of which, at least for the photo-patternable metal oxide-containing films, are incorporated herein by reference. Such films can be fabricated by spin coating techniques or dry vapor deposition. The metal oxide-containing films can be directly patterned (i.e., without using a separate photoresist) by EUV exposure in a vacuum environment to provide sub-30nm patterning resolution, such as those described in U.S. Patent 9,996,004, entitled "EUV PHOTOPATTERNING OF VAPOR-DEPOSITED METAL OXIDE-CONTAINING HARDMASKS," issued on June 12, 2018, and / or in Application PCT / US19 / 31618, entitled "METHODS FOR MAKING EUV PATTERNABLE HARD MASKS," filed on May 9, 2019, the disclosures of which (which at least relate to the composition, deposition, and patterning of the directly photo-patternable metal oxide film to form an EUV photoresist mask) are incorporated herein by reference. Generally, patterning involves exposing the EUV resist to EUV radiation to form an optical pattern in the resist, followed by development to remove a portion of the photoresist according to the optical pattern to form a mask.

[0037] It should also be understood that while the present disclosure relates to lithographic patterning techniques and materials with EUV lithography as an example, it can also be applied to other next-generation lithography techniques. In addition to EUV, which currently includes the standard 13.5nm EUV wavelength in use and development, the radiation sources most relevant to such lithography are DUV (deep UV), which generally refers to the use of excimer laser sources at 248nm or 193nm; X-rays, which formally include EUV in the lower energy range of the X-ray spectrum; and electron beams, which can cover a wide range of energy. These particular methods can depend on the specific materials and applications used in the semiconductor substrate and the final semiconductor device. Thus, the methods described in the present application are only exemplary methods and materials that can be used in this technology.

[0038] Directly photo-patternable EUV resists can be composed of metals and / or metal oxides mixed within an organic component, or contain metals and / or metal oxides mixed within an organic component. The metals / metal oxides are very promising because they can enhance the absorption of EUV photons and generate secondary electrons, and / or exhibit enhanced etch selectivity to the underlying film stack and device layers. To date, these resists have been developed using wet (solvent) methods, which require moving the wafers to a track where the wafers are exposed to the developing solvent, dried, and baked. Wet development not only limits productivity but also causes line collapse due to surface tension effects and / or delamination.

[0039] Dry development has been proposed to overcome these problems by eliminating substrate peeling and interface failures. Dry development can improve performance (e.g., prevent line collapse due to surface tension and peeling in wet development) and increase throughput (e.g., by avoiding wet development tracks). Other advantages can include eliminating the use of organic solvent developers, reducing sensitivity to adhesion problems, improving EUV absorbance for improved dose efficiency, and not having solubility-based limitations. Dry development can also provide more tunability and give further critical dimension (CD) control, as well as scum removal.

[0040] Dry development has its own challenges, including the etch selectivity between unexposed and EUV-exposed resist materials, which may result in a higher dose ratio size requirement for effective resist exposure when compared to wet development. Sub-optimal selectivity may also cause PR corner rounding due to longer exposure to the etch gas, which may increase the CD variation of the lines in subsequent etch transfer steps. Development of EUV Resist

[0041] In various aspects of the present disclosure, a photopatterned metal-containing photoresist is developed by exposure to a halogen-containing chemical. A EUV-sensitive metal, or metal oxide film, such as an organotin oxide, is disposed on a semiconductor substrate. The EUV-sensitive metal, or metal oxide film, is directly patterned by EUV exposure in a vacuum environment. Subsequently, the pattern is developed using a developing chemical to form a resist mask. In some embodiments, the developing chemical is a dry developing chemical. In some embodiments, the dry developing chemical includes hydrogen and a halide. This dry developing technique can be accomplished by flowing the dry developing chemical of hydrogen and a halide while using a mild plasma (high pressure, low power) or heat treatment. The present disclosure provides processes and apparatuses configured to develop a metal-containing resist as part of a resist mask shaping process. Various embodiments include vapor deposition, EUV lithography patterning, and dry development to combine all dry operations. Various other embodiments include combinations of wet and dry processing operations, such as spin coating an EUV resist (wet processing) combined with dry development, or other wet or dry processing described herein. Also described are various post-deposition (or post-application) processes, such as bevel and backside cleaning, chamber cleaning, residue removal, smoothing, and curing, to modify and enhance film characteristics; and rework processes for photoresists.

[0042] Figure 1 A flowchart depicting an exemplary method for depositing and developing a photoresist is presented in accordance with some embodiments. The operations of process 100 may be performed in a different order, and / or with different, fewer, or additional operations. Aspects of process 100 may be described with reference to Figures 2A - 2C , Figure 3 and Figures 4A - 4B . One or more operations of process 100 may be performed using an apparatus described in any of Figures 12 - 15 . In some embodiments, the operations of process 100 may be implemented at least in part in accordance with software stored on one or more non-transitory computer-readable media.

[0043] At block 102 of process 100, a photoresist layer is deposited. This can be a dry deposition process (e.g., a vapor deposition process), or a wet process (e.g., a spin coating deposition process).

[0044] The photoresist can be a metal-containing EUV resist. By any suitable technique, including wet (e.g., spin coating) or dry (e.g., CVD) deposition techniques, a film containing an EUV-sensitive metal or metal oxide can be deposited on a semiconductor substrate. For example, the process has been demonstrated for EUV photoresist compositions based on organotin oxides, where the organotin oxides can be applied to commercial spin-on formulations (e.g., available from Inpria Corp, Corvallis, OR), as well as formulations applied using dry vacuum deposition techniques, which are further described below.

[0045] The semiconductor substrate can include any material structure suitable for lithographic processing, particularly suitable for the fabrication of integrated circuits and other semiconductor devices. In some embodiments, the semiconductor substrate is a silicon wafer. The semiconductor substrate can be a silicon wafer on which features (“underlying features”) have been formed, having an irregular surface topography. As mentioned herein, a “surface” is the surface on which the film of the present disclosure is to be deposited, or the surface to be exposed to EUV during processing. The underlying features can include regions where material has been removed (e.g., by etching) during processing prior to implementing the method of the present disclosure, or regions where material has been added (e.g., by deposition). Such prior processing can include the method of the present disclosure, or other processing methods in a repeated process, by which two or more feature layers are formed on the substrate.

[0046] An EUV-sensitive thin film can be deposited on the semiconductor substrate, and such a film can serve as a resist for subsequent EUV lithography and processing. The materials included in such an EUV-sensitive thin film undergo changes upon exposure to EUV, such as the loss of large pendant substituents bonded to metal atoms in a material rich in low-density M-OH, causing them to crosslink into a denser M-O-M-bonded metal oxide material. Via EUV patterning, regions of the film with altered physical or chemical properties are produced relative to unexposed regions. These properties are exploitable in subsequent processing, such as for dissolving unexposed or exposed regions, or for selectively depositing materials on exposed or unexposed regions. In some embodiments, under the conditions for performing such subsequent processing, the unexposed film has a more hydrophobic surface than the exposed film, and removal of materials can be performed, for example, by taking advantage of differences in the chemical composition, density, and crosslinking of the film. The removal can be carried out by wet processing or dry processing, as further described below.

[0047] In various embodiments, the film is an organometallic material, such as an organotin material including tin oxide, or other metal oxide materials / moieties. The organometallic compound can be prepared by the reaction of an organometallic precursor with a counter-reactant in the gas phase. In various embodiments, the organometallic compound is formed by mixing a specific composition of an organometallic precursor having a large alkyl or fluoroalkyl group with a counter-reactant and polymerizing the mixture in the gas phase to produce a low-density EUV-sensitive material deposited on a semiconductor substrate.

[0048] In various embodiments, the organometallic precursor includes at least one alkyl group on each metal atom that can be retained under gas-phase reaction, and other ligands or ions coordinated to the metal atom can be replaced by the counter-reactant. The organometallic precursors include those having the following chemical formula: M a R b L c (Chemical Formula 1) wherein: M is an element having a high patterned radiation absorption cross-section; R is an alkyl group, such as C n H 2n+1 , where preferably n≥2; L is a ligand, ion, or other group that is reactive with the counter-reactant; a≥1; b≥1; and c≥1.

[0049] In various embodiments, M has an atomic absorption cross-section equal to or greater than 1×10 7 cm 2 / mol. For example, M can be selected from the group consisting of tin, hafnium, tellurium, bismuth, indium, antimony, iodine, germanium, and combinations thereof. In some embodiments, M is tin. R can be fluorinated, such as having the chemical formula C n F x H (2n+1) . In various embodiments, R has at least one β-hydrogen or β-fluorine. For example, R can be selected from the group consisting of ethyl, isopropyl, n-propyl, tert-butyl, isobutyl, n-butyl, sec-butyl, n-pentyl, isopentyl, tert-pentyl, sec-pentyl, and mixtures thereof. L can be any group that is easily replaced by the counter-reactant to produce an M-OH group, such as a group selected from the group consisting of amines (e.g., dialkylamino, monoalkylamino), alkoxy groups, carboxylates, halogens, and mixtures thereof.

[0050] The organometallic precursor can be any one of a variety of candidate metal-organic precursors. For example, when M is tin, such precursors include tert-butyltris(dimethylamino)tin, isobutyltris(dimethylamino)tin, n-butyltris(dimethylamino)tin, sec-butyltris(dimethylamino)tin, isopropyl(tris)dimethylaminotin, n-propyltris(dimethylamino)tin, ethyltris(dimethylamino)tin, and similar alkyl(tris)(tert-butoxy)tin compounds such as tert-butyltris(tert-butoxy)tin. In some embodiments, the organometallic precursor is partially fluorinated.

[0051] The corresponding reactant has the ability to react with a substitution reactive group, ligand, or ion (e.g., L in Chemical Formula 1 above) to link at least two metal atoms via chemical bonding. The corresponding reactant can include water, peroxide (e.g., hydrogen peroxide), di- or polyols, fluorinated di- or polyols, fluorinated ethylene glycol, and other sources of hydroxyl groups. In various embodiments, the corresponding reactant reacts with the organometallic precursor by forming an oxygen bridge between adjacent metal atoms. Other possible corresponding reactants include hydrogen sulfide and disulfide hydrogen that can crosslink metal atoms via a sulfur bridge.

[0052] In addition to the organometallic precursor and the corresponding reactant, the film can further include optional materials to modify the chemical or physical properties of the film, such as modifying the sensitivity of the film to EUV or increasing the etch resistance. Such optional materials can be introduced, for example, by doping during gas phase formation, either before deposition on the semiconductor substrate or after deposition of the film (or both). In some embodiments, a mild remote H 2 plasma can be introduced to replace some of the Sn-L bonds with Sn-H, which can increase the reactivity of the resist under EUV.

[0053] In various embodiments, those gas deposition apparatuses and processes well known in the art are used to fabricate and deposit an EUV-patternable film on a semiconductor substrate. In such processes, the polymeric organometallic material is formed in the gas phase or in situ on the surface of the semiconductor substrate. Suitable processes include, for example, chemical vapor deposition (CVD), atomic layer deposition (ALD), and ALD with a CVD portion, such as a discontinuous ALD-like process in which the metal precursor and the corresponding reactant are independent in time or space.

[0054] Generally, the method includes mixing a vapor stream of an organometallic precursor with a vapor stream of a corresponding reactant to form a polymerized organometallic material; and depositing the organometallic material on the surface of a semiconductor substrate. In some embodiments, more than one organometallic precursor is included in the vapor stream. In some embodiments, more than one corresponding reactant is included in the vapor stream. Those skilled in the art will understand that in a substantially continuous process, the mixing and deposition aspects of the process can occur simultaneously.

[0055] In an exemplary continuous CVD process, two or more gas streams from sources of an organometallic precursor and a corresponding reactant located in separate inlet paths are directed to a deposition chamber of a CVD apparatus where they are mixed and react in the gas phase (e.g., via formation of metal-oxygen-metal bonds) to form an agglomerated polymeric material. The gas streams can be introduced, for example, using separate injection ports or a dual-plenum showerhead. The apparatus is configured such that the gas streams of the organometallic precursor and the corresponding reactant are mixed in the chamber such that the organometallic precursor can react with the corresponding reactant to form a polymerized organometallic material. Without being limited to the mechanism, function, or use of the present technology, it is believed that due to crosslinking of the metal atoms with the corresponding reactant, the product from this gas-phase reaction becomes heavier in molecular weight and then is condensed or otherwise deposited on the semiconductor substrate. In various embodiments, the steric hindrance of large alkyl groups prevents the formation of a densely packed network and results in a smooth, amorphous, and low-density film.

[0056] The CVD process is generally carried out at a reduced pressure, for example, from 10 mTorr to 10 Torr. In some embodiments, the process is carried out at 0.5 Torr to 2 Torr. In some embodiments, the temperature of the semiconductor substrate is equal to or lower than the temperature of the reactant stream. For example, the substrate temperature can be from 0 °C to 250 °C, or from room temperature (e.g., 23 °C) to 150 °C. In various processes, the deposition of the polymerized organometallic material on the substrate occurs at a rate inversely proportional to the surface temperature.

[0057] In some embodiments, wet deposition apparatuses and processes known in the art are used to fabricate and deposit an EUV-patternable film on a semiconductor substrate. For example, an organometallic material is formed on the surface of the semiconductor substrate by spin coating.

[0058] The thickness of the EUV-patternable film formed on the surface of a semiconductor substrate can be varied according to surface characteristics, materials used, and processing conditions. In various embodiments, the film thickness can range from 0.5 nm to 100 nm and can be of sufficient thickness to absorb most of the EUV light under EUV patterning conditions. The EUV-patternable film will have the ability to provide an absorbance of equal to or greater than 30%, thereby significantly reducing the EUV photons available to reach the bottom of the EUV-patternable film. Compared to the bottom of the EUV-exposed film, the higher EUV absorbance causes more crosslinking and densification near the top of the EUV-exposed film. While insufficient crosslinking may cause the resist to be more prone to peeling or collapsing during wet development, this risk does not exist in dry development. A fully dry lithography process can promote more efficient use of EUV photons with a more opaque resist film. While using an EUV-patternable film with a higher overall absorbance can efficiently use EUV photons, it should be understood that in some cases the EUV-patternable film can be less than about 30%. In contrast, most other resist films have a maximum overall absorbance of less than 30% (e.g., 10% or less, or 5% or less) to fully expose the resist material located at the bottom of the resist film. In some embodiments, the film thickness is from 10 nm to 40 nm, or from 10 nm to 20 nm. Without being limited to the mechanisms, functions, or uses of the present disclosure, it is believed that the processes of the present disclosure have fewer restrictions on the surface attachment properties of the substrate than wet spin coating processes in the art and can thus be applied to a wide variety of substrates. Additionally, as described above, the deposited film can conform closely to surface features to provide an advantage in mask formation on a substrate (e.g., a substrate having underlying features) without "filling in" or otherwise planarizing such features.

[0059] At block 104, an optional cleaning process is performed to clean the backside and / or bevel edges of the semiconductor substrate. Cleaning of the backside and / or bevel edges may optionally etch the EUV resist film to evenly remove the film on the substrate backside and bevel edges with various degrees of oxidation or crosslinking. During the application of an EUV-patternable film by wet deposition processing or dry deposition processing, there may be some unintended resist material deposition on the substrate bevel edges and / or backside. Such unintended deposition may result in undesired particles that subsequently move to the top surface of the semiconductor substrate and become particle defects. In addition, such deposition on the bevel edges and backside may cause problems in downstream processing, including contamination of patterning (scanner) and development tools. Conventionally, such deposition on the bevel edges and backside is removed by wet cleaning techniques. For spin-coated photoresist materials, this process is referred to as edge bead removal (EBR) and is performed by introducing solvent flows from above and below the bevel edges while the substrate is rotating. The same process can be applied to soluble organotin oxide-based resists deposited by vapor deposition techniques.

[0060] Cleaning of the substrate bevel edges and / or backside can also be a dry cleaning process. In some embodiments, the dry cleaning process involves a vapor and / or plasma with one or more of the following gases: HBr, HCl, BCl 3 、SOCl 2 、Cl 2 、BBr 3 、H 2 、O 2 、PCl 3 、CH 4 、methanol, ammonia, formic acid, NF 3 、HF. In some embodiments, the dry cleaning process can use the same chemicals as the dry development process described herein. For example, the cleaning of the bevel edges and backside can use hydrogen halide development chemicals. For the cleaning process of the backside and bevel edges, the vapor and / or plasma must be restricted to a specific area of the substrate to ensure that only the backside and bevel are removed without degrading any film on the front side of the substrate.

[0061] The processing conditions can be optimized for the cleaning of the bevel edges and backside. In some embodiments, higher temperature, higher pressure, and / or higher reactant flow rates can result in an increased etch rate. Suitable processing conditions for dry bevel edge and backside cleaning can be: a reactant flow rate of 100 - 10000 sccm (e.g., 500 sccm of HCl, HBr, HI, or H 2 and Cl 2 or Br 2 、BCl 3 or H 2)、a temperature from 20°C to 140°C (e.g., 80°C), a pressure from 20 - 1000 mTorr (e.g., 100 mTorr), a plasma power from 0 to 500 W at a high frequency (e.g., 13.56 MHz), and a time of about 10 to 20 seconds, depending on the photoresist film and composition and properties. It should be understood that although these conditions are suitable for some processing reactors, such as the Kiyo etch tool available from Lam Research Corporation, Fremont, CA, various processing conditions can be used depending on the performance of the processing reactor.

[0062] For example, when the original photoresist is damaged or has other defects, the dry cleaning operation can alternatively be extended to completely remove the photoresist or "reprocess" the photoresist, where the applied EUV resist is removed and the semiconductor substrate is prepared to apply the photoresist again. The reprocessing of the photoresist should be done without damaging the underlying semiconductor substrate, so oxygen-based etching should be avoided. Alternatively, variants of the halide-containing chemicals described herein can be used. It should be understood that the reprocessing operation of the photoresist can be applied at any stage during the process 100. Thus, the reprocessing operation of the photoresist can be applied after depositing the photoresist, after cleaning the bevel edges and the backside, after PAB processing, after EUV exposure, after PEB processing, or after development. In some embodiments, the reprocessing of the photoresist can be performed for non-selective removal of the exposed and unexposed areas of the photoresist, but selective to the underlying layer.

[0063] In some embodiments, the reprocessing treatment of the photoresist involves a vapor and / or plasma having one or more of the following gases: HBr, HCl, HI, BCl 3 、Cl 2 、BBr 3 、H 2 、PCl 3 、CH 4 、methanol, ammonia, formic acid, NF 3 、HF. In some embodiments, the reprocessing treatment of the photoresist can use the same chemicals as the dry development treatment described herein. For example, the reprocessing of the photoresist can use hydrogen halide developing chemicals.

[0064] The processing conditions can be optimized for the reprocessing of the photoresist. In some embodiments, higher temperature, higher pressure, and / or higher reactant flow rate can result in an increased etching rate. Depending on the photoresist film and composition and properties, suitable processing conditions for the reprocessing of the photoresist can be: a reactant flow rate of 100 - 500 sccm (e.g., 500 sccm of HCl, HBr, HI, BCl3 or H 2 and Cl 2 or Br 2 ) a temperature of 20 to 140 °C (e.g., 80 °C), a pressure of 20 - 1000 mTorr (e.g., 300 mTorr), a plasma power of 300 to 800 W (e.g., 500 W) at a high frequency (e.g., 13.56 MHz), a wafer bias of 0 to 200 V b and a time of about 20 seconds to 3 minutes sufficient to completely remove the EUV resist. It should be understood that although these conditions are suitable for some processing reactors, such as the Kiyo etch tool available from Lam Research Corporation, Fremont, CA, various processing conditions may be used depending on the performance of the processing reactor.

[0065] At block 106 of process 100, an optional post - application bake (PAB) is performed after deposition of the EUV - patterning film and before EUV exposure. The PAB process may involve a combination of heat treatment, chemical exposure, and moisture to increase the EUV sensitivity of the EUV - patterning film, thereby reducing the EUV dose used to develop the pattern in the EUV - patterning film. The temperature of the PAB process can be adjusted and optimized to increase the sensitivity of the EUV - patterning film. For example, the processing temperature can be between about 90 °C and about 200 °C, or between about 150 °C and about 190 °C. In some embodiments, the PAB process can be performed at a pressure between atmospheric pressure and vacuum and for a processing duration of about 1 to 15 minutes (e.g., about 2 minutes). In some embodiments, the PAB process can be performed at a temperature between about 100 °C and 200 °C for about 1 minute to 2 minutes.

[0066] At block 108 of process 100, the metal - containing EUV resist film is exposed to EUV radiation to create a pattern. Generally, the EUV exposure causes a change in the chemical composition and cross - linking in the metal - containing EUV resist film, thereby forming an etch - selectivity contrast that can be utilized in subsequent development.

[0067] Next, typically under relatively high vacuum, the region of the metal-containing EUV resist film can be patterned by exposing it to EUV light. EUV apparatuses and imaging methods useful herein include methods well known in the art. In particular, as described above, exposed regions having altered physical or chemical properties of the film are formed relative to unexposed regions via EUV patterning. For example, in the exposed regions, cleavage of metal-carbon bonds can occur, e.g., via β-hydrogen elimination, leaving a reactive and usable metal hydride functionality that can be converted to hydroxides and cross-linked metal oxide groups via metal-oxygen bridges during a subsequent post-exposure bake (PEB) step. This process can be used to form a chemical contrast for development as a negative tone resist. Generally, a larger amount of β-hydrogen in the alkyl group results in a more sensitive film. This can also be interpreted as weaker Sn-C bonding with more branching. After exposure, the metal-containing EUV resist film can be baked to form additional cross-linking of the metal oxide film. The property differences between the exposed and unexposed regions can be exploited in subsequent processing to dissolve the unexposed regions or to deposit materials on the exposed regions. For example, dry methods can be used to develop the pattern to form a mask containing metal oxides.

[0068] In particular, in various embodiments, especially when the exposure is performed using EUV under vacuum, in the exposed regions of the imaging layer, the terminal hydrocarbon tin oxide present on the surface is converted to terminal hydrogen tin oxide. However, moving the exposed imaging layer from vacuum into air, or controlled introduction of oxygen, ozone, H 2 O 2 , or water can cause oxidation of the Sn-H on the surface to Sn-OH. The property differences between the exposed and unexposed regions can be exploited in subsequent processing, for example, by reacting one or more reactants with the irradiated region, the non-irradiated region, or both, to selectively add or remove material from the imaging layer.

[0069] Not limited to the mechanisms, functions, or applications of the present technology, for example, EUV exposure with a dose from 10 mJ / cm 2 to 100 mJ / cm 2 results in cleavage of the Sn-C bond, thereby causing a reduction in the alkyl substituent, alleviating steric hindrance, and causing disintegration of the low-density film. In addition, the reactive metal-H bonds generated in the β-hydrogen elimination reaction can react with neighboring reactive groups (e.g., hydroxyl groups in the film), causing further cross-linking and densification and forming a chemical contrast between the exposed and unexposed regions.

[0070] After exposing a metal-containing EUV resist film to EUV light, a photo-patterned metal-containing EUV resist is provided. The photo-patterned metal-containing EUV resist includes EUV-exposed and unexposed regions.

[0071] At block 110 of process 100, an optional post-exposure bake (PEB) is performed to further enhance the contrast in the etch selectivity of the photo-patterned metal-containing EUV resist. The photo-patterned metal-containing EUV resist can be heat-treated in the presence of various chemicals to promote crosslinking of the EUV-exposed regions, or simply baked on a hotplate in ambient air, for example, between 150 °C and 250 °C for between 1 and 5 minutes (e.g., 2 minutes at 190 °C).

[0072] In various embodiments, the bake strategy involves carefully controlling the bake environment, the introduction of reactive gases, and / or carefully controlling the ramp rate of the bake temperature. Examples of useful reactive gases include, for example, air, H 2 O, H 2 O 2 vapor, CO 2 2, CO, O 2 2, O 3 3, CH 4 4, CH 3 3OH, N 2 2, H 2 2, NH 3 3, N 2 2O, NO, alcohols, acetylacetone, formic acid, Ar, He, or mixtures thereof. The PEB process is designed to (1) drive the complete evaporation of organic fragments generated during EUV exposure, and (2) oxidize any Sn-H, Sn-Sn, or Sn radical species generated by EUV exposure to metal hydroxides, and (3) promote crosslinking between adjacent Sn-OH groups to form a more tightly crosslinked SnO 2Network. The baking temperature is carefully selected to achieve optimal EUV lithography performance. Too low a PEB temperature will result in insufficient crosslinking and thus lower chemical contrast for development at a given dose. Too high a PEB temperature will also have adverse effects, including severe oxidation and film shrinkage in the unexposed areas (in this example, the areas are removed by development of the patterned film to form the mask), and undesired interdiffusion at the interface between the photo-patterned metal-containing EUV resist and the underlying layer, both of which will result in a reduction in chemical contrast and an increase in defect density due to insoluble residues. The PEB treatment temperature can be between about 100 °C and about 300 °C, between about 170 °C and about 290 °C, or about 200 °C and about 240 °C. In some embodiments, the PEB treatment can be carried out at a pressure between atmospheric pressure and vacuum and with a treatment duration of about 1 to 15 minutes (e.g., about 2 minutes). In some embodiments, the PEB heat treatment can be repeated to further increase the etch selectivity.

[0073] In block 112 of process 100, the photo-patterned metal-containing EUV resist is developed to form a resist mask. In various embodiments, the exposed areas (positive tone) or the unexposed areas (negative tone) are removed. In some embodiments, the development can include selective deposition on the exposed or unexposed areas of the photo-patterned metal-containing EUV resist and then an etching operation. In various embodiments, these processes can be dry processes or wet processes. In some embodiments, the development can be completed without igniting a plasma. Alternatively, the development can be completed by activating hydrogen and halides (e.g., H 2 and Cl 2 and / or Br 2 ) fluxes in a remote plasma source or by exposure to remote UV radiation. The photoresist for development can include an element selected from the group consisting of: tin, hafnium, tellurium, bismuth, indium, antimony, iodine, and germanium. The element can have a high patterned radiation absorption cross-section. In some embodiments, the element can have a high EUV absorption cross-section. In some embodiments, the metal-containing EUV resist can have an overall absorption rate greater than 30%. In a fully dry lithography process, this provides a more efficient use of EUV photons, enabling the development of thicker and more EUV-opaque photoresists.

[0074] Examples of the development process involve subjecting an EUV-sensitive photoresist film containing organotin oxide (e.g., 10 - 30 nm thick, e.g., 20 nm) to an EUV exposure dose and post-exposure bake, and then developing. The photoresist film can be deposited, for example, based on the gas-phase reaction of an organotin precursor (e.g., isopropyl(tris)(dimethylamino)tin) and water vapor, or can be a spin-coated film including tin clusters in an organic matrix.

[0075] The patterned metal-containing EUV resist can be developed by exposure to a developing chemical, where the developing chemical is a halide-containing chemical. In some embodiments, the developing chemical includes hydrogen and a halide, such as a hydrogen halide (e.g., HBr or HCl), or hydrogen and a halogen gas (e.g., H 2 and Cl 2 ). In some embodiments, the developing chemical includes a hydrogen halide, hydrogen and a halogen gas, boron trichloride, or a combination thereof. The development of the EUV resist can be accomplished by wet development using a halide-containing chemical or dry development using a hydrogen halide-containing chemical. In embodiments where wet development is used to develop the EUV resist, the wet development can be combined with other wet processing operations, such as wet deposition (e.g., spin coating deposition) of the metal-containing EUV resist film. Alternatively, the wet development can be combined with other dry processing operations, such as chemical vapor deposition (CVD) of the metal-containing EUV resist film. In embodiments where dry development is used to develop the EUV resist, the dry development can be combined with other dry processing operations, such as dry deposition (e.g., CVD) of the metal-containing EUV resist film. In an alternative embodiment where dry development is used to develop the EUV resist, the dry development can be combined with other wet processing operations, such as wet deposition (e.g., spin coating deposition) of the metal-containing EUV resist film.

[0076] In some embodiments, the processing of the semiconductor substrate can incorporate all dry steps, which include film formation by chemical vapor deposition, EUV lithography patterning, and dry development. In fact, each of operations 102-112 in process 100 can be a dry processing operation. Such processing operations can avoid the material and production costs associated with wet processing operations (e.g., wet development). Dry processing can provide more adjustability and improve further control of critical dimensions (CD) and the removal of residues. Wet processing typically involves moisture and / or oxygen, which are more likely to cause residue formation. Wet development is limited by solubility and cluster size, whereas dry development is not limited by solubility and cluster size. Wet development is more likely to cause problems such as pattern collapse and peeling, while dry development avoids these problems. In addition, using all-dry processing operations can facilitate integration within interconnected vacuum processing chambers without exposure to ambient air or trace contaminants contained therein and without being contaminated by ambient air or trace contaminants contained therein. For example, PEB heat treatment (during which the exposed areas are further crosslinked) can be performed in the same chamber as development; however, it should be understood that the PEB heat treatment can be performed in another chamber.

[0077] The development process can be completed by transporting the developer chemicals in a liquid or gas phase. In some embodiments, the dry development process can be completed by using a mild plasma (high pressure, low power) or heat treatment while flowing a dry developer chemical containing hydrogen halide (e.g., HF, HCl, HBr, or HI). For example, dry development can be completed in a heat treatment using a dry developer chemical (e.g., HCl or HBr). In some embodiments, the hydrogen halide chemical can rapidly remove the unexposed material, leaving a pattern of the exposed film, which can be transferred to the underlying layer by a plasma-based etching process (e.g., a known etching process).

[0078] In the heat development process, the substrate is exposed to a developer chemical (e.g., a Lewis acid) in a processing chamber (e.g., an oven). In some embodiments, a vacuum line is coupled to the processing chamber for controlling the pressure, and a developer chemical line can be coupled to the processing chamber for transporting the developer chemical into the processing chamber. The processing chamber can include one or more heaters for controlling the temperature, such as coupling the heater to the substrate support within the processing chamber for controlling the substrate temperature. In some embodiments, a corrosion-resistant film, such as an organic polymer or an inorganic coating, can be coated inside the chamber. One such coating is polytetrafluoroethylene (PTFE), such as Teflon 1M. Such materials can be used in the heat treatment of the present disclosure without the risk of being removed by plasma exposure.

[0079] In the thermal development process, the photo-patterned metal-containing EUV resist is exposed to a developing chemical at a temperature that is optimized for the etch selectivity between the exposed and unexposed regions. Lower temperatures may increase the contrast in etch selectivity, while higher temperatures may decrease the contrast in etch selectivity. In some embodiments, the temperature can be between about -60 °C and about 120 °C, between about -20 °C and about 60 °C, or between about -20 °C and about 20 °C, for example about -10 °C. The chamber pressure can be adjusted, and the chamber pressure can affect the etch selectivity between the exposed and unexposed regions during development. In some embodiments, the chamber pressure can be relatively low and without dilution, where the chamber pressure can be between about 0.1 mTorr and about 300 mTorr, between about 0.2 mTorr and about 100 mTorr, or between about 0.5 mTorr and about 50 mTorr. In some embodiments, the chamber pressure can be between about 20 mTorr and about 800 mTorr, or between about 20 mTorr and about 500 mTorr, for example about 300 mTorr. In some embodiments, the chamber pressure can be relatively high, with a high flow rate and with dilution, where the chamber pressure can be between about 100 mTorr and about 760 mTorr, or between about 200 mTorr and about 760 mTorr. The reactant flow rate can be adjusted, and the reactant flow rate can affect the etch selectivity between the exposed and unexposed regions during development. In some embodiments, the reactant flow rate can be between about 50 sccm and about 2000 sccm, between about 100 sccm and about 2000 sccm, or between about 100 sccm and about 1000 sccm, for example about 500 sccm. In the case of a high flow rate, the reactant flow rate can be between about 1 L and about 10 L. The duration of the exposure in the thermal development process can be adjusted. The duration of the exposure can depend particularly on factors such as how much photoresist needs to be removed, the developing chemical, the amount of crosslinking in the resist, and the composition and properties of the resist. In some embodiments, the duration of the exposure can be between about 5 seconds and about 5 minutes, between about 10 seconds and about 3 minutes, or between about 10 seconds and about 1 minute.

[0080] The thermal development process can expose the photo-patterned metal-containing EUV resist to certain halide-containing chemicals in the gas phase or liquid phase. In some embodiments, the developing chemicals include hydrogen halides, hydrogen and halogen gases, boron trichloride, organic halides, acyl halides, carbonyl halides, thionyl halides, or mixtures thereof. The hydrogen halides can include, but are not limited to, HF, HCl, HBr, and HI. For example, the hydrogen halide can be HCl, or HBr. The hydrogen and halogen gases can include, but are not limited to, those with F 2 , Cl 2, Br 2 , or I 2 mixed hydrogen gas (H 2 ). Boron trichloride (BCl 3 ) can be used in combination with any one of the aforementioned hydrogen halides or the hydrogen and halogen gases. The organic halides can include, but are not limited to, C x H y F z , C x H y Cl z , C x H y Br z , and C x H y I z , where x, y, and z are values equal to or greater than 0. The acyl halides can include, but are not limited to, CH 3 COF, CH 3 COCl, CH 3 COBr, and CH 3 COI. The carbonyl halides can include, but are not limited to, COF 2 , COCl 2 , COBr 2 , and COI 2 . The thionyl halides can include, but are not limited to, SOF 2 , SOCl 2 , SoBr 2 , and SOI 2 . In some embodiments, the halide-containing chemical can flow with or without an inert / carrier gas, such as He, Ne, Ar, Xe, and N 2 .

[0081] The thermal development process can be completed without plasma. By applying a non-plasma thermal method, productivity can be significantly improved because batch development of multiple wafers can be performed simultaneously in a low-cost thermal vacuum chamber / oven. However, in some embodiments, exposure to plasma can follow the thermal development process. The subsequent exposure to plasma can be carried out for desorption, residue removal, smoothing, or other processing operations.

[0082] In plasma development processing, the photo-patterned metal-containing EUV resist is exposed to development chemicals that include radicals / ions of one or more gases. The processing chamber used to process the semiconductor substrate can be a plasma generation chamber or can be coupled to a plasma generation chamber remote from the processing chamber. In some embodiments, dry development can be performed by remote plasma. The plasma generation chamber can be an inductively coupled plasma (ICP) reactor, a transformer coupled plasma (TCP) reactor, or a capacitively coupled plasma (CCP) reactor using equipment and techniques well known in the art, in particular. An electromagnetic field acts on the one or more gases to generate plasma in the plasma generation chamber. Ions and / or radicals from the remote plasma can interact with the photo-patterned metal-containing EUV resist. In some embodiments, a vacuum line is coupled to the processing chamber for controlling pressure, and a development chemical line can be coupled to the plasma generation chamber for delivering the one or more gases into the plasma generation chamber. The processing chamber can include one or more heaters for controlling temperature, such as a heater coupled to a substrate support within the processing chamber for controlling substrate temperature. In some embodiments, an anti-corrosion film, such as an organic polymer or an inorganic coating, can be coated inside the processing chamber. One such coating is polytetrafluoroethylene (PTFE), such as Teflon 1M. Such materials can be used in the heat treatments of the present disclosure without the risk of being removed by plasma exposure.

[0083] In plasma development processing, the optically patterned metal-containing EUV resist is exposed to a remote plasma under conditions optimized for etch selectivity between exposed and unexposed regions. The conditions can be optimized to produce a mild plasma, where the mild plasma can be characterized by high pressure and low power. The chamber pressure can be adjusted, where the chamber pressure can affect the etch selectivity between exposed and unexposed regions during development. In some embodiments, the chamber pressure can be equal to or greater than about 5 mTorr, or equal to or greater than about 15 mTorr. In some embodiments, the chamber pressure can be relatively high, with a high flow rate and dilution, where the chamber pressure can be between about 100 mTorr and about 760 mTorr, or between about 200 mTorr and about 760 mTorr. The RF power level can be adjusted, where the RF power can affect etch selectivity, roughness, residue removal, and other development characteristics. In some embodiments, the RF power can be equal to or less than about 1000 W, equal to or less than about 800 W, or equal to or less than about 500 W. The temperature can be adjusted, where the temperature can affect various aspects of development, such as etch selectivity. In some embodiments, the temperature can be between about -60 °C and about 300 °C, between about 0 °C and about 300 °C, or between about 30 °C and about 120 °C. The gas flow rate can be adjusted, where the gas flow rate can affect the etch selectivity between exposed and unexposed regions during development. In some embodiments, the gas flow rate is between about 50 sccm and about 2000 sccm, between about 100 sccm and about 2000 sccm, or between about 200 sccm and about 1000 sccm, such as about 500 sccm. The duration of exposure in the plasma development process can be adjusted. The duration of exposure can depend in particular on factors such as how much photoresist needs to be removed, the development chemicals, the amount of crosslinking in the resist, and the composition and properties of the photoresist. In some embodiments, the duration of exposure can be between about 1 second and about 50 minutes, between about 3 seconds and about 20 minutes, or between about 10 seconds and about 6 minutes.

[0084] Plasma development processing can expose the optically patterned metal-containing EUV resist to radicals of certain halide-containing gases. In some embodiments, the radicals are generated from a remote plasma source. For example, plasma development can expose the optically patterned metal-containing EUV resist to radicals of hydrogen and halide gases generated from the remote plasma source. In some embodiments, the halide-containing gas includes hydrogen halide, hydrogen and halogen gas, boron trichloride, organic halide, acyl halide, carbonyl halide, thionyl halide, or a mixture thereof. The hydrogen halide can include, but is not limited to, hydrogen fluoride (HF), hydrogen chloride (HCl), hydrogen bromide (HBr), and hydrogen iodide (HI). For example, the hydrogen halide can be HCl or HBr. The hydrogen and halogen gas can include, but is not limited to, hydrogen (H 2 ) mixed with fluorine gas (F 2 ), chlorine gas (Cl 2 ), bromine gas (Br 2 ), or iodine gas (I 2 ). The organic halide can include, but is not limited to, C x H y F z , C x H y Cl z , C x H y Br z , and C x H y I z , where x, y, and z are values equal to or greater than 0. The acyl halide can include, but is not limited to, CH 3 COF, CH 3 COCl, CH 3 COBr, and CH 3 COI. The carbonyl halide can include, but is not limited to, COF 2 , COCl 2 , COBr 2 , and COI 2 . The thionyl halide can include, but is not limited to, SOF 2 , SOCl 2 , SOBr 2 , and SOI 2 . In some embodiments, the halide-containing gas can flow with or without an inert / carrier gas such as He, Ne, Ar, Xe, and N 2 .

[0085] As an addition to or alternative to plasma activation, activation of one or more gases may be carried out in dry development by photoactivation. In some embodiments, photoactivation may be achieved by exposure to ultraviolet (UV) radiation. For example, the processing chamber may include a lamp configured to generate UV radiation, such as a UV lamp. Exposure of one or more gases to UV radiation may generate free radicals of the one or more gases, which may be used in the dry development of the photopatterned metal-containing EUV resist. The one or more gases may be exposed to UV radiation in a manner that does not expose the photopatterned photoresist to UV radiation. In other words, the photopatterned photoresist is outside the range of the UV lamp. Thus, the UV lamp may be remote from the processing chamber or arranged in a manner that avoids exposing the photopatterned photoresist to UV radiation.

[0086] It should be understood that the foregoing thermal development, plasma development, and photoactivation development methods may be combined with each other. These development methods may be applied simultaneously or sequentially. The development methods may be applied while flowing the dry development chemicals in a liquid or gas phase, where the dry development chemicals may include a compound of the chemical formula R x Z y where R = B, Al, Si, C, S, SO, with x > 0, and Z = Cl, H, Br, F, CH 4 and y > 0. The development may result in a positive or negative tone result, where the R x Z y substance selectively removes unexposed or exposed material, leaving the exposed or unexposed relative portion as a mask.

[0087] As described above, by controlling the processing conditions, the etch selectivity during dry development is adjustable, and the processing conditions are particularly, for example, adjustable processing conditions such as temperature, pressure, gas flow, gas composition, and plasma power. Adjusting the etch selectivity in a single step or multiple steps may achieve the desired patterning characteristics. In some embodiments, the etch selectivity during dry development is adjusted across one or more steps to affect the EUV resist profile. More specifically, by applying development chemicals with different etch selectivities during one or more steps, the amount of taper or re-entrant angle in the EUV resist profile may be controlled. Debloating, reprocessing of the photoresist, curing, smoothing, and cleaning operations may also be adjusted according to the adjustable etch selectivity.

[0088] Figures 2A - 2C Cross-sectional schematic views showing various processing stages of dry development according to some embodiments. Figures 2A - 2C The example shown illustrates negative tone dry development. AsFigure 2A As shown, the wafer 200 includes a substrate 202 and a substrate layer 204 to be etched. In some embodiments, the substrate layer 204 includes an ashing-capable hard mask (e.g., spin-on carbon, SoC) or other materials such as silicon, silicon oxide, silicon nitride, silicon carbide, etc. In some embodiments, the substrate layer 204 can be a layer stack disposed on the substrate 202. The wafer 200 also includes a photo-patterned metal-containing EUV resist film 206. For example, the photo-patterned metal-containing EUV resist film 206 can be an organometallic layer disposed above the substrate layer 204 to be etched. The photo-patterned metal-containing EUV resist film 206 can have a thickness between about 5 nm and about 50 nm, or between about 10 nm and about 30 nm. After photo-patterning in an EUV scanner and / or after the PEB process as described above, the photo-patterned metal-containing EUV resist film 206 can be provided in a processing chamber. The photo-patterned metal-containing EUV resist film 206 includes a non-EUV-exposed region 206a and an EUV-exposed region 206b. As Figure 2B shown, the non-EUV-exposed region 206a of the photo-patterned metal-containing EUV resist film 206 can be removed in a dry development process by exposure to a flow of dry development chemicals without igniting a plasma. The dry development chemicals can include halide-containing chemicals such as hydrogen halide or hydrogen and halogen gases. After development by removing the non-EUV-exposed region 206a, a resist mask 208 is formed. Subsequently, the substrate layer 204 to be etched can be etched using the resist mask 208 to provide Figure 2C the structure depicted in

[0089] Figure 3 An exemplary dry development mechanism according to some embodiments for the chemical reaction of HBr with the exposed and unexposed portions of an EUV resist. Figure 3 Possible dry development mechanisms are illustrated, however, it should be understood that the present disclosure is not limited to any particular mechanism, function, theory, or use. The organometallic oxide film can have a tetrahedral coordination structure. The exposed region has a higher degree of Sn-O-Sn crosslinking, resulting in a higher density and a lower / slower reactivity to HBr or HCl. The unexposed region exhibits a lower density due to the presence of large alkyl substituents that hinder the access path and the condensation of Sn-OH groups. In the unexposed region, the hydrogen halide more readily protonates the more "basic" and accessible oxygen lone pairs characteristic of the organotin oxide hydroxide with a more tetrahedral coordination. Volatile by-products of RSnX3 (where X = Cl or Br) can be rapidly produced and removed from the unexposed region. In Figure 3In this process, HBr selectively protonates the oxygen lone pair electrons to form a volatile by-product of R-Sn-Br. Water is also a by-product. Removing water can increase the reaction rate. When the alkyl group is isopropyl, at typical EUV patterning doses, at least two out of every three isopropyl groups are removed, such that after the PEB step, the exposed area condenses to form a higher density SnO 2 -like material, thereby exhibiting a lower reactivity with hydrogen halide due to the more hexacoordinate tin structure in which the accessibility of oxygen atoms is lower, resulting in a slower reactivity with hydrogen halide. In Figure 3 this process, the exposed area experiences a significant decrease in the dry etching rate, which is related to the reduction of isopropyl groups, to allow condensation into a material with more / most oxygen atoms bonded to three (instead of two) tin atoms, thereby significantly reducing the reaction rate with HBr or HCl.

[0090] In some cases, there may be residues or residues after development. The residues may be due to the slower etching components in a more heterogeneous EUV resist formulation (including those applied by spin coating techniques). Such residues may contain a high metal concentration, which may be problematic during subsequent pattern transfer.

[0091] Additionally or alternatively, after development, roughness may form on the sidewalls of the etched features in the developed pattern. Some of these can be attributed to the randomness of light or a non-optimal Gaussian distribution, resulting in partially or fully exposed material in areas where the photoresist should have remained unexposed, and vice versa.

[0092] In some embodiments, dry development can be achieved by a residue removal / smoothing operation. In some embodiments, the residue removal and smoothing operation can be an inert gas plasma desorption operation. For example, the inert gas plasma desorption operation can be a helium plasma desorption operation. The inert gas plasma desorption operation can be performed after dry development or in a cycle with dry development.

[0093] Figure 4A A cross-sectional schematic diagram showing dry development without applying an inert gas plasma according to some embodiments. The metal-containing EUV resist film patterned by light includes exposed and unexposed areas. As Figure 4A shown, metal oxides (e.g., SnO xParticles or clusters of can occupy the unexposed area. As dry development proceeds, the clusters of the metal oxide become more concentrated. The clusters of the metal oxide are generally difficult to remove. Development will be selective for the removal of the organic material. After removing the unexposed area, the clusters of the metal oxide may remain on the surface of the substrate as residues. The metal oxide clusters remaining on the sidewalls of the exposed area may cause roughness.

[0094] Figure 4B A cross-sectional schematic diagram showing dry development in the case of circulating an inert gas plasma to remove residues according to some embodiments. The first stage involves dry development to remove most of the unexposed area of the photopatterned metal-containing EUV resist film. Dry development chemicals can include, for example, HBr. The "most" can mean at least greater than 70% by volume of the unexposed area, greater than 80% by volume of the unexposed area, or greater than 90% by volume of the unexposed area. Clusters of the metal oxide concentrate at the surface of the remaining unexposed area of the EUV resist film. The second stage involves applying an inert gas plasma (e.g., a helium plasma) with low power and high ion energy for a short duration. The helium plasma removes the clusters of the metal oxide. In addition, the helium plasma removes the clusters from the sidewalls and smoothes the sidewalls. Helium plasma treatment can also be used to assist in hardening or curing the patterned EUV resist film to form a tighter metal oxide-like hard mask. After the helium plasma treatment, a less selective dry etching step can be used to remove any residues remaining in the unexposed area of the EUV resist film.

[0095] In some embodiments, dry development can be cycled with helium plasma treatment one or more times until the unexposed area of the EUV resist film is removed. To enhance the effect, helium plasma residue removal / smoothing can be cycled with dry development (as described above). In this way, for example, most of the organic components of the unexposed area of the pattern are removed by dry development, and then a short helium plasma operation can remove some of the concentrated metal at the surface to open a channel to the remaining underlying organic material, so that the underlying organic material can then be removed in subsequent dry development operations / cycles. Another helium plasma cycle can be used to remove any remaining metal to leave a clean and smooth feature surface. The cycles can continue until all, or substantially all, of the residues and roughness residues are removed to leave a clean and smooth feature surface.

[0096] The processing conditions for the residue removal and smoothing operations can be controlled during or after development. In some embodiments, the reaction gas flow rate can be between about 50 sccm and about 1000 sccm, or between about 100 sccm and about 500 sccm, such as He at about 500 sccm. In some embodiments, the temperature can be between about -60 °C and about 120 °C, between about -20 °C and about 60 °C, or between about 20 °C and about 40 °C, such as about 20 °C. In some embodiments, the chamber pressure can be between about 1 mTorr and about 300 mTorr, between about 5 mTorr and about 100 mTorr, between about 5 mTorr and about 20 mTorr, such as about 10 mTorr. The plasma power can be relatively low with high ion energy. In some embodiments, the plasma power can be between about 50 W and about 1000 W, between about 100 W and about 500 W, or between about 100 W and about 300 W, such as about 300 W. In some embodiments, the wafer bias is between about 10 V and about 500 V, between about 50 V and about 300 V, such as about 200 V. A high RF frequency can be used to generate the plasma. In some embodiments, the RF frequency is 13.56 MHz. The duration of exposure to the inert gas plasma can be relatively short to avoid overexposure to UV radiation during plasma exposure. In some embodiments, the duration of exposure is between about 0.5 second and about 5 seconds, between about 1 second and about 3 seconds, such as about 2 seconds.

[0097] The inert gas plasma treatment for removing unexposed resist residues and cleaning can have the incidental benefit of curing the exposed photoresist to harden it, thereby strengthening its hard mask function in subsequent operations for etching the underlying substrate. This resist hardening is achieved by exposing the EUV-exposed resist to the UV radiation generated by the inert gas plasma, and with the bias off, this resist hardening can continue after the residue removal / smoothing is completed. If residue removal / smoothing is not needed or not performed, inert gas plasma curing can be alternatively performed.

[0098] In some embodiments, inert gas plasma desorption for residue removal and smoothing can be used in conjunction with wet development processing. Wet development has very high selectivity and has been shown to exhibit distinct on / off behavior, resulting in the inability of wet development processing to remove areas exposed by "stray" EUV photons. Subsequently, residual residues are left after wet development processing, resulting in residues, as well as high line edge and width roughness. Interestingly, due to the tunability of dry development processing (where the etch rate and selectivity can be adjusted based on multiple knobs such as time, temperature, pressure, gas / flow), inert gas plasma and / or dry development can be further applied to desorb and smooth the metal-containing resist lines by removing these partially exposed residues.

[0099] Figure 5 A graph is shown that compares the etch rates between the exposed and unexposed portions of an EUV resist using a helium plasma during dry development. The EUV resist can be an organotin oxide EUV resist. The unexposed portion is etched at a faster rate than the exposed portion. However, as dry development with HBr proceeds, the etch rate slows down. Without being limited to any theory, it is believed that the presence of tin oxide particles / clusters slows down the etch rate. By applying helium desorption, more of the unexposed portion of the EUV resist can be etched.

[0100] Figure 6A vs. 6B SEM images are shown comparing wet development and dry development with respect to line collapse. In Figure 6A , a photo-patterned metal-containing EUV resist is exposed to wet development chemicals such as organic solvents. After the liquid drying step, some of the patterned lines are observed to collapse. This may be partially attributed to the surface tension effect from capillary forces. In Figure 6B , a photo-patterned metal-containing EUV resist is exposed to dry development chemicals such as hydrogen halide gas. Dry development prevents the patterned lines from collapsing or peeling off through a gas-phase reaction without a liquid drying step.

[0101] Figure 7A vs. 7B SEM images are shown comparing wet development and dry development in terms of controlling roughness and critical dimension (CD). In Figure 7A vs. 7B , an organotin oxide film is deposited on an ashing-hard mask. The organotin oxide film is exposed to EUV at different doses and different focus depths. In Figure 7A , the organotin oxide film is subjected to wet development, while in Figure 7BDry development is carried out in []. After wet development, the organotin oxide resist mask has a square profile, while after dry development, the organotin oxide resist mask has a tapered profile. In wet development, line bridging is observed after pattern transfer, while no line bridging is observed after pattern transfer in dry development. Due to surface tension during solvent drying after wet development, line collapse and wiggling occur at smaller line widths or lower doses. After dry development, no line collapse or wiggling occurs at smaller line widths or lower doses. With dry development, a larger process window can be used for a wider range of doses and focus.

[0102] Figure 8 SEM images comparing wet development and dry development in terms of residue after hard mask opening are shown. As Figure 8 shown, more residue is observed after wet development than after dry development. Without being limited to any theory, dry development uses gas chemicals that do not contain an oxygen or moisture oxidation source, preventing metal oxide crosslinking of the unexposed EUV resist and thus preventing residue formation. Residue is similar to the exposed EUV resist with metal oxide crosslinking. In Figure 8 , a residue removal and smoothing operation can be performed after wet development or dry development.

[0103] Figure 9A and 9B show multiple graphs that describe the effect of post-second-exposure baking on the selectivity of dry development at different pressures and temperatures. As Figure 9A shown, post-second-exposure baking exhibits improved etch selectivity. As Figure 9B shown, during dry development, the etch selectivity improves at lower temperatures. In addition, during dry development, the etch selectivity improves at lower pressures.

[0104] Figure 10 show multiple SEM images that illustrate the effect of pressure on the EUV resist profile. For dry development, pressure variation affects the EUV resist profile. Generally, higher pressures enable higher etch rates. However, lower pressures exhibit improved EUV resist profiles. Figure 10 The lower pressure in [] forms a straighter EUV resist profile.

[0105] Figure 11A and 11BShows SEM images of EUV resists at different line / space pitches and different thicknesses. The EUV resist mask was developed to have 32 nm pitch and 26 nm pitch. The film thickness before development was between 15 nm and 40 nm. For the 32 nm pitch, after development, the thickness of the EUV resist mask was in the range of 7.8 nm to 22.5 nm. No swing was observed. For the 26 nm pitch, after development, the thickness of the EUV resist mask was in the range of 7.9 nm to 22.2 nm. Some swing was observed for film thicknesses equal to or greater than 30 nm due to undercut at the bottom of the resist. Apparatus

[0106] The apparatus of the present disclosure is configured to develop EUV resists. The apparatus can be configured to perform other processing operations such as deposition, beveling, and backside cleaning, post-application bake, EUV scanning, post-exposure bake, photoresist rework, residue removal, smoothing, curing, and other operations. In some embodiments, the apparatus is configured to perform all dry operations. In some embodiments, the apparatus is configured to perform all wet operations. In some embodiments, the apparatus is configured to perform a combination of wet and dry operations. The apparatus can include a single-wafer chamber or multiple stations located within the same processing chamber. With multiple stations located within the same processing chamber, various processing operations such as those described in the present disclosure can be performed at different stations located within the same processing chamber. For example, PEB heat treatment can be performed at one station and development can be performed at another station.

[0107] An apparatus configured to develop EUV resists includes a processing chamber having a substrate support. The apparatus can include a vacuum line coupled to the processing chamber for controlling pressure and a developer chemical line coupled to the processing chamber for delivering developer chemicals. In some embodiments, the developer chemicals include a halide-containing gas or radicals of a halide-containing gas. In some embodiments, the processing chamber is a plasma generation chamber or is coupled to a plasma generation chamber operating as a remote plasma source. The plasma generation chamber can be an ICP, TCP, or CCP reactor. The apparatus can include one or more heaters for controlling temperature. Such heaters can be disposed within the processing chamber and / or within the substrate support.

[0108] In some embodiments, the interior of the processing chamber is coated with an anti-corrosion film such as a polymer or an inorganic coating. In one example, the interior of the processing chamber is coated with anodized aluminum oxide. In another example, the interior of the processing chamber is coated with yttrium oxide (Y 2 O 3 )).

[0109] In some embodiments, the processing chamber is made of an inexpensive material such as plastic. The processing chamber does not have to be made of metal or ceramic. The plastic material may be sufficient to withstand the halide-containing chemicals during development. A vacuum line and / or a development chemical line may be coupled to the plastic chamber.

[0110] In some embodiments, a substrate support may be used to process a substrate using a temperature profile member having radial and azimuthal components. The substrate support may include a plurality of independently controllable temperature control zones disposed near the substrate location above these temperature control zones. This enables one or more heaters located within the substrate support to control the temperature more precisely and locally. The temperature control zones may be arranged to define a pattern, such as a rectangular grid, a hexagonal grid, or other suitable pattern, for generating a desired temperature profile. In some embodiments, the temperature control zones may be spatially arranged in an electrostatic chuck to correct azimuthal non-uniformities or local CD non-uniformities.

[0111] In some embodiments, the apparatus may further include a showerhead for delivering one or more gases into the processing chamber. In some embodiments, the showerhead may supply a plurality of different gases to the reaction zone while largely keeping these gases isolated within the showerhead. The showerhead may include a plurality of gas chamber volumes. This enables isolation of chemicals such as precursor gases, carrier gases, development gases, and cleaning gases, among others.

[0112] Removing water or moisture from the processing chamber may accelerate the reaction of the photo-patterned metal-containing EUV resist with the development chemicals. In some embodiments, a cold trap may be coupled to the processing chamber for removing water vapor by-products. The cold trap may condense the water vapor by-products into a liquid or solid form.

[0113] In some embodiments, the apparatus may further include a UV source (e.g., a UV lamp) and / or an IR source (e.g., an IR lamp) for resist curing and dehalogenation. The UV source and / or the IR source may provide exposure to radiation to cure the EUV resist. Additionally or alternatively, the UV source may assist in the photoactivation of the development chemicals. Additionally or alternatively, the UV source may assist in removing halogens. Halogen residues may form on the semiconductor substrate or chamber surface and thus may be removed by UV exposure.

[0114] Figure 12 A schematic diagram of an embodiment of a processing station 1200 is depicted. The processing station 1200 has a processing chamber body 1202 for maintaining a low-pressure environment suitable for the embodiments of dry development, cleaning, reprocessing, residue removal, and planarization described above. A plurality of processing stations 1200 may be included in a common low-pressure processing tool environment. For example, Figure 13depicts an embodiment of a multi-station processing tool 1300, such as available from Lam Research Corporation (Fremont, CA). In some embodiments, one or more hardware parameters of the processing station 1200 (including those discussed in detail below) can be programmatically adjusted by one or more computer controllers 1250.

[0115] The processing station can be configured as a module in a cluster tool. Figure 15 depicts a semiconductor processing cluster tool architecture with vacuum integrated deposition and patterning modules, suitable for implementing the embodiments described herein. Such a cluster processing tool architecture can include a resist deposition, a resist exposure (EUV scanner), a resist development, and an etch module, as described above and below with reference to Figure 14 and 15 further described.

[0116] In some embodiments, some processing functions can be continuously performed in the same module, such as dry development and etching. Embodiments of the present disclosure relate to methods and apparatuses for receiving a wafer (including a light-patterned EUV resist thin film layer disposed on an etch layer or layer stack) into a dry development / etch chamber after optical patterning in an EUV scanner; dry developing the light-patterned EUV resist thin film layer; and then etching the underlying layer using the patterned EUV resist as a mask, as described herein.

[0117] Returning to Figure 12 , the processing station 1200 is in fluid communication with a reactant delivery system 1201a for delivering a processing gas to a distribution showerhead 1206. The reactant delivery system 1201a optionally includes a mixing vessel 1204 for mixing and / or conditioning the processing gas for delivery to the showerhead 1206. One or more mixing vessel inlet valves 1220 can control the introduction of the processing gas into the mixing vessel 1204. When plasma exposure is used, plasma can also be delivered to the showerhead 1206 or plasma can be generated in the processing station 1200. As described above, in at least some embodiments, non-plasma thermal exposure is advantageous.

[0118] Figure 12It includes an optional vaporization point 1203 for vaporizing the liquid reactants to be supplied to the mixing vessel 1204. In some embodiments, a liquid flow controller (LFC) may be provided upstream of the vaporization point 1203 to control the mass flow rate of the liquid for vaporization and delivery to the processing station 1200. For example, the LFC may include a thermal mass flowmeter (MFM) located downstream of the LFC. Subsequently, the plunger valve of the LFC can be adjusted in response to a feedback control signal provided by a proportional-integral-derivative (PID) controller (electrically connected to the MFM).

[0119] The showerhead 1206 distributes the processing gas towards the substrate 1212. In Figure 12 the illustrated embodiment, the substrate 1212 is located below the showerhead 1206 and is shown placed on the pedestal 1208. The showerhead 1206 can have any suitable shape and can have any suitable number and configuration of ports for distributing the processing gas to the substrate 1212.

[0120] In some embodiments, the pedestal 1208 can be raised or lowered to expose the substrate 1212 to the volume between the substrate 1212 and the showerhead 1206. It should be understood that in some embodiments, the pedestal height can be adjusted programmatically via a suitable computer controller 1250. In some embodiments, the showerhead 1206 can have multiple gas chamber volumes, along with multiple temperature control elements.

[0121] In certain embodiments, the temperature of the pedestal 1208 can be controlled by a heater 1210. In some embodiments, as in the disclosed embodiments, during non-plasma thermal exposure of the photopatterned resist to hydrogen halide dry developing chemicals (e.g., HBr or HCl), the pedestal 1208 can be heated to a temperature greater than 0 °C and up to 300 °C or higher, such as 50 to 120 °C, such as about 65 to 80 °C. In some embodiments, the heater 1210 of the pedestal 1208 can include multiple independently controllable temperature control zones.

[0122] Furthermore, in some embodiments, the pressure control for the processing station 1200 can be provided by a butterfly valve 1218. As shown in the Figure 12 embodiment, the butterfly valve 1218 regulates the vacuum provided by a downstream vacuum pump (not shown). However, in some embodiments, the pressure control for the processing station 1200 can also be adjusted by changing the flow rate of one or more gases introduced into the processing station 1200.

[0123] In some embodiments, the position of the showerhead 1206 can be adjusted relative to the susceptor 1208 to change the volume between the substrate 1212 and the showerhead 1206. Additionally, it should be understood that the vertical position of the susceptor 1208 and / or the showerhead 1206 can be changed by any suitable mechanism within the scope of the present disclosure. In some embodiments, the susceptor 1208 can include a rotational axis for orienting the substrate 1212. It should be understood that in some embodiments, one or more of these exemplary adjustments can be performed programmatically by one or more suitable computer controllers 1250.

[0124] When plasma can be used, such as in mild plasma-based dry development embodiments and / or in etching operations implemented in the same chamber, the showerhead 1206 and the susceptor 1208 are electrically connected to an RF power source 1214 and a matching network 1216 to provide power to the plasma. In some embodiments, the energy of the plasma can be controlled by controlling one or more of the pressure of the processing station, the concentration of the gas, the RF source power, the RF source frequency, and the plasma power pulse timing. For example, the RF power source 1214 and the matching network 1216 can operate at any suitable power to form a plasma having a composition of desired radical species. An example of a suitable power is up to about 500 W.

[0125] In some embodiments, instructions for the controller 1250 can be provided via input / output control (IOC) sequencing instructions. In one example, instructions for setting the conditions of a processing stage can be included in the corresponding recipe stage of a processing recipe. In certain cases, the processing recipe stages can be arranged in sequence such that all instructions for a processing stage are executed concurrently with that processing stage. In some embodiments, instructions for setting one or more reactor parameters can be included in a recipe stage. For example, instructions for setting the flow rate of a dry development chemical reactant gas (such as HBr or HCl), and time delay instructions for a recipe stage. In some embodiments, the controller 1250 can include any of the features of the system controller 1350 described below Figure 13 of.

[0126] As described above, one or more processing stations can be included in a multi-station processing tool. Figure 13A schematic view of an embodiment of a multi-station processing tool 1300 is shown, which has an inbound load lock 1302 and an outbound load lock 1304, one or both of which may include a remote plasma source. A robot 1306 at atmospheric pressure is configured to move wafers from a cassette loaded through a pod 1308 via an atmospheric port 1310 into the inbound load lock 1302. The wafer is placed by the robot 1306 on a pedestal 1312 in the inbound load lock 1302, the atmospheric port 1310 is closed, and the load lock is evacuated. When the inbound load lock 1302 includes a remote plasma source, the wafer may be exposed to remote plasma processing in the load lock to process the silicon nitride surface before being introduced into the processing chamber 1314. Additionally, the wafer may also be heated in the inbound load lock 1302, for example, to remove moisture and adsorbed gases. Next, a chamber transfer port 1316 leading to the processing chamber 1314 is opened, and another robot (not shown) places the wafer on a pedestal of the first station shown in the reactor in the reactor for processing. Although the embodiment depicted in Figure 13 includes a load lock, it should be understood that in some embodiments, the substrate may be directly introduced into the processing station.

[0127] The depicted processing chamber 1314 includes 4 processing stations, Figure 13 numbered 1 to 4 in the shown embodiment. Each station has a heated pedestal (shown as 1318 for station 1) and a gas line inlet. It should be understood that in some embodiments, each processing station may have different or multiple uses. For example, in some embodiments, the processing station may be switchable between a dry development and an etching processing mode. Additionally or alternatively, in some embodiments, the processing chamber 1314 may include a matching pair of one or more dry development and etching processing stations. Although the depicted processing chamber 1314 includes 4 stations, it should be understood that the processing chamber according to the present disclosure may have any suitable number of stations. For example, in some embodiments, the processing chamber may have 5 or more stations, while in other embodiments, the processing chamber may have 3 or fewer stations.

[0128] Figure 13 Some embodiments of a wafer handling system 1390 for transferring wafers within the processing chamber 1314 are depicted. In some embodiments, the wafer handling system 1390 may transfer wafers between various processing stations and / or between the processing stations and the load lock. It should be understood that any suitable wafer handling system may be employed. Non-limiting examples include a wafer turntable and a robot for handling wafers. Figure 13Also depicted is an implementation of a system controller 1350 that is employed to control the processing conditions and hardware states of a processing tool 1300. The system controller 1350 can include one or more memory devices 1356, one or more mass storage devices 1354, and one or more processors 1352. The processor 1352 can include a computer or CPU, analog and / or digital input / output connections, a stepper motor controller board, and the like.

[0129] In some implementations, the system controller 1350 controls all activities of the processing tool 1300. The system controller 1350 executes system control software 1358 stored in the mass storage device 1354, loaded into the memory device 1356, and executed by the processor 1352. Alternatively, the control logic can be hard-coded in the controller 1350. Application-specific integrated circuits, programmable logic devices (such as field-programmable gate arrays, or FPGAs), and the like can be used for these purposes. In the following discussion, whether "software" or "code" is used, functionally equivalent hard-coded logic can be substituted. The system control software 1358 can include instructions for controlling timing, gas mixing, gas flow rate, chamber and / or station pressure, chamber and / or station temperature, wafer temperature, target power level, RF power level, substrate pedestal, chuck, and / or pedestal position, and other parameters of a particular process performed by the processing tool 1300. The system control software 1358 can be configured in any suitable manner. For example, various processing tool component subroutines or control objects can be written to control the operation of the processing tool components for performing various processing tool processes. The system control software 1358 can be encoded in any suitable computer-readable programming language.

[0130] In some implementations, the system control software 1358 can include input / output control (IOC) sequencing instructions for controlling the various parameters described above. In some implementations, other computer software and / or programs stored in the mass storage device 1354 and / or the memory device 1356 and associated with the system controller 1350 can be employed. Examples of programs or program segments for this purpose include a substrate positioning program, a process gas control program, a pressure control program, a heater control program, and a plasma control program.

[0131] The substrate positioning program can include program code for a processing tool component that is used to load a substrate onto a pedestal 1318 and control the spacing between the substrate and other parts of the processing tool 1300.

[0132] The process gas control program may include code for controlling the composition of a halogen-containing gas (e.g., HBr or HCl gas as described herein) and the flow rate and optionally code for flowing the gas to one or more processing stations prior to deposition to stabilize the pressure in the processing station. The pressure control program may include code for controlling the pressure within the processing station by adjusting, for example, a throttle valve in the exhaust system of the processing station, the gas flow into the processing station, and the like.

[0133] The heater control program may include code for controlling the current flowing to a heating unit for heating a substrate. Alternatively, the heater control program may control the conveyance of a heat transfer gas (such as helium) toward the substrate.

[0134] The plasma control program may include code for setting the RF power level applied to a processing electrode within one or more processing stations according to the embodiments herein.

[0135] The pressure control program may include code for maintaining the pressure within the reaction chamber according to the embodiments herein.

[0136] In some embodiments, there may be a user interface associated with the system controller 1350. The user interface may include a display screen, a graphical software display of the apparatus and / or processing conditions, and user input devices such as a pointing device, a keyboard, a touch screen, a microphone, and the like.

[0137] In some embodiments, the parameters adjusted by the system controller 1350 relate to processing conditions. Non-limiting examples include process gas composition and flow rate, temperature, pressure, plasma conditions (e.g., RF bias power level), and the like. These parameters may be provided to the user in the form of a recipe, which may be input using the user interface.

[0138] Signals for monitoring the process may be provided by analog and / or digital input connections of the system controller 1350 from various process tool sensors. Signals for controlling the process may be output through the analog and digital output connections of the process tool 1300. Non-limiting examples of process tool sensors that may be monitored include mass flow controllers, pressure sensors (such as pressure gauges), thermocouples, and the like. Appropriately programmed feedback and control algorithms may be used with the data from these sensors to maintain the processing conditions.

[0139] The system controller 1350 may provide program instructions for performing the deposition process described above. The program instructions may control a variety of processing parameters such as DC power level, RF bias power level, pressure, temperature, and the like. The instructions may control these parameters to operate a dry development and / or etching process according to the various embodiments described in the present invention.

[0140] The system controller 1350 will typically include one or more memory devices and one or more processors configured to execute instructions to cause the apparatus to perform the methods described according to the disclosed embodiments. A machine-readable medium containing instructions for controlling processing operations according to the disclosed embodiments may be coupled to the system controller 1350.

[0141] In some embodiments, the system controller 1350 is part of a system, which may be part of the above-described embodiments. Such a system may include a semiconductor processing apparatus, which includes one or more processing tools, one or more processing chambers, one or more platforms for processing, and / or specific processing components (wafer chucks, gas flow systems, etc.). These systems may be integrated with electronics for controlling their operations before, during, and after processing semiconductor wafers or substrates. The electronics may be referred to as a "controller", which may control various elements or sub-components of one or more systems. Depending on the processing requirements and / or the type of system, the system controller 1350 may be programmed to control any of the processes disclosed herein, including controlling process gas delivery, temperature settings (e.g., heating and / or cooling), pressure settings, vacuum settings, power settings, radio frequency (RF) generator settings, RF matching circuit settings, frequency settings, flow rate settings, fluid delivery settings, position and operation settings, wafer transfer in and out of tools and other transfer tools, and / or load locks connected or interfaced to a specific system.

[0142] Broadly speaking, the system controller 1350 may be defined as an electronic device having various integrated circuits, logic, memory, and / or software that receives instructions, issues instructions, controls operations, enables cleaning operations, enables endpoint measurements, etc. The integrated circuits may include chips in the form of firmware that stores program instructions, digital signal processors (DSPs), chips defined as application specific integrated circuits (ASICs), and / or one or more microprocessors or microcontrollers that execute program instructions (e.g., software). The program instructions may be instructions transmitted to the system controller 1350 in various individual settings (or program files), which define operation parameters for performing specific processes on or for a semiconductor wafer or system. In some embodiments, the operation parameters may be part of a recipe defined by a process engineer for completing one or more processing steps during the preparation of one or more layers, materials, metals, oxides, silicon, silicon dioxide, surfaces, circuits, and / or dies of a wafer.

[0143] In some embodiments, system controller 1350 can be part of or coupled to a computer that is integrated with, coupled to, otherwise networked to the system, or a combination thereof. For example, system controller 1350 can be in the "cloud" or be all or part of a wafer fab host system, thereby allowing remote access to wafer processing. The computer can enable remote access to the system to monitor the current progress of manufacturing operations, examine the history of past manufacturing operations, examine trends or performance criteria for multiple manufacturing operations, change parameters of the current process, set processing steps to follow the current process or initiate a new process. In some embodiments, a remote computer (e.g., a server) can provide a process recipe to the system via a network, which can include a local network or the Internet. The remote computer can include a user interface that allows for the input or programming of parameters and / or settings, which are then transferred from the remote computer to the system. In some embodiments, system controller 1350 receives instructions in the form of data that specify parameters for each processing step to be performed during one or more operations. It should be understood that the parameters can be for the type of processing to be performed as well as the type of tool, and system controller 1350 is configured to connect to or control the type of tool. Thus, as described above, system controller 1350 can be distributed, for example, by including one or more discrete controllers that are connected together via a network and work towards a common goal (e.g., the processing and control described herein). An example of a distributed controller for these purposes can be one or more integrated circuits on a chamber that communicate with one or more remote integrated circuits (e.g., at the platform level or as part of a remote computer) that are combined to control in-chamber processing.

[0144] Under non-limiting conditions, an example system can include a plasma etch chamber or module, a deposition chamber or module, a spin clean chamber or module, a metal plating chamber or module, a cleaning chamber or module, a bevel edge etch chamber or module, a physical vapor deposition (PVD) chamber or module, a chemical vapor deposition (CVD) chamber or module, an ALD chamber or module, an atomic layer etch (ALE) chamber or module, an ion implantation chamber or module, an orbit chamber or module, an EUV lithography chamber (scanner) or module, a developing chamber or module, and any other semiconductor processing system that can be associated with or used in the preparation and / or manufacture of semiconductor wafers.

[0145] As described above, depending on the one or more processing steps to be performed by the tool, system controller 1350 can communicate with one or more other tool circuits or modules, other tool components, combined tools, other tool interfaces, adjacent tools, adjoining tools, tools located throughout the factory, a host, another controller, or tools used in material handling that transport a container of wafers between tool locations and / or load ports in a semiconductor manufacturing facility.

[0146] An inductively coupled plasma (ICP) reactor is now described. In certain embodiments, it can be applicable to etching operations, and the etching process is suitable for the implementation of certain embodiments. Although the ICP reactor is described herein, it should be understood that in some embodiments, a capacitively coupled plasma reactor can also be used.

[0147] Figure 14 A cross-sectional view of an inductively coupled plasma device 1400 is schematically shown, which is suitable for implementing certain embodiments or aspects of embodiments (such as dry development and / or etching). An example of such a device is manufactured by Lam Research Corp., Fremont, CA reactor. In other embodiments, other tools or tool types can be used to implement the solution, and the other tools or tool types have the functionality to perform the dry development and / or etching processes described herein.

[0148] The inductively coupled plasma device 1400 includes a total processing chamber structurally defined by a chamber wall 1401 and a window 1411. The chamber wall 1401 can be made of stainless steel, aluminum, or plastic. The window 1411 can be made of quartz or other dielectric materials. An optional internal plasma grid 1450 divides the total processing chamber into an upper sub-chamber 1402 and a lower sub-chamber 1403. In most embodiments, the plasma grid 1450 can be removed to utilize the chamber space formed by both the sub-chambers 1402 and 1403. A chuck 1417 is positioned in the lower sub-chamber 1403 near the bottom inner surface. The chuck 1417 is configured to receive and hold a semiconductor wafer 1419 on which etching and deposition processes are performed. The chuck 1417 can be an electrostatic chuck for supporting the wafer 1419 when the wafer 1419 is present. In some embodiments, an edge ring (not shown) surrounds the chuck 1417 and has an upper surface substantially in the same plane as the top surface of the wafer 1419 (when the wafer is present above the chuck 1417). The chuck 1417 also includes electrostatic electrodes for clamping and releasing the wafer. A filter and a DC clamp power source (not shown) can be provided for this purpose. Other control systems can also be provided for lifting the wafer 1419 away from the chuck 1417. The chuck 1417 can be charged with an RF power source 1423. The RF power source 1423 is connected to a matching circuit 1421 through a connection member 1427. The matching circuit 1421 is connected to the chuck 1417 through a connection member 1425. In this way, the RF power source 1423 is connected to the chuck 1417. In various embodiments, the bias power supply of the electrostatic chuck can be set to about 50V, or different bias power supplies can be set depending on the process performed according to the disclosed embodiments. For example, the bias power supply can be between about 20V and about 100V, or between about 30V and about 150V.

[0149] The component for plasma generation includes a coil 1433 located above the window 1411. In some embodiments, the coil is not used in the disclosed embodiments. The coil 1433 is made of a conductive material and includes at least one full turn. In Figure 14 the example of the coil 1433 shown includes three turns. The cross-section of the coil 1433 is shown by a symbol, and a coil with an "X" symbol indicates that the coil extends rotationally into the page, and conversely, a coil with a "●" symbol indicates that the coil extends rotationally out of the page. The component for plasma generation also includes an RF power supply 1441 configured to supply RF power to the coil 1433. Generally, the RF power supply 1441 is connected to a matching circuit 1439 through a connection member 14414. The matching circuit 1439 is connected to the coil 1433 through a connection member 1443. In this way, the RF power supply 1441 is connected to the coil 1433. An optional Faraday shield 1449a is positioned between the coil 1433 and the window 1411. The Faraday shield 1449a can be held in a spaced relationship relative to the coil 1433. In some embodiments, the Faraday shield 1449a is disposed directly above the window 1411. In some embodiments, the Faraday shield 1449b is between the window portion 1411 and the chuck 1417. In some embodiments, the Faraday shield 1449b does not maintain a spaced relationship with the coil 1433. For example, the Faraday shield 1449b can be directly below the window 1411 without a gap. Each of the coil 1433, the Faraday shield 1449a, and the window 1411 is configured to be substantially parallel to each other. The Faraday shield 1449a can prevent metal or other substances from depositing on the window 1411 of the processing chamber 1424.

[0150] The processing gas can flow into the processing chamber through one or more main gas inlets 1460 located in the upper sub-chamber 1402 and / or through one or more side gas inlets 1470. Similarly, although not explicitly shown, similar gas inlets can be used to supply the processing gas to the capacitively coupled plasma processing chamber. A vacuum pump, for example, a single-stage or two-stage dry mechanical pump and / or a turbomolecular pump 1440, can be used to evacuate the processing gas from the processing chamber 1424 and maintain the pressure inside the processing chamber 1400. For example, this vacuum pump can be used to evacuate the lower sub-chamber 1403 during an ALD purge operation. A valve-controlled conduit can be used to fluidly connect the vacuum pump to the processing chamber 1424 to selectively control the application of the vacuum environment provided by the vacuum pump. During the operation of the plasma processing, this can be performed using a closed-loop controlled flow restriction device such as a throttle valve (not shown) or a pendulum valve (not shown). Similarly, a vacuum pump and a valve that are controllably fluidly connected to the capacitively coupled plasma processing chamber can also be used.

[0151] During operation of the apparatus 1400, one or more processing gases may be supplied through gas inlets 1460 and / or 1470. In certain embodiments, the processing gas may be supplied only through the main gas inlet 1460 or only through the side gas inlet 1470. In some cases, the gas inlets shown in the figures may be replaced by more complex gas inlets, such as by one or more showerheads. The Faraday shield 1449 and / or optional grid 1450 may include internal channels and apertures through which the processing gas can be delivered to the interior of the chamber. One or both of the Faraday shield 1449 and optional grid 1450 may serve as a showerhead for delivering the processing gas. In some embodiments, a liquid evaporation and delivery system may be located upstream of the processing chamber 1424 such that once a liquid reactant or precursor is evaporated, the evaporated reactant or precursor is introduced into the chamber through gas inlets 1460 and / or 1470.

[0152] RF power is supplied from the RF power source 1441 to the coil 1433 to cause an RF current to flow through the coil 1433. The RF current flowing through the coil 1433 generates an electromagnetic field around the coil 1433. This electromagnetic field generates an induced current within the upper sub-chamber 1402. The resulting ions and radicals physically and chemically interact with the wafer 1419 to etch features of the wafer and selectively deposit a layer on the wafer 1419.

[0153] If a plasma grid 1450 is used such that both an upper sub-chamber 1402 and a lower sub-chamber 1403 are present, the induced current acts on the gas present in the upper sub-chamber 1402 to generate an electron-ion plasma within the upper sub-chamber 1402. The optional internal plasma grid 1450 limits the amount of hot electrons in the lower sub-chamber 1403. In some embodiments, the apparatus 1400 is designed and operated such that the plasma present in the lower sub-chamber 1403 is an "ion-ion" plasma.

[0154] Both the upper electron-ion plasma and the lower ion-ion plasma may contain cations and anions, but the ion-ion plasma will have a greater ratio of anions to cations. Volatile etch and / or deposition by-products may be removed from the lower sub-chamber 1403 through port 1422. The chuck 1417 disclosed herein may be operated within an elevated temperature range between about 10°C and about 250°C. This temperature will depend on the processing operation and the specific recipe.

[0155] The apparatus 1400 can be coupled to a facility (not shown) when installed in a cleanroom or a manufacturing facility. Such facilities include conduits that provide process gases, vacuum, temperature control, and ambient particle control. These facilities are coupled to the apparatus 1400 when installed in the target manufacturing facility. Additionally, the apparatus 1400 can be coupled to a transfer chamber, allowing for the transfer of semiconductor wafers in and out of the apparatus 1400 by a robotic arm using, for example, typical automation.

[0156] In some embodiments, the system controller 1430 (which can include one or more physical or logical controllers) controls some or all of the operations in the processing chamber 1424. The system controller 1430 can include one or more memory devices and one or more processors. In some embodiments, the apparatus 1400 includes a switching system for controlling flow rates and durations when executing the disclosed embodiments. In some embodiments, the apparatus 1400 can have a switching time of up to about 500 ms or up to about 750 ms. The switching time can depend on the flowing chemical composition, recipe selection, reactor architecture, and other factors.

[0157] In some embodiments, the system controller or controller 1430 is part of a system that can be part of the above examples. Such systems can include semiconductor processing equipment that includes one or more processing tools, one or more chambers, one or more platforms for processing, and / or specific processing components (wafer chucks, gas flow systems, etc.). These systems can be integrated with electronics for controlling their operations before, during, and after the processing of semiconductor wafers or substrates. The electronics can be integrated into the controller 1430, which can control various components or sub-components of one or more systems. Depending on the processing parameters and / or system type, the system controller can be programmed to control any of the processes disclosed herein, including controlling the delivery of process gases, temperature settings (e.g., heating and / or cooling), pressure settings, vacuum settings, power settings, radio frequency (RF) generator settings, RF matching circuit settings, frequency settings, flow rate settings, fluid delivery settings, position and operation settings, wafer transfer in and out of the tool and other transfer tools and / or load locks connected to a specific system or interfacing with a specific system.

[0158] Broadly speaking, the controller 1430 can be defined as an electronic device having various integrated circuits, logic, memory, and / or software that receive instructions, issue instructions, control operations, enable cleaning operations, enable endpoint measurements, etc. The integrated circuits can include chips in the form of firmware that stores program instructions, digital signal processors (DSPs), chips defined as application specific integrated circuits (ASICs), and / or one or more microprocessors, or microcontrollers that execute program instructions (e.g., software). The program instructions can be instructions delivered to the controller in the form of various individual settings (or program files), and the individual settings (or program files) define the operating parameters for performing specific processes on or for a semiconductor wafer. In some embodiments, the operating parameters can be part of a recipe defined by a process engineer to complete one or more process steps during the fabrication or removal of one or more layers, materials, metals, oxides, silicon, silicon dioxide, surfaces, circuits, and / or die of a wafer.

[0159] In some embodiments, the system controller 1430 can be part of or coupled to a computer that is integrated with, coupled to, otherwise networked to, or a combination of the system. For example, the controller can be in the "cloud" or in all or part of a wafer fab host system, which can allow remote access to wafer processing. The computer can enable remote access to the system to monitor the current progress of manufacturing operations, examine the history of past manufacturing operations, study trends or performance criteria from multiple manufacturing operations to change the parameters of the current process, set the process steps to follow the current process, or initiate a new process. In some examples, a remote computer (e.g., a server) can provide a process recipe to the system via a network, which can include a local network or the Internet. The remote computer can include a user interface that enables the input or programming of parameters and / or settings, which are then delivered from the remote computer to the system. In some examples, the system controller 1430 receives instructions in the form of data that specify the parameters for each process step to be performed during one or more operations. It should be understood that the parameters can be specific to the type of process to be performed and the type of tool, and the controller is configured to interface with or control the tool. Thus, as described above, the system controller 1430 can be distributed, for example, by including one or more discrete controllers networked together and working towards a common purpose (e.g., the processes and controls described herein). An example of a distributed controller for such a purpose is one or more integrated circuits on a chamber communicating with one or more integrated circuits located remotely (e.g., at the platform level or as part of a remote computer), which are combined to control the processes on the chamber.

[0160] Exemplary systems can include, but are not limited to, a plasma etch chamber or module, a deposition chamber or module, a spin rinse chamber or module, a metal plating chamber or module, a cleaning chamber or module, a bevel edge etch chamber or module, a physical vapor deposition (PVD) chamber or module, a chemical vapor deposition (CVD) chamber or module, an ALD chamber or module, an ALE chamber or module, an ion implantation chamber or module, an orbital chamber or module, an EUV lithography chamber (scanner) or module, a dry lithography chamber or module, and any other semiconductor processing system that can be associated with and / or used for the manufacture and / or preparation of semiconductor wafers.

[0161] As described above, depending on one or more processing steps to be performed by the tool, the controller can communicate with one or more other tool circuits or modules, other tool components, cluster tools, other tool interfaces, adjacent tools, neighboring tools, tools located throughout the factory, a host computer, another controller, or tools used in the material transport that shuttles wafer containers to and from tool locations and / or load ports in a semiconductor manufacturing factory.

[0162] The implementation of EUVL patterning can utilize any suitable tool, which is generally referred to as a scanner, such as the TWINSCAN NXE provided by ASML (Veldhoven, NL): platform. The EUVL patterning tool can be a stand-alone device into which or from which substrates are moved for deposition and etching as described herein. Alternatively, as described below, the EUVL patterning tool can be a module on a larger multi-component tool. Figure 15 Depicted is a semiconductor processing cluster tool architecture having vacuum integrated deposition, EUV patterning, and dry development etch modules docked to a vacuum transfer module, suitable for performing the processes described herein. Although these processes can be implemented without such a vacuum integration device, such a device may be advantageous in certain embodiments.

[0163] Figure 13 Depicted is a semiconductor processing cluster tool architecture having vacuum integrated deposition and patterning modules docked to a vacuum transfer module, suitable for performing the processes described herein. The configuration of the transfer module for "shuttling" wafers between multiple storage devices and processing modules can be referred to as a "cluster tool architecture" system. Depending on the requirements of a particular process, the deposition and patterning modules are vacuum integrated. Other modules (such as for etching) can also be included on the cluster.

[0164] The Vacuum Transfer Module (VTM) 1538 interfaces with four processing modules 1520a - 1520d, which can each be optimized to perform various manufacturing processes. As an example, the processing modules 1520a - 1520d can be used to perform deposition, evaporation, ELD, dry development, etching, stripping, and / or other semiconductor processes. For example, module 1520a can be an ALD reactor that is operable to perform non - plasma thermal atomic layer deposition as described herein, such as the Vector tool available from Lam Research Corporation (Fremont, CA). Module 1520b can be a PEALD tool (e.g., Lam ). It should be understood that the figures are not necessarily drawn to scale.

[0165] The air locks 1542 and 1546 (also referred to as load locks or transfer modules) interface with the VTM 1538 and the patterning module 1540. For example, as described above, a suitable patterning module can be the TWINSCAN NXE: platform (provided by ASML (Veldhoven, NL)). This tool architecture allows for the transfer of a workpiece (e.g., a semiconductor substrate or wafer) under vacuum so as not to react before exposure. The integration of the deposition module with the lithography tool is facilitated by the fact that EUVL also requires a significantly reduced pressure due to the strong optical absorption of environmental gases (e.g., H 2 O, O 2 etc.) for incident photons.

[0166] As described above, this integration architecture is only one possible implementation of the tools for performing the described processes. The performance of these processes can also use more conventional stand - alone EUVL scanners and deposition reactors (e.g., Lam Vector tools) as modules, which are either stand - alone or integrated together with other tools (e.g., etching, stripping, etc. (e.g., Lam Kiyo or Gamma tools)) in a cluster architecture, such as referenced Figure 15 as described (but without an integrated patterning module).

[0167] The air lock 1542 can be an "output" load lock, representing the transfer of the substrate from the VTM 1538 for use by the deposition module 1520a to the patterning module 1540, while the air lock 1546 can be an "input" load lock, indicating the transfer of the substrate from the patterning module 1540 back to the VTM 1538. The input load lock 1546 can also serve as an interface to the outside of the tool for the loading and unloading of substrates. Each processing module has a facet for docking the module to the VTM 1538. For example, the deposition processing module 1520a has a facet 1536. Within each facet, sensors (such as sensors 1-18 shown in the figure) are used to detect the passage of the wafer when the wafer 1526 moves between the corresponding stations. The patterning module 1540 and the air locks 1542, 1546 can be similarly equipped with additional facets and sensors (not shown).

[0168] The main VTM robot 1522 transfers the wafer 1526 between modules, including the air locks 1542 and 1546. In one embodiment, the robot 1522 has one arm, and in another embodiment, the robot 1522 has two arms, where each arm has an end effector 1524 to pick up the wafer (such as the wafer 1526) for conveyance. The front-end robot 1544 is used to transfer the wafer 1526 from the output air lock 1542 into the patterning module 1540 and from the patterning module 1540 into the input air lock 1546. The front-end robot 1544 can also convey the wafer 1526 between the input load lock and the outside of the tool for the loading and unloading of substrates. Since the input air lock module 1546 is capable of matching the environment between atmosphere and vacuum, the wafer 1526 can move between these two pressure environments without being damaged.

[0169] It should be noted that EUVL tools typically operate at a higher vacuum compared to deposition tools. If this is the case, it is desirable to increase the vacuum environment of the substrate during transfer from deposition to the EUVL tool to allow the substrate to outgas before entering the patterning tool. The output air lock 1542 can provide this function by maintaining the transferred wafer at a lower pressure (not higher than the pressure in the patterning module 1540) for a period of time and evacuating any off-gassing, so that the optical components of the patterning tool 1540 are not contaminated by off-gassing from the substrate. A suitable pressure for the output off-gas air lock is not more than 1E-8 Torr.

[0170] In some embodiments, system controller 1550 (which may include one or more physical or logical controllers) controls some or all of the operations of the cluster tool and / or its separate modules. It should be noted that the controller may be local to the cluster architecture, or may be located external to the cluster architecture on the manufacturing floor, or may be located remotely and connected to the cluster architecture via a network. System controller 1550 may include one or more memory devices and one or more processors. The processor may include a central processing unit (CPU) or computer, analog and / or digital input / output connections, a stepper motor control board, and other similar components. A plurality of instructions for implementing appropriate control operations are executed on the processor. These instructions may be stored on a memory device connected to the controller or may be provided via a network. In certain embodiments, the system controller executes system control software.

[0171] The system control software may include instructions for controlling the timing of applications and scaling aspects of any tool or module operation. The system control software may be configured in any suitable manner. For example, various processing tool component subroutines or control objects may be written to control the operation of the processing tool components required to implement various processing tool programs. The system control software may be encoded in any suitable computer-readable programming language. In some embodiments, the system control software includes input / output control (IOC) sequence instructions to control the various parameters described above. For example, each stage of a semiconductor manufacturing process may include one or more instructions executed by the system controller. For example, instructions for setting the processing conditions for condensation, deposition, evaporation, patterning, and / or etching stages may be included in the corresponding recipe stage.

[0172] In various embodiments, an apparatus for forming a negative pattern mask is provided. The apparatus may include processing chambers for patterning, deposition, and etching, and a controller including instructions for forming a negative pattern mask. The instructions may include program code for performing the following processes in the processing chamber: exposing a substrate surface by EUV exposure, patterning features in a chemically amplified resist (CAR) on a semiconductor substrate; performing dry development of the optically patterned resist; and using the patterned photoresist as a mask to etch an underlying layer or layer stack. The development may be performed using a halide-containing chemical.

[0173] It should be noted that the computer controlling wafer movement may be local to the cluster architecture, or may be located external to the cluster architecture on the manufacturing floor, or may be located remotely and connected to the cluster architecture via a network. Regarding Figure 12 、 13 or any one of 14 described above, the controller may be implemented with the Figure 15 tools. Conclusion

[0174] Disclosed are processes and apparatuses in the context of EUV patterning for dry development of metal and / or metal oxide photoresists to form, for example, a patterned mask.

[0175] It should be understood that the examples and embodiments described herein are for illustrative purposes only and various modifications or variations are hereby suggested to those skilled in the art. Although various details have been omitted for the purpose of clarity, various design alternatives are implementable. Accordingly, the examples should be considered illustrative rather than restrictive, and the present disclosure is not limited to the details presented herein but may be modified within the scope of the disclosure.

Claims

1. A method for dry developing a photo-patterned EUV resist on a semiconductor substrate, comprising: dry developing the photo-patterned EUV resist comprising an unexposed organometallic oxide portion and an EUV-exposed metal oxide portion using a dry developing chemical comprising a halide etchant to form a resist mask, wherein the halide etchant selectively removes the unexposed organometallic oxide portion relative to the EUV-exposed metal oxide portion to form the resist mask.

2. The method according to claim 1, wherein the dry developing chemical comprises a hydrogen halide.

3. The method according to claim 1, wherein the hydrogen halide comprises hydrogen bromide (HBr).

4. The method according to claim 1, wherein the hydrogen halide comprises hydrogen chloride (HCl).

5. The method according to claim 1, wherein the dry developing chemical comprises a mixture of HBr and HCl.

6. The method according to claim 1, wherein the dry developing chemical comprises a mixture of a hydrogen halide and boron trichloride (BCl 3 ).

7. The method according to claim 1, wherein dry developing the photo-patterned EUV resist is performed using HBr at a temperature between about -60 °C and about 60 °C.

8. The method according to claim 1, wherein dry developing the photo-patterned EUV resist is performed using HCl at a temperature between about -20 °C and about 120 °C.

9. The method according to claim 1, wherein the dry development of the optically patterned EUV resist is carried out using a mixture of a hydrogen halide and BCl 3 at a temperature between about -20 °C and about 120 °C.

10. The method according to claim 1, wherein the photo-patterned EUV resist comprises an element selected from the group consisting of tin, hafnium, tellurium, bismuth, indium, antimony, iodine, and germanium.

11. The method according to claim 1, wherein the halide etchant selectively breaks metal oxide bonds in the organometallic oxide network of the unexposed organometallic oxide portion to form one or more volatile by-products, while keeping the metal oxide bonds in the metal oxide network of the EUV-exposed metal oxide portion intact to form the resist mask.

12. The method according to claim 1, wherein dry developing the photo-patterned EUV resist produces one or more volatile by-products, the volatile by-products comprising organometallic halides and water.

13. The method according to claim 1, wherein dry developing comprises a combination of plasma-free thermal development and plasma development.

14. A method for developing a photo-patterned EUV resist on a semiconductor substrate, comprising: dry developing the photo-patterned EUV resist on the semiconductor substrate using an etching gas in a plasma-free thermal process to form a resist mask on the semiconductor substrate, wherein the photo-patterned EUV resist comprises an unexposed organometallic oxide portion and an EUV-exposed metal oxide portion.

15. The method according to claim 14, wherein the photo-patterned EUV resist is exposed to EUV light under vacuum before dry developing the photo-patterned EUV resist.

16. The method according to claim 14, wherein the etching gas comprises a hydrogen halide.

17. The method according to claim 14, wherein the etching gas comprises hydrogen bromide (HBr).

18. The method according to claim 14, wherein the etching gas comprises hydrogen chloride (HCl).

19. The method according to claim 14, wherein the photo-patterned EUV resist comprises an element selected from tin, hafnium, tellurium, bismuth, indium, antimony, iodine, and germanium.

20. The method according to claim 14, wherein the etching gas selectively breaks metal-oxide bonds in the metal-oxide network of the unexposed organometallic-oxide portion to form one or more volatile by-products, while keeping the metal-oxide bonds in the metal-oxide network of the EUV-exposed metal-oxide portion intact to form the resist mask.

21. The method according to claim 14, wherein, performing dry development on the photo-patterned EUV resist produces one or more volatile by-products, the volatile by-products comprising organometallic halides and water.

22. The method according to claim 14, wherein, the unexposed organometallic-oxide portion comprises an organic ligand, while the EUV-exposed metal-oxide portion does not have an organic ligand, wherein the etching gas selectively removes the unexposed organometallic-oxide portion containing the organic ligand to form volatile by-products, while keeping the EUV-exposed metal-oxide portion without an organic ligand intact to form the resist mask.

23. A method of developing a photo-patterned EUV resist on a semiconductor substrate, comprising: performing dry development on the photo-patterned EUV resist on the semiconductor substrate using an etching gas in a plasma-less thermal process to form a resist mask on the semiconductor substrate, wherein the photo-patterned EUV resist comprises an unexposed organometallic-oxide portion and an EUV-exposed metal-oxide portion; and exposing the resist mask to a plasma.

24. The method according to claim 23, wherein the plasma comprises an inert gas plasma.

25. The method according to claim 23, wherein the plasma comprises a halide-containing plasma.

26. The method according to claim 23, wherein the plasma comprises an HBr plasma.

27. The method according to claim 23, wherein the plasma comprises BCl 3 plasma.

28. The method according to claim 23, wherein exposing the resist mask to a plasma can make the sidewalls of the resist mask smooth and remove metal-oxide clusters from the resist mask.

29. The method according to claim 23, wherein the etching gas comprises a hydrogen halide.

30. The method according to claim 23, wherein the etching gas comprises hydrogen bromide (HBr).

31. The method according to claim 23, wherein the etching gas comprises hydrogen chloride (HCl).

32. The method according to claim 23, wherein the operations of performing dry development using the etching gas in a plasma-less thermal process and exposing the resist mask to a plasma are repeated for one or more cycles until the unexposed organometallic-oxide portion is completely removed.

33. The method according to claim 23, wherein exposing the resist mask to a plasma comprises hardening the resist mask.

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