Storage device for configuring mapping table and operating method thereof

Abstract

The memory device may include a first main memory configured to store an address mapping table, at least one second main memory configured to store data received from a host device, and a memory controller, and a memory controller configured to compressively convert a host physical address set received from a host device into a device physical address set indicating a range of physical addresses in at least one second main memory associated with the host physical address set, at least one address mapping table entry is generated based on the set of device physical addresses, the at least one address mapping table entry being associated with at least one subset of device physical addresses associated with the set of device physical addresses, and the at least one address mapping table entry is stored in an address mapping table of the first main memory.

Description

[0001] Cross - reference to related applications

[0002] This application claims priority based on Korean Patent Application No. 10 - 2023 - 0180109 filed with the Korean Intellectual Property Office on December 12, 2023, and Korean Patent Application No. 10 - 2024 - 0058131 filed on April 30, 2024, the disclosures of which are incorporated herein by reference in their entireties. Technical field

[0003] Some example embodiments of the inventive concept relate to an electronic device, and more particularly, to a memory device capable of configuring a mapping table, a system including the memory device, and / or an operation method thereof. Background art

[0004] Semiconductor memories are widely used to store data in various electronic devices (such as computers, wireless communication devices, etc.). As a type of semiconductor memory, a dynamic random - access memory (DRAM) operates to write data by storing electric charges in the cell capacitors of memory cells.

[0005] As the data size continuously increases, in order to store more data in a DRAM, a method of physically increasing the storage space amount of the DRAM (e.g., increasing the number of memory cells in the DRAM) is generally used. However, there are limitations in physically increasing the storage space of the DRAM. Therefore, research has been conducted on technologies for expanding the storage space of the DRAM without physically increasing the storage space of the DRAM. Summary of the invention

[0006] Some example embodiments of the inventive concept provide a memory device capable of configuring an address mapping table to reduce a garbage area, a system including the memory device, and / or an operation method of the memory device, etc.

[0007] According to at least one exemplary embodiment of the inventive concept, there is provided a memory device including: a first main memory configured to store an address mapping table; at least one second main memory configured to store data received from a host device; and a memory controller configured to compressively convert a set of host physical addresses received from the host device into a set of device physical addresses including a plurality of device physical addresses in at least one second main memory, generate at least one address mapping table entry associated with at least one device physical address subset of the set of device physical addresses based on the set of device physical addresses, and store the at least one address mapping table entry in the address mapping table of the first main memory, each of the at least one address mapping table entries including: a header indicating a page number of an allocated page or deallocation of the allocated page among a plurality of pages included in the first main memory, a mapping table number corresponding to the set of host physical addresses, a current device physical address subset stored in the allocated page, and a tail indicating an initial device physical address of a subsequent device physical address subset to be read after the current device physical address subset or an end of the set of device physical addresses.

[0008] According to at least one exemplary embodiment of the inventive concept, there is provided a method of operating a memory device, the method including: receiving a set of host physical addresses from a host device, compressively converting the set of host physical addresses into a set of device physical addresses including a plurality of device physical addresses in at least one first main memory, and generating at least one address mapping table entry associated with at least one device physical address subset of the set of device physical addresses, each of the at least one address mapping table entries including: a header indicating a page number of an allocated page or deallocation of the allocated page among a plurality of pages included in the second main memory; a mapping table number corresponding to the set of host physical addresses; a current device physical address subset stored in the allocated page; and a tail indicating an initial device physical address of a subsequent device physical address subset to be read after the current device physical address subset or an end of the set of device physical addresses.

[0009] According to at least one exemplary embodiment of the inventive concept, there is provided a memory device including at least one memory module connected to a channel and a controller including a main memory configured to store an address mapping table. The controller is configured to: compressively convert a set of host physical addresses received from a host device into a set of device physical addresses including a plurality of device physical addresses in the main memory; generate at least one address mapping table entry associated with at least one device physical address subset of the set of device physical addresses; and store the at least one address mapping table entry in the main memory. Each of the at least one address mapping table entries includes: a header indicating a page number of an allocated page or deallocation of the allocated page among a plurality of pages included in the main memory; a mapping table number corresponding to the set of host physical addresses; a current device physical address subset stored in the allocated page; and a tail indicating an initial device physical address of a subsequent device physical address subset to be read after the current device physical address subset or an end of the set of device physical addresses. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Some exemplary embodiments will be understood more clearly from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0011] Figure 1 is a block diagram illustrating a memory system according to at least one exemplary embodiment;

[0012] Figure 2 is a schematic diagram illustrating address mapping according to at least one exemplary embodiment;

[0013] Figure 3 is a schematic diagram illustrating address compression according to at least one exemplary embodiment;

[0014] Figure 4 is a schematic diagram illustrating address recompression according to at least one exemplary embodiment;

[0015] Figure 5 is a schematic diagram illustrating an address mapping table entry according to at least one exemplary embodiment;

[0016] Figure 6 and Figure 7 is a schematic diagram illustrating an updated address mapping table according to at least one exemplary embodiment;

[0017] Figure 8 is a block diagram of a memory controller according to at least one exemplary embodiment;

[0018] Figure 9 is a schematic diagram illustrating a memory device according to at least one exemplary embodiment;

[0019] Figure 10is a flowchart showing an operation method of a memory device according to at least one exemplary embodiment;

[0020] Figure 11 is according to at least one exemplary embodiment Figure 10 of the operation method;

[0021] Figure 12 is according to at least one exemplary embodiment Figure 10 of the operation method;

[0022] Figure 13 is according to at least one exemplary embodiment Figure 10 of the operation method; and

[0023] Figure 14 is according to at least one exemplary embodiment Figure 10 of the operation method. Detailed Description

[0024] Hereinafter, some exemplary embodiments of the inventive concept will be described in detail with reference to the accompanying drawings.

[0025] Figure 1 is a block diagram showing a memory system 1 according to at least one exemplary embodiment.

[0026] Referring to Figure 1 , the memory system 1 may include at least one host 10 (e.g., a host device, etc.) and / or at least one memory device 100, but the exemplary embodiments are not limited thereto, and for example, the memory system 1 may include a greater or smaller number of constituent components, etc.

[0027] The host 10 may communicate with the memory device 100 through at least one interface. The host 10 may send and / or transmit to the memory device 100 at least one write request for storing data in the memory device 100. In addition, the host 10 may send and / or transmit to the memory device 100 the data to be stored in the memory device 100 and the host physical address for identifying and / or corresponding to the data to be stored in the memory device 100, but is not limited thereto. The host 10 may send and / or transmit to the memory device 100 at least one read request for requesting the memory device 100 to read, return, retrieve, and / or provide the data stored therein. In addition, the host 10 may send the host physical address to the memory device 100, and the host physical address is used to identify the data to be read from the memory device 100. In some example embodiments, the host physical address may be included in the read request. The host 10 may be implemented as and / or include a processor (e.g., processing circuitry), such as a central processing unit (CPU), an application processor (AP), a system on a chip (SoC), etc., and may process data, instructions, commands, etc. The host 10 may execute an operating system (OS) and / or various applications. The host 10 may include a physical layer, a multi-protocol multiplexer, an interface circuit, a coherence / cache circuit, a bus circuit, at least one core, and / or at least one input / output device, etc., but is not limited thereto.

[0028] In at least one example embodiment, the host 10 may send at least one host physical address to the memory device 100. A specific and / or desired number of host physical addresses may be referred to as a host physical address set having a specific and / or desired size.

[0029] The memory device 100 may include a memory controller 110 and / or multiple main memories, for example, a first main memory 120, and / or a second main memory 130, etc., but is not limited thereto, and for example, may include more or a number of memories, etc.

[0030] The memory controller 110 (e.g., processing circuitry, etc.) may control the main memory to write data to the main memory and / or read the data stored in the main memory in response to the access and / or request of the host 10.

[0031] In at least one example embodiment, the memory controller 110 may compressively convert a set of host physical addresses received from the host 10 into a set of device physical addresses. In other words, the memory controller 110 may convert the set of host physical addresses into a set of device physical addresses and compress them into a smaller data size. The set of device physical addresses may correspond to the storage space of the second main memory 130, but is not limited thereto. The memory controller 110 may generate at least one address mapping table entry including a subset of device physical addresses based on the set of device physical addresses. The memory controller 110 may store the at least one address mapping table entry in the first main memory 120. For example, the memory controller 110 may receive at least one host physical address from the host 10 and may convert the host physical address into a device physical address. In at least one example embodiment, the memory controller 110 may compressively convert (e.g., convert and compress into a smaller file size, etc.) a set of host physical addresses of a first size into a set of device physical addresses of a second size, etc. The second size may be smaller than the first size. Assume that a set of device physical addresses of a specific and / or desired size represents a specific and / or desired number of device physical addresses. In other words, the set of device physical addresses may be associated with and / or correspond to a plurality of device physical addresses and / or a range of device physical addresses. The memory controller 110 may split the set of device physical addresses of the second size into at least one subset of device physical addresses and generate at least one address mapping table entry, but is not limited thereto. One address mapping table entry may include one subset of device physical addresses, but is not limited thereto. The address mapping table entry may include data indicating a mapping relationship (e.g., conversion information, etc.) between the host physical address and the device physical address. When the memory controller 110 generates at least one address mapping table entry during a write operation, the memory controller 110 may update the at least one address mapping table entry during a rewrite operation, but the example embodiment is not limited thereto.

[0032] The first main memory 120 and the second main memory 130 may each be implemented as a volatile memory, but the example embodiments are not limited thereto, and for example, one or more of the main memories may be a non-volatile memory. The volatile memory may be, for example, a static random access memory (RAM) (SRAM), a dynamic RAM (DRAM), a mobile DRAM, a double data rate (DDR) synchronous DRAM (SDRAM), a low power DDR (LPDDR) SDRAM, a graphics DDR (GDDR) SDRAM, a Rambus DRAM (RDRAM), etc. In at least one example embodiment, the first main memory 120 and the second main memory 130 may each be implemented as a DRAM. However, the example embodiments of the inventive concept are not limited thereto. The first main memory 120 and the second main memory 130 may each include at least one page. For example, the first main memory 120 may include a plurality of pages PG. The size of one page may be, for example, 4 kilobytes (KB), but is not limited thereto.

[0033] The first main memory 120 may store at least one address mapping table entry. The size of the address mapping table entry may be smaller than the size of the set of device physical addresses, but is not limited thereto.

[0034] The second main memory 130 may store data received from the host 10. The second main memory 130 may store (e.g., write) the data in a storage space corresponding to the device physical address based on a write command of the memory controller 110 and the device physical address. The second main memory 130 may output the data stored in the storage space to the memory controller 110 based on a read command of the memory controller 110 and the device physical address.

[0035] According to at least one example embodiment, by linking the address mapping table entries to each other, the garbage area of the memory may be reduced, or in other words, the file size of the garbage area of the memory, etc., may be reduced.

[0036] In addition, according to at least one example embodiment, by compressing the address, the storage space of the memory may be increased and / or the manufacturing cost of the memory may be reduced without physically changing the architecture of the memory (e.g., physically increasing the number of memory cells included in the memory device, etc.).

[0037] Figure 2 is a schematic diagram showing address mapping according to at least one example embodiment.

[0038] Reference Figure 1 and Figure 2, in at least one exemplary embodiment, the memory controller 110 may convert a set of host physical addresses HPAS of a first size (e.g., a first desired size) into a set of device physical addresses DPAS of a first size (e.g., a first desired size), but is not limited thereto. The set of host physical addresses HPAS and the set of device physical addresses DPAS may have a one-to-one correspondence with each other. In this regard, the first size may be, for example, 4KB, but the exemplary embodiments of the inventive concept are not limited thereto, and other sizes may be used.

[0039] Recently, as the size of data has increased, in order to store more data in the main memory (e.g., the second main memory 130), a method of physically increasing the storage space of the main memory is generally used. However, as the size of data increases, the size and / or quantity of host physical addresses also increase. As the size and / or quantity of host physical addresses increase, the size and / or quantity of device physical addresses that are mapped so as to have a one-to-one size correspondence with the host physical addresses increase, and thus, the storage space of the main memory also needs to be physically increased. There are limitations in physically expanding the storage space of the main memory. Therefore, as at least one exemplary embodiment of storing more data in the main memory without physically expanding the storage space of the main memory, the memory controller 110 may compress the data received from the host 10 and store the compressed data in the main memory (e.g., the second main memory 130). In this regard, the memory controller 110 may also compress the size of the set of device physical addresses DPAS to reduce and / or eliminate the need to expand the physical size of the main memory and / or add more main memories, etc.

[0040] Figure 3 is a schematic diagram showing address compression according to at least one exemplary embodiment.

[0041] Reference Figure 1 and Figure 3 , in at least one exemplary embodiment, the memory controller 110 may receive host physical addresses of a specific size (e.g., a desired size, etc.) from the host 10, and aggregate the host physical addresses into a set of host physical addresses HPAS in units of a first size (e.g., a first desired size, etc.). For example, the specific size of each host physical address may be 64 bytes (B), and the first size of each of the first to third sets of host physical addresses HPAS1, HPAS2, and HPAS3 may be 4KB. However, the exemplary embodiments of the inventive concept are not limited thereto, and other sizes may be used. Although Figure 3 shows three sets of host physical addresses HPA, the number of sets of host physical addresses is not limited to Figure 3 the number shown.

[0042] The memory controller 110 may convert a set of host physical addresses HPAS of a first size into a set of device physical addresses DPAS having a size smaller than the first size. For example, the memory controller 110 may convert a first set of host physical addresses HPAS1 of 4 KB into a first set of device physical addresses DPAS1 of 3 KB, but the example embodiments are not limited thereto. As another example, the memory controller 110 may convert a second set of host physical addresses HPAS2 of 4 KB into a second set of device physical addresses DPAS2 of 2 KB, and so on. As another example, the memory controller 110 may convert a third set of host physical addresses HPAS3 of 4 KB into a third set of device physical addresses DPAS3 of 1 KB, and so on. The sizes of each of the first to third sets of device physical addresses DPAS1, DPAS2, and DPAS3 may be changed for each write operation. For example, when a write operation is performed on the first set of host physical addresses HPAS1, the size of the first set of device physical addresses DPAS1 may be compressed to 3 KB, as Figure 3 shown. After that, when a write operation is performed on the first set of host physical addresses HPAS1 again, the size of the first set of device physical addresses DPAS1 may be compressed to a size smaller than 4 KB, such as 2 KB, 1 KB, etc.

[0043] The set of device physical addresses DPAS may include subsets of device physical addresses, each subset of device physical addresses having a specific size. The subsets of device physical addresses may have the same size, for example, 0.5 KB or 1 kB, but the example embodiments of the inventive concept are not limited thereto, and for example, different sizes may be used. Referring to Figure 3 , for example, a first set of device physical addresses DPAS1 of 3 KB may include six subsets of device physical addresses DPASS each having a size of 0.5 KB, but the example embodiments are not limited thereto. As another example, a second set of device physical addresses DPAS2 of 2 KB may include four subsets of device physical addresses DPASS each having a size of 0.5 KB, and so on. As another example, a third set of device physical addresses DPAS3 of 1 KB may include two subsets of device physical addresses DPASS each having a size of 0.5 KB, and so on.

[0044] In at least one example embodiment, the subsets of device physical addresses may include device physical addresses each having a specific and / or desired size (e.g., 64 B), but the example embodiments are not limited thereto.

[0045] Figure 4 is a schematic diagram showing address recompression according to at least one example embodiment.

[0046] Referring to Figure 1 and Figure 4, multiple write operations may be performed multiple times over time in the memory device 100. For example, a first write operation WRITE1 may be performed, and after the first write operation WRITE1 is completed, a second write operation WRITE2 may be performed, and so on. However, the example embodiments of the inventive concept are not limited thereto.

[0047] In the first write operation WRITE1, for example, a first host physical address set HPAS1 of 4KB may be converted into a first device physical address set DPAS1 of 2KB, a second host physical address set HPAS2 of 4KB may be converted into a second device physical address set DPAS2 of 2KB, and a third host physical address set HPAS3 of 4KB may be converted into a third device physical address set DPAS3 of 2KB, but the example embodiments are not limited thereto. The first to third device physical address sets DPAS1, DPAS2, and DPAS3 may be stored continuously in the first main memory 120. Each of the first to third device physical address sets DPAS1, DPAS2, and DPAS3 may include device physical address subsets of equal size (e.g., 0.5KB, 1KB, etc.), but is not limited thereto. In Figure 4 , it is assumed that the size of the device physical address subset is 1KB, but the example embodiments are not limited thereto.

[0048] In the second write operation WRITE2, as in the first write operation WRITE1, a first host physical address set HPAS1 of 4KB may be converted into a first device physical address set DPAS1 of 2KB. Conversely, different from the first write operation WRITE1, a second host physical address set HPAS2 of 4KB may be converted into a second device physical address set DPAS2 of 1KB, and a third host physical address set HPAS3 of 4KB may be converted into a third device physical address set DPAS3 of 3KB.

[0049] In this regard, when the size of the compressed address (conveniently referred to as the "second compression size") in the next (e.g., subsequent, future, etc.) write operation is smaller than the size of the compressed address (conveniently referred to as the "first compression size") in the previous write operation, the area storing the addresses corresponding to the difference in size between the first compression size and the second compression size may become a garbage area (e.g., a memory area storing garbage data, etc.). Refer to Figure 4, for example, the size of the second device physical address set DPAS2 in the first write operation WRITE1 can be 2KB, and the size of the second device physical address set DPAS2 in the second write operation WRITE2 can be 1KB. Therefore, the area in the existing 2KB second device physical address set DPAS2 where 1KB of the second device physical address set DPAS2 is stored can become a garbage area (for example, the second DPASS in the area storing the second device physical address set DPAS2 can contain garbage data, etc.).

[0050] In some cases, the second compression size can be greater than the first compression size, or in other words, the compression ratio for the second compression size can be lower than the compression ratio for the first compression size, and so on. Refer to Figure 4 , for example, the size of the third device physical address set DPAS3 in the first write operation WRITE1 can be 2KB, and the size of the third device physical address set DPAS3 in the second write operation WRITE2 can be 3KB, but not limited thereto. When a new storage space (such as a page) for storing device physical addresses is allocated, the newly allocated storage space needs to be continuous with the storage space storing the existing device physical addresses. However, when individual device physical addresses are stored in consecutive pages, the resources of the memory device 100 may be wasted and / or quite wasted because the memory controller 110 causes the corresponding pages in which the individual device physical addresses are stored to be free pages (for example, deallocating consecutive pages corresponding to different device physical addresses, etc.), and allocating new free pages (such as free consecutive pages) to store each of the individual device physical addresses. Additionally or alternatively, the memory controller 110 can allocate free pages and store the device physical address sets in the allocated pages. Refer to Figure 4 , for example, the memory controller 110 can allocate at least one free page FPG corresponding to a 3KB storage space to the third device physical address set DPAS3, and can store the third device physical address set DPAS3 in the newly allocated page. However, even according to the above example, since the existing storage space (such as a page) where the 2KB third device physical address set DPAS3 is stored in the first write operation WRITE1 becomes a garbage area, the resources of the memory device 100 may be wasted. Therefore, it may be desirable and / or necessary to reduce the address mapping table entries for the garbage area.

[0051] Figure 5 is a schematic diagram showing an address mapping table entry according to at least one example embodiment.

[0052] Refer to Figure 1 and Figure 5, in at least one example embodiment, the memory controller 110 may convert a 4KB host physical address set (HPAS) into a 2KB device physical address set (DPAS), but is not limited thereto. In this regard, the sizes of the host physical address set HPAS and / or the device physical address set DPAS are merely examples, and other size values may be used. For example, the memory controller 110 may split the 2KB device physical address set DPAS into, for example, first to fourth device physical address subsets DPASS1, DPASS2, DPASS3, and DPASS4, each subset having a size of 0.5KB, but the example embodiment is not limited thereto. In this regard, the sizes and quantities of the device physical address subsets DPASS are examples, and other size and / or quantity values may be used. Each of the first to fourth device physical address subsets DPASS1, DPASS2, DPASS3, and DPASS4 may include device physical addresses (DPA) each having a size of 64B. In this regard, the size of the device physical address DPA is an example, and other size values may be used. The device physical address DPA may correspond to, for example, the storage space of the second main memory 130. The device physical addresses DPA included in each device physical address subset may be read sequentially. The device physical addresses iDPA1, iDPA2, iDPA3, and iDPA4 included in the first to fourth device physical address subsets DPASS1, DPASS2, DPASS3, and DPASS4 may each be the first address to be read in each device physical address subset. The device physical addresses iDPA1, iDPA2, iDPA3, and iDPA4 may each be referred to as an initial device physical address and / or a starting device physical address, etc.

[0053] The memory controller 110 may define and / or discretely define a mapping granularity and then generate address mapping table entries with a size smaller than the size of the device physical address set DPAS, but is not limited thereto. For example, the memory controller 110 may generate first to fourth address mapping table entries AMTE1, AMTE2, AMTE3, and AMTE4 based on the first to fourth device physical address subsets DPASS1, DPASS2, DPASS3, and DPASS4, but is not limited thereto. The number of address mapping table entries and the number of device physical address subsets may be the same. The address mapping table may include a plurality of address mapping table entries (e.g., first to fourth address mapping table entries AMTE1, AMTE2, AMTE3, and AMTE4, etc.).

[0054] Each of the first to fourth address mapping table entries AMTE1, AMTE2, AMTE3, and AMTE4 may include a header, a first field FLD1, a second field FLD2, and / or a tail (e.g., a tail pointer, etc.), but is not limited thereto.

[0055] The header may include information indicating the number of pages of each DPASS among the multiple pages allocated to the first main memory 120. For example, the headers of the first to fourth address mapping table entries AMTE1, AMTE2, AMTE3, and AMTE4 may include values indicating the same or different numbers of pages based on the number of pages of the DPASS associated with the first to fourth address mapping table entries. Additionally or alternatively, the header may include information indicating the deallocation of the pages corresponding to the respective DPASSs. Here, deallocation may mean making the allocated pages free, etc.

[0056] The first field FLD1 may include a value of a mapping table number corresponding to a set of host physical addresses. For example, since the first to fourth address mapping table entries AMTE1, AMTE2, AMTE3, and AMTE4 are generated based on the same set of device physical addresses, the values of the first field FLD1 of the first to fourth address mapping table entries AMTE1, AMTE2, AMTE3, and AMTE4 may be the same, but the exemplary embodiments are not limited thereto.

[0057] The second field FLD2 may include a value of a subset of device physical addresses (e.g., a memory address, etc.) stored in the allocated pages. For example, the second field FLD2 of the first address mapping table entry AMTE1 may include the value of the first device physical address subset DPASS1. For example, the second field FLD2 of the second address mapping table entry AMTE2 may include the value of the second device physical address subset DPASS2. For example, the second field FLD2 of the third address mapping table entry AMTE3 may include the value of the third device physical address subset DPASS3. For example, the second field FLD2 of the fourth address mapping table entry AMTE4 may include the value of the fourth device physical address subset DPASS4.

[0058] The tail (e.g., tail pointer, etc.) may include information indicating an initial device physical address in a first memory of another (e.g., second, subsequent, etc.) device physical address subset to be read after the current device physical address subset. For example, the tail of the first address mapping table entry AMTE1 may include a pointer indicating the value of the device physical address iDPA2 of the second device physical address subset DPASS2 (e.g., an address in the first main memory, etc.). For example, the tail of the second address mapping table entry AMTE2 may include a pointer indicating the value of the device physical address iDPA3 (e.g., an address in the first main memory, etc.). For example, the tail of the third address mapping table entry AMTE3 may include a pointer indicating the value of the device physical address iDPA4 (e.g., an address in the first main memory, etc.). Additionally or alternatively, the tail may include information indicating an end address ADD END in a first memory of the device physical address set DPAS. The end address ADD END of the device physical address set DPAS may mean that there are no more device physical address subsets to read. For example, the tail of the fourth address mapping table entry AMTE4 may include information indicating the end address ADD END in the first main memory of the device physical address set DPAS.

[0059] According to at least one example embodiment, by linking address mapping table entries to each other, the amount of memory space occupied by the garbage area can be reduced, thereby increasing, improving, and / or protecting the storage space of the memory, etc.

[0060] Figure 6 and Figure 7 is a schematic diagram showing an example method for updating an address mapping table according to at least one example embodiment. Specifically, Figure 6 is a schematic diagram showing an example method for updating an address mapping table according to at least one example embodiment when the first compression size of a previous write operation is greater than the second compression size of a next write operation (or in other words, the first compression ratio corresponding to the first write operation is less than the second compression ratio corresponding to the second write operation). Figure 7 is a schematic diagram showing an example method for updating an address mapping table according to at least one example embodiment when the first compression size is less than the second compression size.

[0061] Reference Figure 6, in the first write operation WRITE1, a 4KB host physical address set HPAS can be converted into a 2KB device physical address set DPAS, but the exemplary embodiments are not limited thereto. The 2KB device physical address set DPAS can be split into 0.5KB units to generate four device physical address subsets DPASS, but not limited thereto. Multiple mapping table entries can be generated based on the four device physical address subsets DPASS. For example, the first to fourth address mapping table entries AMTE1, AMTE2, AMTE3, and AMTE4, etc. Assume that the first to fourth address mapping table entries AMTE1, AMTE2, AMTE3, and AMTE4 are the same as those described above with reference to Figure 5 , but the exemplary embodiments are not limited thereto. For example, the tail (e.g., tail pointer) of the first address mapping table entry AMTE1 can indicate (e.g., point to) the value of the device physical address iDPA2, the tail of the second address mapping table entry AMTE2 can indicate (e.g., point to) the value of the device physical address iDPA3, and the tail of the third address mapping table entry AMTE3 can indicate (e.g., point to) the value of the device physical address iDPA4, and so on.

[0062] In the second write operation WRITE2, a 4KB host physical address set HPAS can be translated into a 1KB device physical address set DPAS, but is not limited thereto. The 1KB device physical address set DPAS can be split into 0.5KB units to generate two device physical address subsets DPASS, but is not limited thereto. In this case, two address mapping table entries may be desired and / or required. In at least one example embodiment, the memory controller 110 can update the address mapping table by writing information indicating deallocation DEMALLOC to the header of each of the third address mapping table entry AMTE3 and the fourth address mapping table entry AMTE4. In other words, the memory controller 110 can indicate that the DPASS corresponding to the third address mapping table entry AMTE3 and the fourth address mapping table entry is being deallocated, but is not limited thereto. Additionally, the memory controller 110 can update the address mapping table by writing information indicating the end address ADD END of the device physical address set DPAS to the tail of the second address mapping table entry AMTE2, but the example embodiment is not limited thereto. Since the headers of the updated third address mapping table entry AMTE3' and the fourth address mapping table entry AMTE4' each indicate deallocation DEMALLOC, the link between the updated third address mapping table entry AMTE3' and the fourth address mapping table entry AMTE4' may be broken and / or may be garbage, etc. Since the tail of the updated second address mapping table entry AMTE2' includes information indicating the end address ADD END of the device physical address set DPAS, the link between the updated second address mapping table entry AMTE2' and the third address mapping table entry AMTE3' may be disconnected, etc.

[0063] Reference Figure 7 , the first write operation WRITE1 is the same as that in Figure 6 , and thus, its redundant description is omitted. In the second write operation WRITE2, a 4KB host physical address set HPAS can be translated into a 3KB device physical address set DPAS, but the example embodiment is not limited thereto. The 3KB device physical address set DPAS can be split into 0.5KB units to generate six device physical address subsets DPASS, but the example embodiment is not limited thereto. In this case, six address mapping table entries may be desired and / or required. In at least one example embodiment, the memory controller 110 can update the address mapping table by writing a pointer NXT MADD indicating the next initial device physical address to the tail of the fourth address mapping table entry AMTE4. The pointer NXT MADD written to the tail of the updated fourth address mapping table entry AMTE4' can indicate at Figure 5The initial device physical address (not shown) of the fifth device physical address subset (not shown) to be read after the fourth device physical address subset DPASS4, and so on, but the example embodiments are not limited thereto. The memory controller 110 may update the address mapping table by additionally generating a fifth address mapping table entry AMTE5 and a sixth address mapping table entry AMTE6, but is not limited thereto. For example, the memory controller 110 may allocate pages for storing the fifth address mapping table entry AMTE5 and the sixth address mapping table entry AMTE6 by writing the page number PN to the headers of the fifth address mapping table entry AMTE5 and the sixth address mapping table entry AMTE6. The memory controller 110 may write the pointer NXT MADD to the tail of the fifth address mapping table entry AMTE5, and write the information indicating the end ADD END of the device physical address set DPAS to the tail of the sixth address mapping table entry AMTE6. The address mapping table entries (e.g., AMTE1, AMTE2, AMTE3, AMTE4', AMTE5, and AMTE6) in the second write operation WRITE2 may be linked to each other.

[0064] According to at least one example embodiment, the garbage area may be reduced by linking the address mapping table entries to each other (e.g., the size of the garbage area may be reduced, etc.).

[0065] Figure 8 is a block diagram of a memory controller 110 according to at least one example embodiment.

[0066] Reference Figure 8 In at least one example embodiment, the memory controller 110 may include a compression logic circuit 111 and / or a mapping management circuit 112, and so on, but is not limited thereto. According to some example embodiments, the memory controller 110, the compression logic circuit 111, and / or the mapping management circuit 112, and so on, may be implemented as a processing circuit. The processing circuit may include hardware or a hardware circuit including a logic circuit; a hardware / software combination, such as a processor executing software and / or firmware; or a combination thereof. For example, the processing circuit may more specifically include, but is not limited to, a central processing unit (CPU), an arithmetic logic unit (ALU), a digital signal processor, a microcomputer, a field programmable gate array (FPGA), a system on chip (SoC), a programmable logic unit, a microprocessor, an application specific integrated circuit (ASIC), and so on, but is not limited thereto.

[0067] The compression logic circuit 111 may compress the desired data. In at least one example embodiment, the compression logic circuit 111 may compress a set of host physical addresses of a first size (e.g., a first desired size, etc.) into a set of device physical addresses of a second size (e.g., a second desired size, etc.). In at least one example embodiment, the compression logic circuit 111 may split the set of device physical addresses into multiple device physical address subsets of the same size, but is not limited thereto. At least one example embodiment is the same as or substantially the same as at least one example embodiment described in conjunction with Figure 3 and 5 but the example embodiments are not limited thereto.

[0068] The mapping management circuit 112 may manage an address mapping table, but is not limited thereto. In at least one example embodiment, the mapping management circuit 112 may generate address mapping table entries based on device physical address subsets, etc. At least one example embodiment is the same as and / or similar to at least one example embodiment described above in conjunction with Figure 5 but is not limited thereto. In at least one example embodiment, the mapping management circuit 112 may update address mapping table entries based on device physical address subsets, but is not limited thereto. At least one example embodiment is the same as or similar to at least one example embodiment described above with reference to Figure 6 and Figure 7 but is not limited thereto.

[0069] Although not shown, in at least one example embodiment, the memory controller 110 may further include a first main memory 120, etc.

[0070] Figure 9 is a schematic diagram showing a memory device 200 according to at least one example embodiment.

[0071] Referring to Figure 9 the memory device 200 may include a controller 210 and at least one memory module, etc., but is not limited thereto.

[0072] In at least one example embodiment, the controller 210 may include a compression logic circuit 211, a mapping management circuit 212, and / or a main memory 213, etc., but is not limited thereto. The compression logic circuit 211 and the mapping management circuit 212 may be the same as the compression logic circuit 111 and the mapping management circuit 112 described in conjunction with Figure 8 but is not limited thereto. The main memory 213 may be the same as the first main memory 120 of Figure 1 but is not limited thereto. According to some example embodiments, the controller 210, the compression logic circuit 211, the mapping management circuit 212, and / or the main memory 213, etc., may be implemented as a processing circuit.

[0073] One or more memory modules may be connected to the controller 210 via at least one channel. The number of memory modules connected to the controller 210 via a single channel may be one or more. The memory modules may be split into single in-line memory modules (SIMMs) having a structure in which tabs are formed on one side and / or dual in-line memory modules (DIMMs) having a structure in which tabs are formed on both sides. For example, Figure 9 the first through the i-th memory modules 120_1, 120_2, …, and 120_i shown in

[0074] In some example embodiments, the memory device 200 may include two or more memory modules, but the example embodiments of the inventive concept are not limited thereto. Referring to Figure 9 , for example, the memory device 200 may include first through the i-th memory modules 120_1, 120_2, ..., and 120_i. The first memory module 120_1 may be connected to the controller 210 via the first channel CH1, the second memory module 120_2 may be connected to the controller 210 via the second channel CH2, the i-th memory module 120_i may be connected to the controller 210 via the i-th channel CHi, and so on. Each of the first through the i-th memory modules 120_1, 120_2, ..., and 120_i may include a plurality of DRAM chips. For example, the first memory module 120_1 may include a plurality of DRAM chips 121_1, 122_1, 123_1, …, the second memory module 120_2 may include a plurality of DRAM chips 121_2, 122_2, 123_2, …, and the i-th memory module 120_i may include a plurality of DRAM chips 121_i, 122_i, 123_i, ….

[0075] In Figure 9 , the main memory 213 may be included in the controller 210. However, different from that shown in Figure 9 , in other example embodiments, the main memory 213 may not be included in the controller 210, but may be externally connected to the controller 210 via at least one bus or the like.

[0076] Figure 10 is a flowchart illustrating an example operation method of a memory device according to at least one example embodiment.

[0077] Referring to Figure 10 , operation S100 may include receiving, by the memory controller 110, a set of host physical addresses (e.g., a host physical address range, etc.) from the host 10.

[0078] Operation S200 may include the memory controller 110 compressing the conversion of a set of host physical addresses into a set of device physical addresses (e.g., a device physical address range, etc.).

[0079] Operation S300 may include the memory controller 110 generating at least one address mapping table entry including a subset of device physical addresses (e.g., including a sub-range of device physical addresses, etc.) based on the set of device physical addresses. In at least one example embodiment, the at least one address mapping table entry may include a header indicating the number of pages allocated or the deallocation of pages corresponding to the DPASS allocated among multiple pages, a mapping table number corresponding to the set of host physical addresses, a subset of device physical addresses corresponding to the DPASS stored in the associated page, and / or a tail (e.g., a tail pointer, etc.) indicating the initial device physical address of another and / or next subset of device physical addresses to be read after the end of one subset of device physical addresses and / or the set of device physical addresses, etc., but the example embodiment is not limited thereto.

[0080] In at least one example embodiment, Figure 10 the operation method of may further include operation S400 in which the memory controller 110 stores the at least one address mapping table entry in the main memory (e.g., the first main memory 120).

[0081] Figure 11 is according to at least one example embodiment of Figure 10 the flowchart of the operation method of. Figure 11 At least one example embodiment of may be the same as and / or similar to at least one example embodiment described in conjunction with Figure 5 but the example embodiment is not limited thereto.

[0082] Referring to Figure 11 Figure 10 Operation S300 of may include operation S310 and operation S320, but is not limited thereto.

[0083] In operation S310, the memory controller 110 may generate at least a first address mapping table entry including at least a first subset of device physical addresses, but is not limited thereto. The first address mapping table entry may include a header indicating the number of pages allocated to the first DPASS among multiple pages, a first mapping table number, a first subset of device physical addresses, and / or a tail (e.g., a tail pointer, etc.) indicating the initial device physical address in the first memory of a second subset of device physical addresses (e.g., the next subset of device physical addresses, the subsequent subset of device physical addresses, etc.).

[0084] ​In operation S320, the memory controller 110 may generate a second address mapping table entry including a subset of second device physical addresses, but is not limited thereto. The second address mapping table entry may include a header indicating the number of pages allocated to the second DPASS, a second mapping table number, a subset of second device physical addresses, and / or a tail indicating the end of the set of device physical addresses, but is not limited thereto.

[0085] Figure 12 is a flowchart of an operation method according to at least one example embodiment Figure 10 of Figure 12 At least one example embodiment of Figure 5 may be the same as and / or similar to at least one example embodiment described in connection with

[0086] Reference Figure 12 , operation S200 may include operation S210, and operation S300 may include operation S330, but the example embodiments are not limited thereto.

[0087] In operation S210, the memory controller 110 may convert (and / or compress) a first set of host physical addresses of a first size (e.g., a first desired size, etc.) into a first set of device physical addresses of a second size smaller than the first size.

[0088] In operation S330, the memory controller 110 may generate first to nth address mapping table entries each having a third size based on the first set of device physical addresses, where n may be (second size / third size), but the example embodiments are not limited thereto.

[0089] Figure 13 is a flowchart of an operation method according to at least one example embodiment Figure 10 of Figure 13 At least one example embodiment of Figure 6 may be the same as and / or similar to at least one example embodiment described in connection with

[0090] Reference Figure 13 , operation S200 may include operation S210 and operation S220, and operation S300 may include operation S330, operation S340, operation S350, and operation S360, but the example embodiments are not limited thereto.

[0091] After operation S330, in operation S220, the memory controller 110 may convert the first set of host physical addresses into a second set of device physical addresses of a fourth size smaller than the second size, but is not limited thereto.

[0092] After operation S220, in operation S340, the memory controller 110 may generate first to mth address mapping table entries each having a third size based on the second set of device physical addresses, where m may be (fourth size / third size) and may be less than n, but is not limited thereto.

[0093] After operation S340, in operation S350, the memory controller 110 may write information indicating the end of the set of device physical addresses to the tail of the mth address mapping table entry and the like.

[0094] After operation S350, in operation S360, the memory controller 110 may write information indicating the deallocation of the page assigned to the device physical address subset DPASS associated with the corresponding address mapping table entry to the head of each of the (m + 1)th to nth address mapping table entries.

[0095] Figure 14 is according to at least one example embodiment Figure 10 of the operation method. Figure 14 At least one example embodiment of Figure 7 may be the same as and / or similar to at least one example embodiment described in connection with

[0096] Reference Figure 14 , operation S200 may include operation S210 and operation S230, and operation S300 may include operation S330, operation S370, operation S380, and operation S390, but the example embodiments are not limited thereto.

[0097] After operation S330, in operation S230, the memory controller 110 may convert the first set of host physical addresses into a third set of device physical addresses having a fifth size that is less than the first size and greater than the second size, but the example embodiments are not limited thereto.

[0098] After operation S230, in operation S370, the memory controller 110 may generate first to kth address mapping table entries each having a third size based on the third set of device physical addresses, where k may be (fifth size / third size) and may be greater than n, but is not limited thereto.

[0099] After operation S370, in operation S380, the memory controller 110 may write page numbers to the head of each of the (n + 1)th to kth address mapping table entries and the like.

[0100] After operation S380, in operation S390, the memory controller 110 may write the initial device physical addresses of the subset of device physical addresses included in the (n + 1)-th address mapping table entry to the tail of the n-th address mapping table entry or the like.

[0101] Although some example embodiments of the inventive concept have been specifically shown and described herein, it should be understood that various changes in form and detail may be made therein without departing from the spirit and scope of the appended claims.

Claims

1. A memory device, comprising: A first main memory is configured to store an address mapping table; at least one second main memory configured to store data received from the host device; and The memory controller is configured to compressively converting a host physical address set received from the host device into a device physical address set including a plurality of device physical addresses in the at least one second host memory, generating, based on the set of device physical addresses, at least one address mapping table entry associated with at least one device physical address subset of the set of device physical addresses, and storing the at least one address mapping table entry in the address mapping table of the first main memory, Each of the at least one address mapping table entry comprises, a header indicating a page number of an allocated page among a plurality of pages included in the first main memory or deallocation of the allocated page, a mapping table number corresponding to the host physical address set, a subset of the current device physical addresses, stored in the allocated pages, and A tail portion indicates an initial device physical address of a subsequent device physical address subset to be read after the current device physical address subset or the end of the device physical address set.

2. The memory device according to claim 1, wherein: The memory controller is further configured to: splitting the device physical address set into a plurality of device physical address subsets; and A plurality of mapping table entries are generated based on the plurality of device physical address subsets.

3. The memory device according to claim 1, wherein: The memory controller is further configured to: converting a first set of host physical addresses of a first size into a first set of device physical addresses of a second size, the second size being smaller than the first size; and First to nth address mapping table entries are generated based on the first device physical address set, the first to nth address mapping table entries each having a third size, where n is an integer greater than 1.

4. The memory device according to claim 3, wherein: The memory controller is further configured to: converting the first host physical address set to a second device physical address set of a fourth size, the fourth size being smaller than the second size; generating first to m-th address mapping table entries based on the second device physical address set, the first to m-th address mapping table entries each having the third size, wherein m is less than n; updating the mth address mapping table entry by writing information indicating the end of the second device physical address set into a tail of the mth address mapping table entry; and The m+1th to nth address mapping table entries are updated by writing information indicating deallocation into a header of each of the m+1th to nth address mapping table entries.

5. The memory device according to claim 3, wherein: The memory controller is further configured to: converting the first host-physical address set to a third device-physical address set of a fifth size, the fifth size being smaller than the first size and larger than the second size; generating first to k-th address mapping table entries based on the third device physical address set, the first to k-th address mapping table entries each having the third size, wherein k is greater than n; Allocating at least one page in the first main memory for storing the n+1th address mapping table entry to the kth address mapping table entry; and The nth address mapping table entry is updated by writing an initial device physical address of the subset of device physical addresses included in the n+1th address mapping table entry into a tail portion of the nth address mapping table entry.

6. The memory device according to claim 1, wherein: The memory controller is further configured to: generating the device physical address set based on the host physical address set; splitting the device physical address set into a plurality of device physical address subsets; generating the at least one address mapping table entry based on the plurality of device physical address subsets; as well as The at least one address mapping table entry is stored in the first main memory.

7. The memory device according to claim 1, wherein: The first main memory is included in the memory controller.

8. The memory device according to claim 1, wherein: The first main memory and the at least one second main memory are each volatile memories.

9. A method for operating a memory device, the method comprising: receiving a set of host physical addresses from a host device; compressively converting the host physical address set to a device physical address set including a plurality of device physical addresses in at least one first main memory; and generating, based on the set of device physical addresses, at least one address mapping table entry associated with at least one device physical address subset of the set of device physical addresses, Each of the at least one address mapping table entry comprises, a header indicating a page number of an allocated page among a plurality of pages included in the second main memory or deallocation of the allocated page, a mapping table number corresponding to the host physical address set, a subset of the current device physical addresses, stored in the allocated pages, and A tail portion indicates an initial device physical address of a subsequent device physical address subset to be read after the current device physical address subset or the end of the device physical address set.

10. The operating method according to claim 9, wherein: The generating the at least one address mapping table entry further comprises: splitting the device physical address set into a plurality of device physical address subsets; and A plurality of mapping table entries are generated based on the plurality of device physical address subsets.

11. The operating method according to claim 9, wherein: The compressively converting the host physical address set to the device physical address set also includes, converting a first set of host physical addresses of a first size into a first set of device physical addresses of a second size, the second size being smaller than the first size; as well as The generating the at least one address mapping table entry further comprises: First to nth address mapping table entries are generated based on the first device physical address set, the first to nth address mapping table entries each having a third size, where n is an integer greater than 1.

12. The operating method according to claim 11, wherein: The compressively converting the host physical address set to the device physical address set further comprises: after the generating the first address mapping table entry to the nth address mapping table entry, converting the first host-physical address set to a second device-physical address set of a fourth size, the fourth size being smaller than the second size; and The generating the at least one address mapping table entry further comprises: generating first to m-th address mapping table entries based on the second device physical address set, the first to m-th address mapping table entries each having the third size, writing information indicating the end of the second device physical address set into the tail of the mth address mapping table entry; and writing information indicating deallocation into the header of each of the m+1th address mapping table entry to the nth address mapping table entry, Among them, m is less than n.

13. The operating method according to claim 11, wherein: The compressively converting the host physical address set to the device physical address set further comprises: after the generating the first address mapping table entry to the nth address mapping table entry, converting the first set of host-physical addresses to a third set of device-physical addresses of a fifth size, the fifth size being smaller than the first size and larger than the second size; and The generating the at least one address mapping table entry further comprises: generating first to k-th address mapping table entries based on the third device physical address set, the first to k-th address mapping table entries each having the third size, Writing information indicating the number of pages allocated to the device physical address subset associated with the n+1th to kth address mapping table entries into the header of each of the n+1th to kth address mapping table entries writing the initial device physical address of the device physical address subset included in the n+1th address mapping table entry into the tail of the nth address mapping table entry, Among them, k is greater than n.

14. The operating method according to claim 9, further comprising: The at least one address mapping table entry is stored in the second main memory.

15. A memory device comprising: at least one memory module connected to the channel; and A controller, comprising a main memory, wherein the main memory is configured to store an address mapping table, and the controller is configured to: compressively converting a host physical address set received from a host device into a device physical address set comprising a plurality of device physical addresses in the main memory, generating, based on the set of device physical addresses, at least one address mapping table entry associated with at least one device physical address subset of the set of device physical addresses, and storing the at least one address mapping table entry in the main memory, Each of the at least one address mapping table entry comprises, a header indicating a page number of an allocated page among a plurality of pages included in the main memory or deallocation of the allocated page, a mapping table number corresponding to the host physical address set, a subset of the current device physical addresses, stored in the allocated pages, and A tail portion indicates an initial device physical address of a subsequent device physical address subset to be read after the current device physical address subset or the end of the device physical address set.

16. The memory device of claim 15, wherein: The controller is also configured to: splitting the device physical address set into a plurality of device physical address subsets; and A plurality of address mapping table entries are generated based on the plurality of device physical address subsets.

17. The memory device of claim 15, wherein: The controller is also configured to: converting a first set of host physical addresses of a first size into a first set of device physical addresses of a second size, the second size being smaller than the first size; and First to nth address mapping table entries are generated based on the first device physical address set, the first to nth address mapping table entries each having a third size, where n is an integer greater than 1.

18. The memory device of claim 17, wherein: The controller is also configured to: converting the first host physical address set to a second device physical address set of a fourth size, the fourth size being smaller than the second size; generating first to m-th address mapping table entries based on the second device physical address set, the first to m-th address mapping table entries each having the third size, wherein m is less than n; updating the mth address mapping table entry by writing information indicating the end of the second device physical address set into a tail of the mth address mapping table entry; and The m+1th to nth address mapping table entries are updated by writing information indicating deallocation into a header of each of the m+1th to nth address mapping table entries.

19. The memory device of claim 17, wherein: The controller is also configured to: converting the first host-physical address set to a third device-physical address set of a fifth size, the fifth size being smaller than the first size and larger than the second size; generating first to k-th address mapping table entries based on the third device physical address set, the first to k-th address mapping table entries each having the third size, wherein k is greater than n; Allocating at least one page in the main memory for storing the n+1th address mapping table entry to the kth address mapping table entry; and The nth address mapping table entry is updated by writing an initial device physical address of the subset of device physical addresses included in the n+1th address mapping table entry into a tail portion of the nth address mapping table entry.

20. The memory device of claim 15, wherein: The at least one memory module includes at least one volatile memory; and The main memory includes the at least one volatile memory.

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