Vector cyclic shift method and related device

Abstract

The invention provides a vector cyclic shift method, which comprises the following steps of: when carrying out cyclic shift on an original vector, firstly, determining a target register according to a data storage mode of the original vector, then, carrying out cyclic shift operation on the original vector by utilizing the target register, and in the cyclic shift operation process, carrying out cyclic shift on the original vector by utilizing the target register. And storing a plurality of first elements or a plurality of second elements in the original vector by utilizing the target registers, and performing shift operation on the plurality of first elements and the plurality of second elements by utilizing each target register based on a first direction and a second direction, so that the shift operation is performed on the plurality of first elements and the plurality of second elements. According to the method, the bit width of the target register can be fully utilized to operate a plurality of complex elements at one time, hardware resources can be fully utilized, the number of times of cyclic shift operation required in the vector cyclic shift process is reduced, and therefore the execution efficiency of vector cyclic shift is improved.

Description

Technical Field

[0001] This specification relates to the field of computer application technologies. Specifically, it relates to vector circular shift technologies in the field of computer application technologies. More specifically, it relates to a vector circular shift method and related devices. Background Art

[0002] Vector circular shift refers to moving the elements in a vector in a certain direction (usually left or right), and the elements shifted out of the end of the vector will reappear at the other end of the vector. Vector circular shift, especially complex circular vector shift, is very useful in the fields of signal processing, image processing, and cryptography, and can help implement circular buffers and perform operations such as Fourier transform.

[0003] In related technologies, the efficiency of vector circular shift largely determines the efficiency of operations such as Fourier transform. Therefore, it is necessary to improve the execution efficiency of vector circular shift and improve the performance of various operations. Summary of the Invention

[0004] Embodiments of this specification provide a vector circular shift method and related devices to achieve the purpose of improving the execution efficiency of vector circular shift.

[0005] To achieve the above technical purpose, the embodiments of this specification provide the following technical solutions:

[0006] In a first aspect, a vector circular shift method is provided. The data processing method includes:

[0007] In response to a circular shift instruction for an original vector, determine a target register according to the data storage method of the original vector; the original vector includes a plurality of complex elements arranged in sequence; the circular shift instruction carries a target quantity;

[0008] Use the target register to perform a circular shift operation on the original vector until the circular shift operation of the target quantity of complex elements in the original vector is completed to obtain a target vector; the number of target registers is multiple;

[0009] The circular shift operation includes:

[0010] Use the target register to store a plurality of first elements or a plurality of second elements in the original vector. The first elements include the complex elements in the original vector that have not been shifted starting from a first direction, and the second elements include the complex elements in the original vector that have not been shifted starting from a second direction. The first direction is different from the second direction, and the second direction includes the shift direction of the circular shift operation;

[0011] Based on the first direction and the second direction, perform a shift operation on the multiple first elements and the multiple second elements by using each of the target registers.

[0012] In combination with the first aspect, in some embodiments of the first aspect, the data storage method includes: a first method and a second method, the first method includes cross - continuous storage of real and imaginary parts, and the second method includes separate - continuous storage of real and imaginary parts;

[0013] When the data storage method of the original vector is the first method, the target register is used to store the real and imaginary parts of the first element, or to store the real and imaginary parts of the second element;

[0014] When the data storage method of the original vector is the second method, the target register is used to store at least one of the real part of the first element, the imaginary part of the first element, the real part of the second element, and the imaginary part of the second element.

[0015] In combination with the first aspect, in some embodiments of the first aspect, the multiple target registers include a first register and a second register;

[0016] When the data storage method of the original vector is the first method, the using the target register to store multiple first elements in the original vector, or multiple second elements includes:

[0017] Using the first register to store the real and imaginary parts of multiple first elements, and using the second register to store the real and imaginary parts of multiple second elements;

[0018] When the data storage method of the original vector is the second method, the first register includes a first sub - register and a second sub - register, and the second register includes a third sub - register and a fourth sub - register; the using the target register to store multiple first elements in the original vector, or multiple second elements includes:

[0019] Using the first sub - register to store the real parts of multiple first elements, using the second sub - register to store the imaginary parts of multiple first elements, using the third sub - register to store the real parts of multiple second elements, and using the fourth sub - register to store the imaginary parts of multiple second elements.

[0020] In combination with the first aspect, in some embodiments of the first aspect, the using the first register to store the real and imaginary parts of multiple first elements, and using the second register to store the real and imaginary parts of multiple second elements includes:

[0021] Use the first register to store the real and imaginary parts of A first elements, and use the second register to store the real and imaginary parts of A second elements, where A is equal to the ratio of the bit width of the first register to the first storage unit; the first storage unit includes the storage space size occupied by the complex element;

[0022] The use of the first sub-register to store the real parts of multiple first elements, the second sub-register to store the imaginary parts of multiple first elements, the third sub-register to store the real parts of multiple second elements, and the fourth sub-register to store the imaginary parts of multiple second elements includes:

[0023] Use the first sub-register to store the real parts of B first elements, the second sub-register to store the imaginary parts of B first elements, the third sub-register to store the real parts of B second elements, and the fourth sub-register to store the imaginary parts of B second elements; B is equal to the ratio of the bit width of the first sub-register to the second storage unit; the second storage unit includes the storage space size occupied by the real or imaginary part of the complex element.

[0024] Combined with the first aspect, in some embodiments of the first aspect, when the data storage mode of the original vector is the first mode, the performing a shift operation on multiple first elements and multiple second elements by using each target register based on the first direction and the second direction includes:

[0025] Store the real and imaginary parts of the first element stored in the first register at a first target position of the target vector, the first target position corresponding to the first element, the first target position including the position of the (i + K - N)-th element starting from the first direction in the target vector, the first element being the i-th element starting from the first direction in the original vector, K being the number of bits to be shifted for the original vector, and N being the number of complex elements in the original vector;

[0026] Store the real and imaginary parts of the second element stored in the first register at a second target position of the target vector, the second target position corresponding to the second element, the second target position including the position of the (j + K)-th element starting from the first direction in the target vector, the second element being the j-th element starting from the first direction in the original vector.

[0027] Combined with the first aspect, in some embodiments of the first aspect, when the data storage mode of the original vector is the second mode, the target vector includes a real part storage area and an imaginary part storage area;

[0028] Performing a shift operation on a plurality of the first elements and a plurality of the second elements by using each of the target registers based on the first direction and the second direction includes:

[0029] Storing the real part of the first element stored in the first sub-register at a third target position in a real part storage area of the target vector, where the third target position corresponds to the first element, and the third target position includes the position of the (i + K - N)-th element in the target vector starting from the first direction. The first element is the i-th element in the original vector starting from the first direction, K is the number of bits by which the original vector needs to be shifted, and N is the number of complex elements in the original vector;

[0030] Storing the imaginary part of the first element stored in the second sub-register at a fourth target position in an imaginary part storage area of the target vector, where the fourth target position corresponds to the first element, and the third target position includes the position of the (i + K - N)-th element in the target vector starting from the first direction. The first element is the i-th element in the original vector starting from the first direction, K is the number of bits by which the original vector needs to be shifted, and N is the number of complex elements in the original vector;

[0031] Storing the real part of the second element stored in the third sub-register at a fifth target position in a real part storage area of the target vector, where the fifth target position corresponds to the second element, and the fifth target position includes the position of the (j + K)-th element in the target vector starting from the first direction. The second element is the j-th element in the original vector starting from the first direction;

[0032] Storing the imaginary part of the second element stored in the fourth sub-register at a sixth target position in an imaginary part storage area of the target vector, where the sixth target position corresponds to the second element, and the sixth target position includes the position of the (j + K)-th element in the target vector starting from the first direction. The second element is the j-th element in the original vector starting from the first direction.

[0033] Combined with the first aspect, in some embodiments of the first aspect, in the cyclic shift operation, a single instruction stream multiple data stream instruction is used to operate on the first element and / or the second element.

[0034] A second aspect provides a vector cyclic shift device, including:

[0035] A register determination module, configured to determine a target register according to a data storage mode of the original vector in response to a cyclic shift instruction for the original vector; the original vector includes a plurality of sequentially arranged complex elements; the cyclic shift instruction carries a target quantity;

[0036] A cyclic shift module, configured to perform a cyclic shift operation on the original vector by using the target register until the target number of complex elements in the original vector complete the shift operation, so as to obtain a target vector; the number of the target registers is multiple;

[0037] The cyclic shift operation includes:

[0038] Storing, by using the target register, multiple first elements or multiple second elements in the original vector, where the first elements include the unshifted complex elements in the original vector starting from a first direction, the second elements include the unshifted complex elements in the original vector starting from a second direction, the first direction is different from the second direction, and the second direction includes the shift direction of the cyclic shift operation;

[0039] Performing a shift operation on the multiple first elements and the multiple second elements by using each of the target registers based on the first direction and the second direction.

[0040] Combined with the second aspect, in some embodiments of the second aspect, the data storage method includes: a first method and a second method, the first method includes cross - continuous storage of real and imaginary parts, and the second method includes separate - continuous storage of real and imaginary parts;

[0041] When the data storage method of the original vector is the first method, the target register is used to store the real and imaginary parts of the first element, or to store the real and imaginary parts of the second element;

[0042] When the data storage method of the original vector is the second method, the target register is used to store at least one of the real part of the first element, the imaginary part of the first element, the real part of the second element, and the imaginary part of the second element.

[0043] Combined with the second aspect, in some embodiments of the second aspect, the multiple target registers include a first register and a second register;

[0044] When the data storage method of the original vector is the first method, the cyclic shift module uses the target register to store multiple first elements or multiple second elements in the original vector, specifically:

[0045] Using the first register to store the real and imaginary parts of the multiple first elements, and using the second register to store the real and imaginary parts of the multiple second elements;

[0046] When the data storage mode of the original vector is the second mode, the first register includes a first sub-register and a second sub-register, and the second register includes a third sub-register and a fourth sub-register; the cyclic shift module uses the target register to store multiple first elements or multiple second elements in the original vector, specifically for:

[0047] Using the first sub-register to store the real parts of multiple first elements, using the second sub-register to store the imaginary parts of multiple first elements, using the third sub-register to store the real parts of multiple second elements, and using the fourth sub-register to store the imaginary parts of multiple second elements.

[0048] Combined with the second aspect, in some embodiments of the second aspect, the cyclic shift module uses the first register to store the real and imaginary parts of multiple first elements, and uses the second register to store the real and imaginary parts of multiple second elements, specifically for:

[0049] Using the first register to store the real and imaginary parts of A first elements, and using the second register to store the real and imaginary parts of A second elements, where A is equal to the ratio of the bit width of the first register to the first storage unit; the first storage unit includes the storage space size occupied by the complex element;

[0050] The using the first sub-register to store the real parts of multiple first elements, using the second sub-register to store the imaginary parts of multiple first elements, using the third sub-register to store the real parts of multiple second elements, and using the fourth sub-register to store the imaginary parts of multiple second elements includes:

[0051] Using the first sub-register to store the real parts of B first elements, using the second sub-register to store the imaginary parts of B first elements, using the third sub-register to store the real parts of B second elements, and using the fourth sub-register to store the imaginary parts of B second elements; B is equal to the ratio of the bit width of the first sub-register to the second storage unit; the second storage unit includes the storage space size occupied by the real or imaginary part of the complex element.

[0052] Combined with the second aspect, in some embodiments of the second aspect, when the data storage mode of the original vector is the first mode, the cyclic shift module performs a shift operation on multiple first elements and multiple second elements based on the first direction and the second direction using each target register, specifically for:

[0053] Store the real part and the imaginary part of the first element stored in the first register at a first target position of the target vector. The first target position corresponds to the first element, and the first target position includes the position of the (i + K - N)-th element starting from the first direction in the target vector. The first element is the i-th element starting from the first direction in the original vector, K is the number of bits by which the original vector needs to be shifted, and N is the number of complex elements in the original vector.

[0054] Store the real part and the imaginary part of the second element stored in the first register at a second target position of the target vector. The second target position corresponds to the second element, and the second target position includes the position of the (j + K)-th element starting from the first direction in the target vector. The second element is the j-th element starting from the first direction in the original vector.

[0055] Combined with the second aspect, in some embodiments of the second aspect, when the data storage mode of the original vector is the second mode, the target vector includes a real part storage area and an imaginary part storage area.

[0056] The cyclic shift module performs a shift operation on a plurality of the first elements and a plurality of the second elements by using each of the target registers based on the first direction and the second direction. Specifically, it is used for:

[0057] Store the real part of the first element stored in the first sub-register in the target vector at a third target position in the real part storage area. The third target position corresponds to the first element, and the third target position includes the position of the (i + K - N)-th element starting from the first direction in the target vector. The first element is the i-th element starting from the first direction in the original vector, K is the number of bits by which the original vector needs to be shifted, and N is the number of complex elements in the original vector.

[0058] Store the imaginary part of the first element stored in the second sub-register in the target vector at a fourth target position in the imaginary part storage area. The fourth target position corresponds to the first element, and the third target position includes the position of the (i + K - N)-th element starting from the first direction in the target vector. The first element is the i-th element starting from the first direction in the original vector, K is the number of bits by which the original vector needs to be shifted, and N is the number of complex elements in the original vector.

[0059] Store the real part of the second element stored in the third sub-register at the fifth target position in the real part storage area of the target vector. The fifth target position corresponds to the second element, and the fifth target position includes the position of the (j + K)-th element in the target vector starting from the first direction. The second element is the j-th element in the original vector starting from the first direction.

[0060] Store the imaginary part of the second element stored in the fourth sub-register at the sixth target position in the imaginary part storage area of the target vector. The sixth target position corresponds to the second element, and the sixth target position includes the position of the (j + K)-th element in the target vector starting from the first direction. The second element is the j-th element in the original vector starting from the first direction.

[0061] Combined with the second aspect, in some embodiments of the second aspect, in the cyclic shift operation, a single instruction stream multiple data stream instruction is used to operate on the first element and / or the second element.

[0062] In a third aspect, a computing device is provided, including a memory, a processor, and a computer program stored on the memory and executable on the processor. When the processor executes the computer program, the vector cyclic shift method described above is implemented.

[0063] In a fourth aspect, a computer-readable storage medium is provided. A computer program is stored on the computer-readable storage medium. When the computer program is executed by a processor, the vector cyclic shift method described above is implemented.

[0064] In a fifth aspect, a computer program product or a computer program is provided. The computer program product includes a computer program stored in a computer-readable storage medium. The processor of the computer device reads the computer program from the computer-readable storage medium. When the processor executes the computer program, the steps of the vector cyclic shift method described above are implemented. Optionally, the computer program can be stored in the readable storage medium or cloud of the computer device. The processor of the computer device reads the computer program from the readable storage medium or cloud.

[0065] As can be seen from the above technical solution, when the vector cyclic shift method provided by the embodiments of this specification performs cyclic shift on the original vector, first, the target register is determined according to the data storage mode of the original vector, and then the target register is used to perform the cyclic shift operation on the original vector. During the cyclic shift operation, the target register is used to store multiple first elements or multiple second elements in the original vector, and based on the first direction and the second direction, each target register is used to perform the shift operation on the multiple first elements and the multiple second elements. In this way, the bit width of the target register can be fully utilized to operate on multiple complex elements at one time, which is beneficial to fully utilize the hardware resources, reduce the number of cyclic shift operations required during the vector cyclic shift, and thus improve the execution efficiency of the vector cyclic shift. BRIEF DESCRIPTION OF THE DRAWINGS

[0066] In order to more clearly illustrate the technical solutions in the embodiments of this specification or the prior art, the following will briefly introduce the drawings required for the description of the embodiments or the prior art. Obviously, the drawings in the following description are only the embodiments of this specification. For those of ordinary skill in the art, other drawings can be obtained based on the provided drawings without creative efforts.

[0067] Figure 1 Schematic diagram of a vector cyclic right shift by k bits;

[0068] Figure 2 Schematic diagram of a vector cyclic left shift by k bits;

[0069] Figure 3 Different data storage modes in an original vector provided by the embodiments of this specification;

[0070] Figure 4 Flow chart of a vector cyclic shift method provided by the embodiments of this specification;

[0071] Figure 5 Schematic diagram of a cyclic right shift when the data storage mode in the original vector is real and imaginary parts cross - continuously stored in an embodiment of this specification;

[0072] Figure 6 Schematic diagram of a cyclic right shift when the data storage mode in the original vector is real and imaginary parts separately - continuously stored in an embodiment of this specification;

[0073] Figure 7 Schematic diagram of the comparison before and after a cyclic right shift of the original vector in an embodiment of this specification;

[0074] Figure 8A schematic diagram for comparing a raw vector before and after a cyclic left shift provided for an embodiment of this specification;

[0075] Figure 9 A schematic diagram of the structure of a computing device provided for an embodiment of this specification. Detailed implementation manners

[0076] Unless otherwise defined, technical terms or scientific terms used in the embodiments of this specification shall have the ordinary meanings understood by those of ordinary skill in the art to which this specification pertains. The terms "first", "second", and similar terms used in the embodiments of this specification do not denote any order, quantity, or importance, but are merely used to avoid confusion of components.

[0077] Unless otherwise required by the context, throughout this specification, "a plurality of" means "at least two", and "comprising" is interpreted in an open, inclusive sense, that is, "including, but not limited to". In the description of this specification, the terms "one embodiment", "some embodiments", "exemplary embodiments", "examples", "specific examples", or "some examples", etc. are intended to indicate that specific features, structures, materials, or characteristics related to the embodiment or example are included in at least one embodiment or example of this specification. The schematic representations of the above terms do not necessarily refer to the same embodiment or example.

[0078] Next, the technical solutions in the embodiments of this specification will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of this specification. Obviously, the described embodiments are only a part of the embodiments of this specification, rather than all of the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments in this specification without creative efforts shall fall within the scope of protection of this specification.

[0079] Overview

[0080] Referring to Figure 1 and Figure 2 , taking the cyclic shift of a complex vector as an example, for a complex vector A of length N: A j (A j = w j + x j i j = 0, 1, 2... N - 1) is moved a specified number of positions in a certain direction (such as left shift or right shift), and during the movement, the elements shifted out of the vector from one end will re-enter the vector from the other end, forming a cyclic effect. Suppose the above complex vector A is cyclically right shifted k times to obtain a complex vector R: R j (R j = y j + z jIf \(i, j = 0, 1, 2,\cdots,N - 1\), then in the complex vector \(R\), \(R\) 0 \(\sim R\) k―1 These \(k\) elements are the elements \(A\) in the complex vector \(A\) N―k \(\sim A\) N―1 These \(k\) elements, the \(R\) in the complex vector \(R\) k \(\sim R\) N―1 These \(N - k\) elements are the elements \(A\) in the complex vector \(A\) 0 \(\sim A\) N―k―1 These \(N - k\) elements, the above operation process is the complex vector circular shift process. For example, in Figure 1 it shows a schematic diagram of circularly shifting the complex vector \(A\) to the right by \(k\) bits to obtain the complex vector \(R\). Figure 2 it shows a schematic diagram of circularly shifting the complex vector \(A\) to the left by \(k\) bits to obtain the complex vector \(R\).

[0081] Taking the circular right shift of the complex vector \(A\) j as an example, the execution process in the related art may include:

[0082] Step S1: Store the real part \(w\) j and the imaginary part \(x\) of the first element \(A\) of the complex vector \(A\) starting from the left 0 in a register (assumed to be stored in register D0); 0 0 0 0

[0083] Step S2: Store the data stored in register D0 into the position of the \((k + 1)\)-th element of the vector \(R\) starting from the left j ;

[0084] Step S3: Store the real part \(w\) of the second element \(A\) of the complex vector \(A\) starting from the left j 1 and the imaginary part \(x\) 1 1 1 1 in a register (assumed to be stored in register D0);

[0085] Step S4: Store the data stored in register D0 into the position of the \((k + 2)\)-th element of the vector \(R\) starting from the left j ;

[0086] Step S5: And so on, repeat the above steps until the first \(N - k\) elements of the complex vector \(A\) starting from the left are copied to the positions of the \(N - k\) elements from the right in the complex vector \(R\) j j ; j

[0087] Step S6: The real part \(w\) of the \((N - k + 1)\)-th element \(A\) of the complex vector \(A\) starting from the left j N―k N―k N―k N―k and the imaginary part \(x\) N―kStored in a register (assumed to be stored in register D1);

[0088] Step S7: Store the data stored in register D1 into vector R j At the position of the first element from the left;

[0089] Step S8: For the complex vector A j From the (N - k + 2)-th element A from the left N―k+1 The real part w N―k+1 And the imaginary part x N―k Stored in a register (assumed to be stored in register D1);

[0090] Step S9: Store the data stored in register D1 into vector R j At the position of the second element from the left;

[0091] Step S10: And so on, repeat the above steps until the complex vector A j The first k elements from the right are copied to the complex vector R j At the positions of the k elements from the left.

[0092] From the above process, it can be found that in the above complex vector circular shift process, in each loop operation, only one element can be shifted and copied to the address saved in the vector after circular shift. If k elements need to be shifted, 2k loops are required, resulting in low efficiency of the vector circular shift operation.

[0093] In order to improve the efficiency of vector circular shift, the inventor found through studying the vector circular shift process in related technologies that in the vector circular shift operation in related technologies, when the data to be processed is of integer or single-precision floating-point type, only 32-bit data can be shifted each time, and when the data to be processed is of boolean or double-precision floating-point type, only 8-bit data or 64-bit data can be shifted each time. However, the bit width of registers in the current on-chip system is generally large. Taking a 128-bit register as an example, in each loop process, 32-bit data only occupies a small part of the register space, resulting in low utilization rate of the register space. If the register space can be fully utilized during the vector circular shift process to achieve parallel operation of multiple elements in the vector, the efficiency of vector circular shift can be greatly improved.

[0094] Specifically, according to the data storage method of complex elements in the vector to be shifted (hereinafter referred to as the original vector), the register required for the circular shift operation (hereinafter referred to as the target register) can be determined, specifically, the number of target registers can be determined, etc. Refer to Figure 3 The data storage method of complex elements in the original vector can include: real part and imaginary part cross-continuous storage and real part and imaginary part separated continuous storage. Combining Figure 3It can be known that if the data storage mode of the complex elements in the original vector is real-part and imaginary-part cross-continuous storage, the real parts and imaginary parts of the complex elements in the original vector can be stored in a continuous memory block (memory block 0 in Figure 3 ). In this memory block, the real parts and imaginary parts of the complex elements in the original vector are stored in adjacent positions. Between adjacent complex elements, the imaginary part (x j ) of the previous complex element is adjacent to the real part (w j+1 ) of the next complex element.

[0095] If the data storage mode of the complex elements in the original vector is real-part and imaginary-part separated continuous storage, the real parts and imaginary parts of the complex elements in the original vector can be stored in different memory blocks (memory block 1 and memory block 2 in Figure 3 ). In memory block 1, the real parts of different complex elements are stored adjacent and continuously; in memory block 2, the imaginary parts of different complex elements are stored adjacent and continuously.

[0096] To improve the moving efficiency of the original vector with different data storage modes in the cyclic shift operation, when the data storage mode of the complex elements in the original vector is real-part and imaginary-part cross-continuous storage, two target registers can be used to perform the cyclic shift operation on the original vector in parallel to improve the execution efficiency. When the data storage mode of the complex elements in the original vector is real-part and imaginary-part separated continuous storage, four target registers can be used to perform the cyclic shift operation on the original vector in parallel to improve the execution efficiency. The parallel execution logic will be specifically introduced below.

[0097] Generally speaking, when performing a cyclic shift on the original vector, the target register can be determined according to the data storage mode of the original vector, and then the cyclic shift operation is performed on the original vector by using the target register. During the cyclic shift operation, the target register is used to store multiple first elements (the complex elements in the original vector that have not been shifted starting from the first direction, and the second direction includes the shift direction of the cyclic shift operation) in the original vector, or multiple second elements (the complex elements in the original vector that have not been shifted starting from the second direction), and based on the first direction and the second direction, each target register is used to perform a shift operation on the multiple first elements and the multiple second elements. In this way, the bit width of the target register can be fully utilized to operate multiple complex elements at one time, which is beneficial to fully utilize the hardware resources, reduce the number of cyclic shift operations required during the vector cyclic shift, and thus improve the execution efficiency of the vector cyclic shift.

[0098] Based on the above concept, the embodiments of this specification provide a vector cyclic shift method, which will be described exemplarily below with reference to the accompanying drawings.

[0099] Exemplary Method

[0100] Figure 4 is a schematic flowchart of a vector cyclic shift method provided by an exemplary embodiment of this specification. This embodiment can be applied to a system on a chip, such as Figure 4 as shown, and includes the following steps:

[0101] S401: In response to a cyclic shift instruction for an original vector, determine a target register according to the data storage mode of the original vector; the original vector includes a plurality of sequentially arranged complex elements; the cyclic shift instruction carries a target quantity;

[0102] S402: Use the target register to perform a cyclic shift operation on the original vector until the target quantity of complex elements in the original vector complete the shift operation to obtain a target vector; the number of target registers is multiple;

[0103] The cyclic shift operation includes:

[0104] Use the target register to store a plurality of first elements or a plurality of second elements in the original vector. The first elements include the complex elements in the original vector that have not been shifted starting from a first direction, and the second elements include the complex elements in the original vector that have not been shifted starting from a second direction. The first direction is different from the second direction, and the second direction includes the shift direction of the cyclic shift operation;

[0105] Based on the first direction and the second direction, use each target register to perform a shift operation on the plurality of first elements and the plurality of second elements.

[0106] In this embodiment, during the cyclic shift operation of the original vector, the target register can be used to store a plurality of first elements in the original vector and perform a shift operation on the plurality of first elements based on the first direction, or the target register can be used to store a plurality of second elements in the original vector and perform a shift operation on the plurality of second elements based on the second direction, so as to achieve the purpose of parallel shifting of a plurality of complex elements during the cyclic shift operation, thereby facilitating the improvement of the execution efficiency of the cyclic shift operation. Before the shift starts, the first K complex elements in the original vector starting from the second direction can be called the second elements, and the first N - K complex elements in the original vector starting from the first direction can be called the first elements, where N is the number of complex vectors in the original vector and K is the number of bits that the original vector needs to be moved.

[0107] Specifically, refer to Figure 5, the original vector may include vector A, and the data of vector A is stored in the memory in a way that the real and imaginary parts are stored continuously in an interleaved manner. If it is desired to circularly shift vector A to the right by K bits, the shifting direction of the circular shift operation is to the right. Then, the first direction may include the direction from right to left, and the second direction may include the direction from left to right, as shown by the arrows in Figure 5 . The first elements may include the K elements starting from the right in vector A, and the second elements may include the N-K elements starting from the left in vector A, where N is the total number of elements in vector A. During the circular shift operation, the target registers may include register D0 and register D1. Register D0 is used to store multiple second elements, and register D1 is used to store multiple first elements. The number of elements stored in each target register may be determined according to the bit width of the target register and the data type of the complex elements in the original vector. For example, assuming that both register D0 and register D1 are 128-bit registers and the data type of the complex elements in the original vector A is single-precision floating-point data, then the storage space required for each real and imaginary part in the complex elements is 32 bits. In the implementation shown in Figure 5 , register D0 may be used to store the real and imaginary parts of two second elements, and register D1 may be used to store the real and imaginary parts of two first elements. After storing multiple complex elements in the target registers, based on the shifting direction of the circular shift operation, the complex elements stored in the target registers may be placed at the corresponding positions in the target vector (such as vector R), thereby completing the circular shift operation. In this way, the number of circular shift operations performed on the first elements can be reduced from K times to K / 2 times, and the number of circular shift operations performed on the second elements can be reduced from N-K times to (N-K) / 2 times, so as to achieve the purpose of reducing the required number of circular shift operations and improving the processing efficiency by improving the utilization efficiency of the target registers.

[0108] It can be understood that if the data type of the complex elements in the original vector is boolean, then the storage space required for a single real and imaginary part in the complex elements is 8 bits, and each target register can store 128 / 8 = 16 real and / or imaginary parts at a time. Similarly, when performing the operation of circularly shifting to the right / left by K bits, the number of circular shift operations performed on the first elements can be reduced from K times to K / 8 times, and the number of circular shift operations performed on the second elements can be reduced from N-K times to (N-K) / 8 times. When the space occupied by the real / imaginary part in the complex elements of the original vector is smaller, or the number of bits required for circular shifting is larger, the efficiency improvement of performing the circular shift operation using the vector circular shift method provided in the embodiments of this specification is more obvious.

[0109] In one embodiment, still referring to Figure 5, the Single Instruction Multiple Data (SIMD) instructions can be used to operate on the first element and / or the second element. Specifically, taking an ARM processor as an example, the SIMD instructions can include access instructions such as vld1q_f32, vst1q_f32, vld1_f32, vst1_f32 in the NEON intrinsics instruction set. Among them, the vld1q_f32 and vld1_f32 instructions are used to store data of different sizes in memory into registers, and the vst1q_f32 and vst1_f32 instructions are used to store data of different sizes in registers into memory. For example, in Figure 5 , the vld1q_f32 instruction can be used to store the real and imaginary parts of the first element or the second element into the target register, and the vst1q_f32 instruction can be used to store the data in the target register to the positions of the elements in the vector R in memory.

[0110] In one embodiment, when the data storage methods of the original vector are different, the data stored in the target register may change accordingly. Specifically, the data storage methods include: a first method and a second method. The first method includes cross-continuous storage of the real and imaginary parts, and the second method includes separate continuous storage of the real and imaginary parts;

[0111] When the data storage method of the original vector is the first method, the target register is used to store the real and imaginary parts of the first element, or to store the real and imaginary parts of the second element;

[0112] When the data storage method of the original vector is the second method, the target register is used to store at least one of the real part of the first element, the imaginary part of the first element, the real part of the second element, and the imaginary part of the second element.

[0113] Still referring to Figure 5 , when the data storage method of the original vector includes the first method, the target register can include register D0 and register D1. Register D0 can be used to store the real and imaginary parts of the second element, and register D1 can be used to store the real and imaginary parts of the first element.

[0114] Referring to Figure 6 , Figure 6 shows a schematic diagram of the process of circularly shifting the original vector (vector A) to the right by K bits. In Figure 6Among them, the data storage method of the original vector includes the second method. The number of target registers can be 4. These 4 registers can include register Q0, register Q1, register Q2, and register Q3. Register Q0 can be used to store the real part of the second element, register Q2 can be used for the imaginary part in the second element, register Q1 can be used to store the real part of the first element, and register Q3 can be used to store the imaginary part of the first element. In loop s0, using register Q0 and register Q2 can achieve the purpose of circularly shifting the second element to the right by K bits. In loop s1, using register Q1 and register Q3 can achieve the purpose of circularly shifting the first element to the right by K bits.

[0115] Specifically, in one embodiment, the multiple target registers include a first register and a second register;

[0116] When the data storage method of the original vector is the first method, the use of the target register to store multiple first elements or multiple second elements in the original vector includes:

[0117] Using the first register to store the real and imaginary parts of multiple first elements, and using the second register to store the real and imaginary parts of multiple second elements;

[0118] For example, refer to Figure 5 , the first register may include register D1, and the second register may include register D0.

[0119] When the data storage method of the original vector is the second method, the first register includes a first sub-register and a second sub-register, and the second register includes a third sub-register and a fourth sub-register; the use of the target register to store multiple first elements or multiple second elements in the original vector includes:

[0120] Using the first sub-register to store the real parts of multiple first elements, using the second sub-register to store the imaginary parts of multiple first elements, using the third sub-register to store the real parts of multiple second elements, and using the fourth sub-register to store the imaginary parts of multiple second elements.

[0121] For example, refer to Figure 6 , the first sub-register may include register Q1, the second sub-register may include register Q3, the third sub-register may include register Q0, and the fourth sub-register may include register Q2.

[0122] In one embodiment, the use of the first register to store the real and imaginary parts of multiple first elements, and the use of the second register to store the real and imaginary parts of multiple second elements includes:

[0123] Use the first register to store the real and imaginary parts of A first elements, and use the second register to store the real and imaginary parts of A second elements, where A is equal to the ratio of the bit width of the first register to the first storage unit; the first storage unit includes the storage space size occupied by the complex element;

[0124] It can be understood that as the circular shift operation progresses, there may be a situation in a certain loop where the remaining first elements in the original vector cannot fill the first register, or the remaining second elements in the original vector cannot fill the second register. In this case, the number of first elements stored in the first register can be less than A, and the number of second elements stored in the second register can be less than A.

[0125] The use of the first sub-register to store the real parts of multiple first elements, the second sub-register to store the imaginary parts of multiple first elements, the third sub-register to store the real parts of multiple second elements, and the fourth sub-register to store the imaginary parts of multiple second elements includes:

[0126] Use the first sub-register to store the real parts of B first elements, the second sub-register to store the imaginary parts of B first elements, the third sub-register to store the real parts of B second elements, and the fourth sub-register to store the imaginary parts of B second elements; B is equal to the ratio of the bit width of the first sub-register to the second storage unit; the second storage unit includes the storage space size occupied by the real or imaginary part of the complex element.

[0127] Similarly, as the circular shift operation progresses, there may be a situation in a certain loop where the number of real / imaginary parts of the remaining first elements in the original vector is less than B, or the number of real / imaginary parts of the remaining second elements in the original vector is less than B. At this time, the number of real / imaginary parts stored in each target register (the first sub-register to the fourth sub-register) can be less than B.

[0128] In this embodiment, a method for determining the number of real and imaginary parts of complex elements stored in each register is provided. Through this method, as much data as possible can be stored in each register, improving the utilization rate of the register and enhancing the execution efficiency of the method. It can be understood that in order to avoid data overflow in the register, when the ratio of the bit width of the first register to the first storage unit is not an integer, A can be equal to the floor result of the ratio of the bit width of the first register to the first storage unit; correspondingly, when the ratio of the bit width of the first sub-register to the second storage unit is not an integer, B can be equal to the floor result of the ratio of the bit width of the first sub-register to the second storage unit.

[0129] In one embodiment, a feasible method is provided for storing a first element and a second element from a target register to a specified position to obtain a target vector when the data storage mode of the original vector is the first mode. Specifically, performing a shift operation on a plurality of the first elements and a plurality of the second elements by using each of the target registers based on the first direction and the second direction includes:

[0130] Storing the real part and the imaginary part of the first element stored in the first register at a first target position of the target vector, the first target position corresponding to the first element, the first target position including a position of an element at the (i + K - N)-th from the first direction in the target vector, the first element being the i-th element from the first direction in the original vector, K being the number of bits to be shifted for the original vector, and N being the number of complex elements in the original vector;

[0131] Storing the real part and the imaginary part of the second element stored in the first register at a second target position of the target vector, the second target position corresponding to the second element, the second target position including a position of an element at the (j + K)-th from the first direction in the target vector, the second element being the j-th element from the first direction in the original vector.

[0132] Reference Figure 7 , assuming that the original vector includes complex elements a0 to a4 and a cyclic right shift operation of 2 bits (K = 2) needs to be performed, then in the obtained target vector, the arrangement order of the complex elements is: a3, a4, a0, a1, and a2. In the original vector, the complex elements a3 and a4 are the first elements, and a0, a1, and a2 are the second elements. Taking a0 as an example, it is the first element from the second direction in the original vector, and in the target vector, its position is the position of the 3rd (1 + 2 = 3) element. Taking a3 as an example, it is the 4th element from the second direction in the original vector, and in the target vector, its position is the position of the 1st (4 + 2 - 5 = 1) element from the second direction.

[0133] Reference Figure 8, assuming the original vector includes complex elements a0 to a4 and a cyclic left shift operation of 2 bits (K = 2) needs to be performed, then in the obtained target vector, the arrangement order of the complex elements is: a2, a3, a4, a0, and a1. In the original vector, the complex elements a0 and a1 are the second elements, and a2, a3, and a4 are the first elements. Taking a0 as an example, it is the 5th element starting from the second direction in the original vector, and in the target vector, its position is the position of the 2nd (5 + 2 - 5 = 2) element; taking a2 as an example, it is the 3rd element starting from the second direction in the original vector, and in the target vector, its position is the position of the 5th (3 + 2 = 5) element starting from the second direction.

[0134] Exemplary Apparatus

[0135] In an exemplary embodiment of the present specification, a vector cyclic shift device is further provided, including:

[0136] A register determination module, configured to respond to a cyclic shift instruction for the original vector and determine a target register according to the data storage mode of the original vector; the original vector includes a plurality of sequentially arranged complex elements; the cyclic shift instruction carries a target quantity;

[0137] A cyclic shift module, configured to use the target register to perform a cyclic shift operation on the original vector until the target quantity of complex elements in the original vector complete the shift operation to obtain a target vector; the number of the target registers is multiple;

[0138] The cyclic shift operation includes:

[0139] Using the target register to store a plurality of first elements or a plurality of second elements in the original vector, where the first elements include the complex elements in the original vector that are not shifted starting from the first direction, and the second elements include the complex elements in the original vector that are not shifted starting from the second direction, the first direction is different from the second direction, and the second direction includes the shift direction of the cyclic shift operation;

[0140] Based on the first direction and the second direction, using each of the target registers to perform a shift operation on the plurality of first elements and the plurality of second elements.

[0141] Optionally, in some embodiments, the data storage mode includes: a first mode and a second mode, the first mode includes cross - continuous storage of real and imaginary parts, and the second mode includes separate - continuous storage of real and imaginary parts;

[0142] When the data storage mode of the original vector is the first mode, the target register is used to store the real part and the imaginary part of the first element, or to store the real part and the imaginary part of the second element;

[0143] When the data storage mode of the original vector is the second mode, the target register is used to store at least one of the real part of the first element, the imaginary part of the first element, the real part of the second element, and the imaginary part of the second element.

[0144] Optionally, in some embodiments, the multiple target registers include a first register and a second register;

[0145] When the data storage mode of the original vector is the first mode, the cyclic shift module uses the target register to store multiple first elements in the original vector, or multiple second elements specifically for:

[0146] Using the first register to store the real part and the imaginary part of multiple first elements, and using the second register to store the real part and the imaginary part of multiple second elements;

[0147] When the data storage mode of the original vector is the second mode, the first register includes a first sub-register and a second sub-register, and the second register includes a third sub-register and a fourth sub-register; the cyclic shift module uses the target register to store multiple first elements in the original vector, or multiple second elements specifically for:

[0148] Using the first sub-register to store the real part of multiple first elements, using the second sub-register to store the imaginary part of multiple first elements, using the third sub-register to store the real part of multiple second elements, and using the fourth sub-register to store the imaginary part of multiple second elements.

[0149] Optionally, in some embodiments, using the first register to store the real part and the imaginary part of multiple first elements, and using the second register to store the real part and the imaginary part of multiple second elements specifically for:

[0150] Using the first register to store the real part and the imaginary part of A first elements, and using the second register to store the real part and the imaginary part of A second elements, where A is equal to the ratio of the bit width of the first register to the first storage unit; the first storage unit includes the storage space size occupied by the complex element;

[0151] Storing the real parts of a plurality of the first elements in the first sub-register, storing the imaginary parts of the plurality of the first elements in the second sub-register, storing the real parts of a plurality of the second elements in the third sub-register, and storing the imaginary parts of the plurality of the second elements in the fourth sub-register includes:

[0152] Storing the real parts of B of the first elements in the first sub-register, storing the imaginary parts of B of the first elements in the second sub-register, storing the real parts of B of the second elements in the third sub-register, and storing the imaginary parts of B of the second elements in the fourth sub-register; B is equal to the ratio of the bit width of the first sub-register to the second storage unit; the second storage unit includes the storage space size occupied by the real part or the imaginary part of the complex element.

[0153] Optionally, in some embodiments, when the data storage mode of the original vector is the first mode, the cyclic shift module performs a shift operation on a plurality of the first elements and a plurality of the second elements based on the first direction and the second direction, and specifically is used for:

[0154] Storing the real part and the imaginary part of the first element stored in the first register at a first target position of the target vector, the first target position corresponding to the first element, and the first target position including the position of the (i + K - N)-th element starting from the first direction in the target vector, where the first element is the i-th element starting from the first direction in the original vector, K is the number of bits to be shifted for the original vector, and N is the number of complex elements in the original vector;

[0155] Storing the real part and the imaginary part of the second element stored in the first register at a second target position of the target vector, the second target position corresponding to the second element, and the second target position including the position of the (j + K)-th element starting from the first direction in the target vector, where the second element is the j-th element starting from the first direction in the original vector.

[0156] Optionally, in some embodiments, when the data storage mode of the original vector is the second mode, the target vector includes a real part storage area and an imaginary part storage area;

[0157] The cyclic shift module performs a shift operation on a plurality of the first elements and a plurality of the second elements based on the first direction and the second direction, and specifically is used for:

[0158] Store the real part of the first element stored in the first sub-register at the third target position in the real part storage area of the target vector. The third target position corresponds to the first element, and the third target position includes the position of the (i + K - N)-th element in the target vector starting from the first direction. The first element is the i-th element in the original vector starting from the first direction, K is the number of bits by which the original vector needs to be shifted, and N is the number of complex elements in the original vector;

[0159] Store the imaginary part of the first element stored in the second sub-register at the fourth target position in the imaginary part storage area of the target vector. The fourth target position corresponds to the first element, and the third target position includes the position of the (i + K - N)-th element in the target vector starting from the first direction. The first element is the i-th element in the original vector starting from the first direction, K is the number of bits by which the original vector needs to be shifted, and N is the number of complex elements in the original vector;

[0160] Store the real part of the second element stored in the third sub-register at the fifth target position in the real part storage area of the target vector. The fifth target position corresponds to the second element, and the fifth target position includes the position of the (j + K)-th element in the target vector starting from the first direction. The second element is the j-th element in the original vector starting from the first direction;

[0161] Store the imaginary part of the second element stored in the fourth sub-register at the sixth target position in the imaginary part storage area of the target vector. The sixth target position corresponds to the second element, and the sixth target position includes the position of the (j + K)-th element in the target vector starting from the first direction. The second element is the j-th element in the original vector starting from the first direction.

[0162] Optionally, in some embodiments, in the cyclic shift operation, a single instruction stream multiple data stream instruction is used to operate on the first element and / or the second element.

[0163] For the specific limitations of the vector cyclic shift device, reference can be made to the limitations of the vector cyclic shift method in the above text, which will not be elaborated here. Each module in the above vector cyclic shift device can be implemented in whole or in part by software, hardware, and their combination. The above modules can be embedded in the processor of the computer device in hardware form or be independent of it, or can be stored in the memory of the computer device in software form so that the processor can call and execute the operations corresponding to the above modules.

[0164] Exemplary Computing Device

[0165] Another embodiment of this specification also proposes a computing device. Refer to Figure 9 As shown, an exemplary embodiment of this specification also provides a computing device, including: a memory and a processor. The memory stores a computer program, and when the processor executes the computer program, it executes the steps in the vector cyclic shift method according to various embodiments of this specification described in the above embodiments of this specification.

[0166] The internal structure of this computing device can be as Figure 9 As shown, this computing device includes a processor, a memory, a network interface, and an input device connected through a system bus. Among them, the processor of this computing device is used to provide computing and control capabilities. The memory of this computing device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system and a computer program. The internal memory provides an environment for the operation of the operating system and the computer program in the non-volatile storage medium. The network interface of this computing device is used to communicate with an external terminal through a network connection. When the computer program is executed by the processor, it performs the steps in the vector cyclic shift method according to various embodiments of this specification described in the above embodiments of this specification.

[0167] The processor may include a main processor and may also include a baseband chip, a modem, etc.

[0168] It can be understood that the processor in the embodiment of this specification can be an integrated circuit chip with signal processing capabilities. In the implementation process, each step of the above method embodiment can be completed by the integrated logic circuit in the hardware of the processor or the instructions in the form of software. The above-mentioned processor can be a general-purpose processor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components. It can implement or execute the various methods, steps, and logic block diagrams disclosed in the embodiments of this specification. The general-purpose processor can be a microprocessor or the processor can also be any conventional processor, etc. The steps of the method disclosed in combination with the embodiments of this specification can be directly embodied as being executed by a hardware decoding processor, or executed by a combination of hardware and software modules in the decoding processor. The software module can be located in a mature storage medium in the art such as a random access memory, a flash memory, a read-only memory, a programmable read-only memory, or an electrically erasable programmable memory, a register, etc. This storage medium is located in the memory, and the processor reads the information in the memory and combines its hardware to complete the steps of the above method.

[0169] It can be understood that the memory in the embodiments of this specification can be a volatile memory or a non-volatile memory, or can include both volatile and non-volatile memories. Among them, the non-volatile memory can be a read-only memory (ROM), a programmable read-only memory (Programmable ROM, PROM), an erasable programmable read-only memory (Erasable PROM, EPROM), an electrically erasable programmable read-only memory (EEPROM), or a flash memory. The volatile memory can be a random access memory (RAM). It should be noted that the memory of the systems and methods described herein is intended to include, but is not limited to, these and any other suitable types of memory.

[0170] The input device can include devices for receiving data and information input by the user, such as a keyboard, a mouse, a camera, a scanner, a light pen, a voice input device, a touch screen, a pedometer, or a gravity sensor, etc.

[0171] The output device can include devices for allowing information to be output to the user, such as a display screen, a printer, a speaker, etc.

[0172] The communication interface can include devices of any transceiver type for communicating with other devices or communication networks, such as Ethernet, a radio access network (RAN), a wireless local area network (WLAN), etc.

[0173] The computing device can also include a display component and a voice component. The display component can be a liquid crystal display screen or an electronic ink display screen. The input device of the computing device can be a touch layer covering the display component, or can be a button, a trackball, or a touchpad provided on the housing of the computing device, or can also be an external keyboard, a touchpad, or a mouse, etc.

[0174] Those skilled in the art can understand that Figure 9 the structure shown in

[0175] Exemplary Computer Program Product and Storage Medium

[0176] In addition to the above methods and devices, the vector cyclic shift method provided by the embodiments of this specification can also be a computer program product, which includes computer program instructions. When the computer program instructions are run by a processor, the processor is caused to execute the steps in the vector cyclic shift method according to various embodiments of this specification described in the "Exemplary Method" section above.

[0177] The above computer program product can be specifically implemented in the form of hardware, software, or a combination thereof. In an alternative embodiment, the computer program product is specifically embodied as a computer storage medium. In another alternative embodiment, the computer program product is specifically embodied as a software product, such as a Software Development Kit (SDK), etc.

[0178] The computer program product can be written in any combination of one or more programming languages to write program code for performing the operations of the embodiments of this specification. The programming languages include object-oriented programming languages such as Java, C++, etc., and also include conventional procedural programming languages such as the "C" language or similar programming languages. The program code can be executed entirely on the user's computing device, partially on the user's device, executed as an independent software package, partially on the user's computing device and partially on a remote computing device, or entirely on a remote computing device or server.

[0179] In addition, the embodiments of this specification also provide a computer-readable storage medium, on which a computer program is stored, and the computer program is executed by a processor to perform the steps in the vector cyclic shift method according to various embodiments of this specification described in the above "Exemplary Method" section.

[0180] Those of ordinary skill in the art can understand that all or part of the processes of implementing the above embodiments of the method can be completed by instructing relevant hardware through a computer program. The computer program can be stored in a non-volatile computer-readable storage medium. When the computer program is executed, it can include the processes of the embodiments of the above methods. Among them, any reference to a memory, storage, database, or other medium used in the various embodiments provided in this specification can include non-volatile and / or volatile memories. Non-volatile memories can include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), or flash memory. Volatile memories can include random access memory (RAM) or external cache memory. By way of illustration and not limitation, RAM is available in many forms, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDR SDRAM), enhanced SDRAM (ESDRAM), synchronous link (Synchlink) DRAM (SLDRAM), memory bus (Rambus) direct RAM (RDRAM), direct memory bus dynamic RAM (DRDRAM), and memory bus dynamic RAM (RDRAM), etc.

[0181] The technical features of the above embodiments can be combined arbitrarily. For the sake of brevity of description, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, it should be considered as the scope described in this specification.

[0182] The above-described embodiments merely represent several embodiments of this specification, and their descriptions are relatively specific and detailed. However, it should not be construed as a limitation on the scope of the solutions provided by the embodiments of this specification. It should be noted that for those of ordinary skill in the art, without departing from the concept of this specification, several modifications and improvements can still be made, and these all fall within the protection scope of this specification. Therefore, the protection scope of the patent of this specification shall be subject to the appended claims.

Claims

1. A vector cyclic shift method, characterized in that: The data processing method comprises: In response to a circular shift instruction for an original vector, determining a target register according to a data storage method of the original vector; the original vector includes a plurality of complex elements arranged in sequence; the circular shift instruction carries a target number; Using the target register, performing a circular shift operation on the original vector until the target number of complex elements in the original vector completes the shift operation, so as to obtain a target vector; the number of the target registers is multiple; The cyclic shift operation comprises: storing, using the target register, a plurality of first elements or a plurality of second elements in the original vector, wherein the first elements include complex elements in the original vector that have not been shifted from a first direction, and the second elements include complex elements in the original vector that have not been shifted from a second direction, wherein the first direction is different from the second direction, and the second direction includes a shift direction of the circular shift operation; Based on the first direction and the second direction, a shift operation is performed on a plurality of the first elements and a plurality of the second elements using each of the target registers.

2. The method according to claim 1, characterized in that The data storage method includes: a first method and a second method, the first method includes interleaving and continuous storage of the real part and the imaginary part, and the second method includes separate and continuous storage of the real part and the imaginary part; When the data storage mode of the original vector is the first mode, the target register is used to store the real part and the imaginary part of the first element, or is used to store the real part and the imaginary part of the second element; When the data storage mode of the original vector is the second mode, the target register is used to store at least one of the real part of the first element, the imaginary part of the first element, the real part of the second element, and the imaginary part of the second element.

3. The method according to claim 2, characterized in that The plurality of target registers include a first register and a second register; When the data storage mode of the original vector is the first mode, the storing of the plurality of first elements or the plurality of second elements in the original vector by using the target register includes: Using the first register to store a plurality of real parts and imaginary parts of the first elements, and using the second register to store a plurality of real parts and imaginary parts of the second elements; When the data storage mode of the original vector is the second mode, the first register includes a first sub-register and a second sub-register, and the second register includes a third sub-register and a fourth sub-register; the storing of the plurality of first elements or the plurality of second elements in the original vector by using the target register includes: The first subregister is used to store the real parts of the first elements, the second subregister is used to store the imaginary parts of the first elements, the third subregister is used to store the real parts of the second elements, and the fourth subregister is used to store the imaginary parts of the second elements.

4. The method according to claim 3, characterized in that The using the first register to store the real parts and the imaginary parts of the first elements, and using the second register to store the real parts and the imaginary parts of the second elements comprises: Using the first register to store A real parts and imaginary parts of the first elements, and using the second register to store A real parts and imaginary parts of the second elements, A is equal to the ratio of the bit width of the first register to the first storage unit; the first storage unit includes the storage space occupied by the complex elements; The using the first subregister to store the real parts of the plurality of first elements, using the second subregister to store the imaginary parts of the plurality of first elements, using the third subregister to store the real parts of the plurality of second elements, and using the fourth subregister to store the imaginary parts of the plurality of second elements comprises: The first subregister is used to store B real parts of the first elements, the second subregister is used to store B imaginary parts of the first elements, the third subregister is used to store B real parts of the second elements, and the fourth subregister is used to store B imaginary parts of the second elements; B is equal to the ratio of the bit width of the first subregister to the second storage unit; the second storage unit includes the storage space occupied by the real part or imaginary part of the complex element.

5. The method according to claim 3, characterized in that: When the data storage mode of the original vector is the first mode, performing a shift operation on a plurality of the first elements and a plurality of the second elements by using each of the target registers based on the first direction and the second direction includes: The real part and the imaginary part of the first element stored in the first register are stored in a first target position of the target vector, where the first target position corresponds to the first element, and the first target position includes the position of the i+KNth element in the target vector from the first direction, where the first element is the i-th element in the original vector from the first direction, K is the number of bits required to shift the original vector, and N is the number of complex elements in the original vector; The real part and the imaginary part of the second element stored in the first register are stored in a second target position of the target vector, where the second target position corresponds to the second element, and the second target position includes the position of the j+Kth element in the target vector from the first direction, and the second element is the jth element in the original vector from the first direction.

6. The method according to claim 3, characterized in that When the data storage mode of the original vector is the second mode, the target vector includes a real part storage area and an imaginary part storage area; The performing a shift operation on the plurality of the first elements and the plurality of the second elements by using each of the target registers based on the first direction and the second direction comprises: The real part of the first element stored in the first subregister is stored in the target vector and in a third target position of the real part storage area, the third target position corresponds to the first element, the third target position includes the position of the i+KNth element in the target vector from the first direction, the first element is the i-th element in the original vector from the first direction, K is the number of bits required to shift the original vector, and N is the number of complex elements in the original vector; The imaginary part of the first element stored in the second subregister is stored in the target vector, in a fourth target position of the imaginary part storage area, the fourth target position corresponds to the first element, the third target position includes the position of the i+KNth element in the target vector from the first direction, the first element is the i-th element in the original vector from the first direction, K is the number of bits required to shift the original vector, and N is the number of complex elements in the original vector; The real part of the second element stored in the third subregister is stored in the target vector, in a fifth target position of the real part storage area, the fifth target position corresponding to the second element, the fifth target position including the position of the j+Kth element from the first direction in the target vector, and the second element is the jth element from the first direction in the original vector; The imaginary part of the second element stored in the fourth subregister is stored in the target vector, in the sixth target position of the imaginary part storage area, the sixth target position corresponding to the second element, the sixth target position including the position of the j+Kth element in the target vector from the first direction, and the second element is the jth element in the original vector from the first direction.

7. The method according to claim 1, characterized in that In the circular shift operation, the first element and / or the second element are operated using a single instruction stream multiple data stream instruction.

8. A vector cyclic shift device, characterized in that: include: A register determination module, configured to determine a target register in response to a circular shift instruction for an original vector according to a data storage method of the original vector; the original vector includes a plurality of complex elements arranged in sequence; the circular shift instruction carries a target number; a circular shift module, configured to perform a circular shift operation on the original vector using the target register until the target number of complex elements in the original vector completes the shift operation to obtain a target vector; the number of the target registers is multiple; The cyclic shift operation comprises: storing, using the target register, a plurality of first elements or a plurality of second elements in the original vector, wherein the first elements include complex elements in the original vector that have not been shifted from a first direction, and the second elements include complex elements in the original vector that have not been shifted from a second direction, wherein the first direction is different from the second direction, and the second direction includes a shift direction of the circular shift operation; Based on the first direction and the second direction, a shift operation is performed on a plurality of the first elements and a plurality of the second elements using each of the target registers.

9. A computing device, characterized in that The invention comprises a memory, a processor and a computer program stored in the memory and executable on the processor, wherein the processor implements the vector circular shift method according to any one of claims 1 to 7 when executing the computer program.

10. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the vector circular shift method according to any one of claims 1 to 7 is implemented.

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