Chip design method and chip system

Abstract

The present invention belongs to the field of semiconductor technology, and specifically relates to a chip design method and a chip system. The chip design method includes: integrating a local DRAM controller, a global DRAM controller, and a shared DRAM controller on a processor core, and integrating several processor cores on a logic chip. The DRAM chips are stacked vertically on the logic chip, each global DRAM controller is connected to the shared DRAM storage space, and the shared DRAM controllers are respectively connected to their corresponding private DRAM storage spaces. The present invention directly connects to the shared DRAM storage space through the global DRAM controller, reduces the intermediate links, shortens the data path, and improves the data exchange speed. The shared DRAM controller is directly connected to the private DRAM storage space of each processor core, thereby realizing memory sharing data interaction between the processor cores.

Description

Technical Field

[0001] The present invention belongs to the field of semiconductor technology, and particularly relates to a chip design method and a chip system. Background Art

[0002] Three-dimensional DRAM technology greatly improves storage density and data access speed by vertically stacking memory cells. However, in large-scale parallel data processing scenarios, how to efficiently manage data flow and avoid bus congestion becomes a key factor restricting system performance.

[0003] Traditional data routing algorithms are unable to cope with highly concurrent access and high bandwidth requirements, especially in distributed bus architectures. The flexibility and efficiency of data routing directly affect the response speed and energy efficiency of the entire storage system. Summary of the Invention

[0004] The present invention aims to provide a chip design method and a chip system to solve the technical problem that existing data transmission paths have delays or congestion, which affects storage response speed and energy efficiency.

[0005] In order to solve the aforementioned technical problems, a first aspect of the present invention provides a chip design method, the chip design method comprising:

[0006] Integrating a local DRAM controller, a global DRAM controller connected to the local DRAM controller, and a shared DRAM controller on a processor core, integrating several of the processor cores on a logic chip, and connecting the local DRAM controllers in the logic chip;

[0007] A DRAM chip having a shared DRAM storage space and several private DRAM storage spaces is vertically stacked on the logic chip through three-dimensional stacking storage technology, each global DRAM controller is connected to the shared DRAM storage space, and each shared DRAM controller is respectively connected to the corresponding private DRAM storage space.

[0008] Optionally, in the chip design method as described above, the local DRAM controllers are connected through a NoC structure, so that the local DRAM controller of each processor core is responsible for managing its local memory access requests and working in conjunction with the local controllers of other processor cores through the NoC.

[0009] Optionally, in the chip design method as described above, a logic layer is also integrated on the logic chip, and each local DRAM controller is connected to the logic layer through an independent bus to form multiple parallel data transmission channels, allowing multiple data transmissions to be performed simultaneously.

[0010] Optionally, in the chip design method as described above, the logic layer is a CPU or an NPU.

[0011] Optionally, in the aforementioned chip design method, the chip design method further includes:

[0012] A central arbiter is designed to allocate bandwidth resources of the bus.

[0013] Optionally, in the aforementioned chip design method, the chip design method further includes:

[0014] A memory data prefetch model is integrated in the local DRAM controller, and the memory data prefetch model is used to predict future data access, and the global DRAM controller or the shared DRAM controller is used to load data from the shared DRAM storage space or the private DRAM storage space to the cache in advance.

[0015] Optionally, in the chip design method as described above, the global DRAM controller is connected to the shared DRAM storage space by using metal layer copper interconnection.

[0016] Optionally, in the chip design method as described above, the shared DRAM controller is connected to the corresponding private DRAM storage space by using metal layer copper interconnection to achieve connection.

[0017] In order to solve the aforementioned technical problem, a second aspect of the present invention provides a chip system, comprising:

[0018] A logic chip, wherein the logic chip integrates several processor cores, each of which integrates a local DRAM controller, a global DRAM controller, and a shared DRAM controller, wherein the local DRAM controllers are connected to the global DRAM controller and the shared DRAM controller, respectively, and the local DRAM controllers of the processor cores are connected to each other;

[0019] A DRAM chip is stacked vertically on the logic chip, and the DRAM chip has a shared DRAM storage space and a plurality of private DRAM storage spaces. The shared DRAM storage spaces are respectively connected to the global DRAM controller, and each private DRAM storage space is connected to a corresponding one of the shared DRAM controllers.

[0020] Optionally, in the chip system as described above, the local DRAM controllers are connected through a NoC structure, so that the local DRAM controller of each processor core is responsible for managing its local memory access requests and working in conjunction with the local controllers of other processor cores through the NoC.

[0021] Optionally, in the chip system as described above, the logic chip is further integrated with a logic layer, and each local DRAM controller is connected to the logic layer via an independent bus to form multiple parallel data transmission channels, allowing multiple data transmissions to be performed simultaneously.

[0022] Optionally, in the chip system as described above, the logic layer is a CPU or an NPU.

[0023] Optionally, in the chip system as described above, the chip system further includes:

[0024] A central arbiter is used to allocate bandwidth resources of the bus.

[0025] Optionally, in the chip system as described above, a memory data prefetch model is integrated in the local DRAM controller, and the memory data prefetch model is used to predict future data access, and the global DRAM controller or the shared DRAM controller is used to load data from the shared DRAM storage space or the private DRAM storage space to the cache in advance.

[0026] Optionally, in the chip system as described above, the global DRAM controller is connected to the shared DRAM storage space using metal layer copper interconnection.

[0027] Optionally, in the chip system as described above, the shared DRAM controller is connected to the corresponding private DRAM storage space using metal layer copper interconnection.

[0028] The positive progress effect of the present invention is:

[0029] 1. The present invention adds two DRAM controllers when the processor core has a local DRAM controller. Specifically, the global DRAM controller is directly connected to the shared DRAM storage space, which reduces the intermediate links, shortens the data path, and improves the data exchange speed. The shared DRAM controller is directly connected to the private DRAM storage space of each processor core, thereby realizing memory sharing and data interaction between processor cores.

[0030] 2. The local DRAM controller of each processor core of the present invention is connected to the logic layer through an independent high-speed bus, forming multiple parallel data transmission channels, allowing multiple data transmissions to be performed simultaneously, significantly improving data throughput.

[0031] 3. The present invention adopts a distributed memory management strategy. Each processor core has a local DRAM controller responsible for managing its local memory access requests, reducing the pressure of global arbitration. It also cooperates with the local DRAM controllers of other processor cores through NoC (Network-on-Chip) technology to ensure efficient scheduling and consistency of global memory access.

[0032] 4. The present invention uses a central arbiter design to dynamically allocate resources based on task priority, data locality, and bus idle status, ensuring efficient and orderly data access.

[0033] 5. The present invention predicts future data access through the memory data prefetch model integrated in the local DRAM controller, closely cooperates with the cache subsystem, optimizes data flow, reduces unnecessary data migration, and further improves the overall performance and response speed of the system. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] The disclosure of the present invention will become more apparent with reference to the accompanying drawings. It should be understood that these drawings are for illustrative purposes only and are not intended to limit the scope of protection of the present invention. In the drawings:

[0035] Figure 1 It is a schematic diagram of some connection relationships of the present invention;

[0036] Figure 2 A partial connection diagram of the DRAM chip and logic chip of the present invention;

[0037] Figure 3 A schematic diagram of a portion of the structure of a DRAM chip vertically stacked on a logic chip according to the present invention;

[0038] Figure 4 This is a connection block diagram of the DRAM chip and logic chip of the present invention. DETAILED DESCRIPTION

[0039] The following describes the embodiments of the present invention through specific examples. Those skilled in the art will readily understand the other advantages and benefits of the present invention from the disclosure herein. The present invention may also be implemented or applied through various other specific embodiments, and the details in this specification may be modified or altered based on different perspectives and applications without departing from the spirit of the present invention.

[0040] It should be noted that, unless there is any conflict, the following embodiments and features therein may be combined with each other.

[0041] In the description of the present invention, it should be noted that, for directional words, such as the terms "outside", "middle", "inside", "outside", etc., the directions and positional relationships indicated are based on the directions or positional relationships shown in the accompanying drawings. They are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific direction, be constructed and operated in a specific direction, and cannot be understood as limiting the specific scope of protection of the present invention.

[0042] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features. Therefore, the terms "first" and "second" may explicitly or implicitly refer to one or more of these features. Throughout the description of the present invention, "several" and "a number" mean two or more, unless otherwise specifically defined.

[0043] An embodiment of the present invention provides a chip design method, which includes:

[0044] S1, a local DRAM controller, a global DRAM controller connected to the local DRAM controller, and a shared DRAM controller connected to the local DRAM controller are integrated into a processor core, and several processor cores are integrated into a logic chip. In the logic chip, the local DRAM controllers are connected to each other.

[0045] S2, vertically stacking DRAM chips with shared DRAM storage space and several private DRAM storage spaces on the logic chip through three-dimensional stacking storage technology, connecting each global DRAM controller to the shared DRAM storage space, and connecting each shared DRAM controller to its corresponding private DRAM storage space.

[0046] In the prior art, a local DRAM controller is typically installed on the processor core to manage its local memory access requests. Building on this, the present invention integrates two additional DRAM controllers into the processor core, which are directly connected to the DRAM stacked above.

[0047] In DRAM, the present invention divides it into a shared DRAM storage space and several private DRAM storage spaces. Among them, the shared DRAM storage space is a storage space shared by all processor cores and accessible to all, and the private DRAM storage space is a storage space unique to each processor core, and each processor core cannot directly access the private DRAM storage space of other processor cores. Therefore, the two DRAM controllers of the present invention are a global DRAM controller and a shared DRAM controller, wherein the global DRAM controller is directly connected to the shared DRAM storage space, which reduces the intermediate links, shortens the data path, and improves the data exchange speed. The shared DRAM controller connects the respective unique private DRAM storage spaces to realize memory sharing data interaction between processor cores through the shared DRAM controller.

[0048] Through the above methods, the data transmission path is optimized, the delay is reduced, and the bandwidth utilization is improved, thereby significantly enhancing the overall performance of the storage system in big data processing, high-performance computing and cloud computing environments.

[0049] In some embodiments, the local DRAM controllers are connected through a NoC structure so that the local DRAM controller of each processor core is responsible for managing its local memory access requests, and works together with the local controllers of other processor cores through the NoC to ensure efficient scheduling and consistency of global memory access.

[0050] In some embodiments, a logic layer is also integrated on the logic chip, and each local DRAM controller is connected to the logic layer through an independent bus to form multiple parallel data transmission channels, allowing multiple data transmissions to be performed simultaneously, significantly improving data throughput.

[0051] In some embodiments, the logic layer is a CPU or an NPU.

[0052] In some embodiments, the chip design method further includes: designing a central arbitrator, where the central arbitrator is used to allocate bandwidth resources of the bus.

[0053] The central arbiter in this embodiment can directly adopt existing technologies. For example, the central arbiter processes bus access requests based on preset rules and real-time load information. Another example is that the central arbiter dynamically allocates resources based on at least one factor among task priority, data locality, and bus idle status, to ensure efficient and orderly data access.

[0054] In some embodiments, the chip design method also includes: integrating a memory data prefetch model in a local DRAM controller, the memory data prefetch model is used to predict future data access, and using a global DRAM controller or a shared DRAM controller to load data from a shared DRAM storage space or a private DRAM storage space to a cache in advance.

[0055] The memory data prefetching model in this embodiment can directly adopt existing technologies, such as models that use the principle of locality to predict future data access. By preloading data from DRAM to cache and closely coordinating with the cache subsystem, data flow is optimized, unnecessary data migration is reduced, and overall system performance and responsiveness are further improved.

[0056] In some embodiments, the global DRAM controller is connected to the shared DRAM storage space using metal layer copper interconnection.

[0057] In some embodiments, the shared DRAM controller is connected to the corresponding private DRAM storage space using metal layer copper interconnection.

[0058] An embodiment of the present invention further provides a chip system, which includes a logic chip and a DRAM chip, wherein the DRAM chip is vertically stacked on the logic chip using a three-dimensional stacking storage technology.

[0059] The logic chip integrates several processor cores, each of which integrates a local DRAM controller, a global DRAM controller, and a shared DRAM controller. The local DRAM controllers are connected to the global DRAM controller and the shared DRAM controller respectively, and the local DRAM controllers of each processor core are connected to each other.

[0060] The DRAM chip has a shared DRAM storage space and several private DRAM storage spaces. The shared DRAM storage spaces are connected to the global DRAM controller respectively, and each private DRAM storage space is connected to a corresponding shared DRAM controller.

[0061] like Figure 1 As shown in FIG, four processor cores in a logic chip are shown, namely a first processor core 10, a second processor core 20, a third processor core 30 and a fourth processor core 40. Of course, the logic chip can also have more or fewer processor cores. Taking four processor cores as an example,

[0062] The first processor core 10 has a first local DRAM controller 11 , a first global DRAM controller 12 and a first shared DRAM controller 13 , wherein the first local DRAM controller 11 is connected to the first global DRAM controller 12 and the first shared DRAM controller 13 .

[0063] The second processor core 20 has a second local DRAM controller 21 , a second global DRAM controller 22 and a second shared DRAM controller 23 , wherein the second local DRAM controller 21 is connected to the second global DRAM controller 22 and the second shared DRAM controller 23 .

[0064] The third processor core 30 has a third local DRAM controller 31 , a third global DRAM controller 32 and a third shared DRAM controller 33 , wherein the third local DRAM controller 31 is connected to the third global DRAM controller 32 and the third shared DRAM controller 33 .

[0065] The fourth processor core 40 has a fourth local DRAM controller 41 , a fourth global DRAM controller 42 and a fourth shared DRAM controller 43 , wherein the fourth local DRAM controller 41 is connected to the fourth global DRAM controller 42 and the fourth shared DRAM controller 43 .

[0066] Signal connections are established between the first local DRAM controller 11, the second local DRAM controller 21, the third local DRAM controller 31, and the fourth local DRAM controller 41 to enable collaborative work of the processor cores through a distributed memory management strategy, thereby ensuring efficient scheduling and consistency of global memory access.

[0067] Each of the four processor cores is assigned an independent private DRAM storage space. Specifically, the first processor core 10 corresponds to a first private DRAM storage space 51, which is connected to the first shared DRAM controller 13. The second processor core 20 corresponds to a second private DRAM storage space 52, which is connected to the second shared DRAM controller 23. The third processor core 30 corresponds to a third private DRAM storage space 53, which is connected to the third shared DRAM controller 33. The fourth processor core 40 corresponds to a fourth private DRAM storage space 54, which is connected to the fourth shared DRAM controller 43.

[0068] The four processor cores have a common shared DRAM memory space 55. The shared DRAM memory space 55 is connected to the first global DRAM controller 12, the second global DRAM controller 22, the third global DRAM controller 32, and the fourth global DRAM controller 42 respectively.

[0069] like Figure 2 and Figure 3As shown in FIG, a logic chip 6 has eight processor cores, and local DRAM controllers corresponding to the processor cores form a local DRAM controller cluster. Each local DRAM controller is connected to each storage space in the DRAM chip 7 through a shared DRAM controller or a global DRAM controller.

[0070] like Figure 4 As shown in FIG, the logic chip 6 has two processor cores, namely processor core 61 and processor core 62. The processor core 61 or processor core 62 is connected to each storage space in the DRAM chip 7 by hybrid bonding (or Hybrid Bonding).

[0071] Since the DRAM chip 7 of the present invention is vertically stacked on the logic chip 6 through three-dimensional stacking storage technology, the hybrid bonding technology is adopted, which can be well applied in the three-dimensional stacking scenario.

[0072] In some embodiments, the local DRAM controllers of each processor core are connected through a NoC structure, so that the local DRAM controller of each processor core is responsible for managing its local memory access requests, and works in coordination with the local controllers of other processor cores through the NoC to ensure efficient scheduling and consistency of global memory access.

[0073] In some embodiments, the logic chip also integrates a logic layer, and each local DRAM controller is connected to the logic layer through an independent bus to form multiple parallel data transmission channels, allowing multiple data transmissions to be performed simultaneously, significantly improving data throughput.

[0074] The chip system also includes a central arbiter, which is used to allocate bandwidth resources of the bus.

[0075] In some embodiments, the logic layer is a CPU or an NPU.

[0076] In some embodiments, a memory data prefetch model is integrated into the local DRAM controller. The memory data prefetch model is used to predict future data access and use the global DRAM controller or shared DRAM controller to load data from the shared DRAM storage space or the private DRAM storage space to the cache in advance.

[0077] In some embodiments, the global DRAM controller is connected to the shared DRAM storage space using metal layer copper interconnection.

[0078] In some embodiments, the shared DRAM controller is connected to the corresponding private DRAM storage space using metal layer copper interconnection.

[0079] The aforementioned embodiments of the present invention utilize distributed bus DRAM control technology, specifically distributing control logic within a three-dimensional stacked structure, optimizing data paths, and achieving efficient data read and write operations. This technology is particularly suitable for high-performance computing scenarios such as intelligent driving. This approach not only improves storage bandwidth and density, but also enhances the system's ability to process real-time data. The present invention utilizes an architecture that combines distributed control logic with a multi-bus design to further improve the efficiency of data read and write operations.

[0080] The present invention has been described in detail above with reference to the embodiments of the accompanying drawings. A person skilled in the art can make various modifications to the present invention based on the above description. Therefore, certain details in the embodiments should not be construed as limiting the present invention. The scope of protection of the present invention shall be determined by the scope defined in the appended claims.

Claims

1. A chip design method, characterized in that: The chip design method comprises: Integrating a local DRAM controller, a global DRAM controller connected to the local DRAM controller, and a shared DRAM controller on a processor core, integrating several of the processor cores on a logic chip, and connecting the local DRAM controllers in the logic chip; Vertically stacking DRAM chips having a shared DRAM storage space and a plurality of private DRAM storage spaces on the logic chip using a three-dimensional stacking storage technology, connecting each of the global DRAM controllers to the shared DRAM storage space, and connecting each of the shared DRAM controllers to the corresponding private DRAM storage space; The local DRAM controllers are connected to each other via a NoC structure, so that the local DRAM controller of each processor core is responsible for managing its local memory access requests and working in conjunction with the local controllers of other processor cores via the NoC; A logic layer is also integrated on the logic chip. Each local DRAM controller is connected to the logic layer via an independent bus to form multiple parallel data transmission channels, allowing multiple data transmissions to be performed simultaneously.

2. The chip design method according to claim 1, wherein: The logic layer is a CPU or an NPU; And / or, the chip design method further includes: designing a central arbitrator, wherein the central arbitrator is used to allocate bandwidth resources of the bus.

3. The chip design method according to claim 1, wherein: The chip design method further includes: A memory data prefetch model is integrated in the local DRAM controller, and the memory data prefetch model is used to predict future data access, and the global DRAM controller or the shared DRAM controller is used to load data from the shared DRAM storage space or the private DRAM storage space to the cache in advance.

4. The chip design method according to claim 1, wherein: The global DRAM controller is connected to the shared DRAM storage space by using a metal layer copper interconnection to achieve connection; The shared DRAM controller is connected to the corresponding private DRAM storage space by using metal layer copper interconnection to achieve connection.

5. A chip system, characterized in that: The chip system includes: A logic chip, wherein the logic chip integrates several processor cores, each of which integrates a local DRAM controller, a global DRAM controller, and a shared DRAM controller, wherein the local DRAM controllers are connected to the global DRAM controller and the shared DRAM controller, respectively, and the local DRAM controllers of the processor cores are connected to each other; a DRAM chip, wherein the DRAM chip is vertically stacked on the logic chip, the DRAM chip having a shared DRAM storage space and a plurality of private DRAM storage spaces, the shared DRAM storage spaces being respectively connected to the global DRAM controller, and each of the private DRAM storage spaces being connected to a corresponding one of the shared DRAM controllers; The local DRAM controllers are connected via a NoC structure; A logic layer is also integrated on the logic chip, and each of the local DRAM controllers is connected to the logic layer via an independent bus.

6. The chip system according to claim 5, wherein: The logic layer is a CPU or an NPU; And / or, the chip system further includes: a central arbitrator, wherein the central arbitrator is configured to allocate bandwidth resources of the bus.

7. The chip system according to claim 5, wherein: The local DRAM controller integrates a memory data prefetch model, which is used to predict future data access and use the global DRAM controller or the shared DRAM controller to load data from the shared DRAM storage space or the private DRAM storage space to the cache in advance.

8. The chip system according to claim 5, wherein: The global DRAM controller is connected to the shared DRAM storage space by using a metal layer copper interconnection to achieve connection; The shared DRAM controller is connected to the corresponding private DRAM storage space by using metal layer copper interconnection to achieve connection.

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