Secondary equipment loop model generation method based on CAD drawing recognition

Abstract

The invention provides a secondary equipment loop model generation method based on CAD drawing recognition, and the method comprises the following steps: S1, preprocessing an input secondary equipment CAD drawing, extracting geometric features and semantic features in the drawing, and recognizing electrical symbols and functional attributes thereof; s2, on the basis of the geometric features and the semantic features, a double-layer atlas structure of a topological atlas and a logic atlas is constructed, the topological atlas represents a physical connection relation, and the logic atlas represents an electrical logic relation; s3, conflict detection and correction are conducted on the topological graph and the logic graph through a dynamic knowledge graph, and a standardized secondary equipment loop model is generated.

Description

Technical Field

[0001] The present invention relates to the technical field of secondary circuit design of substations, and particularly relates to a method for generating a secondary equipment circuit model based on CAD drawing recognition. Background Technique

[0002] At present, there have been many studies on the secondary circuit modeling of intelligent substations in China, but the research on the modeling and panoramic visualization of the secondary full circuit (including cable circuits) of substations is still in the development stage, lacking systematic research and specific engineering application results. The secondary circuit modeling of intelligent substations is one of the current research focuses. A standardized design method for secondary circuits is proposed to standardize the design ideas and coding rules of secondary circuits, creating conditions for the implementation of new secondary operation and maintenance technologies. The "GB / T 37755-2019 Technical Specification for Secondary Circuit Modeling and Coding of Intelligent Substations" provides standardized guidance for the modeling and coding of secondary circuits. Compared with secondary circuits, the research on the modeling of secondary cable circuits in traditional substations lags behind.

[0003] Moreover, the design and display of secondary cable circuits mainly rely on the CAD drawings of design institutes, lacking effective digital models and specifications. Although there are studies proposing a secondary drawing modeling method based on the GIM standard, the existing secondary equipment circuit model generation technologies mainly rely on the following methods. First, the rule template matching method: based on a predefined symbol library and connection rules, a topological structure is generated through image matching. However, it cannot recognize non-standard symbols (such as manufacturer-customized components), and is sensitive to drawing deformation and occlusion, with a high misrecognition rate. Second, the single graph analysis method: after converting the CAD drawing into a topological graph, the connection relationship is extracted through graph traversal. However, it ignores symbol semantics and electrical logic constraints, resulting in incorrect loop attribute annotation (such as misjudging a control loop as a measurement loop), and it takes a long time to correct manually. Third, the static feature extraction method: it relies on fixed features (such as color and shape) to identify components, but it is difficult to distinguish symbols with similar functions (such as relay contacts of different models). Summary of the Invention

[0004] The purpose of the present invention is to provide a method for generating a secondary equipment circuit model based on CAD drawing recognition to solve the problems raised in the above background technique.

[0005] The present invention is realized through the following technical solutions:

[0006] A method for generating a secondary equipment circuit model based on CAD drawing recognition, the method includes the following steps:

[0007] Step S1: Preprocess the input secondary equipment CAD drawing, extract the geometric features and semantic features in the drawing, and identify the electrical symbols and their functional attributes;

[0008] Step S2: Based on the geometric features and semantic features, construct a two-layer graph structure of a topological graph and a logical graph, where the topological graph represents the physical connection relationship and the logical graph represents the electrical logical relationship;

[0009] Step S3: Use the dynamic knowledge graph to perform conflict detection and correction on the topological graph and the logical graph, and generate a standardized secondary equipment circuit model.

[0010] Optionally, the specific steps of step S1 include:

[0011] Step S1.1: Perform vectorization and denoising processing on the CAD drawing, and separate the layers and blocks;

[0012] Step S1.2: Extract the contour, line width, and connection line features of the components through the improved U-Net network of the geometric channel;

[0013] Step S1.3: Identify the text annotations in the drawing through the OCR-Robust model of the semantic channel, and parse the component functions in combination with the electrical field dictionary;

[0014] Step S1.4: Establish a dynamic symbol library, and perform similarity matching and self-learning annotation on the uncollected non-standard symbols.

[0015] Optionally, the specific steps of step S1.4 include:

[0016] Step S1.4.1: Calculate the similarity between the non-standard symbol and the symbols in the library through the siamese network;

[0017] Step S1.4.2: If the similarity is lower than the preset threshold, generate a temporary feature label and trigger manual review;

[0018] Step S1.4.3: Incrementally update the symbol features after review to the dynamic symbol library.

[0019] Optionally, the method for constructing the topological graph in step S2 includes:

[0020] Step S2.1: Calculate the node connection weight based on the improved PageRank algorithm to generate an anti-interference adjacency matrix;

[0021] Step S2.2: Use a hybrid strategy of breadth-first search and depth-first search to parse the cross lines and distinguish the real nodes from the pseudo nodes;

[0022] Step S2.3: Perform electrical rule verification on the virtual connections in the topological graph to eliminate incorrect connections.

[0023] Optionally, the specific steps of step S2.1 include:

[0024] Perform electrical rule checking on the intersection points of line segments. If an intersection point meets any of the following conditions, it is determined to be a pseudo-node:

[0025] There is no electrical connection symbol;

[0026] It does not conform to the loop topology hierarchy relationship.

[0027] Optionally, the method for constructing a logic graph in step S2 includes:

[0028] Step S2.4: Map the semantic functions of components to logical nodes, and generate logical relationship edges through a pre-set electrical rule engine;

[0029] Step S2.5: Dynamically label loop attributes according to logical relationships, including control loops, signal loops, and protection loops.

[0030] Optionally, step S3 specifically includes:

[0031] Step S3.1: Embed the topology graph and the logic graph into the domain knowledge graph, specifically including aligning the topology node embedding vectors with the knowledge graph entity vectors through the TransE model;

[0032] Step S3.2: Detect logical contradictions, including missing blocking conditions and component function conflicts;

[0033] Step S3.3: Recommend a correction plan based on reinforcement learning and generate a visual conflict report.

[0034] Compared with the prior art, the beneficial effects achieved by the present invention are as follows:

[0035] A method for generating a secondary equipment loop model based on CAD drawing recognition provided by the present invention extracts CAD drawing features through a geometric-semantic dual-channel network, constructs a topology-logic double-layer graph, and uses a dynamic knowledge graph for conflict checking, solving the technical problems of non-standard symbol recognition, virtual connection elimination, and incomplete logical annotation, and realizing the automatic and high-precision generation of secondary loop models. Brief Description of the Drawings

[0036] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following will briefly introduce the drawings required for description in the embodiments. Obviously, the drawings in the following description are only the preferred embodiments of the present invention. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0037] Figure 1 It is a flowchart of a method for generating a secondary equipment loop model based on CAD drawing recognition provided by the present invention.

[0038] Figure 2 It is a schematic diagram for the recognition of the secondary circuit schematic diagram. Specific implementation manners

[0039] In order to make the objectives, technical solutions and advantages of the present invention more obvious, exemplary embodiments according to the present invention will be described in detail below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments of the present invention. It should be understood that the present invention is not limited by the exemplary embodiments described herein. Based on the embodiments of the present invention described herein, all other embodiments obtained by those skilled in the art without creative efforts shall fall within the protection scope of the present invention.

[0040] In the following description, numerous specific details are given to provide a more thorough understanding of the present invention. However, it is obvious to those skilled in the art that the present invention may be implemented without one or more of these details. In other instances, in order to avoid confusion with the present invention, some well-known technical features are not described.

[0041] It should be understood that the present invention can be implemented in different forms and should not be construed as limited to the embodiments presented herein. On the contrary, providing these embodiments will make the disclosure thorough and complete, and will fully convey the scope of the present invention to those skilled in the art.

[0042] The purpose of the terms used herein is only to describe specific embodiments and is not a limitation of the present invention. When used herein, the singular forms "a", "an" and "the" are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms "comprising" and / or "including", when used in this specification, determine the presence of the described features, integers, steps, operations, elements and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or groups. When used herein, the term "and / or" includes any and all combinations of the related listed items.

[0043] In order to thoroughly understand the present invention, detailed structures will be presented in the following description to explain the technical solutions proposed by the present invention. The optional embodiments of the present invention are described in detail as follows. However, in addition to these detailed descriptions, the present invention may also have other implementation manners.

[0044] Refer to Figure 1 A method for generating a secondary equipment circuit model based on CAD drawing recognition, the method comprising the following steps:

[0045] Step S1: Preprocess the input CAD drawings of secondary equipment, extract the geometric features and semantic features in the drawings, and identify the electrical symbols and their functional attributes;

[0046] Step S2: Based on the geometric features and semantic features, construct a two-layer graph structure of a topological graph and a logical graph. The topological graph represents the physical connection relationship, and the logical graph represents the electrical logical relationship;

[0047] Step S3: Detect and correct conflicts in the topological graph and the logical graph through a dynamic knowledge graph, and generate a standardized secondary equipment circuit model, including a component list, connection relationships, functional attributes, logical relationships, and a corrected complete electrical diagram. This model can be used for simulation, analysis, and automatic control.

[0048] Optionally, the specific steps of Step S1 include:

[0049] Step S1.1: Perform vectorization and denoising processing on the CAD drawing, and separate the layers and blocks;

[0050] Specifically, for the vectorization process, the Douglas-Peucker algorithm based on edge detection is used to convert line segments and arcs in the CAD drawing into vector paths, and raster noise (such as burrs and breakpoints) in the scanned drawing is eliminated.

[0051] Layer separation: By parsing the layer attributes of the DXF file, separate the text layer, symbol layer, and connection line layer, and filter out decorative elements (such as borders and annotation boxes)

[0052] Step S1.2: Extract the outline, line width, and connection line features of components through an improved U-Net network in the geometric channel;

[0053] Specifically, the improved U-Net network adds a residual module (ResBlock) to the encoder of the standard U-Net. The residual connection forces the network to learn the residual (i.e., the difference) between the input and the output. This means that the network no longer needs to learn a complete mapping, but only needs to learn the residual part. This makes the network more sensitive to small changes in the input data. For small components in the binary vector map, the network can more sensitively capture subtle changes such as their outlines and line widths, so as to perform segmentation more accurately and improve the segmentation accuracy of small components (such as relay contacts); the specific input is a binary vector map, and the output is a labeled component mask (such as "KM1 coil" and "TA terminal"). Then, detect the intersection points of line segments based on the Hough transform, and combine the endpoint clustering algorithm to distinguish independent line segments and connection line clusters.

[0054] Step S1.3: Identify the text annotations in the drawing through the OCR-Robust model in the semantic channel, and parse the component functions in combination with the electrical domain dictionary;

[0055] Specifically, the OCR-Robust model adopts a Transformer-CNN hybrid network architecture to recognize skewed and blurred text (such as "NC contact" rotated 45°), and then corrects the recognition result through an electrical dictionary (such as "KM" = contactor, "TA" = current transformer) and maps it to a standard function label.

[0056] The OCR-Robust model refers to an improved version of an optical character recognition (OCR) technology. It has stronger robustness and can more accurately recognize text under various complex conditions. This model is usually optimized and trained to handle different types of image quality, font styles, background interference, etc., so as to improve the accuracy and reliability of text recognition.

[0057] Step S1.4: Establish a dynamic symbol library to perform similarity matching and self-learning annotation on uncollected non-standard symbols.

[0058] Optionally, the specific steps of step S1.4 include:

[0059] Step S1.4.1: Calculate the similarity between non-standard symbols and symbols in the library through a Siamese network;

[0060] Specifically, based on the similarity matrix for component matching, the component symbol to be matched in the secondary drawing is G1(u), and the symbol in the symbol library is G2(v). A similarity matrix S(u, v) is constructed, where the similarity between two nodes in different graphs is expressed as S(u i , v j ), and its expression is as follows:

[0061] S(u i , v j ) = 1 - exp(-||u i - v j || 2 / (2δ) 2 )

[0062] where δ is the density parameter of the function, and its value is selected between 0 and 1. In the topological process of the graph, due to the possible different reading orders of node data, the order of appearance of feature vectors is also different. Therefore, it is necessary to correct the order of symbols and feature vectors of the data. Use the above formula to calculate the similarity matrix to complete symbol matching. The matrix performs similarity matching to obtain the similarity matrix.

[0063] Step S1.4.2: If the similarity is lower than the preset threshold, generate a temporary feature label and trigger manual review;

[0064] Step S1.4.3: Incrementally update the symbol features after review to the dynamic symbol library.

[0065] Specifically, the geometric features (contour curvature, key points) of the input non-standard symbols are calculated for similarity with the symbols in the library (cosine similarity ≥ 0.7 is regarded as the same type). If the similarity is insufficient, a temporary label (such as "unknown relay - model X") is generated, and the manual review interface is triggered (highlight the symbol area and provide a list of recommended labels). After manual confirmation, the symbol feature vector is stored in the dynamic symbol library and associated with electrical rules (such as "contact type: normally open").

[0066] Optionally, the method for constructing the topological graph in step S2 includes:

[0067] Step S2.1: Calculate the node connection weights based on the improved PageRank algorithm to generate an anti-interference adjacency matrix;

[0068] Specifically, first, all component nodes and intersection nodes are regarded as vertices in the graph. If there is a directly connected line segment between two nodes (determined by the Hough transform and endpoint clustering), an edge is added between the two nodes. The initial weight of the edge can be set to 1. Different initial weights are assigned according to the type of component (for example, power supply node, key component node). During the iteration process, the electrical rule knowledge base is considered. For example, if two components should not be directly connected electrically, the connection weight between them is reduced. When connecting components with a long distance, its connection weight should be appropriately attenuated to avoid the influence of non-critical paths. Then, the improved PageRank algorithm is used to iteratively calculate the weight of each node.

[0069] The adjacency matrix is a two-dimensional array, where A[i][j] represents the connection weight between node i and node j.

[0070] Based on the node weights calculated according to the improved PageRank algorithm and the initial connection information, an adjacency matrix is generated. The value of A[i][j] represents the connection strength between node i and node j. If there is no direct connection between two nodes, the value of A[i][j] is 0.

[0071] Step S2.2: Adopt a hybrid strategy of breadth-first search and depth-first search to parse the cross lines and distinguish real nodes from pseudo nodes;

[0072] Step S2.3: Conduct electrical rule verification on the virtual connections in the topological graph to eliminate misconnections.

[0073] Specifically, rule library design: It is prohibited to directly connect across levels (for example, direct connection between the power supply layer and the signal layer requires an isolation component);

[0074] Verify the loop closure (for example, the control loop must include a coil and a contact closed path);

[0075] Virtual connection elimination: If a connection violating the rules is detected, remove it from the adjacency matrix and record an exception log.

[0076] Optionally, step S2.1 specifically includes:

[0077] Perform electrical rule verification on the line intersection points. If the intersection point meets any of the following conditions, it is determined as a pseudo-node:

[0078] No electrical connection symbol;

[0079] Does not conform to the loop topology hierarchy relationship.

[0080] Specifically, start breadth-first search from the power supply nodes (such as "L1", "N"), traverse adjacent nodes according to the electrical hierarchy (power supply layer → control layer → load layer); then supplement the scan through depth-first search. For complex loops not covered by BFS (such as self-locking loops), enable depth-first search backtracking detection to ensure full connection coverage.

[0081] The node type is determined as follows:

[0082] Real node: The intersection point of the connection line and there is an electrical symbol (such as a terminal block);

[0083] Pseudo-node: Only the line intersects but there is no symbol or annotation, filtered by rules (such as no "T" mark at the cross intersection)

[0084] mark).

[0085] Optionally, the method for constructing a logic graph in step S2 includes:

[0086] Step S2.4: Map the semantic functions of components to logic nodes, and generate logic relation edges through a preset electrical rule engine;

[0087] Specifically, preset a rule library: for example, "If the node is a coil (KM1), then the state of the downstream contact (KM1-1) is controlled by it"; generate dynamic logic edges: automatically add logic relation edges according to the component function labels (such as "KM1 coil → KM1-1 normally open contact").

[0088] Step S2.5: Dynamically label the loop attributes according to the logic relationship, including control loops, signal loops, and protection loops.

[0089] Specifically, rule matching and annotation:

[0090] Control loop: A closed path containing "coil + contact + power supply";

[0091] Signal loop: Contains sensors (such as TA) and indicating components (such as indicator lights);

[0092] Protection circuit: includes a protection relay (such as KVP) and a trip coil.

[0093] Priority setting: For a composite function circuit (such as control + protection), assign main attribute tags according to a preset priority (protection > control > signal).

[0094] Optionally, step S3 specifically includes:

[0095] Step S3.1: Embed the topology graph and the logic graph into the domain knowledge graph, specifically including aligning the topology node embedding vectors with the knowledge graph entity vectors through the TransE model; based on the CIM standard and the relay protection specification, construct a triple knowledge base including "element function", "connection rule", and "circuit type".

[0096] Step S3.2: Detect logical contradictions, including missing blocking conditions and element function conflicts;

[0097] Specifically, for logical contradiction detection:

[0098] Missing blocking: For example, the circuit breaker is not in series with an overcurrent protection contact;

[0099] Function conflict: For example, the same contact is marked as "normally open" and "normally closed" at the same time;

[0100] Circuit integrity check: Verify whether a key circuit (such as a trip circuit) contains necessary components (such as a protection relay and a trip coil).

[0101] Step S3.3: Recommend a correction plan based on reinforcement learning and generate a visual conflict report.

[0102] Specifically, define the state-action space: State, conflict type (missing blocking, function conflict), context node; Action, add virtual contacts, correct element labels, insert isolation components; Set the reward function, if the model passes the knowledge graph verification after correction, the reward is +1, otherwise the penalty is -1; Policy output: Intelligently recommend the top-3 correction plans (such as "add a KVP contact between nodes A and B").

[0103] As Figure 2 shown, this method is used to extract the connection relationship between the terminal block terminals, components and device board terminals, as well as the internal wiring and circuit schematic of the device from the secondary schematic diagram.

[0104] The above are only the preferred embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of the present invention shall be included within the scope of protection of the present invention.

Claims

1. A method for generating a secondary equipment circuit model based on CAD drawing recognition, characterized in that: The method comprises the following steps: Step S1: preprocessing the input secondary equipment CAD drawings, extracting geometric features and semantic features in the drawings, and identifying electrical symbols and their functional attributes; Step S2: Based on the geometric features and semantic features, a double-layer graph structure of a topological graph and a logical graph is constructed, wherein the topological graph represents the physical connection relationship, and the logical graph represents the electrical logic relationship; Step S3: Conflict detection and correction are performed on the topological map and the logical map through a dynamic knowledge map to generate a standardized secondary equipment loop model.

2. A method for generating a secondary equipment circuit model based on CAD drawing recognition according to claim 1, characterized in that: The step S1 specifically includes: Step S1.1: performing vectorization and denoising processing on the CAD drawing to separate layers and blocks; Step S1.2: extracting the contour, line width and connection line features of the component through the improved U-Net network of the geometric channel; Step S1.3: Recognize the text annotations in the drawings through the OCR-Robust model of the semantic channel, and combine the electrical field dictionary to parse the component function; Step S1.4: Establish a dynamic symbol library to perform similarity matching and self-learning annotation on non-standard symbols that are not included.

3. The method for generating a secondary equipment circuit model based on CAD drawing recognition according to claim 2 is characterized in that: The step S1.4 specifically includes: Step S1.4.1: Calculate the similarity between the non-standard symbol and the symbol in the library through the twin network; Step S1.4.2: If the similarity is lower than the preset threshold, a temporary feature tag is generated and a manual review is triggered; Step S1.4.3: Incrementally update the reviewed symbol features to the dynamic symbol library.

4. The method for generating a secondary equipment circuit model based on CAD drawing recognition according to claim 3 is characterized in that: The method for constructing a topological map in step S2 includes: Step S2.1: Calculate the node connection weights based on the improved PageRank algorithm and generate an anti-interference adjacency matrix; Step S2.2: Use a hybrid strategy of breadth-first search and depth-first search to parse the cross-links and distinguish between real nodes and pseudo nodes; Step S2.3: Conduct electrical rule verification on virtual connections in the topology map to eliminate incorrect connections.

5. The method for generating a secondary equipment circuit model based on CAD drawing recognition according to claim 4 is characterized in that: The step S2.1 specifically includes: Electrical rule checks are performed on the intersections of line segments. If the intersection meets any of the following conditions, it is considered a pseudo node: No electrical connection symbols; Does not comply with loop topology hierarchy.

6. A method for generating a secondary equipment circuit model based on CAD drawing recognition according to claim 5, characterized in that: The method for constructing a logic graph in step S2 includes: Step S2.4: Mapping the semantic functions of the components into logical nodes, and generating logical relationship edges through a preset electrical rule engine; Step S2.5: Dynamically label loop attributes according to logical relationships, including control loops, signal loops, and protection loops.

7. A method for generating a secondary equipment circuit model based on CAD drawing recognition according to claim 6, characterized in that: The step S3 specifically includes: Step S3.1: embedding the topological graph and the logical graph into the domain knowledge graph, specifically including aligning the topological node embedding vector with the knowledge graph entity vector through the TransE model; Step S3.2: Detecting logical contradictions, including missing blocking conditions and component function conflicts; Step S3.3: Recommend correction solutions based on reinforcement learning and generate a visual conflict report.

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