Low-power infrared intelligent sensing chip and image processing method for edge devices

Abstract

The present invention provides a low-power edge-oriented infrared intelligent sensing chip and image processing method, comprising: a transconductance amplifier circuit, which converts the photocurrent generated by the infrared detector into a voltage signal and includes a switchable reset mode and integration mode; a binary neural network simulation calculation circuit, connected to the output of the transconductance amplifier circuit, to implement analog domain multiplication and accumulation operations; a weight storage circuit, which utilizes a non-volatile memory unit and is directly hard-wired to the binary neural network simulation calculation circuit to support real-time loading of weights for the neural network calculation phase; a comparator linear activation circuit, which executes the multiplication and accumulation results at the activation output phase; and a timing control module, which dynamically coordinates the phase switching of each circuit, so that the three phases of photocurrent integration, neural network calculation, and activation output are executed sequentially to reduce the time overlap rate. The present invention provides a more intelligent, more integrated, and lower-power infrared intelligent sensing chip and image processing method.

Description

Technical Field

[0001] The present invention relates to an infrared image processing method, and in particular to an edge-oriented low-power infrared intelligent sensing chip and an image processing method. Background Art

[0002] With the rapid development of infrared technology and artificial intelligence, intelligent infrared technology is in great demand. Low-power intelligent infrared chips that can be deployed at the edge are a key development direction. However, existing infrared intelligent perception systems suffer from high power consumption, low frame rates, and slow processing speeds. Research has shown that on-chip infrared sensors can directly pre-process image information after acquiring image data. This avoids the need for subsequent high-performance processing chips, significantly reducing overall system power consumption while increasing processing speed. This on-chip pre-processing infrared intelligent visual perception architecture provides new ideas for the future deployment of infrared intelligent chips at the edge.

[0003] The implementation of infrared smart chips requires preprocessing of infrared image information. In 2016, Glauco et al. from New Mexico State University designed and published an infrared image area visual enhancement chip in the TCAS-I journal. The infrared image area was visually enhanced by changing the bias of the readout circuit. In 2016, Sechang Oh et al. from Michigan State University designed and published a low-power infrared motion detection chip at the VLSI conference. The chip used wake-up trigger technology to process infrared motion image information and achieve low-power detection. In 2024, Yanwen Su et al. from Huazhong University of Science and Technology designed and published an infrared vision-driven perception chip in the TCAS-II journal. Due to the characteristics of its visual drive circuit, the chip has an extremely high processing speed of thousands of frames.

[0004] Although the infrared smart chip with pre-processing function mentioned above is expected to be deployed in the edge infrared smart sensing system, the existing chip architecture cannot achieve a high level of power consumption, frame rate processing speed, intelligence, etc., and there is still much room for improvement:

[0005] 1) Power consumption and frame rate issues: Although existing work has achieved high levels of either power consumption or speed, both metrics cannot be simultaneously high. The following describes the power consumption and frame rate issues separately.

[0006] a) Since readout and intelligent processing introduce a large amount of static current bias circuits, the chip consumes a lot of power. As a result, infrared smart chips deployed at the edge still have problems such as not being able to work for a long time and frequent and difficult battery replacement.

[0007] b) Because existing chip architectures often convert analog image information into digital information through ADC and input it into the DSP module for processing, processing time is wasted in the process of information conversion and transmission, which makes the infrared perception speed slow and the frame rate low.

[0008] 2) Intelligence problem: The definition of intelligence is whether more information can be extracted after obtaining information. The amount of information extracted by existing work is relatively small.

[0009] a) The visual enhancement of infrared image processing chips only processes image information and does not acquire new information, so it is not intelligent enough.

[0010] b) The infrared motion detection chip can obtain information about whether an object is moving and use wake-up technology to reduce overall power consumption. This has made significant progress in power consumption, but the amount of information obtained is relatively small, with only "motion" and "non-motion" information obtained, and its intelligence is still insufficient.

[0011] c) The infrared sensing chip based on infrared vision drive uses an adaptive threshold voltage generation circuit and performs infrared intelligent perception through event-driven. Similar to the motion detection chip, it is event-driven and only obtains two types of information: whether there is an event, which is not intelligent enough. Summary of the Invention

[0012] The first object of the present invention is to provide a low-power infrared intelligent sensing chip for edge devices to address the problems in the prior art.

[0013] To this end, the above-mentioned purpose of the present invention is achieved through the following technical solutions:

[0014] Low-power infrared smart sensing chips for edge devices, including:

[0015] A transconductance amplifier circuit converts the photocurrent generated by the infrared detector into a voltage signal, including a switchable reset mode and an integration mode;

[0016] A binary neural network simulation calculation circuit is connected to the output end of the transconductance amplifier circuit to implement analog domain multiplication and accumulation operations:

[0017] Reset phase: clear the charge of the computing capacitor array through the M8 / M9 tube;

[0018] Multiplication and accumulation phase: alternately turn on the M1 / M2 tubes to complete double sampling, and synchronously drive the M3-M6 tubes driven by the weight storage circuit to import binary weights;

[0019] Full connection phase: Close the charge averaging switch to complete charge sharing and perform full connection;

[0020] The weight storage circuit uses a non-volatile memory unit to directly connect to the binary neural network simulation calculation circuit, supporting real-time acquisition of the weights of the neural network calculation phase;

[0021] Comparator linear activation circuit to quantize the multiplication and accumulation results:

[0022] Precharge: Charge the load capacitor to VDD;

[0023] Comparative quantification: Output binary classification through dynamic comparator and quantify the results;

[0024] The timing control module controls the circuit phase switching so that the three phases of photocurrent integration, neural network calculation and activation output are executed sequentially to reduce the time overlap rate.

[0025] While adopting the above technical solutions, the present invention may also adopt or combine the following technical solutions:

[0026] As a preferred technical solution of the present invention: the transconductance amplifier circuit includes:

[0027] Programmable integrating capacitor array with capacitance configuration range of 50fF-200fF;

[0028] Reset switch, clearing the charge of the integration capacitor during the reset phase;

[0029] Dynamic bias circuit, automatically adjusts the transconductance gain according to the input photocurrent intensity.

[0030] As a preferred technical solution of the present invention: the binary neural network simulation calculation circuit includes:

[0031] Double sampling switch array to eliminate MOS tube threshold voltage mismatch;

[0032] The weight control switch array is directly driven by the weight storage circuit;

[0033] Configurable computational capacitor array, supporting 4×4 to 32×32 pixel scale processing;

[0034] Charge averaging switch network to achieve fully connected operations in the analog domain.

[0035] As a preferred technical solution of the present invention, during the multiplication-accumulation phase, the binary neural network analog calculation circuit implements a dual sampling operation by alternately turning on transistors M1 and M2. When transistor M1 is turned on, the positive phase of the input voltage signal is sampled and temporarily stored in a first sampling capacitor. When transistor M2 is turned on, the negative phase signal is sampled in a second sampling capacitor, thereby eliminating errors introduced by MOS transistor threshold voltage mismatch. Simultaneously, a weight storage circuit dynamically drives the conduction combination of transistors M3-M6 based on pre-trained binary weights (+1 / -1). When the weight is +1, transistors M3 / M6 are turned on to inject the sampled charge forward into the calculation capacitor array. When the weight is -1, transistors M4 / M5 are turned on to inject the charge backward. This directly completes the multiplication-accumulation operation of "voltage sample × binary weight" in the analog domain. A hard-wired connection achieves zero-delay loading of the weights with a speed of <1ns, and the charge injection amount strictly matches the weight polarity. Ultimately, an analog voltage signal equivalent to the neural network multiplication-accumulation operation is formed on the calculation capacitor array.

[0036] As a preferred technical solution of the present invention: the comparator linear activation circuit adopts three-phase timing control to achieve efficient nonlinear activation: in the enable phase, the power switch tube completely cuts off the circuit power supply to achieve zero static power consumption; after entering the pre-charge phase, the charging network is controlled to charge the load capacitor to the VDD reference level, and the common-mode operating point is stabilized by the differential pair tube; finally, in the linear activation phase, the positive feedback comparator with an adjustable hysteresis window performs a nonlinear transformation on the input signal, and its cross-coupled transistor pair M17-M18 produces a voltage conversion characteristic similar to a Sigmoid function. At the same time, the output stage push-pull structure ensures that the rail-to-rail swing is completed within 20ns. Through the synergistic mechanism of capacitive coupling and positive feedback, while realizing the neural network activation function, the dynamic energy consumption is reduced to 0.05pJ / activation.

[0037] As a preferred technical solution of the present invention: the comparator linear activation circuit:

[0038] The activation threshold voltage is adjustable within the range of ±200mV;

[0039] Response time <20ns@0.5pF load.

[0040] A second object of the present invention is to provide an infrared image processing method to address the problems in the prior art.

[0041] To this end, the above-mentioned purpose of the present invention is achieved through the following technical solutions:

[0042] The infrared image processing method is implemented based on a low-power infrared intelligent sensing chip at the edge, and includes the following steps:

[0043] S1. Photoelectric conversion stage: The photocurrent is integrated into a voltage signal through a transconductance amplifier;

[0044] S2. Feature extraction stage: Perform binary neural network multiplication and accumulation operations in the analog domain;

[0045] S3. Linear activation stage: uses a dynamic comparator to output the classification result.

[0046] While adopting the above technical solutions, the present invention may also adopt or combine the following technical solutions:

[0047] As a preferred technical solution of the present invention: In the photoelectric conversion stage, the photocurrent generated by the infrared detector is integrated by a dynamic bias transconductance amplifier and converted into a voltage signal in the range of 0.3-0.7VDD, wherein the integral capacitor value is programmable to adapt to different lighting conditions.

[0048] As the preferred technical solution of the present invention: in the feature extraction stage, analog domain binary neural network processing is adopted, device mismatch error is eliminated through M1 / M2 tube double sampling, and the M3-M6 tube array directly driven by the weight storage circuit is combined to realize analog multiplication and accumulation operations on the calculation capacitor.

[0049] As a preferred technical solution of the present invention: in the decision output stage, the dynamic comparator is pre-charged to the VDD reference, and then uses a positive feedback comparator with an adjustable hysteresis window to complete nonlinear activation and output a binary classification result.

[0050] Compared with existing technologies, the low-power infrared intelligent sensing chip and image processing method for edge devices of the present invention have the following beneficial effects: Through innovative chip architecture and collaborative algorithms, the present invention successfully solves the problems of high power consumption restricting endurance, large data processing delays, and insufficient intelligence of traditional infrared sensing architectures in edge-side deployment of infrared intelligent sensing systems, achieving breakthrough innovation in the field of infrared intelligent sensing edge computing:

[0051] First, innovations that enhance intelligence:

[0052] The first to integrate a programmable binary neural network (BNN) analog computing unit into a single infrared sensor chip, achieving an integrated sensing-computing design. This architecture supports 32×32 pixel parallel processing and achieves fully connected analog domain computing through innovative charge sharing technology. This solves the problem that existing infrared smart chips cannot extract new information from infrared images or extract too little information, and can realize infrared handwritten digit recognition.

[0053] The computing delay is low, and the energy consumption of a single calculation is low under the same computing time;

[0054] Second, technological breakthroughs in power consumption optimization:

[0055] The dynamic bias technology of the transconductance amplifier circuit solves the problem of excessive power consumption in the photoelectric conversion link in traditional infrared sensing systems. By adopting a switchable reset / integration dual-phase operating mode, the integration phase is only activated when the photocurrent is input, avoiding the waste of continuous bias current.

[0056] By utilizing the charge domain operations of binary neural network analog computing circuits, the problem of low energy efficiency of MAC operations in the digital domain is solved: dual sampling of M1 / M2 tubes is adopted to eliminate static power consumption, multiplication and accumulation operations are performed directly in the analog domain, and the weighted direct connection architecture eliminates storage access overhead, achieving high computing energy efficiency.

[0057] The timing control module's precise phase management solves the problem of system-level static power accumulation: by powering the comparator circuit only during the activation phase and strictly isolating the three phases of integration, calculation, and activation, achieving a combined reduction in static and dynamic power consumption.

[0058] Through the above-mentioned synergistic effect, the total power consumption of single-pin processing is reduced, the energy efficiency ratio is greatly improved, and a breakthrough low-power consumption effect is achieved.

[0059] The present invention innovatively proposes a full-analog domain infrared intelligent sensing chip architecture, which achieves revolutionary innovation in edge computing through three core technological breakthroughs: first, a sensing-computing integrated design that directly couples a transconductance amplifier with a binary neural network analog computing circuit completely avoids the analog-to-digital conversion link, reducing the power consumption of photocurrent processing by an order of magnitude; second, a multiplexed dual-sampling multiplication-accumulation circuit (M1-M6 tube array) realizes binary fully connected neural network calculation in the analog domain, and the computing energy efficiency is improved by several times; finally, dynamic power consumption management is achieved through a timing control module with ns-level precision, reducing static power consumption to less than 10μW, providing a more intelligent, more integrated, and lower-power-consuming low-power infrared intelligent sensing chip and image processing method for the edge, which has great application prospects in industrial, consumer electronics and other technical fields. BRIEF DESCRIPTION OF THE DRAWINGS

[0060] Figure 1 This is a schematic diagram of the architecture of the low-power infrared intelligent sensing chip for edge devices of the present invention;

[0061] Figure 2 Schematic diagram of a binary neural network simulation calculation circuit of the present invention;

[0062] Figure 3 Schematic diagram of the weight storage circuit of the present invention;

[0063] Figure 4 Schematic diagram of the comparator linear activation circuit of the present invention. DETAILED DESCRIPTION

[0064] The present invention will be described in further detail with reference to the accompanying drawings and specific embodiments.

[0065] The low-power infrared intelligent sensing chip for edge terminals of the present invention comprises:

[0066] A transconductance amplifier circuit converts the photocurrent generated by the infrared detector into a voltage signal, including a switchable reset mode and an integration mode;

[0067] A binary neural network simulation calculation circuit is connected to the output end of the transconductance amplifier circuit to implement analog domain multiplication and accumulation operations:

[0068] Reset phase: clear the charge of the computing capacitor array through the M8 / M9 tube;

[0069] Multiplication and accumulation phase: alternately turn on the M1 / M2 tubes to complete double sampling, and synchronously drive the M3-M6 tubes driven by the weight storage circuit to import binary weights;

[0070] Full connection phase: Close the charge averaging switch to complete charge sharing and perform full connection;

[0071] The weight storage circuit uses a non-volatile memory unit to directly connect to the binary neural network simulation calculation circuit, supporting real-time acquisition of the weights of the neural network calculation phase;

[0072] Comparator linear activation circuit to quantize the multiplication and accumulation results:

[0073] Precharge: Charge the load capacitor to VDD;

[0074] Comparative quantification: Output binary classification through dynamic comparator and quantify the results;

[0075] The timing control module controls the circuit phase switching so that the three phases of photocurrent integration, neural network calculation and activation output are executed sequentially to reduce the time overlap rate.

[0076] The transconductance amplifier circuit comprises:

[0077] Programmable integrating capacitor array with capacitance configuration range of 50fF-200fF;

[0078] Reset switch, clearing the charge of the integration capacitor during the reset phase;

[0079] Dynamic bias circuit, automatically adjusts the transconductance gain according to the input photocurrent intensity.

[0080] The binary neural network simulation calculation circuit includes:

[0081] Double sampling switch array to eliminate MOS tube threshold voltage mismatch;

[0082] The weight control switch array is directly driven by the weight storage circuit;

[0083] Configurable computational capacitor array, supporting 4×4 to 32×32 pixel scale processing;

[0084] Charge averaging switch network to achieve fully connected operations in the analog domain.

[0085] During the multiplication-accumulation phase, the binary neural network analog calculation circuit implements dual sampling by alternately turning on transistors M1 and M2. When transistor M1 is turned on, the positive phase of the input voltage signal is sampled and temporarily stored in a first sampling capacitor. When transistor M2 is turned on, the negative phase signal is sampled in a second sampling capacitor to eliminate errors introduced by MOS transistor threshold voltage mismatch. Simultaneously, the weight storage circuit dynamically drives the conduction combination of transistors M3-M6 based on pre-trained binary weights (+1 / -1). When the weight is +1, transistors M3 / M6 are turned on to inject the sampled charge forward into the calculation capacitor array. When the weight is -1, transistors M4 / M5 are turned on to inject the charge in the reverse direction. This directly completes the multiplication-accumulation operation of "voltage sample × binary weight" in the analog domain. Through hardwiring, zero-delay loading of the weights is achieved with a speed of <1ns, and the charge injection amount is strictly matched to the weight polarity. Ultimately, an analog voltage signal equivalent to the neural network multiplication-accumulation operation is generated on the calculation capacitor array.

[0086] The comparator linear activation circuit uses three-phase timing control to achieve efficient nonlinear activation: in the enable phase, the power switch tube completely cuts off the circuit power supply to achieve zero static power consumption; after entering the pre-charge phase, the charging network is controlled to charge the load capacitor to the VDD / 2 reference level, and the common-mode operating point is stabilized through the differential pair tube; finally, in the linear activation phase, the positive feedback comparator with an adjustable hysteresis window performs a nonlinear transformation on the input signal, and its cross-coupled transistor pair M17-M18 generates a Sigmoid function-like voltage conversion characteristic. At the same time, the output stage push-pull structure ensures rail-to-rail swing within 20ns. Through the synergistic mechanism of capacitive coupling and positive feedback, the dynamic energy consumption is reduced to 0.05pJ per activation while implementing the neural network activation function.

[0087] As a preferred technical solution of the present invention: the comparator linear activation circuit:

[0088] The activation threshold voltage is adjustable within the range of ±200mV;

[0089] Response time <20ns@0.5pF load.

[0090] The present invention provides an infrared image processing method, which is implemented based on a low-power infrared intelligent sensing chip at the edge, comprising the following steps:

[0091] S1. Photoelectric conversion stage: The photocurrent is integrated into a voltage signal through a transconductance amplifier;

[0092] S2. Feature extraction stage: Perform binary neural network multiplication and accumulation operations in the analog domain;

[0093] S3. Linear activation stage: uses a dynamic comparator to output the classification result.

[0094] In the photoelectric conversion stage, the photocurrent generated by the infrared detector is integrated and processed by a dynamic bias transconductance amplifier and converted into a voltage signal in the range of 0.3-0.7VDD. The integration capacitor value is programmable to adapt to different lighting conditions.

[0095] In the feature extraction stage, analog domain binary neural network processing is adopted to eliminate device mismatch errors through M1 / M2 tube double sampling, and the M3-M6 tube array directly driven by the weight storage circuit is used to realize analog multiplication and accumulation operations on the calculation capacitor.

[0096] In the decision output stage, the dynamic comparator is precharged to the VDD / 2 reference, and then uses a positive feedback comparator with an adjustable hysteresis window to complete nonlinear activation and output a binary classification result.

[0097] The low-power infrared intelligent sensing chip and image processing method for the edge of the present invention significantly improves the intelligence of the infrared intelligent system and reduces power consumption, making it more conducive to deployment in edge devices and scenarios. After simulation on EDA simulation software platforms such as Cadence Virtuoso, the chip architecture can realize the calculation of a layer of binary fully connected neural network. The calculation result can be used as the output result of the first layer of infrared image classification. The power consumption is 2-3 orders of magnitude lower than that of other infrared sensing systems. Compared with other infrared chips and systems, it has higher intelligence, higher integration and lower power consumption:

[0098] 1. A new architecture for the all-analog infrared intelligent sensing chip: This eliminates the need for analog-to-digital converters, effectively reducing overall power consumption. This also reduces conversion time and improves processing speed and frame rate.

[0099] 2. On-chip infrared image recognition is achieved by designing a reused dual-sampling multiplication-accumulation fully connected neural network computing unit circuit.

[0100] Example 1

[0101] In order to better deploy intelligent infrared vision perception chips at the edge, the present invention proposes a low-power infrared intelligent perception chip for the edge for the first time, and provides a low-power infrared intelligent perception chip architecture. Figure 1As shown. The architecture includes a transconductance amplifier circuit, a binary neural network simulation calculation circuit, a weight storage circuit, and a comparator linear activation circuit. The working mode of this architecture is: the infrared detector detects the infrared image information and converts the radiation information into photocurrent through the photoelectric effect, and then inputs the photocurrent into the infrared vision intelligent perception chip. First, it passes through the transconductance amplifier circuit. The transconductance amplifier has two working phases. When the photocurrent is not input, the reset phase switch is closed. When the photocurrent is input, the transconductance amplifier enters the integration phase. The photocurrent will be integrated on the integration capacitor to linearly convert the current signal into a voltage signal. The voltage signal is input into the binary neural network simulation calculation circuit, as shown Figure 2 As shown in the figure, the circuit has three working phases: reset phase, multiplication and accumulation calculation phase, and full connection phase. Reset phase: Before starting the calculation, the reset phase is first performed. The M8 and M9 tubes are turned on to clear and reset the charge of the calculation capacitor array. Multiplication and accumulation calculation phase: The read voltage signal is input into the calculation circuit. The M1 and M2 tubes will be turned on in turn to perform double sampling of the voltage signal. At the same time, the weight storage unit, such as Figure 3 As shown, the weight signal of the entire network will be directly connected to the binary neural network simulation calculation circuit to save the time and power consumption of read and write transmission. The weight signal will turn on the M3 tube, M4 tube, M5 tube, and M6 tube according to the trained network weight, and import its double-sampled signals into the calculation capacitor array respectively. Because the double sampling operation and the binary neural network are similar in mathematical form. Therefore, this step realizes the first layer of multiplication and accumulation operation of the binary neural network. Fully connected phase: After the signals of all pixels are input into the calculation capacitor array through the sampling switch, the charge averaging switch will be closed for full connection to average the charge. After the calculation is completed, the calculation result will be output to the comparator linear activation circuit, as shown Figure 4 As shown in Figure 1, this circuit has three operating phases: the enable phase, the precharge phase, and the linear activation phase. The enable phase: When calculations are not complete, the enable signal shuts down the module to save power. The precharge phase: When calculations are about to complete, the circuit is charged to prepare for the subsequent linear activation comparison. The linear activation phase: The calculated results are linearly activated, pulling larger values ​​to a high level and smaller values ​​to a low level. Finally, the activation results are output to off-chip processing.

[0102] This invention significantly improves the intelligence of infrared intelligent systems and reduces power consumption, making them more suitable for deployment in edge devices and scenarios. Simulations using EDA simulation software platforms such as Cadence Virtuoso have shown that this chip architecture can implement the calculation of a single-layer binary fully connected neural network. The calculation results can be used as the output of the first layer of infrared image classification. The power consumption is 2-3 orders of magnitude lower than that of other infrared sensing systems. Compared with other infrared chips and systems, it has higher intelligence, higher integration, and lower power consumption:

[0103] 1. A new architecture for the all-analog infrared intelligent sensing chip: This eliminates the need for analog-to-digital converters, effectively reducing overall power consumption. This also reduces conversion time and improves processing speed and frame rate.

[0104] 2. On-chip infrared image recognition is achieved by designing a reused dual-sampling multiplication-accumulation fully connected neural network computing unit circuit.

[0105] The above-mentioned specific implementation methods are used to illustrate the present invention and are only preferred embodiments of the present invention, rather than limiting the present invention. Any modifications, equivalent substitutions, improvements, etc. made to the present invention within the spirit of the present invention and the scope of protection of the claims shall fall within the scope of protection of the present invention.

Claims

1. Low-power infrared intelligent sensing chip for edge devices, characterized by: include: A transconductance amplifier circuit converts the photocurrent generated by the infrared detector into a voltage signal, including a switchable reset mode and an integration mode; A binary neural network simulation calculation circuit is connected to the output end of the transconductance amplifier circuit to implement analog domain multiplication and accumulation operations: Reset phase: clear the charge of the computing capacitor array through the M8 / M9 tube; Multiplication and accumulation phase: alternately turn on the M1 / M2 tubes to complete double sampling, and synchronously drive the M3-M6 tubes driven by the weight storage circuit to import binary weights; Full connection phase: Close the charge averaging switch to complete charge sharing and perform full connection; The weight storage circuit uses a non-volatile memory unit to directly connect to the binary neural network simulation calculation circuit, supporting real-time acquisition of the weight of the neural network calculation phase; Comparator linear activation circuit to quantize the multiplication and accumulation results: Precharge: Charge the load capacitor to VDD; Comparative quantification: Output binary classification through dynamic comparator and quantify the results; The timing control module controls the circuit phase switching so that the three phases of photocurrent integration, neural network calculation and activation output are executed sequentially to reduce the time overlap rate.

2. The low-power infrared intelligent sensing chip for edge devices according to claim 1, characterized in that: The transconductance amplifier circuit comprises: Programmable integrating capacitor array with capacitance configuration range of 50fF-200fF; Reset switch, clearing the charge of the integration capacitor during the reset phase; Dynamic bias circuit, self-regulating transconductance gain according to input photocurrent intensity.

3. The low-power infrared intelligent sensing chip for edge devices according to claim 1, characterized in that: The binary neural network simulation calculation circuit includes: Double sampling switch array to eliminate MOS tube threshold voltage mismatch; The weight control switch array is directly driven by the weight storage circuit; Configurable computational capacitor array, supporting 4×4 to 32×32 pixel scale processing; Charge averaging switch network to achieve fully connected operations in the analog domain.

4. The low-power infrared intelligent sensing chip for edge devices according to claim 1, characterized in that: During the multiplication-accumulation phase, the binary neural network analog calculation circuit implements a dual sampling operation by alternately turning on M1 / M2 transistors. When M1 is turned on, the positive phase of the input voltage signal is sampled and temporarily stored in a first sampling capacitor. When M2 is turned on, the negative phase signal is sampled in a second sampling capacitor to eliminate errors introduced by MOS transistor threshold voltage mismatch. Synchronously, the weight storage circuit dynamically drives the conduction combination of M3-M6 transistors based on a pre-trained binary weight of +1 / -1. When the weight is +1, M3 / M6 transistors are turned on to inject the sampled charge forward into the calculation capacitor array. When the weight is -1, M4 / M5 transistors are turned on to inject the charge in the reverse direction. This directly completes the multiplication-accumulation operation of "voltage sample × binary weight" in the analog domain. Through hardwiring, zero-delay loading of the weights is achieved with a speed of <1ns, and the charge injection amount is strictly matched to the weight polarity. Ultimately, an analog voltage signal equivalent to the neural network multiplication-accumulation operation is formed on the calculation capacitor array.

5. The low-power infrared intelligent sensing chip for edge devices according to claim 1, characterized in that: The comparator linear activation circuit adopts three-phase timing control to achieve efficient nonlinear activation: in the enable phase, the power switch tube completely cuts off the circuit power supply to achieve zero static power consumption; After entering the pre-charge phase, the charging network is controlled to charge the load capacitor to the VDD / 2 reference level and stabilize the common-mode operating point through the differential pair transistors. Finally, in the linear activation phase, the positive feedback comparator with an adjustable hysteresis window performs a nonlinear transformation on the input signal. Its cross-coupled transistor pair M17-M18 produces a voltage conversion characteristic similar to a Sigmoid function. At the same time, the output stage push-pull structure ensures rail-to-rail swing within 20ns. Through the synergistic mechanism of capacitive coupling and positive feedback, the dynamic energy consumption is reduced to 0.05pJ / activation while realizing the neural network activation function.

6. The low-power infrared intelligent sensing chip for edge devices according to claim 5, characterized in that: The comparator linear activation circuit: The activation threshold voltage is adjustable within the range of ±200mV; Response time <20ns@0.5pF load.

7. An infrared image processing method, implemented on a low-power infrared intelligent sensing chip at the edge based on any one of claims 1-6, comprising the steps of: S1. Photoelectric conversion stage: integrating the photocurrent into a voltage signal via a transconductance amplifier; S2. Feature extraction stage: Perform binary neural network multiplication and accumulation operations in the analog domain; S3. Linear activation stage: uses a dynamic comparator to output the classification result.

8. The infrared image processing method according to claim 7, wherein: In the photoelectric conversion stage, the photocurrent generated by the infrared detector is integrated and processed by a dynamic bias transconductance amplifier and converted into a voltage signal in the range of 0.3-0.7VDD. The integration capacitor value is programmable to adapt to different lighting conditions.

9. The infrared image processing method according to claim 7, wherein: In the feature extraction stage, analog domain binary neural network processing is adopted to eliminate device mismatch errors through M1 / M2 tube double sampling, and the M3-M6 tube array directly driven by the weight storage circuit is used to realize analog multiplication and accumulation operations on the calculation capacitor.

10. The infrared image processing method according to claim 7, wherein: In the decision output stage, the dynamic comparator is pre-charged to the VDD reference, and then uses a positive feedback comparator with an adjustable hysteresis window to complete nonlinear activation and output a binary classification result.

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