Pixel

Abstract

The present disclosure provides a pixel. The pixel includes: a first transistor including a first electrode connected to a first node, a second electrode connected to a second node, and a gate electrode connected to a third node; a second transistor connected between the data line and a third node, and including a gate electrode electrically connected to the first sub-gate line; a third transistor connected between a first power line configured to supply the first power voltage and the first node, and including a gate electrode electrically connected to the emission control line; a first capacitor connected between the first node and the third node; and a light emitting element connected between the second node and a second power line configured to supply a second power voltage.

Description

[0001] Cross - reference to related applications

[0002] This application claims the priority and benefit of Korean Patent Application No. 10 - 2023 - 0174691, filed with the Korean Intellectual Property Office on December 5, 2023, the entire disclosure of which is incorporated herein by reference. Technical field

[0003] Various embodiments of the present disclosure relate to pixels and a display device including the pixels. Background art

[0004] With the development of information technology, the importance of display devices as a connection medium between users and information has increased. Due to the importance of display devices, the use of various display devices such as liquid crystal display devices and organic light - emitting display devices has increased.

[0005] Recently, head - mounted display devices (HMDs) have been developed. A head - mounted display device (HMD) is a display device that allows a user to wear in the form of glasses or a helmet and is used to create a virtual reality (VR) experience or an augmented reality (AR) experience, in which the focus is formed at a short distance in front of the user's eyes. The head - mounted display device employs a high - resolution panel and uses pixels that can be applied to the high - resolution panel. Summary of the invention

[0006] Various embodiments of the present disclosure relate to pixels applicable to a high - resolution panel and a display device including the pixels.

[0007] One or more embodiments of the present disclosure may provide a pixel including: a first transistor including a first electrode connected to a first node, a second electrode connected to a second node, and a gate electrode connected to a third node; a second transistor connected between a data line and the third node and including a gate electrode electrically connected to a first sub - gate line; a third transistor connected between a first power line configured to supply a first power voltage and the first node and including a gate electrode electrically connected to an emission control line; a first capacitor connected between the first node and the third node; and a light - emitting element connected between the second node and a second power line configured to supply a second power voltage.

[0008] During an emission period in which the light - emitting element is configured to emit light with a brightness corresponding to the current supplied from the first transistor, the second power voltage may be configured to have a first voltage level, wherein during a data - writing period before the emission period, the second power voltage is configured to have a second voltage level higher than the first voltage level.

[0009] A single frame period may include an initialization period, a compensation period, a data writing period, and a transmission period. During the data writing period, the third transistor is configured to be set in an off state, the first transistor and the second transistor are configured to be set in an on state, and a data signal having a data voltage level is configured to be supplied to the data line.

[0010] During the transmission period after the data writing period, the second transistor may be configured to be set in an off state, the first transistor and the third transistor may be configured to be set in an on state, and a data signal having a reference voltage level lower than the data voltage level may be configured to be supplied to the data line.

[0011] The reference voltage level may be lower than the voltage level of the first power voltage and higher than the first voltage level.

[0012] During the compensation period before the data writing period, the third transistor may be configured to be set in an off state, the first transistor and the second transistor may be configured to be set in an on state, a data signal having a reference voltage level may be configured to be supplied to the data line, and the second power voltage is configured to have a second voltage level.

[0013] During the initialization period before the compensation period, the first transistor, the second transistor, and the third transistor may be configured to be set in an on state, a data signal having a reference voltage level may be configured to be supplied to the data line, and the second power voltage may be configured to have a first voltage level.

[0014] The first capacitor may include a metal-insulator-metal (MIM) capacitor.

[0015] The first capacitor may include a metal oxide semiconductor (MOS) capacitor.

[0016] The pixel may further include a second capacitor connected between the first node and the third node.

[0017] The first capacitor may include a metal-insulator-metal (MIM) capacitor, and the second capacitor includes a metal oxide semiconductor (MOS) capacitor.

[0018] The first voltage level and the second voltage level may be lower than the voltage level of the first power voltage.

[0019] One or more embodiments of the present disclosure may provide a display device including pixels connected to gate lines, data lines, and emission control lines. Among them, one of the plurality of pixels at the i-th pixel row and the j-th pixel column (i and j are integers) includes: a first transistor including a first electrode connected to a first node, a second electrode connected to a second node, and a gate electrode connected to a third node; a second transistor connected between the j-th data line among the plurality of data lines and the third node, and configured to receive a gate signal through the i-th gate line among the plurality of gate lines; a third transistor connected between the first node and a first power line configured to supply a first power voltage, and configured to receive an emission control signal through the i-th emission control line among the plurality of emission control lines; a first capacitor connected between the first node and the third node; and a light-emitting element connected between the second node and a second power line configured to supply a second power voltage.

[0020] During an emission period in which the light-emitting element is configured to emit light with a brightness corresponding to the current supplied from the first transistor, the second power voltage may be configured to have a first voltage level. During a data writing period before the emission period, the second power voltage is configured to have a second voltage level higher than the first voltage level.

[0021] A single frame period may include an initialization period, a compensation period, a data writing period, and an emission period. During the data writing period, a gate signal for setting the second transistor to an on state is configured to be supplied to the i-th gate line, an emission control signal for setting the third transistor to an off state is configured to be supplied to the i-th emission control line, and a data signal having a data voltage level is configured to be supplied to the j-th data line.

[0022] During the emission period after the data writing period, an emission control signal for setting the third transistor to an on state may be configured to be supplied to the i-th emission control line, a gate signal for setting the second transistor to an off state may be configured to be supplied to the i-th gate line, and a data signal having a reference voltage level lower than the data voltage level may be configured to be supplied to the j-th data line.

[0023] During the compensation period before the data writing period, a gate signal for setting the second transistor to an on state may be configured to be supplied to the i-th gate line, an emission control signal for setting the third transistor to an off state may be configured to be supplied to the i-th emission control line, and a data signal having a reference voltage level may be configured to be supplied to the j-th data line.

[0024] The first capacitor may include a metal-insulator-metal (MIM) capacitor.

[0025] The first capacitor may include a metal-oxide-semiconductor (MOS) capacitor.

[0026] The display device may further include a second capacitor connected between the first node and the third node, wherein the first capacitor includes a metal-insulator-metal (MIM) capacitor, and the second capacitor includes a metal-oxide-semiconductor (MOS) capacitor. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1 is a diagram illustrating a transistor according to one or more embodiments of the present disclosure.

[0028] Figure 2 is a block diagram illustrating a display device according to an embodiment of the present disclosure.

[0029] Figure 3 is a diagram illustrating Figure 2 a block diagram of one or more embodiments of any one of a plurality of sub-pixels.

[0030] Figure 4 is a diagram illustrating Figure 3 a circuit diagram of one or more embodiments of the sub-pixel shown in.

[0031] Figure 5 is a diagram illustrating driving Figure 4 a wavelength diagram of one or more embodiments of a method for the sub-pixel shown in.

[0032] Figures 6 to 9 is a diagram illustrating the operation process of the sub-pixel in response to Figure 5 a signal of.

[0033] Figure 10 is a diagram illustrating Figure 3 a circuit diagram of one or more embodiments of the sub-pixel shown in.

[0034] Figure 11 is a diagram illustrating Figure 3 a circuit diagram of one or more embodiments of the sub-pixel shown in. DETAILED DESCRIPTION

[0035] Aspects of some embodiments of the present disclosure, as well as methods of implementing the same, can be more easily understood through the detailed description of the reference embodiments and the accompanying drawings. The described embodiments are provided as examples so that the present disclosure will be comprehensive and complete, and will fully convey the aspects of the present disclosure to those skilled in the art. Accordingly, processes, elements, and techniques that are redundant, not relevant or unrelated to the description of the embodiments, or not necessary for those of ordinary skill in the art to fully understand the aspects of the present disclosure may be omitted. Unless otherwise stated, throughout the drawings and the written description, like reference numerals, characters, or combinations thereof represent like elements, and thus, their repeated description may be omitted.

[0036] The described embodiments may have various modifications and may be embodied in different forms, and should not be construed as limited to the embodiments illustrated herein. When describing the embodiments, the use of "can", "may", or "may not" corresponds to one or more embodiments of the present disclosure. The present disclosure encompasses all modifications, equivalents, and substitutions within the spirit and scope of the present disclosure. In addition, the multiple features of the respective embodiments of the present disclosure may be partially or wholly combined with each other, and various interlocks and drives in technology are possible. Multiple embodiments may be realized independently of each other, or may be realized in association with each other.

[0037] It will be understood that when an element, layer, region or component is referred to as being "formed on", "on", "connected to" or "(operatively or communicatively) coupled to" another element, layer, region or component, the one element, layer, region or component can be directly formed on, directly on, directly connected to or directly coupled to the other element, layer, region or component, or can be indirectly formed on, indirectly on, indirectly connected to or indirectly coupled to the other element, layer, region or component, such that there can be one or more intervening elements, layers, regions or components. Additionally, this can be collectively referred to as direct coupling or connection or indirect coupling or connection and integral coupling or connection or non-integral coupling or connection. For example, when a layer, region or component is referred to as being "electrically connected" to or "electrically coupled" to another layer, region or component, the one layer, region or component can be directly electrically connected to or directly coupled to the other layer, region and / or component, or there can be one or more intervening layers, regions or components. One or more intervening components can include switches, resistors, capacitors, etc. When describing embodiments, an expression of connection indicates an electrical connection unless explicitly described as a direct connection, and "direct connection / direct coupling" or "directly on" means that a component is directly connected or directly coupled to another component, or directly on another component, without an intermediate component.

[0038] Additionally, in this specification, when a part of a layer, film, region, plate, etc. is formed on another part, the forming direction is not limited to the upward direction, but includes forming the part on a side surface or in a downward direction. Conversely, when a part of a layer, film, region, plate, etc. is formed "under" another part, this includes not only the case where one part is directly under another part, but also the case where there is another part between one part and another part. Meanwhile, other expressions describing the relationship between components (such as "between", "immediately between", "adjacent" and "directly adjacent") can be similarly interpreted. It will be understood that when an element or layer is referred to as being "between" two elements or layers, the one element or layer can be the only element or layer between the two elements or layers, or there can also be one or more intervening elements or layers.

[0039] For the purposes of the present disclosure, when expressions such as "at least one of...", "any one of...", or "one or more of..." follow a list of elements, they modify the entire list of elements and not individual elements in the list. For example, "at least one of X, Y, and Z", "at least one of X, Y, or Z", "at least one selected from the group consisting of X, Y, and Z", and "at least one selected from the group consisting of X, Y, or Z" can be interpreted as only X, only Y, only Z, or any combination of two or more of X, Y, and Z, such as by way of example XYZ, XY, YZ, XZ, and any variations thereof. Similarly, the expressions "at least one of A and B" and "at least one of A or B" can include A, B, or A and B. As used herein, "or" generally means "and / or", and the term "and / or" includes any and all combinations of one or more of the associated listed items. For example, the expression "A and / or B" can include A, B, or A and B. Similarly, expressions such as "at least one of...", "a plurality of...", "one of...", and other prepositional phrases, when located after a list of elements, modify the entire list of elements and not individual elements in the list.

[0040] It will be understood that although the terms "first", "second", "third", etc. may be used herein to describe various elements, components, regions, layers, and / or sections, these elements, components, regions, layers, and / or sections should not be limited by these terms. These terms do not correspond to a particular order, position, or preference, and are only used to distinguish one element, member, component, region, area, layer, section, or part from another element, member, component, region, area, layer, section, or part. Thus, a first element, first component, first region, first layer, or first section described below can be referred to as a second element, second component, second region, second layer, or second section without departing from the spirit and scope of the present disclosure. A description of an element as a "first" element does not require or imply the existence of a second element or other elements. The terms "first", "second", etc. may also be used herein to distinguish different categories or sets of elements. For the sake of brevity, the terms "first", "second", etc. may respectively represent "first category (or first set)", "second category (or second set)", etc.

[0041] The terms used herein are for the purpose of describing embodiments only and are not intended to limit the disclosure. As used herein, the singular forms "a" and "an" are intended to include the plural forms as well, and the plural forms are also intended to include the singular form, unless the context clearly indicates otherwise. It will also be understood that the terms "comprises," "comprising," "has," "having," "includes," and "including," when used in this specification, specify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0042] As used herein, the terms "substantially," "about," "approximate," and similar terms are used as approximating terms and not terms of degree, and are intended to account for the inherent deviations in measured or calculated values as would be recognized by a person of ordinary skill in the art. For example, "substantially" may include a range of + / - 5% of the corresponding value. Taking into account the measurements involved and the errors associated with the measurement of a particular quantity (such as the limitations of the measurement system), "about" or "approximate" as used herein includes the stated value and means within an acceptable range of deviation for the particular value as determined by a person of ordinary skill in the art. For example, "about" may mean within one or more standard deviations, or within + / - 30%, 20%, 10%, 5% of the stated value. Additionally, when describing embodiments of the disclosure, the use of "may" refers to "one or more embodiments of the disclosure."

[0043] In some embodiments, well-known structures and devices may be described in connection with one or more functional blocks (e.g., block diagrams), units, and / or modules in the drawings to avoid unnecessarily obscuring the various embodiments. Those skilled in the art will understand that such blocks, units, and / or modules are physically implemented by logic circuits, individual components, microprocessors, hardwired circuits, memory elements, wire connections, and other electronic circuits. This may be formed using semiconductor-based manufacturing techniques or other manufacturing techniques. Blocks, units, and / or modules implemented by a microprocessor or other similar hardware may be programmed and controlled using software to perform the various functions discussed herein, optionally driven by firmware and / or software. Additionally, each block, unit, and / or module may be implemented by dedicated hardware or a combination of dedicated hardware that performs certain functions and a processor (e.g., one or more programmed microprocessors and associated circuits) that performs functions different from those of the dedicated hardware. Additionally, in some embodiments, a block, unit, and / or module may be physically divided into two or more interacting individual blocks, units, and / or modules without departing from the scope of the disclosure. Additionally, in some embodiments, a block, unit, and / or module may be physically combined into more complex blocks, units, and / or modules without departing from the scope of the disclosure.

[0044] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. It will also be understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and this specification, and should not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

[0045] Figure 1 is a diagram illustrating a transistor 10 according to one or more embodiments of the present disclosure.

[0046] Reference Figure 1 , according to one or more embodiments of the present disclosure, the transistor 10 may include a first electrode 12, a second electrode 14, a gate electrode 16, and a body electrode 18. For example, the transistor 10 may be a metal oxide semiconductor field effect transistor (MOSFET). The transistor 10 (e.g., MOSFET) including the body electrode 18 is suitable for implementing a high-resolution pixel due to its reduced mounting area.

[0047] The transistor 10 may be formed on a silicon wafer. For example, a panel may be implemented by stacking layers such as a transistor layer, an emission layer, and a cover layer on the silicon wafer. However, the foregoing description is illustrative, and the transistor 10 may be formed on various known substrates (e.g., a glass substrate).

[0048] The first electrode 12 of the transistor 10 may be set as a source electrode (or a drain electrode), and the second electrode 14 of the transistor 10 may be set as a drain electrode (or a source electrode). In the case where the transistor 10 includes the body electrode 18, the threshold voltage of the transistor 10 may change due to the body effect. The body effect refers to a change in the threshold voltage of the transistor 10 caused by a voltage difference between the body electrode 18 of the transistor 10 and the first electrode 12 of the transistor 10.

[0049] Figure 2 is a block diagram illustrating a display device 100 according to an embodiment of the present disclosure.

[0050] Reference Figure 2 , the display device 100 may include a display panel 110, a gate driver 120, a data driver 130, a voltage generator 140, and a controller 150.

[0051] The display panel 110 may include sub-pixels SP. The sub-pixels SP may be connected to the gate driver 120 through the first gate line GL1 to the m-th gate line GLm. The sub-pixels SP may be connected to the data driver 130 through the first data line DL1 to the n-th data line DLn, where m and n are positive integers greater than 0.

[0052] Each of the plurality of sub-pixels SP may include at least one light-emitting element configured to generate light. Thus, each of the plurality of sub-pixels SP may generate light of a corresponding color (such as red, green, blue, cyan, magenta, or yellow). Two or more of the plurality of sub-pixels SP may form a pixel PXL. For example, as Figure 2 illustrated, three sub-pixels SP may form a pixel PXL.

[0053] The gate driver 120 may be connected to the plurality of sub-pixels SP arranged in the row direction through the first gate line GL1 to the m-th gate line GLm. The gate driver 120 may output a gate signal to the first gate line GL1 to the m-th gate line GLm in response to a gate control signal GCS. In an embodiment, the gate control signal GCS may include a start signal indicating the start of each frame, a horizontal synchronization signal for outputting a gate signal in synchronization with the timing at which a data signal is applied, and the like.

[0054] In an embodiment, first emission control lines EL1 to ELm connected to the plurality of sub-pixels SP in the row direction may be further provided. In this case, the gate driver 120 may include an emission control driver configured to control the first emission control lines EL1 to ELm. The emission control driver may operate under the control of the controller 150.

[0055] The gate driver 120 may be located on one side of the display panel 110. However, the embodiment is not limited to the foregoing example. For example, the gate driver 120 may be divided into two or more drivers physically and / or logically distinguishable from each other. The plurality of drivers may be located on the first side of the display panel 110 and the second side of the display panel 110 opposite to the first side, respectively. Thus, according to an embodiment, the gate driver 120 may be located around the display panel 110 in various forms.

[0056] The data driver 130 may be connected to the plurality of sub-pixels SP arranged in the column direction through the first data line DL1 to the n-th data line DLn. The data driver 130 may receive image data DATA and a data control signal DCS from the controller 150. The data driver 130 may operate in response to the data control signal DCS. In an embodiment, the data control signal DCS may include a source start pulse, a source shift clock, a source output enable signal, and the like.

[0057] By using the voltage from the voltage generator 140, the data driver 130 can apply data signals having gray-scale voltages corresponding to the image data DATA to the first data line DL1 to the nth data line DLn. When the gate signal is applied to each of the first gate line GL1 to the mth gate line GLm, data signals having data voltage levels corresponding to the image data DATA can be applied to the first data line DL1 to the nth data line DLn. Accordingly, the corresponding sub-pixel SP can generate light corresponding to the data signal. Accordingly, an image can be displayed on the display panel 110.

[0058] In one or more embodiments, the data driver 130 can use the voltage from the voltage generator 140 and thus can apply data signals having a reference voltage level to the first data line DL1 to the nth data line DLn. The reference voltage level can be lower than the data voltage level.

[0059] In an embodiment, the gate driver 120 and the data driver 130 can include complementary metal oxide semiconductor (CMOS) circuit elements.

[0060] The voltage generator 140 is graded in response to a voltage control signal VCS provided from the controller 150. The voltage generator 140 is configured to generate a plurality of voltages and provide the generated plurality of voltages to a plurality of components of the display device 100. For example, the voltage generator 140 can receive an input voltage from an external device provided outside the display device 100, can adjust the received voltage, and can regulate the adjusted voltage to generate a plurality of voltages.

[0061] The voltage generator 140 can generate a first power voltage VDD and a second power voltage VSS. The generated first power voltage VDD and second power voltage VSS can be provided to the sub-pixel SP. The first power voltage VDD can have a relatively high voltage level. The second power voltage VSS can have a voltage level lower than that of the first power voltage VDD. In other embodiments, the first power voltage VDD or the second power voltage VSS can be provided by an external device of the display device 100.

[0062] In one or more embodiments, the voltage generator 140 can generate a second power voltage VSS having a first voltage level and a second power voltage VSS having a second voltage level under the control of the controller 150. Each of the first voltage level and the second voltage level can be lower than the voltage level of the first power voltage VDD. The second voltage level can be higher than the first voltage level.

[0063] The controller 150 may control the overall operation of the display device 100. The controller 150 may receive input image data IMG and a control signal CTRL for controlling the operation of displaying the input image data IMG from an external device. The controller 150 may provide a gate control signal GCS, a data control signal DCS, and a voltage control signal VCS in response to the control signal CTRL.

[0064] The controller 150 may convert the input image data IMG to be suitable for the display device 100 or the display panel 110, and then may output image data DATA. In an embodiment, the controller 150 may align the input image data IMG on a row basis to be suitable for the sub-pixels SP, and then output the image data DATA.

[0065] Two or more components of the data driver 130, the voltage generator 140, and the controller 150 may be mounted on a single integrated circuit. As Figure 2 illustrated, the data driver 130, the voltage generator 140, and the controller 150 may be included in the driver integrated circuit DIC. In this case, the data driver 130, the voltage generator 140, and the controller 150 may be components that are functionally separated from each other in a single driver integrated circuit DIC. In other embodiments, at least one of the data driver 130, the voltage generator 140, and the controller 150 may be provided as a component separate from the driver integrated circuit DIC.

[0066] Figure 3 is a block diagram of one or more embodiments of any one of the plurality of sub-pixels SP illustrated Figure 2 . In Figure 3 , illustrated is Figure 2 the sub-pixel SPij located on the i-th row (where i is an integer between 1 and m, including 1 and m) and the j-th column (where j is an integer between 1 and n, including 1 and n) among the plurality of sub-pixels SP.

[0067] Referring to Figure 3 , the sub-pixel SPij may include a sub-pixel circuit SPC and a light-emitting element LD.

[0068] The light-emitting element LD is connected between a first power voltage node VDDN and a second power voltage node VSSN. Here, the first power voltage node VDDN may be a node provided to transmit Figure 1 the first power voltage VDD. The second power voltage node VSSN may be a node provided to transmit Figure 1 the second power voltage VSS.

[0069] The anode electrode AE of the light-emitting element LD can be connected to the first power voltage node VDDN through the sub-pixel circuit SPC. The cathode electrode CE of the light-emitting element LD can be connected to the second power voltage node VSSN. For example, the anode electrode AE of the light-emitting element LD can be connected to the first power voltage node VDDN through one or more transistors included in the sub-pixel circuit SPC.

[0070] The sub-pixel circuit SPC can be connected to Figure 1 the i-th gate line GLi among the first gate line GL1 to the m-th gate line GLm of Figure 1 the i-th emission control line ELi among the first emission control line EL1 to the m-th emission control line ELm of Figure 1 and the j-th data line DLj among the first data line DL1 to the n-th data line DLn of . The sub-pixel circuit SPC is configured to control the light-emitting element LD in response to signals received through the aforementioned signal lines.

[0071] The sub-pixel circuit SPC can operate in response to a gate signal received through the i-th gate line GLi.

[0072] The sub-pixel circuit SPC can operate in response to an emission control signal received through the i-th emission control line ELi. In an embodiment, the i-th emission control line ELi can include one or more sub-emission control lines. In the case where the i-th emission control line ELi includes two or more sub-emission control lines, the sub-pixel circuit SPC can operate in response to emission control signals received through the corresponding sub-emission control lines.

[0073] The sub-pixel circuit SPC can receive a data signal through the j-th data line DLj. The sub-pixel circuit SPC can store a voltage corresponding to the data signal in response to a gate signal received through the i-th gate line GLi. The sub-pixel circuit SPC can adjust a current flowing from the first power voltage node VDDN through the light-emitting element LD to the second power voltage node VSSN according to the stored voltage in response to an emission control signal received through the i-th emission control line ELi. Therefore, the light-emitting element LD can emit light with a brightness corresponding to the data signal.

[0074] Figure 4 is a circuit diagram Figure 3 showing one or more embodiments of the sub-pixel SPij shown in .

[0075] Referring to Figure 4 , the sub-pixel SPij can include the sub-pixel circuit SPC and the light-emitting element LD.

[0076] The light-emitting element LD can be connected between the first power line PL1 and the second power line PL2. For example, the first electrode (or anode electrode AE) of the light-emitting element LD can be connected to the first power voltage node VDDN via the second node N2, the first transistor M1, the first node N1, the third transistor M3, and the first power line PL1.

[0077] The second electrode (or cathode electrode CE) of the light-emitting element LD can be connected to the second power voltage node VSSN through the second power line PL2.

[0078] The light-emitting element LD can generate light of a specific brightness corresponding to the amount of current supplied from the first power line PL1 to the second power line PL2 via the sub-pixel circuit SPC.

[0079] An organic light-emitting diode can be selected as the light-emitting element LD. In addition, an inorganic light-emitting diode such as a micro light-emitting diode (LED) or a quantum dot light-emitting diode can be selected as the light-emitting element LD. The light-emitting element LD can be an element formed by a combination of organic materials and inorganic materials.

[0080] Although Figure 4 the figure shows that the sub-pixel SPij includes a single light-emitting element LD, the sub-pixel SPij in one or more embodiments can include multiple light-emitting elements LD. The multiple light-emitting elements LD can be connected in series, parallel, or series-parallel with each other.

[0081] The sub-pixel circuit SPC can be connected to the i-th gate line GLi, connected to the i-th emission control line ELi, and connected to the j-th data line DLj. The sub-pixel circuit SPC can include a first transistor M1, a second transistor M2, a third transistor M3, and a capacitor Cst.

[0082] Each of the first transistor M1, the second transistor M2, and the third transistor M3 can be a transistor including a body electrode. For example, each of the first transistor M1, the second transistor M2, and the third transistor M3 can be formed by a metal-oxide semiconductor field-effect transistor (MOSFET). In this case, the first transistor M1, the second transistor M2, and the third transistor M3 can be mounted in a relatively small area, enabling the sub-pixel SPij to be applied to a high-resolution panel.

[0083] In one or more embodiments, each of the first transistor M1, the second transistor M2, and the third transistor M3 can be formed by a P-type transistor. However, this is illustrative, and at least one of the first transistor M1, the second transistor M2, and the third transistor M3 can be replaced with an N-type transistor.

[0084] The first transistor M1 may include a first electrode connected to a first node N1 and a second electrode connected to a second node N2. Here, the term "connected" means an electrical link or junction. The gate electrode of the first transistor M1 may be connected to a third node N3. The first node N1 may refer to the node to which the second electrode of the third transistor M3 is connected. The second node N2 may refer to the node to which the first electrode of the light-emitting element LD is connected. The first transistor M1 may control the amount of current supplied from the first power line PL1 supplying the first power voltage VDD via the light-emitting element LD to the second power line PL2 supplying the second power voltage VSS in response to the voltage of the third node N3.

[0085] The second transistor M2 may be connected between the j-th data line DLj and the third node N3. The gate electrode of the second transistor M2 may be electrically connected to the i-th gate line GLi. If a gate signal GW for setting the second transistor M2 to an on state is supplied to the i-th gate line GLi, the j-th data line DLj and the third node N3 may be electrically connected to each other.

[0086] The first electrode of the third transistor M3 may be electrically connected to the first power line PL1, and the second electrode of the third transistor M3 may be connected to the first node N1. The gate electrode of the third transistor M3 may be electrically connected to the i-th emission control line ELi. If an emission control signal EM for setting the third transistor M3 to an on state is supplied to the i-th emission control line ELi, the first power line PL1 and the first node N1 may be electrically connected to each other.

[0087] The capacitor Cst may be connected between the first node N1 and the third node N3. The capacitor Cst may send a change in the voltage of the first node N1 to the third node N3 (e.g., may send a certain range of voltages). In addition, the capacitor Cst may store the voltage of the third node N3.

[0088] In one or more embodiments, a metal-insulator-metal (MIM) capacitor may be used to implement the capacitor Cst.

[0089] Figure 5 is a wavelength diagram of one or more embodiments of a method of driving Figure 4 the sub-pixel SPij shown in

[0090] Reference Figure 2 、 Figure 4 and Figure 5, which illustrates signals supplied to the sub-pixel SPij from the gate driver 120, data driver 130, and voltage generator 140 of the display device 100 during the frame period FR. The frame period FR may refer to the period during which an image of one screen is displayed on the display panel 110. The frame period FR may include a first period T1, a second period T2, a third period T3, and a fourth period T4.

[0091] The gate driver 120 may supply a gate signal GW for setting the second transistor M2 to an on state to the i-th gate line GLi during the first period T1, the second period T2, and the third period T3.

[0092] In one or more embodiments, the emission control driver of the gate driver 120 may supply an emission control signal EM for setting the third transistor M3 to an on state to the i-th emission control line ELi during the first period T1 and during the fourth period T4.

[0093] The data driver 130 may supply a data signal Dm having a data voltage level VDT to the j-th data line DLj during the third period T3. The data driver 130 may supply a data signal Dm having a reference voltage level VRF to the j-th data line DLj during the first period T1, the second period T2, and the fourth period T4. The reference voltage level VRF may be lower than the data voltage level VDT. The reference voltage level VRF may be higher than each of the first voltage level VS1 and the second voltage level VS2.

[0094] The voltage generator 140 may supply a first power voltage VDD to the first power voltage node VDDN under the control of the controller 150 during the first period T1, the second period T2, the third period T3, and the fourth period T4.

[0095] The voltage generator 140 may supply a second power voltage VSS having a first voltage level VS1 to the second power voltage node VSSN during the first period T1 and the fourth period T4, and may supply a second power voltage VSS having a second voltage level VS2 to the second power voltage node VSSN during the second period T2 and the third period T3. The second voltage level VS2 may be higher than the first voltage level VS1. Each of the first voltage level VS1 and the second voltage level VS2 may be lower than the voltage level of the first power voltage VDD.

[0096] The first period T1 may be a period during which the first power voltage VDD is supplied to the first node N1 and a data signal Dm having a reference voltage level VRF is supplied to the third node N3. The first period T1 may be referred to as an initialization period.

[0097] The second period T2 may be a period during which a data signal Dm having a reference voltage level VRF is supplied to the third node N3 and a second power supply voltage VSS having a second voltage level VS2 is supplied to the second power supply voltage node VSSN. During the second period T2, the threshold voltage of the first transistor M1 is stored in the capacitor Cst. The second period T2 may be referred to as a threshold voltage compensation period.

[0098] The third period T3 may be a period during which a data signal Dm having a data voltage level VDT is supplied to the third node N3 and a second power supply voltage VSS having a second voltage level VS2 is supplied to the second power supply voltage node VSSN. During the third period T3, the threshold voltage of the first transistor M1 is stored in the capacitor Cst. The third period T3 may be referred to as a data writing period.

[0099] The fourth period T4 may be a period during which a second power supply voltage VSS having a first voltage level VS1 is supplied to the second power supply voltage node VSSN. During the fourth period T4, the first transistor M1 may control the amount of current flowing from the first power supply voltage node VDDN through the light-emitting element LD to the second power supply voltage node VSSN in response to the voltage of the third node N3. During the fourth period T4, the light-emitting element LD may emit light with a brightness corresponding to the amount of current supplied from the first transistor M1. The fourth period T4 may be referred to as an emission period.

[0100] Figures 6 to 9 is a circuit diagram showing the operation process of the sub-pixel SPij in response to Figure 5 the signal. Figures 6 to 9 The sub-pixel circuit SPC of Figure 4 may correspond to the sub-pixel circuit SPC of

[0101] Reference Figure 5 and Figure 6 , a gate signal GW for setting the second transistor M2 to an on state is supplied to the i-th gate line GLi during the first period T1. In addition, during the first period T1, an emission control signal EM for setting the third transistor M3 to an on state is supplied to the i-th emission control line ELi. If the third transistor M3 is turned on, the first power supply voltage VDD is supplied to the first node N1.

[0102] During the first period T1, a second power supply voltage VSS having a first voltage level VS1 is supplied to the second power supply voltage node VSSN, and a data signal Dm having a reference voltage level VRF is supplied to the j-th data line DLj.

[0103] If the second transistor M2 is turned on, a data signal Dm having a reference voltage level VRF is supplied from the j-th data line DLj to the third node N3. Here, the capacitor Cst can be initialized with a voltage corresponding to the reference voltage level VRF and the first power supply voltage VDD. For example, the capacitor Cst can be charged with a voltage corresponding to the reference voltage level VRF and a voltage corresponding to the first power supply voltage VDD, regardless of the voltage charged in the previous period (or previous frame period) during the first period T1.

[0104] Reference Figure 5 and Figure 7 , during the second period T2, the first transistor M1 and the second transistor M2 can be held in the on state. During the second period T2, an emission control signal EM for setting the third transistor M3 to the off state can be supplied to the i-th emission control line ELi. If the third transistor M3 is off, the electrical connection between the first power line PL1 and the first node N1 may be interrupted.

[0105] During the second period T2, a second power supply voltage VSS having a second voltage level VS2 is supplied to the second power supply voltage node VSSN, and a data signal Dm having a reference voltage level VRF is supplied to the j-th data line DLj.

[0106] Since the second transistor M2 is set to the on state during the second period T2, a data signal Dm having a reference voltage level VRF is supplied to the third node N3. The voltage at the first node N1 can be reduced from the first power supply voltage VDD to a voltage obtained by adding the threshold voltage of the first transistor M1 to the voltage corresponding to the reference voltage level VRF. The voltage of the third node N3 can be held at the voltage corresponding to the reference voltage level VRF. Therefore, during the second period T2, the threshold voltage of the first transistor M1 can be stored in the capacitor Cst.

[0107] Here, in order to keep the light emitting element LD in the non-emission state, the following formula should be satisfied.

[0108] Formula 1

[0109] Vref + Vth - Vs2 < Vf

[0110] Vref can represent the voltage corresponding to the reference voltage level VRF. Vth can represent the threshold voltage of the first transistor M1. Vs2 can represent the voltage corresponding to the second voltage level VS2. Vf can represent the drive voltage suitable for allowing the light emitting element LD to emit light.

[0111] During the second period T2, since the second power supply voltage VSS has a second voltage level VS2 that satisfies Equation 1, the light-emitting element LD can be maintained in a non-emitting state even when the current supplied from the first transistor M1 passes through the light-emitting element LD.

[0112] That is, in the case of the present disclosure, even without including a bypass circuit for maintaining the non-emitting state of the light-emitting element LD, the light-emitting element LD can be maintained in the non-emitting state because the second power supply voltage VSS has a second voltage level VS2 that satisfies Equation 1. Therefore, a pixel having a simplified pixel circuit and improved integration degree suitable for a high-resolution panel can be realized.

[0113] Reference Figure 5 and Figure 8 , during the third period T3, the first transistor M1 and the second transistor M2 can be maintained in the on state, and the third transistor M3 can be maintained in the off state.

[0114] During the third period T3, the second power supply voltage VSS having the second voltage level VS2 is supplied to the second power supply voltage node VSSN, and the data signal Dm having the data voltage level VDT is supplied to the j-th data line DLj.

[0115] Since the second transistor M2 is set in the on state during the third period T3, the data signal Dm having the data voltage level VDT is supplied to the third node N3. The voltage of the first node N1 can be the sum of the voltage corresponding to the data voltage level VDT and the threshold voltage of the first transistor M1. The voltage of the third node N3 can be maintained at the voltage corresponding to the data voltage level VDT. Therefore, during the second period T2, the threshold voltage of the first transistor M1 can be stored in the capacitor Cst.

[0116] In addition, in a manner similar to the second period T2, during the third period T3, since the second power supply voltage VSS has a second voltage level VS2 that satisfies the condition for allowing the light-emitting element LD to be in the non-emitting state, the light-emitting element LD can be maintained in the non-emitting state even when the current supplied from the first transistor M1 passes through the light-emitting element LD.

[0117] Reference Figure 5 and Figure 9 , the gate signal GW for setting the second transistor M2 in the off state is supplied to the i-th gate line GLi during the fourth period T4. In addition, during the fourth period T4, the emission control signal EM for setting the third transistor M3 in the on state is supplied to the i-th emission control line ELi. If the third transistor M3 is turned on, the first power supply voltage VDD can be supplied to the first node N1.

[0118] During a fourth period T4, a second power voltage VSS having a first voltage level VS1 is supplied to a second power voltage node VSSN, and a data signal Dm having a reference voltage level VRF is supplied to a j-th data line DLj.

[0119] Here, a first transistor M1 can control the amount of current supplied from a first power line PL1 supplying a first power voltage VDD via a light-emitting element LD to a second power line PL2 supplying a second power voltage VSS in response to the voltage of a third node N3. During the fourth period T4, the light-emitting element LD can emit light with a brightness corresponding to the amount of drive current supplied from the first transistor M1.

[0120] Figure 10 is a diagram Figure 3 showing a circuit diagram of one or more embodiments of a sub-pixel SPij shown in

[0121] Reference Figure 10 , the sub-pixel SPij may include a sub-pixel circuit SPC and a light-emitting element LD. The sub-pixel circuit SPC and the light-emitting element LD of Figure 4 may be described in a manner similar to the sub-pixel circuit SPC and the light-emitting element LD of Figure 10 , and overlapping descriptions will be simplified or omitted.

[0122] The sub-pixel circuit SPC may be connected to an i-th gate line GLi, an i-th emission control line ELi, and a j-th data line DLj. The sub-pixel circuit SPC may include a first transistor M1, a second transistor M2, a third transistor M3, and a capacitor Cst.

[0123] The capacitor Cst may be connected between a first node N1 and a third node N3. The capacitor Cst may transmit a change in the voltage of the first node N1 to the third node N3.

[0124] In one or more embodiments, the capacitor Cst may be implemented using a metal-oxide semiconductor (MOS) capacitor.

[0125] Figure 11 is a diagram Figure 3 showing a circuit diagram of one or more embodiments of a sub-pixel SPij shown in

[0126] Reference Figure 11 , the sub-pixel SPij may include a sub-pixel circuit SPC and a light-emitting element LD. The sub-pixel circuit SPC and the light-emitting element LD of Figure 4 may be described in a manner similar to the sub-pixel circuit SPC and the light-emitting element LD of Figure 11 , and overlapping descriptions will be simplified or omitted.

[0127] The sub-pixel circuit SPC can be connected to the i-th gate line GLi, the i-th emission control line ELi, and the j-th data line DLj. The sub-pixel circuit SPC can include a first transistor M1, a second transistor M2, a third transistor M3, a first capacitor Cm, and a second capacitor Cs.

[0128] The first capacitor Cm can be connected between the first node N1 and the third node N3. The second capacitor Cs can be connected between the first node N1 and the third node N3. In other words, the first capacitor Cm and the second capacitor Cs can be connected in parallel between the first node N1 and the third node N3. Since the first capacitor Cm and the second capacitor Cs are connected in parallel with each other, a large-capacity capacitor can be realized.

[0129] In one or more embodiments, a metal-insulator-metal (MIM) capacitor can be used to implement the first capacitor Cm, and a MOS capacitor can be used to implement the second capacitor Cs.

[0130] According to the pixels and the display device including the pixels according to the embodiments of the present disclosure, transistors suitable for high resolution (e.g., metal-oxide-semiconductor field-effect transistors (MOSFETs)) can be used to implement the pixels.

[0131] Although the spirit and scope of the present disclosure are described through detailed embodiments, it should be noted that the above embodiments are only descriptive and should not be considered restrictive. Those skilled in the art should understand that various changes, substitutions, and alterations can be made herein without departing from the scope of the present disclosure as defined by the appended claims, and functional equivalents of the claims are included within the scope of the present disclosure.

[0132] The scope of the present disclosure is not limited by the detailed description of this specification and should be defined by the appended claims. In addition, all changes or modifications derived from the meaning and scope of the claims and their equivalents should be interpreted as being included within the scope of the present disclosure.

Claims

1. A pixel comprising: a first transistor including a first electrode connected to the first node, a second electrode connected to the second node, and a gate electrode connected to a third node; a second transistor connected between the data line and the third node and including a gate electrode electrically connected to the first sub-gate line; a third transistor connected between a first power line configured to supply a first power voltage and the first node and including a gate electrode electrically connected to an emission control line; a first capacitor connected between the first node and the third node; as well as A light emitting element is connected between the second node and a second power line configured to supply a second power voltage.

2. The pixel according to claim 1, wherein: During an emission period in which the light emitting element is configured to emit light with brightness corresponding to the current supplied from the first transistor, the second power voltage is configured to have a first voltage level, and During a data writing period before the transmission period, the second power voltage is configured to have a second voltage level higher than the first voltage level.

3. The pixel according to claim 2, wherein: A single frame period includes an initialization period, a compensation period, the data writing period, and the emission period, and During the data writing period, the third transistor is configured to be set to an off state, the first transistor and the second transistor are configured to be set to an on state, and a data signal having a data voltage level is configured to be supplied to the data line.

4. The pixel according to claim 3, wherein: During the emission period after the data write period, the second transistor is configured to be set to the off state, the first transistor and the third transistor are configured to be set to the on state, and a data signal having a reference voltage level lower than the data voltage level is configured to be supplied to the data line.

5. The pixel according to claim 4, wherein: The reference voltage level is lower than a voltage level of the first power voltage and higher than the first voltage level.

6. The pixel according to claim 3, wherein: During the compensation period before the data writing period, the third transistor is configured to be set to the off state, the first transistor and the second transistor are configured to be set to the on state, a data signal having a reference voltage level is configured to be supplied to the data line, and the second power voltage is configured to have the second voltage level.

7. The pixel according to claim 3, wherein: During the initialization period before the compensation period, the first transistor, the second transistor and the third transistor are configured to be set to the on state, a data signal having a reference voltage level is configured to be supplied to the data line, and the second power voltage is configured to have the first voltage level.

8. The pixel according to claim 1, wherein: The first capacitor comprises a metal-insulator-metal capacitor.

9. The pixel according to claim 1, wherein: The first capacitor includes a metal oxide semiconductor capacitor.

10. The pixel according to claim 1, further comprising: A second capacitor is connected between the first node and the third node.

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