Method for manufacturing silicon-based packaging module with large cavity ratio

Abstract

The invention belongs to the technical field of packaging, and discloses a manufacturing method of a silicon-based packaging module with a large cavity ratio. The invention provides a manufacturing method of a large-cavity-ratio silicon-based packaging module. High-density integration of the large-cavity-ratio silicon-based packaging module is completed in a flip-chip bonding and laser cutting combined mode. A through cavity structure is manufactured on a silicon-based adapter plate, a structural strength enhancing area is reserved on the periphery of the through cavity, and structural enhancing micro-convex blocks are prepared in the structural enhancing area, so that the structural strength of the silicon-based adapter plate in the stacking process is improved, and the difficulty that a substrate is fragile in the high-reliability airtight integration process of a large-cavity-ratio silicon-based module is overcome; by arranging round chamfers at four corners of the silicon cavity, the risk of local stress concentration in multiple flip-chip welding is reduced; according to the invention, the integration of the silicon-based module with a large silicon cavity ratio of more than 70% can be realized, and the manufacturing yield and the system integration degree of the silicon-based packaging module with the large cavity ratio are ensured.

Description

Technical Field

[0001] The present invention mainly relates to the field of packaging technology, and particularly to a method for manufacturing a silicon-based packaging module with a large cavity ratio. Background Art

[0002] The application of silicon-based three-dimensional packaging modules is rapidly developing towards the direction of high integration, miniaturization, multi-functionality, and high performance. With the continuous improvement of the requirements for functional density and performance of electronic devices, the demand for the internal packaging space of modules is increasing day by day. However, due to the brittle and fragile characteristics of thin silicon-based interposer, it is extremely easy to break or be damaged during the packaging process, which brings great technical challenges to module packaging and further limits the cavity size inside the silicon-based packaging module.

[0003] At present, there are already technologies for realizing the packaging of devices in multiple silicon cavities. Compared with the traditional multi-chip module packaging technology (Multi Chip Module, MCM), it can reduce the volume of the RF system to a certain extent, improve the packaging density of the RF system, reduce the transmission loss of interconnection lines, and enhance the performance of the RF system. However, the silicon cavity volume is limited by the substrate thickness and material brittleness, and there are difficulties and bottlenecks in further improving the silicon cavity ratio and system integration.

[0004] Regarding the integration of silicon-based modules, how to improve the cavity ratio, increase the integration space inside the module, and ensure the manufacturing yield of silicon-based modules with a large cavity ratio has become a difficulty in the packaging of silicon-based modules with a large cavity ratio. Summary of the Invention

[0005] The purpose of the present invention is to provide a method for manufacturing a silicon-based packaging module with a large cavity ratio, aiming to complete the high-density integration of a silicon-based packaging module with a large cavity ratio by combining multiple flip-chip weldings and laser cutting; by reserving a structural strength enhancement area and structural enhancement micro-bumps on the silicon-based interposer, the structural strength of the silicon-based interposer in multiple stacked weldings is increased, overcoming the difficulty of the fragile substrate in the high-reliability airtight integration process of the silicon-based module with a large cavity ratio. At the same time, round chamfers are set at the four corners of the silicon cavity to reduce the risk of local stress concentration in multiple flip-chip weldings. After the N-layer silicon substrate is stacked and integrated, the reserved substrate area is removed by laser cutting, and the integration of a silicon-based module with a silicon cavity ratio of more than 70% can be realized, ensuring the manufacturing yield and system integration of the silicon-based packaging module with a large cavity ratio.

[0006] To achieve the above object, the present invention provides a method for manufacturing a silicon-based packaging module with a large cavity ratio, including the following steps: Step 1: Make alignment marks and laser cutting marks on the upper surface of the first-layer silicon-based interposer for determining the laser cutting position of the final silicon-based packaging module; Step 2: Fabricate the N-layer silicon-based interposer using the Through-Silicon Via (TSV) process. Each silicon-based interposer is provided with an airtight packaging ring, electrical interconnection micro-bumps, and structural reinforcement micro-bumps. Fabricate a through-cavity structure on the module formed by the 2nd to (N-1)th layer silicon-based interposer boards. Reserve a structural strength reinforcement area around the through-cavity structure, and structural reinforcement micro-bumps are provided on the structural strength reinforcement area. Step 3: Use the flip-chip bonding process to complete the three-dimensional stacking of the 1st to (N-1)th layer silicon-based interposer boards. Step 4: Place functional devices inside the through-cavity structure. Step 5: Use the flip-chip bonding process to complete the three-dimensional stacking of the (N-1)th to Nth layer silicon-based interposer boards. Step 6: Use the laser cutting process to cut off the structural strength reinforcement area reserved around the through-cavity structure, forming an effective area including the functional module package structure.

[0007] Further, the flip-chip bonding process in Step 3 further includes Step S1: Fix the first layer silicon-based interposer on the hot stage through vacuum adsorption.

[0008] Further, the value range of N is 3 to 10.

[0009] Further, the value of N is 5.

[0010] Further, the materials of the electrical interconnection micro-bumps and the structural reinforcement micro-bumps in Step 2 are gold-tin.

[0011] Further, use the Dry Reactive Ion Etching (DRIE) process or the laser process in Step 2 to fabricate the through-cavity structure on the 2nd to (N-1)th layer silicon-based interposer boards.

[0012] Further, Step 2 further includes Step S2: Set a round chamfer around the silicon cavity of the through-cavity structure to reduce the risk of local stress concentration during multiple flip-chip bondings.

[0013] Further, the functional devices placed inside the through-cavity structure in Step 4 include gallium arsenide bare chips or silicon-based bare chips.

[0014] Further, during the flip-chip bonding process of each silicon-based interposer layer, it includes the welding of electrical interconnection micro-bumps and the welding of the airtight packaging ring completed by heating and pressurizing.

[0015] Beneficial effects: The present invention provides a method for fabricating a silicon-based packaging module with a large cavity ratio, which achieves high-density integration of a silicon-based packaging module with a large cavity ratio by combining flip-chip bonding and laser cutting. The DRIE etching process or laser process is used to fabricate a through-cavity structure on the silicon-based interposer, and a structural strength enhancement area is reserved around the through-cavity. Structural enhancement micro-bumps are fabricated in the structural enhancement area to increase the structural strength during the stacking process of the silicon-based interposer, overcoming the difficulty of substrate fragility during the highly reliable hermetic integration of the silicon-based module with a large cavity ratio. A reliable adsorption area is provided for the vacuum adsorption of the silicon-based module during flip-chip bonding by reserving the structural strength enhancement area. Rounded chamfers are provided at the four corners of the silicon cavity to reduce the risk of local stress concentration during multiple flip-chip bondings. After the stacking integration of the N-layer silicon substrates, the reserved substrate area is removed by laser cutting, avoiding problems such as uneven stress or damage to the silicon-based module caused by cutting with a diamond knife. The present invention can achieve the integration of a silicon-based module with a silicon cavity ratio of more than 70%, ensuring the production yield and system integration of the silicon-based packaging module with a large cavity ratio. Description of the Drawings

[0017] Figure 1 is a side cross-sectional view of the high-density integration of the silicon-based packaging module with a large cavity ratio according to an embodiment of the present invention; Figure 2 is a top view of the Nth-layer silicon-based interposer of the silicon-based packaging module with a large cavity ratio before laser scribing according to an embodiment of the present invention; Figure 3 is a top view of the 2nd to (N - 1)th layer silicon-based interposers of the silicon-based packaging module with a large cavity ratio according to an embodiment of the present invention; Figure 4 is a top view of the 1st-layer silicon-based interposer of the silicon-based packaging module with a large cavity ratio according to an embodiment of the present invention; Figure 5 is a side cross-sectional view of the Nth-layer silicon-based interposer of the silicon-based packaging module with a large cavity ratio according to an embodiment of the present invention; Figure 6 is a side cross-sectional view of the 2nd to (N - 1)th layer silicon-based interposers of the silicon-based packaging module with a large cavity ratio according to an embodiment of the present invention; Figure 7 is a side cross-sectional view of the 1st-layer silicon-based interposer of the silicon-based packaging module with a large cavity ratio according to an embodiment of the present invention; Figure 8 is a side cross-sectional view after the three-dimensional stacking of the 1st-layer silicon-based interposer and the 2nd-layer silicon-based interposer based on the flip-chip bonding process; Figure 9 is a side cross-sectional view after the three-dimensional stacking of the 3rd-layer silicon-based interposer based on the flip-chip bonding process; Figure 10 is a side cross-sectional view after the three-dimensional stacking of the (N - 1)th layer silicon-based interposer based on the flip-chip bonding process; Figure 11 This is a side cross-sectional view after the internal devices of the silicon-based packaging module with a large cavity ratio involved in the embodiment of the present invention are assembled; Figure 12 This is a side cross-sectional view after stacking the Nth layer of silicon-based interposer using the flip-chip bonding process; Figure 13 This is a schematic diagram of removing the reserved structural strength enhancement area using the laser scribing process.

[0018] Explanation of reference numerals: 1 is the first layer of silicon-based interposer; 2 is the second layer of silicon-based interposer; 3 is the third layer of silicon-based interposer; 4 is the (N - 1)th layer of silicon-based interposer; 5 is the Nth layer of silicon-based interposer; 6 is the effective area of the silicon-based packaging module with a large cavity ratio; 7 is the internal device A of the silicon-based packaging module with a large cavity ratio; 8 is the internal device B of the silicon-based packaging module with a large cavity ratio; 9 is the electrical interconnection microbump; 10 is the hermetic packaging ring; 11 is the structural enhancement microbump; 12 is the reserved structural strength enhancement area of the silicon-based interposer; 13 is the alignment mark and laser cutting mark; 14 is the laser etching process operation area; 15 is the through cavity structure in the silicon-based interposer. Detailed implementation manners

[0019] The following further describes the preferred mechanisms and implementation methods of the present invention in conjunction with the drawings and specific implementation manners.

[0020] Flip-chip bonding is an advanced chip packaging technology. Different from traditional chip packaging methods (such as wire bonding), flip-chip bonding places the front side (i.e., the side containing circuits and pads) of the silicon-based interposer downward and directly connects it to the substrate or packaging carrier through solder bumps (Bumps). For example, the second layer of silicon-based interposer is stacked three-dimensionally on the first layer of silicon-based interposer, and the third layer of silicon-based interposer is stacked three-dimensionally on the second layer of silicon-based interposer. This technology is widely used in modern electronic packaging due to its high density, high performance, and low parasitic effects.

[0021] TSV (Through-Silicon Via) process is an advanced semiconductor packaging technology mainly used to achieve electrical interconnection in the vertical direction of chips. It creates vertical conductive channels penetrating the silicon substrate on the silicon wafer (wafer) to directly connect the front and back sides of the chip, thereby realizing the stacking of multiple chips and three-dimensional integration.

[0022] Electrical interconnection microbumps (Microbump) are key components in advanced packaging technologies, mainly used to achieve high-density electrical connections between chips and between chips and substrates. The structural enhancement microbumps ensure the overall structural strength during multiple flip-chip bonding processes.

[0023] Micro-bumps are usually made of metal materials and have dimensions ranging from a few micrometers to dozens of micrometers. As a bridge for electrical connection, micro-bumps transmit signals, power, and ground wires from the chip to the substrate or other chips to achieve electrical conduction; due to their small size, micro-bumps can achieve more connection points per unit area, thus supporting high-density interconnection and meeting the requirements for integration of modern electronic devices; by directly connecting the chip to the substrate or other chips through micro-bumps, the signal transmission path is shortened, reducing delay and parasitic effects and improving high-frequency performance; micro-bumps provide mechanical support between the chip and the substrate, ensuring the stability and reliability of the chip in the package; micro-bumps can serve as a heat conduction path to help transfer the heat generated by the chip to the substrate or the heat dissipation structure, improving the heat dissipation performance; in the package, micro-bumps are used to connect chips with different process nodes or functions (such as logic chips, memory chips, sensors, etc.) to achieve heterogeneous integration. Embodiment

[0024] As Figures 1 to 13 shown, an embodiment of the present invention discloses a method for fabricating a silicon-based packaging module with a large cavity ratio.

[0025] In this embodiment, there are a total of 5 layers of silicon-based interposer.

[0026] A method for fabricating a silicon-based packaging module with a large cavity ratio is specifically implemented as follows: (1) As Figure 5 shown, on the upper surface of the top layer (the Nth layer) silicon-based interposer 5, alignment marks and laser cutting marks 13 are fabricated, and on the lower surface of the silicon-based interposer, flip-chip solder micro-bumps 9 and hermetic sealing rings 10 for electrical interconnection are prepared. A structural strength enhancement area 12 is reserved outside the effective area of the silicon-based interposer, and structural enhancement micro-bumps 11 are fabricated on the structural strength enhancement area; (2) As Figure 6 shown, on the upper and lower surfaces of the second layer to the N-1th layer silicon-based interposer, flip-chip solder micro-bumps 9 and hermetic sealing rings 10 for electrical interconnection are prepared. A structural strength enhancement area 12 is reserved outside the effective area of the silicon-based interposer, and structural enhancement micro-bumps 11 are fabricated on the structural strength enhancement area. A cavity structure for avoiding devices is fabricated at the middle position of the substrate. The pattern on the lower surface of each layer of silicon-based interposer corresponds to the pattern on the upper layer of the next layer of silicon-based interposer; (3) As Figure 7 shown, on the upper surface of the first layer silicon-based interposer 1, alignment marks and laser cutting marks 13 are fabricated, and on the lower surface of the silicon-based interposer, flip-chip solder micro-bumps 9 and hermetic sealing rings 10 for electrical interconnection are prepared. A structural strength enhancement area 12 is reserved outside the effective area of the silicon-based interposer, and structural enhancement micro-bumps 11 are fabricated on the structural strength enhancement area; (4) As Figure 8As shown in the figure, the second-layer silicon-based interposer is three-dimensionally stacked on the first-layer silicon-based interposer by using the flip-chip stacking process. During the stacking process, the device suction head picks up the reserved structure reinforcement area of the second-layer silicon-based interposer, and the bottom-layer silicon-based interposer is vacuum adsorbed and fixed on the bottom carrier of the flip-chip device. (5) As Figures 9 to 10 shown in the figure, repeat step (4), and use the flip-chip stacking process to three-dimensionally stack the third-layer to the (N-1)-layer silicon-based interposers on the bottom-layer silicon-based interposer assembly in sequence to form a silicon-based module package structure. (6) As Figure 11 shown in the figure, integrate device 7 and device 8 in the silicon-based module package structure (the types and quantities of devices can be adjusted according to actual requirements). (7) As Figure 12 shown in the figure, use the flip-chip stacking process to three-dimensionally stack the top-layer silicon-based interposer, that is, the Nth-layer silicon-based interposer, on the silicon-based module package structure to complete the hermetic packaging of the entire module. (8) As Figure 13 shown in the figure, use a laser to cut from the Nth layer of the silicon-based module to separate the effective area 6 of the silicon-based module, and realize the preparation of a silicon-based packaging module structure with a large cavity ratio.

[0027] The present invention provides a method for manufacturing a silicon-based packaging module with a large cavity ratio. By combining flip-chip welding and laser cutting, a high-density integration of a silicon-based packaging module with a large cavity ratio is completed. By making a through-cavity structure on the silicon-based interposer, reserving a structure strength reinforcement area around the through-cavity, and preparing structure reinforcement micro-bumps in the structure reinforcement area, the structure strength during the stacking process of the silicon-based interposer is increased, overcoming the difficulty of the substrate being fragile during the high-reliability hermetic integration of the silicon-based module with a large cavity ratio. By setting round chamfers at the four corners of the silicon cavity, the risk of local stress concentration during multiple flip-chip weldings is reduced. The present invention can realize the integration of a silicon-based module with a silicon cavity ratio of more than 70%, ensuring the production yield and system integration of the silicon-based packaging module with a large cavity ratio.

[0028] Finally, it should be noted that the above are only the preferred embodiments of the present invention and are not used to limit the present invention. Although the present invention has been described in detail with reference to the embodiments, for those skilled in the art, they can still modify the technical solutions recorded in the foregoing embodiments, or perform equivalent replacements for some of the technical features. However, any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. A method for manufacturing a large cavity ratio silicon-based packaging module, characterized in that: The following steps are involved: Step 1: Make alignment marks and laser cutting marks on the upper surface of the first layer of silicon-based adapter board to determine the laser cutting position of the final silicon-based packaging module; Step 2: Use the through silicon via (TSV) process to make an N-layer silicon-based transfer layer, each of which is provided with an airtight sealing ring, an electrical interconnection micro-bump, and a structural enhancement micro-bump; A through-cavity structure is fabricated on the module formed by the 2nd to N-1th silicon-based adapter plates, a structural strength enhancement area is reserved around the through-cavity structure, and a structural enhancement micro-bump is provided on the structural strength enhancement area; Step 3: Use the flip-chip welding process to complete the three-dimensional stacking of the silicon-based adapter plates from the 1st layer to the N-1th layer; Step 4: placing functional devices in the through-cavity structure; Step 5: Use the flip-chip welding process to complete the three-dimensional stacking of the silicon-based adapter plates from the N-1 layer to the N layer; Step 6: Use a laser cutting process to cut off the reserved structural strength enhancement area around the through-cavity structure to form an effective area including the functional module shell and tube structure.

2. The method for manufacturing a large cavity ratio silicon-based packaging module according to claim 1, characterized in that: The flip chip welding process in step 3 also includes step S1: fixing the first layer of silicon-based adapter plate on the hot stage by vacuum adsorption.

3. The method for manufacturing a large cavity ratio silicon-based packaging module according to claim 1, characterized in that: The value of N ranges from 3 to 10.

4. The method for manufacturing a large cavity ratio silicon-based packaging module according to claim 1, characterized in that: The value of N is 5.

5. The method for manufacturing a large cavity ratio silicon-based packaging module according to claim 1, characterized in that: In step 2, the electrical interconnect micro-bumps and the structural enhancement micro-bumps are made of gold-tin.

6. The method for manufacturing a large cavity ratio silicon-based packaging module according to claim 1, characterized in that: In step 2, a dry etching DRIE process or a laser process is used to form a through cavity structure on the 2nd to N-1th silicon-based adapter plates.

7. The method for manufacturing a large cavity ratio silicon-based packaging module according to claim 1, characterized in that: Step 2 also includes step S2: providing round chamfers around the silicon cavity of the through-cavity structure to reduce the risk of local stress concentration during multiple flip-chip bonding.

8. The method for manufacturing a large cavity ratio silicon-based packaging module according to claim 1, characterized in that: The functional device placed in the through-cavity structure in step 4 includes a gallium arsenide bare chip or a silicon-based bare chip.

9. The method for manufacturing a large cavity ratio silicon-based packaging module according to claim 1, characterized in that: The flip chip welding process of each silicon-based transfer layer includes electrical interconnect micro-bump welding and airtight sealing ring welding completed by heating and pressurizing.

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