Preparation method of semiconductor structure, semiconductor structure, device and equipment

Abstract

The invention provides a preparation method of a semiconductor structure, the semiconductor structure, a device and equipment. The method comprises the following steps: providing a wafer; forming a calculation unit on the wafer; the calculation unit at least comprises a plurality of calculation core particles which are distributed in an array; the wafer is inverted, and the wafer is thinned; forming a power supply network on the inverted wafer; the power supply network comprises a plurality of power supply core particles which are distributed in an array, and the power supply core particles are used for supplying power to the calculation core particles. According to the invention, power supply loss can be reduced.

Description

Technical Field

[0001] This application relates to the field of semiconductors, and particularly to a method for fabricating a semiconductor structure, a semiconductor structure, a device, and an apparatus. Background Art

[0002] Chiplet packaging technology, especially three-dimensional integration solutions, aims to maximize the utilization of limited wafer space through ingenious stacking designs. This solution constructs a powerful integrated circuit system by orderly stacking chiplets with different functions on one side of the wafer. However, although the single-sided three-dimensional chiplet integration solution has its unique features, it also exposes some limitations. For example, problems such as uneven power supply and large power supply loss caused by large-scale chiplet integration. Summary of the Invention

[0003] This application provides a method for fabricating a semiconductor structure, a semiconductor structure, a device, and an apparatus to reduce power supply loss.

[0004] In a first aspect, an embodiment of this application provides a method for fabricating a semiconductor structure, the method including: providing a wafer; forming a computing unit on the wafer; the computing unit at least includes a plurality of computing chiplets distributed in an array; flipping the wafer and thinning the wafer; forming a power supply network on the flipped wafer; the power supply network includes a plurality of power chiplets distributed in an array, and the power chiplets are used to supply power to the computing chiplets.

[0005] In some possible implementation manners, forming a power supply network on the flipped wafer includes: forming a plurality of first metal vias in the flipped wafer; the first metal vias penetrate the wafer; forming a plurality of power chiplets on the flipped wafer; the power chiplets are electrically connected to the computing chiplets through the first metal vias; depositing an insulating material on the plurality of power chiplets to form a redistribution layer; forming a plurality of microbumps on the redistribution layer; the microbumps are electrically connected to the power chiplets and the computing chiplets.

[0006] In some possible implementation manners, the microbumps include power microbumps and data microbumps; the power microbumps are electrically connected to the power chiplets; the data microbumps are electrically connected to the computing chiplets through the first metal vias.

[0007] In some possible implementation manners, the computing unit further includes a plurality of data allocation chiplets distributed in an array; forming a computing unit on the wafer includes: sequentially forming a plurality of computing chiplets and a plurality of data allocation chiplets on the wafer; the plurality of computing chiplets and the plurality of data allocation chiplets are stacked in a first direction.

[0008] In some possible embodiments, the computing unit further includes a plurality of memory dies distributed in an array; forming the computing unit on a wafer includes: sequentially forming a plurality of computing dies and a plurality of memory dies on the wafer; the plurality of computing dies and the plurality of memory dies are stacked in a first direction.

[0009] In some possible embodiments, the computing unit further includes a plurality of data allocation dies distributed in an array and a plurality of memory dies distributed in an array; forming the computing unit on a wafer includes: sequentially forming a plurality of computing dies, a plurality of data allocation dies, and a plurality of memory dies on the wafer; the plurality of computing dies, the plurality of data allocation dies, and the plurality of memory dies are stacked in a first direction.

[0010] In some possible embodiments, sequentially forming a plurality of computing dies, a plurality of data allocation dies, and a plurality of memory dies on a wafer includes: forming a plurality of computing dies distributed in an array on the wafer; depositing an insulating material on the plurality of computing dies to form a first isolation layer; forming a plurality of second metal vias in the first isolation layer; forming a plurality of data allocation dies distributed in an array on the first isolation layer; the plurality of data allocation dies are electrically connected to the computing dies through the second metal vias; forming a plurality of first metal interconnect structures on the first isolation layer and between the plurality of data allocation dies; the first metal interconnect structures are used to electrically connect adjacent data allocation dies; depositing an insulating material on the plurality of data allocation dies and the plurality of metal interconnect structures to form a second isolation layer; forming a plurality of third metal vias in the second isolation layer; forming a plurality of memory dies distributed in an array on the second isolation layer; the memory dies are electrically connected to the data allocation dies through the third metal vias.

[0011] In a second aspect, the present application provides a semiconductor structure, which is prepared by the method for preparing the semiconductor structure provided in the first aspect above. The semiconductor structure includes: a wafer; a computing unit; the computing unit at least includes a plurality of computing dies distributed in an array; the computing unit is located on the front side of the wafer; a power supply network; the power supply network includes a plurality of power supply dies distributed in an array, and the power supply dies are used to supply power to the computing dies; the power supply network is located on the back side of the wafer.

[0012] In a third aspect, an embodiment of the present application provides a semiconductor device, which includes: the semiconductor structure as described in the second aspect above.

[0013] In a fourth aspect, an embodiment of the present application provides an electronic device, which includes: a circuit board and the semiconductor device as described in the third aspect above, and the semiconductor device is disposed on the circuit board.

[0014] In the present application, a computing unit is fabricated on the front side of a wafer. By flipping the wafer and forming a plurality of power die with an array distribution on the flipped wafer (i.e., the back side of the wafer), distributed power supply can be achieved while reducing power supply loss.

[0015] Furthermore, fabricating a power supply network on the back side of the wafer is also beneficial to improving the system performance of the semiconductor structure.

[0016] It should be understood that the above general description and the following detailed description are only exemplary and explanatory, and cannot limit the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] The accompanying drawings herein are incorporated into the specification and form a part of the specification, showing embodiments consistent with the present application, and are used together with the specification to explain the principles of the present application.

[0018] Figure 1 It is a schematic structural diagram of a semiconductor structure in an embodiment of the present application;

[0019] Figure 2 It is a schematic implementation flowchart of a preparation method of a semiconductor structure in an embodiment of the present application;

[0020] Figures 3A to 3F It is a schematic diagram of a preparation process of a semiconductor structure in an embodiment of the present application;

[0021] In the above figures:

[0022] 31. Wafer; 32. Computing die; 33. Data allocation die; 34. Storage die; 35. Carrier wafer; 36. Power die; 37. Microbump; 41. First isolation layer; 42. Second metal via; 43. First metal interconnect structure; 44. Second isolation layer; 45. Third metal via; 46. Insulating layer; 47. First metal via; 48. Redistribution layer; 49. Second metal interconnect structure. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0023] Here, exemplary embodiments will be described in detail, and the examples are shown in the accompanying drawings. When the following description refers to the accompanying drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present application.

[0024] In the current context of the continuous deepening of Moore's Law, chiplet packaging technology has great potential in improving system computing power, system yield, and reducing the cost of computing systems. It is an important direction for the system integration of integrated circuits. At the same time, 3D integration is an important way to make full use of the wafer space, continuously improve the system computing power and reduce the data interaction delay in a limited space. The 3D integration of chiplets is the key means for the development of the integrated circuit packaging field.

[0025] Currently, the 3D integration solution is to stack chiplets with different functions on one side of the wafer to jointly form an integrated circuit system, and the power supply components are still provided by the system side. In the 3D chiplet integration solution on one side, the power supply unit is located on the outermost layer of the system, and only one side of the wafer space is utilized. At the same time, the multi-layer stacking on one side not only causes the impedance ratio of the vertical vias to become higher, but also affects the system performance and the power supply network voltage drop deteriorates.

[0026] To solve the above technical problems, the embodiments of the present application provide a method for preparing a semiconductor structure, a semiconductor structure, a device, and a device to reduce power supply loss.

[0027] In some possible implementation manners, Figure 1 is a schematic structural diagram of a semiconductor structure in the embodiments of the present application; see Figure 1 As shown, the above semiconductor structure at least includes: a wafer; a computing unit; the computing unit at least includes a plurality of computing chiplets distributed in an array; the computing unit is located on the front side of the wafer; a power supply network; the power supply network includes a plurality of power chiplets distributed in an array, and the power chiplets are used to supply power to the computing chiplets; the power supply network is located on the back side of the wafer.

[0028] It can be understood that the semiconductor structure is prepared based on the wafer. The computing chiplets are formed on the front side of the wafer, and the power supply network is formed on the back side of the wafer; the power supply network includes a plurality of power chiplets, and the plurality of power chiplets are distributed in an array on the back side of the wafer to supply power to the semiconductor structure.

[0029] In the embodiments of the present application, the power chiplets distributed (i.e., distributed in an array) can make more effective use of the wafer space, so that each computing chiplet in the computing unit can obtain a relatively uniform working environment, thereby improving the overall working efficiency. This arrangement avoids the heat dissipation problem caused by the over-concentration of power chiplets and the performance fluctuations caused by the differences in the working environment. In addition, by distributing the power chiplets on the back side of the wafer, the impact of the failure of a single power chiplet on the entire system can be reduced. If a certain power chiplet fails, other power chiplets can still work normally, thereby improving the overall reliability of the system. In addition, the distributed arrangement helps to achieve redundant design and further enhance the stability of the system.

[0030] In some embodiments, the wafer may be fabricated using silicon (Si) material, i.e., a silicon wafer. The size of the silicon wafer depends on the size of the computing units formed on the wafer.

[0031] In some embodiments, the power die may be designed as a DC-to-DC converter or a low dropout regulator (LDO) according to actual needs, or it may be other forms of power dies. The embodiments of the present application do not make specific limitations on this.

[0032] In some possible implementation manners, in the semiconductor structure, the computing units on the front side of the wafer may further include a plurality of data allocation dies, and the plurality of data allocation dies are arranged above the plurality of computing dies; the data allocation dies and the computing dies are stacked in a first direction and are electrically connected through second metal vias. The first direction is the direction perpendicular to the front side and the back side of the wafer.

[0033] In some possible implementation manners, in the semiconductor structure, the computing units on the front side of the wafer may further include a plurality of memory dies, and the plurality of memory dies are arranged above the plurality of computing dies; the memory dies and the computing dies are stacked in a first direction and are electrically connected through third metal vias.

[0034] In some embodiments, the computing die is a tiny chip unit with specific computing functions, and the computing die has specific computing functions, such as data processing, logical operations, etc.

[0035] In some embodiments, the data allocation die is a special integrated circuit (IC), and the data allocation die has functions such as data processing, storage and forwarding, and routing selection.

[0036] In some embodiments, the memory die is a special integrated circuit, and the memory die has the function of data storage.

[0037] In some embodiments, the composition forms of the computing units may include but are not limited to the following: 1. A plurality of computing dies; 2. A plurality of computing dies and a plurality of data allocation dies; 3. A plurality of computing dies and a plurality of memory dies; 4. A plurality of computing dies, a plurality of data allocation dies and a plurality of memory dies. Other dies with other functions may also be added to the computing unit according to actual needs. The embodiments of the present application do not make specific limitations on this.

[0038] Figure 2 This is a schematic flow chart of an implementation of the method for preparing the semiconductor structure in the embodiments of the present application. Refer to Figure 2 As shown, the method for preparing the above semiconductor structure may include:

[0039] Step S201: Provide a wafer.

[0040] It can be understood that according to actual needs, determine the required size and material of the wafer, and provide a circular silicon wafer.

[0041] It should be noted that the material of the wafer is silicon, which is only one example of the embodiments of this application. The wafer can also be designed with other semiconductor materials, and the embodiments of this application do not make specific limitations in this regard.

[0042] Step S202: Form computing units on the wafer. Among them, the computing units at least include a plurality of computing dielets distributed in an array.

[0043] It can be understood that first design the circuit diagram of the computing dielets. For example, logic design, physical design, layout and wiring, etc. Then, transfer the designed circuit pattern to the wafer through lithography technology to form a plurality of computing dielets.

[0044] Step S203: Invert the wafer and thin the wafer.

[0045] It can be understood that in Steps 201 and 202, the upper surface of the wafer is the front side of the wafer. After inverting the wafer in Step 203, the upper surface of the wafer is the back side of the wafer.

[0046] In some embodiments, after the wafer is inverted, the wafer is placed with the back side facing up. At this time, the wafer can be thinned by chemical mechanical polishing (CMP) treatment, which can precisely control the thickness of the wafer and remove some defects on the wafer surface, such as scratches and microcracks, thereby improving the final chip yield.

[0047] In some embodiments, before Step S203, the method for preparing the above semiconductor structure may further include: depositing an insulating material on the computing unit to form an insulating layer; bonding the insulating layer to a carrier wafer.

[0048] It can be understood that bonding the carrier wafer can provide physical support for the inverted wafer and the computing unit, effectively preventing the wafer and the computing unit from being broken by external forces during the process of preparing the power supply network.

[0049] Step S204: Form a power supply network on the inverted wafer. Among them, the power supply network includes a plurality of power dielets distributed in an array, and the power dielets are used to supply power to the computing dielets.

[0050] It can be understood that after the wafer is inverted, on the back side of the wafer, use semiconductor standard technologies such as lithography, ion implantation, etching, and deposition to form the pattern of the power dielets.

[0051] In some possible embodiments, the above step S201 may include: forming a plurality of first metal vias in the wafer after flipping; the first metal vias penetrate the wafer; forming a plurality of power dies on the wafer after flipping; the power dies are electrically connected to the computing dies through the first metal vias; depositing an insulating material on the plurality of power dies to form a redistribution layer; forming a plurality of micro-bumps on the redistribution layer; the micro-bumps are electrically connected to the power dies and the computing dies.

[0052] It can be understood that after the wafer is flipped, a plurality of first metal vias are formed in the wafer. Then, a plurality of power dies are fabricated on the back side of the wafer, and the power dies are electrically connected to the computing dies on the front side of the wafer through the first metal vias. There are also a plurality of micro-bumps above the power dies. The micro-bumps are made of metal materials and are electrically connected to the power dies. The micro-bumps can serve as interfaces for connecting the semiconductor structure to the external circuit.

[0053] In the embodiments of the present application, the spacing between the distributed power dies is relatively large, and heat is more easily dissipated, thereby reducing the complexity of the heat dissipation design. In addition, the distributed arrangement helps to achieve a more uniform heat dissipation effect and avoid local overheating.

[0054] In some embodiments, a plurality of first metal vias are formed in the wafer through processes such as photolithography, etching, and deposition on the back side of the wafer. The first metal vias penetrate the wafer. After the first metal vias are fabricated, a plurality of power dies are fabricated on the wafer. Then, an insulating material is deposited on the power dies and the wafer to form a redistribution layer. Then, a plurality of second metal interconnect structures are formed in the redistribution layer through processes such as photolithography, etching, and deposition. The second metal interconnect structures are connected to a part of the first metal vias. The second metal interconnect structures and the power dies are in the same plane. Then, a plurality of micro-bumps are formed on the redistribution layer. The methods for forming the micro-bumps can be one of the following: printed bumps, ball placement method, evaporation plating method, and electroplating process.

[0055] In some embodiments, after the micro-bumps are formed, the semiconductor structure can be aligned with the packaging substrate, and the packaging can be completed according to the standard processes for fabricating chips.

[0056] In some possible embodiments, the micro-bumps include power micro-bumps and data micro-bumps; the power micro-bumps are electrically connected to the power dies; the data micro-bumps are electrically connected to the computing dies through the first metal vias.

[0057] It can be understood that according to the different structures of the connections inside the semiconductor structure, the micro-bumps can be divided into two categories, namely power micro-bumps and data micro-bumps. The power micro-bumps are connected to the power dies and are used to transfer electrical energy. The data micro-bumps are connected to the computing dies and are used for data transmission.

[0058] In some embodiments, the data microbumps are directly connected to the metal interconnect structure, which is in turn connected to the first metal via, and the first metal via is connected to the computing die; through the second metal interconnect structure and the first metal via, the data microbumps achieve electrical connection with the computing die.

[0059] In some possible implementation manners, the computing unit further includes a plurality of data allocation dies arranged in an array; forming the computing unit on the wafer includes: sequentially forming a plurality of computing dies and a plurality of data allocation dies on the wafer; the plurality of computing dies and the plurality of data allocation dies are stacked in a first direction.

[0060] It can be understood that in the case where the computing unit includes a computing die and a data allocation die, the computing die is first fabricated on the front side of the wafer, and then, the data allocation die is fabricated on the computing die. The data allocation die and the computing die are connected through a second metal via.

[0061] In some embodiments, after forming a plurality of computing dies, an insulating material is deposited above the computing dies and above the wafer to form a first isolation layer; the height of the first isolation layer is greater than the height of the computing die. Through photolithography, a plurality of grooves are formed in the first isolation layer, and a metal material is deposited in the grooves to form a plurality of second metal vias. Then, a plurality of data allocation dies are formed above the second metal vias; a metal material with a preset height is deposited between the data allocation dies and on the first isolation layer to form a first metal interconnect structure; adjacent data allocation dies are electrically connected through the first metal interconnect structure. Two ends of the second metal via are respectively connected to the computing die and the data allocation die, and the data of the computing die can enter the data allocation die through the second metal via and then be distributed by the data allocation die through the first metal interconnect structure.

[0062] In some possible implementation manners, the computing unit further includes a plurality of memory dies arranged in an array; forming the computing unit on the wafer includes: sequentially forming a plurality of computing dies and a plurality of memory dies on the wafer; the plurality of computing dies and the plurality of memory dies are stacked in a first direction.

[0063] It can be understood that in the case where the computing unit includes a computing die and a memory die, the computing die is first fabricated on the front side of the wafer, and then, the memory die is fabricated on the computing die. The memory die and the computing die are connected through a third metal via.

[0064] In some embodiments, after forming a plurality of computing dies, an insulating material is deposited over the computing dies and over the wafer to form a second isolation layer; the height of the second isolation layer is greater than the height of the computing dies. Through lithography, a plurality of grooves are formed in the second isolation layer, and a metal material is deposited in the grooves to form a plurality of third metal vias. Then, a plurality of memory dies are formed over the third metal vias; both ends of the third metal vias are respectively connected to the computing die and the memory die, and data of the computing die can enter the memory die through the third metal vias, and then the memory die stores the data.

[0065] In some possible implementation manners, the computing unit further includes a plurality of data allocation dies distributed in an array and a plurality of memory dies distributed in an array; forming the computing unit on the wafer includes: sequentially forming a plurality of computing dies, a plurality of data allocation dies, and a plurality of memory dies on the wafer; the plurality of computing dies, the plurality of data allocation dies, and the plurality of memory dies are stacked in a first direction.

[0066] It can be understood that in the case where the computing unit includes a computing die, a data allocation die, and a memory die, the computing die is first fabricated on the front side of the wafer, then the data allocation die is fabricated on the computing die, and finally the memory die is fabricated on the data allocation die. The data allocation die and the computing die are connected through a second metal via, and the memory die and the data allocation die are connected through a third metal via.

[0067] In some possible implementation manners, in the case where the computing unit includes a computing die, a data allocation die, and a memory die, the above-mentioned sequentially forming a plurality of computing dies, a plurality of data allocation dies, and a plurality of memory dies on the wafer includes: forming a plurality of computing dies distributed in an array on the wafer; depositing an insulating material over the plurality of computing dies to form a first isolation layer; forming a plurality of second metal vias in the first isolation layer; forming a plurality of data allocation dies distributed in an array on the first isolation layer; the plurality of data allocation dies are electrically connected to the computing dies through the second metal vias; forming a plurality of first metal interconnect structures between the plurality of data allocation dies and on the first isolation layer; the first metal interconnect structures are used to electrically connect adjacent data allocation dies; depositing an insulating material over the plurality of data allocation dies and the plurality of metal interconnect structures to form a second isolation layer; forming a plurality of third metal vias in the second isolation layer; forming a plurality of memory dies distributed in an array on the second isolation layer; the memory dies are electrically connected to the data allocation dies through the third metal vias.

[0068] In some embodiments, Figure 1 The semiconductor structure shown can be prepared through Figures 3A to 3F The process shown, Figures 3A to 3F is a schematic diagram of the preparation process of the semiconductor structure in the embodiments of the present application. It should be noted that, Figures 3A to 3FIn Figure (a), it is a top view of the semiconductor structure, and in Figure (b), it is a cross-sectional view of the semiconductor structure.

[0069] In one example, the fabrication process of the semiconductor structure may include the following steps:

[0070] The first step: Provide a silicon wafer 31, and form a plurality of computationally arranged dielets 32 in an array on the wafer 31 (see Figure 3A ).

[0071] The second step: Deposit an insulating material on the computationally arranged dielets 32 and the wafer 31 to form a first isolation layer 41; form a plurality of second metal vias 42 in the first isolation layer 41 through photolithography, etching, and deposition processes; form a data distribution dielet 33 and a first metal interconnect structure 43 on the first isolation layer 41 (see Figure 3B ). Among them, the data distribution dielet 33 is electrically connected to the computationally arranged dielets 32 through the second metal vias 42.

[0072] The third step: Deposit an insulating material on the first metal interconnect structure 43 and the data distribution dielet 33 to form a second isolation layer 44; form a plurality of third metal vias 45 in the second isolation layer 44; then, form a plurality of memory dielets 34 on the second isolation layer 44 (see Figure 3C ). Among them, the memory dielets 34 are electrically connected to the data distribution dielet 33 through the third metal vias 45.

[0073] The fourth step: Deposit an insulating material on the memory dielets 34 to form an insulating layer 46; bond a carrier wafer 35 to the insulating layer 46; flip the wafer 31, and thin the wafer 31 (see Figure 3D ).

[0074] The fifth step: Form a first metal via 47 in the thinned wafer 31; then, form a power supply dielet 36 on the thinned wafer 31 (see Figure 3E ). Among them, the power supply dielet 36 is electrically connected to the computationally arranged dielets 32 through the first metal via 47. The position of the power supply dielet 36 matches that of the computationally arranged dielets 32 to ensure the power supply for each computationally arranged dielet 32.

[0075] The sixth step: Deposit an insulating material on the power supply dielet 36 and the wafer 31 to form a redistribution layer 48; form a second metal interconnect structure 49 in the redistribution layer 48; then, form a plurality of microbumps 37 on the second metal interconnect structure 49 and the power supply dielet 36 (see Figure 3F ). Among them, a part of the microbumps 37 is electrically connected to the power supply dielet 36, and another part of the microbumps is electrically connected to the computationally arranged dielets 32 through the second metal interconnect structure 49 and the first metal via 47.

[0076] Thus, the above-mentioned semiconductor structure is fabricated.

[0077] In the embodiments of the present application, a computing unit is fabricated on the front side of a wafer. By flipping the wafer and forming a plurality of power die distributed in an array on the flipped wafer (i.e., the back side of the wafer), distributed power supply can be achieved while reducing power supply loss.

[0078] Furthermore, fabricating a power supply network on the back side of the wafer is also beneficial to improving the system performance of the semiconductor structure.

[0079] Furthermore, the semiconductor structure provided by the embodiments of the present application can be detected using detection and analysis instruments, such as: scanning electron microscope (SEM), transmission electron microscope (TEM), scanning transmission electron microscopy (STEM), etc. Taking TEM as an example, the semiconductor structure provided by the embodiments of the present application can be detected by means of TEM sectioning. For example, the computing die and the power die are located on two sides of the wafer respectively and are connected through a first metal via; the redistribution layer, the micro-bump and the power die are located on the same side of the wafer (i.e., the back side); the micro-bump is connected to the power die; the micro-bump is connected to the computing die through a second metal interconnect structure and a first metal via.

[0080] In the embodiments of the present application, the above semiconductor structure can be applied to semiconductor devices such as memories and processors.

[0081] The embodiments of the present application provide a semiconductor device, including: the semiconductor structure as described in the above embodiments. For the specific definition of the semiconductor structure, reference can be made to the semiconductor structure shown above, which will not be elaborated here. Figure 1 shown semiconductor structure, which will not be elaborated here.

[0082] The embodiments of the present application provide an electronic device, including: a circuit board and the semiconductor device as described in the above embodiments, and the semiconductor device is disposed on the circuit board. The semiconductor device includes the above semiconductor structure. For the specific definition of the semiconductor structure, reference can be made to the above, Figure 1 which will not be elaborated here.

[0083] In the description of the present application, the description referring to terms such as "one embodiment", "some embodiments", "example", "specific example", or "some examples" means that the specific features, structures, materials, or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the embodiments of the present application. In the present application, the schematic expressions of the above terms are not necessarily directed to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described can be combined in any one or more embodiments or examples in a suitable manner. In addition, without contradiction, those skilled in the art can combine the different embodiments or examples described in the present application and the features of different embodiments or examples.

[0084] The above are only the preferred embodiments of the present application and are not used to limit the present application. For those skilled in the art, the present application can have various changes and modifications. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included within the protection scope of the present application.

Claims

1. A method for preparing a semiconductor structure, characterized in that: include: providing a wafer; forming a computing unit on the wafer; The computing unit at least includes a plurality of computing core particles distributed in an array; Flipping the wafer and thinning the wafer; A power supply network is formed on the flipped wafer; the power supply network includes a plurality of power supply core particles distributed in an array, and the power supply core particles are used to supply power to the computing core particles.

2. The method according to claim 1, characterized in that The step of forming a power supply network on the flipped wafer includes: forming a plurality of first metal through holes in the flipped wafer; the first metal through holes penetrate the wafer; forming a plurality of power core particles on the flipped wafer; the power core particles are electrically connected to the computing core particles through the first metal vias; depositing an insulating material on the plurality of power chips to form a redistribution layer; A plurality of micro bumps are formed on the redistribution layer; the micro bumps are electrically connected to the power core particle and the computing core particle.

3. The method according to claim 2, characterized in that The micro-bumps include power micro-bumps and data micro-bumps; The power micro-bump is electrically connected to the power core particle; The data micro-bump is electrically connected to the computing core particle through the first metal through hole.

4. The method according to claim 1, characterized in that: The computing unit also includes a plurality of data deployment core particles distributed in an array; The forming of a computing unit on the wafer comprises: The plurality of computing core particles and the plurality of data allocation core particles are sequentially formed on the wafer; the plurality of computing core particles and the plurality of data allocation core particles are stacked in a first direction.

5. The method according to claim 1, characterized in that The computing unit also includes a plurality of storage core particles distributed in an array; The forming of a computing unit on the wafer comprises: The plurality of computing cores and the plurality of storage cores are sequentially formed on the wafer; the plurality of computing cores and the plurality of storage cores are stacked in a first direction.

6. The method according to claim 1, characterized in that The computing unit also includes a plurality of storage core particles distributed in an array and a plurality of storage core particles distributed in an array; The forming of a computing unit on the wafer comprises: The plurality of computing core particles, the plurality of data allocation core particles and the plurality of storage core particles are sequentially formed on the wafer; the plurality of computing core particles, the plurality of data allocation core particles and the plurality of storage core particles are stacked in a first direction.

7. The method according to claim 6, characterized in that The step of sequentially forming the plurality of computing core particles, the plurality of data allocation core particles and the plurality of storage core particles on the wafer comprises: forming a plurality of computing core particles distributed in an array on the wafer; Depositing an insulating material on the plurality of computing cores to form a first isolation layer; forming a plurality of second metal vias in the first isolation layer; A plurality of data allocation core particles distributed in an array are formed on the first isolation layer; the plurality of data allocation core particles are electrically connected to the computing core particles through the second metal through holes; A plurality of metal interconnect structures are formed on the first isolation layer and between the plurality of data deployment core particles; the metal interconnect structures are used to electrically connect adjacent data deployment core particles; Depositing an insulating material on the plurality of data deployment cores and the plurality of metal interconnect structures to form a second isolation layer; forming a plurality of third metal vias in the second isolation layer; A plurality of storage core particles distributed in an array are formed on the second isolation layer; the storage core particles are electrically connected to the data allocation core particles through the third metal through holes.

8. A semiconductor structure, characterized in that: Prepared by the method according to any one of claims 1 to 7, the semiconductor structure comprises: Wafer; A computing unit; the computing unit at least comprises a plurality of computing core particles distributed in an array; the computing unit is located on the front side of the wafer; A power supply network; the power supply network includes a plurality of power core particles distributed in an array, and the power core particles are used to supply power to the computing core particles; the power supply network is located on the back side of the wafer.

9. A semiconductor device, characterized in that: include: The semiconductor structure as claimed in claim 8.

10. An electronic device, characterized in that: include: A circuit board and a semiconductor device as claimed in claim 9, wherein the semiconductor device is arranged on the circuit board.

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