Microelectronic device assemblies and packages and related methods and systems

Abstract

A microelectronic device assembly is disclosed that includes a substrate having a conductor exposed on a surface thereof. Two or more microelectronic devices are stacked on the substrate, each microelectronic device including an active surface having a bond pad operably coupled to a conductive trace extending over a dielectric material to a via location outside at least one side of the stack, and a via extending through the dielectric material at the via location and comprising a conductive material in contact with at least some of the conductive traces of each of the two or more microelectronic devices and extending to an exposed conductor of the substrate. Methods of manufacture and related electronic systems are also disclosed.

Description

[0001] Priority Statement

[0002] This application is a divisional application of a patent application for invention with an application date of September 21, 2020, an application number of "202080081502.5", and an invention title of "Microelectronic Device Assemblies and Packages and Related Methods and Systems". The parent case is the national stage entry of the international patent application PCT / US2020 / 051727, which was filed on September 21, 2020, designating the People's Republic of China and published in English as international patent publication WO 2021 / 076274 A1 on April 22, 2021. The said application claims the benefit of U.S. Provisional Patent Application Serial No. 62 / 916,371, filed on October 17, 2019, entitled "Methods for Fabrication of Microelectronic Device Packages and Related Packages and Systems", U.S. Provisional Patent Application Serial No. 63 / 037,902, filed on June 11, 2020, entitled "Methods for Fabrication of Microelectronic Device Packages and Related Packages and Systems", and U.S. Patent Application Serial No. 16 / 939,756, filed on July 27, 2020, entitled "Microelectronic Device Assemblies and Packages and Related Methods and Systems", the disclosure of each of which is incorporated herein by reference in its entirety.

[0003] The subject matter of the present application relates to U.S. Patent Application Serial No. 16 / 939,650, entitled "Microelectronic Device Assemblies and Packages Including Multiple Device Stacks and Related Methods," filed on July 27, 2020, U.S. Patent Application Serial No. 16 / 939,678, entitled "Microelectronic Device Assemblies and Packages and Related Methods," filed on July 27, 2020, and U.S. Patent Application Serial No. 16 / 939,720, entitled "Microelectronic Device Assemblies and Packages Including Surface Mount Components," filed on July 27, 2020, the disclosures of each of which are incorporated herein by reference in their entirety. TECHNICAL FIELD

[0004] The embodiments disclosed herein relate to the manufacture of microelectronic device assemblies and packages. More specifically, the embodiments disclosed herein relate to microelectronic device assemblies and packages including stacked microelectronic devices employing external vertical conduction paths, and to manufacturing methods and systems incorporating such packages. BACKGROUND ART

[0005] As the electronics industry moves toward three-dimensional assemblies of stacked microelectronic devices, most commonly in the form of stacked semiconductor die, the time and cost of vertically connecting aligned conductive elements of a stacked die to conductive elements of a substrate prior to encapsulating the die stack has become an issue. Conventionally, multiple singulated semiconductor die, including so-called through-substrate vias (TSVs, also referred to as "through-silicon vias") where conductive elements in the form of pillars and pads terminate at opposite surfaces of each semiconductor die, are stacked together with the pillars of one die aligned with the pads of an adjacent die. Each die stack may be formed on and aligned with conductive elements at die sites of an unsingulated substrate wafer, other bulk semiconductor substrate, or other component. The pillars may comprise a single conductive material such as copper, or a conductive material capped with solder. While the topmost semiconductor die in a stack may not be equipped with TSVs, the pillars of such semiconductor die are aligned with the pads of the next lower semiconductor die and communicate through the TSVs for signal, power, and ground (e.g., bias) purposes, as is the case for other semiconductor die in the stack.

[0006] The use of TSVs presents a number of issues in terms of manufacturing cost and the resulting package. For example, the fabrication of TSVs conventionally involves forming blind holes in a semiconductor wafer prior to thinning, followed by lining the holes with a dielectric material to electrically isolate the conductive material of the TSV. In a post-wafer final processing step, conductive pillars are formed on one side of the TSV (i.e., on the active surface of the wafer), and conductive pads are formed thereon after the semiconductor wafer is thinned to expose the conductive material. Additionally, after singulating semiconductor die from the semiconductor wafer, the semiconductor die are stacked together with aligned pillars, TSVs, and pads for subsequent interconnection of adjacent pillars and pads by thermocompression bonding according to the state of the art.

[0007] Thermocompression bonding techniques that apply heat and pressure (i.e., vertical force) to diffusion bond conductive elements of a semiconductor die to conductive elements of another semiconductor die or other substrate have proven to provide robust mechanical and electrical connections between components. However, when multiple stacked semiconductor die are to be diffusion bonded, thermocompression bonding is expensive and time-consuming, and the implementation of three-dimensional (3D) assemblies of semiconductor die with smaller conductive elements in the form of copper pillars at reduced pitch is an increasingly common requirement at a commercial scale. For example, stacks of memory die can be fabricated that include four, eight, twelve, or even sixteen die as a complete assembly, or stacks of memory die in combination with logic die as may be implemented in a hybrid memory cube architecture, and such stacks that contain device logic die in the case of a high bandwidth memory (HBM) architecture.

[0008] For example, when multiple semiconductor die are to be stacked on die sites of a bulk semiconductor substrate (e.g., a wafer), as the stack is formed, a singulated die of a given layer is placed and then thermocompression groups are bonded one by one to the base wafer or the die of a lower layer by applying heat and pressure, and this process is repeated die layer by die layer until a stack of die of a desired number (e.g., four die, eight die, etc.) is reached. Even when such stacking and group bonding is performed at the wafer level, it will be understood that such an approach is cost and time intensive, requiring multiple actions of stacking and individually group bonding the die of each die layer using a pick-and-place apparatus with a bonding head before proceeding to form the next higher layer. Additionally, conventional thermocompression bonding of copper-copper conductive elements is a solid-state diffusion bonding process that results in atomic interdiffusion and grain growth between two adjacent metal surfaces occurring at undesirably high temperatures, even for so-called "low temperature" bonding which is on the order of about 300 °C. Due to the thermal budget limitations of the die, as well as thermal mechanical stress control and alignment accuracy limitations after bonding, it is desirable to avoid such temperatures associated with thermocompression bonding.

[0009] In addition to the foregoing, the use of TSVs for vertical conductive paths in the stacking of semiconductor die also consumes valuable substrate area (i.e., area) on each die. As semiconductor die become smaller and the critical dimensions and pitch of features decrease in size to increase circuit density, the use of TSVs becomes less desirable, especially as the number of semiconductor die in the stack increases. This is a particular problem for memory devices incorporating an increasing number of smaller and more densely distributed memory cells, although the problem is not limited thereto. SUMMARY OF THE INVENTION

[0010] Embodiments of the present disclosure include a microelectronic device assembly that includes: a substrate having a conductor exposed on its surface; a stack of two or more microelectronic devices on the substrate, each microelectronic device including an active surface having bonding pads operably coupled to conductive traces that extend over a dielectric material to a via location outside of at least one side of the stack; and vias that extend through the dielectric material at the via location and include conductive material that contacts at least some of the conductive traces of each of the two or more microelectronic devices and extends to the exposed conductor of the substrate.

[0011] Embodiments of the present disclosure include an electronic system, the electronic system including an input device, an output device, a processor device, and at least one memory device. At least one of the processor device, the at least one memory device, or a combination thereof is configured to include a stacked assembly on a substrate composed of two or more semiconductor die, each semiconductor die including an active surface operatively coupled to a conductive trace, the conductive trace extending over a dielectric material toward a conductive via located outside at least one side of the stack, wherein the via extends through the dielectric material to a conductor of the substrate, and at least some of the conductive traces of each of the two or more semiconductor die are operatively coupled to at least some of the conductive vias.

[0012] Embodiments of the present disclosure include a method, the method including: providing a singulated semiconductor die on a dielectric material, the singulated semiconductor die having a conductive trace extending over its active surface and outside at least one lateral periphery thereof; forming a stack of the singulated semiconductor die on a substrate in a spaced-apart relationship; forming a via at a location through the conductive trace and the dielectric material to a conductive pad or trace extending onto an adjacent surface of the substrate outside at least one lateral periphery of the semiconductor die in the stack; and filling the via with a conductive material.

[0013] Embodiments of the present disclosure include a method, the method including: forming a reconstituted wafer or panel of semiconductor die by adhesively attaching semiconductor die to a fan-out package configuration redistribution layer (FOP-configured RDL) wafer or panel through their active surfaces in a spaced-apart relationship, the FOP-configured RDL wafer or panel having traces extending from bond pads to areas on the RDL outside a coverage area of each semiconductor die; laterally encapsulating the reconstituted wafer or panel of semiconductor die in an epoxy molding compound (EMC); attaching the reconstituted wafer or panel of semiconductor die to a die attach film (DAF) on one side of the EMC opposite the FOP-configured wafer or panel; singulating the semiconductor die, the FOP-configured RDL wafer or panel, the EMC, and the DAF; stacking the singulated semiconductor die, the FOP-configured RDL, the EMC, and the DAF; forming an opening at a via location through the singulated RDL, EMC, and DAF; and filling the opening with a conductive material.

[0014] Embodiments of the present disclosure include a method comprising: forming a reconstructed wafer or panel of semiconductor dies by adhesively attaching singulated semiconductor dies to a redistribution layer (RDL) wafer or panel in a fan-out package configuration (FOP-configured RDL) through an active surface in a spaced-apart relationship, the FOP-configured RDL wafer or panel having traces extending from bonding pads to areas on the RDL beyond the coverage regions of each semiconductor die; encapsulating the reconstructed wafer or panel of semiconductor dies in an epoxy molding compound (EMC); laminating a polymer film over the FOP-configured RDL; singulating the semiconductor dies, the EMC, the FOP-configured RDL wafer or panel, and the polymer film; inverting and stacking the singulated semiconductor dies, the FOP-configured RDL, the EMC, and the polymer film; forming openings through the singulated RDL, EMC, and polymer film at via locations; and filling the openings with a conductive material. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1A1 and 1A2 A flowchart of an embodiment of a method for manufacturing a microelectronic device package according to the present disclosure;

[0016] Figure 1B is a side cross-sectional schematic view of a microelectronic device package according to an embodiment of the present disclosure, and the microelectronic device package can be manufactured according to Figure 1A1 and 1A2 the method;

[0017] Figure 2A is a flowchart of another embodiment of a method for manufacturing a microelectronic device package according to the present disclosure;

[0018] Figure 2B is a side partial cross-sectional schematic view of a microelectronic device package according to an embodiment of the present disclosure, and the microelectronic device package can be manufactured according to Figure 2A the method;

[0019] Figure 3A is a flowchart of an embodiment of a method for manufacturing a microelectronic device package according to the present disclosure;

[0020] Figure 3B is a side cross-sectional schematic view of a microelectronic device package according to an embodiment of the present disclosure, and the microelectronic device package can be manufactured according to Figure 3A the method;

[0021] Figure 4A - 4D is a schematic top elevation view of a die stack according to an embodiment of the present disclosure, showing various embodiments including through-poly vias on one side, two sides, three sides, or four sides of the die stack;

[0022] Figure 5A and 5B are schematic top elevation views of die stacks according to embodiments of the present disclosure, which show different arrangements of multiple rows of through-polysilicon vias, and Figure 5C is a schematic side elevation view of an embodiment of the present disclosure, which includes a Faraday cage that includes surrounding through-silicon vias and a ground structure over the die stack;

[0023] Figure 6A - 6D is a schematic diagram of different exemplary configurations of the connection between a conductive trace and the conductive material of a through-polysilicon via;

[0024] Figure 7 is a block diagram of an electronic system incorporating one or more semiconductor packages according to embodiments of the present disclosure;

[0025] Figure 8A is a flowchart of an embodiment of a method for manufacturing a microelectronic device package including a stack of multiple microelectronic devices according to the present disclosure, and Figure 8B is a schematic side cross-sectional view of a microelectronic device package including a stack of multiple microelectronic devices according to embodiments of the present disclosure;

[0026] Figure 9A is a flowchart of an embodiment of a method for manufacturing a microelectronic device for directly attaching a chip to a substrate according to the present disclosure, and Figure 9B depicts the process sequence regarding Figure 9A described;

[0027] Figure 9C depicts additional embodiments for forming Figure 9A and 9B of a die stack;

[0028] Figure 10A is a flowchart of an embodiment of a method for manufacturing a microelectronic device assembly incorporating surface-mounted components according to the present disclosure, and Figure 10B1 - 10D shows different die assemblies incorporating surface-mounted components;

[0029] Figure 11A is a flowchart of an embodiment of a method for manufacturing a microelectronic device assembly incorporating an inductive coupling loop (ICL) for data signal transmission and through-polysilicon vias (TPVs) for power and ground biasing according to the present disclosure, and Figure 11B is a schematic side cross-sectional elevation view of a microelectronic device package according to embodiments of the present disclosure, which can be manufactured according to the method of Figure 11A ;

[0030] Figure 12 is a side - view cross - sectional schematic elevation view of a microelectronic device assembly incorporating through - silicon vias (TSVs) and through - polysilicon vias (TPVs) according to an embodiment of the present disclosure;

[0031] Figure 13A is a flowchart of an embodiment of a method for manufacturing a microelectronic device package with a redistribution layer (RDL) using a fan - out package (FOP) configuration according to the present disclosure, and Figure 13B is a side - view cross - sectional schematic view of a microelectronic device package with an RDL using an FOP configuration according to an embodiment of the present disclosure; and

[0032] Figure 14A is a flowchart of an embodiment of a method for manufacturing a microelectronic device package with an RDL using an FOP configuration combined with a TPV according to the present disclosure, and Figure 14B is a side - view cross - sectional schematic view of a microelectronic device package with an RDL using an FOP configuration combined with a TPV according to an embodiment of the present disclosure. Detailed Description

[0033] A microelectronic device package including a plurality of stacked microelectronic devices (e.g., semiconductor dies) without TSVs and a method for manufacturing such a package and related electronic systems.

[0034] The following description provides specific details, such as size, shape, material composition, and orientation, in order to provide a comprehensive description of embodiments of the present disclosure. However, those of ordinary skill in the art should understand that embodiments of the present disclosure may be practiced without necessarily adopting these specific details. Embodiments of the present disclosure may be practiced in conjunction with conventional manufacturing techniques employed in the industry. Additionally, the description provided below does not form a complete process flow for manufacturing a microelectronic package, a structure including a microelectronic package, or a system including a microelectronic package (e.g., an electronic system). Only those process operations and materials necessary for understanding embodiments of the present disclosure are described in detail below. Additional operations and materials for forming a complete microelectronic device package, a complete structure including a microelectronic package, or a complete system including a microelectronic package may be performed by conventional manufacturing processes.

[0035] The accompanying drawings presented herein are for illustrative purposes only and are not intended as actual views of any specific material, component, structure, device, or system. Variations in the shapes depicted in the drawings due to, for example, manufacturing techniques and / or tolerances should be expected. Thus, the embodiments described herein should not be construed as limited to the specific shapes or regions shown, but rather include shape deviations resulting from, for example, manufacturing. For example, regions shown or described as box-shaped may have rough and / or non-linear features, and regions shown or described as circular may contain some rough and / or linear features. Additionally, acute angles between the surfaces shown may be rounded, and vice versa. Thus, the regions shown in the drawings are schematic in nature, and their shapes are not intended to show the exact shape of the regions and do not limit the scope of the claims of the present invention. The drawings are not necessarily drawn to scale.

[0036] As used herein, the terms "comprising," "including," "containing," "characterized by," and their grammatical equivalents are inclusive or open-ended terms that do not exclude additional, unrecited elements or method acts, and also encompass the more restrictive terms "consisting of" and "consisting essentially of" and their grammatical equivalents. As used herein, the term "may" with respect to a material, structure, feature, or method act indicates that these are contemplated for use in embodiments of the present disclosure, and such terms are used in preference to the more restrictive term "is" to avoid any implication that other compatible materials, structures, features, and methods that could be used in conjunction therewith should or must be excluded.

[0037] As used herein, the terms "longitudinal," "vertical," "lateral," and "horizontal" refer to the main plane of the substrate (e.g., the base material, base structure, base configuration, etc.) in or on which one or more structures and / or features are formed, and the one or more structures and / or features are not necessarily defined by the Earth's gravitational field. The "lateral" or "horizontal" direction is a direction that is substantially parallel to the main plane of the substrate, while the "longitudinal" or "vertical" direction is a direction that is substantially perpendicular to the main plane of the substrate. The main plane of the substrate is defined by a substrate surface that has a relatively larger area compared to other surfaces of the substrate.

[0038] As used herein, for ease of description, spatial relative terms such as "below", "beneath", "lower", "bottom", "above", "over", "upper", "top", "front", "rear", "left", "right", etc. may be used to describe the relationship of one element or feature shown in the drawings to another or other elements or features. Unless otherwise stated, spatial relative terms are also intended to cover different material orientations in addition to the orientation depicted in the drawings. For example, if the material in the drawings is inverted, an element described as "above" or "over" or "on top of" or "at the top of" other elements or features will be oriented "below" or "beneath" or "under" or "at the bottom of" other elements or features. Thus, depending on the context in which the term is used, the term "above" can cover both the above and below orientations, which will be apparent to those of ordinary skill in the art. The material may be oriented otherwise (e.g., rotated 90 degrees, inverted, flipped), and the spatial relative descriptors used herein may be interpreted accordingly.

[0039] As used herein, unless the context clearly indicates otherwise, the singular forms "a / an" and "the" are intended to also include the plural forms.

[0040] As used herein, the terms "configured" and "configuration" refer to the size, shape, material composition, orientation, and arrangement of one or more of at least one structure and at least one device, which facilitate the operation of one or more of the structure and device in a predetermined manner.

[0041] As used herein, the term "substantially" with respect to a given parameter, property, or condition means and includes to a degree that one of ordinary skill in the art would understand that the given parameter, property, or condition meets a degree of variance, such as variance within acceptable manufacturing tolerances. By way of example, depending on the particular parameter, property, or condition that is substantially met, the parameter, property, or condition may be met at least 90.0%, at least 95.0%, at least 99.0%, or even at least 99.9%.

[0042] As used herein, "about" or "approximately" with respect to a value of a particular parameter encompasses the recited value and a degree of variation from the recited value that a person of ordinary skill in the art will understand to be within an acceptable tolerance for the particular parameter. For example, "about" or "approximately" with respect to a value may include additional values that are within the range of 90.0% to 110.0% of the recited value, such as within the range of 95.0% to 105.0% of the recited value, within the range of 97.5% to 102.5% of the recited value, within the range of 99.0% to 101.0% of the recited value, within the range of 99.5% to 100.5% of the recited value, or within the range of 99.9% to 100.1% of the recited value.

[0043] As used herein, the terms "layer" and "film" mean and include a layer, sheet, or coating of material residing on a structure, which layer or coating may be continuous or discontinuous and conformal or non-conformal between portions of the material, unless otherwise specified.

[0044] As used herein, the term "substrate" means and includes a base material or structure on which additional materials are formed or additional structures are positioned or both. A substrate may be a semiconductor substrate, a base semiconductor layer on a support structure, a metal electrode, or a semiconductor substrate having one or more materials, one or more layers, one or more structures, or one or more regions formed thereon. Materials on a semiconductor substrate may include, but are not limited to, semiconductor materials, insulating materials, conductive materials, etc. A substrate may be a conventional silicon substrate or other bulk substrate including a layer of semiconductor material. As used herein, the term "bulk substrate" means and includes not only silicon wafers but also silicon-on-insulator ("SOI") substrates (such as silicon-on-sapphire ("SOS") substrates and silicon-on-glass ("SOG") substrates), silicon epitaxial layers on a base semiconductor foundation, and other semiconductor or optoelectronic materials such as silicon-germanium, germanium, gallium arsenide, gallium nitride, and indium phosphide. A substrate may be doped or undoped. In some embodiments, a substrate may include an interlayer or a circuit board.

[0045] As used herein, the terms "comprises," "comprising," "includes," "including," "has," "having," and their grammatical equivalents are inclusive or open-ended terms that do not exclude additional, unrecited elements or method steps, and also include the more restrictive terms "consisting of" and "consisting essentially of" and their grammatical equivalents.

[0046] As used herein, the term "configured" refers to the size, shape, material composition, orientation, and arrangement of one or more of at least one structure and at least one device, the size, shape, material composition, orientation, and arrangement being adapted to operate one or more of the structure and device in a predetermined manner.

[0047] As used herein, the term "may" with respect to a material, structure, feature, or method act indicates that these are contemplated for use in embodiments of the present disclosure, and such terms are used in preference to the more restrictive term "is" to avoid any implication that other compatible materials, structures, features, and methods that should or must be excluded from being used in combination therewith.

[0048] As used herein, the term "wafer" shall be broadly construed to mean and include conventional semiconductor material wafers as well as other bulk substrates including semiconductor material on another support material.

[0049] As used herein, the term "microelectronic device" means and includes singulated semiconductor die, multiple sets of non-singulated semiconductor die, die and die sets that include functions in addition to those that rely on the functionality of semiconductor material (e.g., optical devices and MEMS devices). Also, as used herein, the term "semiconductor die" may be broadly construed to encompass other microelectronic devices.

[0050] As used herein, the terms "fan-out package" and "FOP" mean and include a microelectronic device package that includes at least one layer of conductive traces carried on a dielectric material such as a film and operatively coupled to bond pads of an associated semiconductor die and extending (i.e., fanning out) to a location beyond the periphery of the die on one or more of its sides. Similarly, a redistribution layer or "RDL" in a FOP configuration is a redistribution layer that includes at least one layer of conductive traces carried on a dielectric material such as a film and is configured to have an inner end at the location of the bond pads of the semiconductor to be operatively coupled to conductive traces that extend (e.g., fan out) to a location beyond the periphery of the mounting location of the semiconductor die, leading to a location beyond the periphery of the mounting location of the die on one or more of its sides.

[0051] As used herein, "memory device" means and includes microelectronic devices that exhibit, but are not limited to, memory functionality.

[0052] Figure 1A1 and 1A2These are two parts of a flowchart of an embodiment of a method 100 for manufacturing a microelectronic device package according to the present disclosure. In operation 102, an active circuit system (e.g., DRAM, NAND, 3D XPoint (e.g., SXP)) without TSVs is fabricated at die locations on the active surface of a semiconductor substrate (e.g., a wafer). In operation 104, the wafer is probed to determine the locations of known good dies (KGDs). In operation 106, the wafer is thinned, e.g., from an initial thickness of about 600 μm to about 700 μm, e.g., to a thickness of about 5 μm to about 200 μm, and as a specific non-limiting example, to a thickness approximating about 100 μm, about 50 μm, or about 30 μm. However, it should be noted that embodiments of the method are not limited to any particular die thickness. Then, at operation 108, the wafer is singulated (i.e., cut) into individual KGDs using conventional processes (saw blade, laser, stealth (i.e., laser-induced street-like defects followed by fracture caused by radial expansion of a carrier film), etc.). In operation 110, the singulated KGDs are then (optionally) formed into a reconstituted wafer or panel of KGDs by placing and adhering them in a spaced-apart relationship to each other through their back sides on an adhesive film (e.g., a die attach film (DAF) or a film-on-die (FOD)-type material). In operation 112, a film is laminated over the front sides (i.e., the active surfaces) of the spaced-apart KGDs of the reconstituted wafer or panel, or over the active surfaces of the singulated KGD locations thereon, the film being, for example, a wafer or panel-level film such as a non-conductive film (NCF) including silica-filled epoxy, a b-stage polyimide film, a polytetrafluoroethylene (PTFE) film, or other polymer film. In operation 114, openings are formed through the film (e.g., by laser ablation) to expose the bond pad locations on the active surfaces of the KGDs, and subsequently, optionally, a solvent cleaning operation is performed to remove any residues generated by the laser ablation at the bond pad locations, thereby ensuring robust electrical connections between the conductive traces to be formed on the polymer film in operation 116. In operation 116, a conductive material, e.g., an Ag or Cu paste, is dispensed to form conductive traces on the polymer film, the conductive traces extending from the bond pads to a predetermined via location outside the lateral periphery of the KGDs. Alternatively, the conductive traces can be applied by inkjet technology. In operation 118, the KGDs are singulated laterally outside the predetermined via locations through the polymer film, and the KGDs are stacked on a substrate, which can be a wafer-level substrate to be singulated into individual substrates and carrying multiple stacks of KGDs in a spaced-apart relationship. In operation 120, vias (which can be referred to as through-polysilicon vias (TPVs)) can be formed, e.g., by laser or patterned and anisotropic etching, through the film in the KGD stack at the via locations and extending them to conductive pads or traces on an adjacent surface of the substrate.In operation 122, the vias are filled with a sintered Ag or Cu paste or other conductive material, such as using an inkjet type applicator. As another method, the vias can be filled with Sn solder in a wave soldering process. In operation 124, the assembly can be (optionally) encapsulated with an epoxy molding compound (EMC), conductive elements (e.g., solder bumps in a ball grid array (BGA) format coupled to conductive paths that are coupled to conductive pads or traces extending onto the substrate surface adjacent to the KGD stack) are applied or formed on the substrate opposite the KGD stack, testing is performed, and the KGD stack is singulated through the EMC (if present) and the substrate to form a package. In operation 126, the top of the die stack can be covered with EMC or it can be left exposed, e.g., for attaching a heat sink with a thermal interface material (TIM).

[0053] Figure 1B is a side cross-sectional schematic view of a microelectronic device package 150 according to an embodiment of the present disclosure, and the microelectronic device package can be according to Figure 1A1 and 1A2Manufactured by the method. The microelectronic device package 150 includes a substrate 152 having traces (not shown) carried in a dielectric material and extending from conductive pads 154 on its upper surface to conductive elements 156 on its opposite lower surface. The conductive elements 156 can include, for example, solder balls formed on or applied to the under bump metallization (UBM) layer of the substrate 152. A plurality of semiconductor dies 160A - 160D (e.g., dies configured as double data rate (DDRx) DRAM, NAND flash memory, or 3D Xpoint (e.g., SXP) memory) are stacked on the upper surface of the substrate 152. Each semiconductor die 160A - 160D is laminated to a polymer film 162, such as a non - conductive film (NCF), a b - stage polyimide film, or a polytetrafluoroethylene (PTFE) film that extends beyond at least one lateral periphery of the corresponding die 160A - 160D on one or more of its sides (two sides are shown). Each semiconductor die 160A - 160D is attached to a DAF 164 on its back surface 166. If an NCF exhibiting sufficient adhesive properties is used for lamination purposes, the DAF can be eliminated. Conductive traces 168 extend laterally outward from bonding pad locations (not shown) on the active surface 170 of each semiconductor die 160A - 160D above the upper surface 172 of the polymer film 162, extending at least to the location of vias 174 filled with conductive material 176 that extend between the semiconductor dies 160A - 160D and to the conductive pads 154 of the substrate 152. As shown by the dashed line, the semiconductor dies 160A - 160D can be encapsulated in an EMC 178 that extends, for example, at least around the lateral periphery of the die stack 180 and abuts the upper surface of the substrate 152. As shown, the EMC 178 can extend above the uppermost semiconductor die 160D. Alternatively, the EMC 178 can have the uncovered active surface 170 and the conductive traces 168 covered by a thin dielectric layer that can include a thermal interface material (TIM) 182 and a heat sink 184, both shown by the dashed line, for enhancing heat transfer from the microelectronic device package 150.

[0054] Figure 2AFIG. 0 is a flow chart of an embodiment of a method 200 for fabricating a microelectronic device package in accordance with the present disclosure. In 202, an active circuit system (e.g., DRAM, NAND, 3D XPoint (e.g., SXP)) without TSVs is fabricated at die locations on an active surface of a semiconductor substrate (e.g., a wafer). In act 204, the wafer is probed to determine the locations of known good dies (KGDs). In act 206, the wafer is thinned, e.g., from an initial thickness of about 600 μm to about 700 μm, e.g., to a thickness of about 5 μm to about 50 μm, and as a specific example, to a thickness approximating about 30 μm. However, it should be noted that embodiments of the method are not limited to any particular die thickness. The wafer is then singulated (i.e., cut) at act 208 using conventional processes (saw blade, laser, stealth (i.e., laser-induced street-like defects followed by fracture caused by radial expansion of a carrier film), etc.). In act 210, a reconstructed wafer or panel of KGDs is then formed by placing the singulated KGDs face-up (i.e., active surface) in a spaced-apart relationship and adhering them to die mounting locations on a panel or wafer configured as a plurality of fan-out package (FOP) redistribution layers (RDLs), each layer having one or more conductive (e.g., copper) traces carried by a dielectric material, the conductive traces extending beyond at least one lateral periphery of the associated die location. In act 212, a film is laminated over the backside of the KGDs of the reconstructed wafer or panel, the film being, e.g., a wafer-level film such as a non-conductive film (NCF), a b-stage polyimide film, a polytetrafluoroethylene (PTFE) film, or other polymer film. In act 214, the polymer film and the FOP-configured panel or wafer are singulated into segments, each segment carrying a separate FOP RDL and KGD. In act 216, the segments are then stacked on a substrate, which may be a wafer-level substrate to be singulated into individual substrates and carrying a plurality of KGD stacks in a spaced-apart relationship. In act 218, openings (which may be referred to as TPVs) are formed through the polymer film and through conductive traces of the FOP-configured RDLs that extend onto an adjacent surface of the substrate, e.g., by laser ablation or anisotropic etching. In act 220, the vias are filled with an Ag or Cu paste or other conductive material, e.g., using an inkjet-type applicator. As another example, the vias may be filled with Sn solder in a wave soldering process. In act 222, the assembly may be (optionally) encapsulated with an epoxy molding compound (EMC), conductive elements (e.g., solder bumps in a ball grid array (BGA) format) are applied or formed on the substrate opposite the KGD stack, testing is performed, and the KGD stack is singulated through the EMC (if present) and the substrate to form packages.In operation 224, the top of the die stack may be covered with an EMC (if present), or it may be exposed, e.g., for attaching a heat sink with a thermal interface material (TIM).

[0055] Figure 2B FIG. 4 is a side cross-sectional schematic view of a microelectronic device package 250 according to an embodiment of the present disclosure, and the microelectronic device package may be manufactured according to Figure 2A the method. The microelectronic device package 250 includes a substrate 252 having traces (not shown) carried in a dielectric material and extending from conductive pads 254 on its upper surface to conductive elements 256 on its opposite lower surface. The conductive elements 256 may include, for example, solder balls formed on or applied to the under bump metallization (UBM) layer of the substrate 252. A plurality of semiconductor dies 260A-260D (e.g., dies configured as double data rate (DDRx) DRAM, NAND flash memory, or 3D XPoint (e.g., SXP) memory) are stacked on the upper surface of the substrate 252. Each semiconductor die 260A-260D is laminated to a polymer film 262, such as a non-conductive film (NCF), a b-stage polyimide film, a polytetrafluoroethylene (PTFE) film, or other polymer film that extends beyond the lateral periphery of the corresponding die 260A-260D on one or more of its sides (two sides are shown). An RDL 266 in a FOP configuration carrying conductive traces 268 is secured to the active surface 270 of each semiconductor die 260A-260D, and the conductive traces 268 extend laterally outward from a bonding pad location (not shown) on the active surface 270 of each semiconductor die 260A-260D through or over the RDL 266, at least to the location of a via 274 filled with a conductive material 276, the via extending between the semiconductor dies 260A-260D and extending to the conductive pad 254 of the substrate 252. As shown in dashed lines, the semiconductor dies 260A-260D are encapsulated in an EMC 278 that extends, for example, at least around the lateral periphery of the die stack 280 and abuts the upper surface of the substrate 252. As shown, the EMC 278 may extend over the topmost semiconductor die 260D. Alternatively, the EMC 278 may cover the uncovered active surface 270 and the conductive traces 268 with a thin dielectric layer that may include a thermal interface material (TIM) 282 and a heat sink 284, both shown in dashed lines, for enhancing heat transfer from the microelectronic device package 250.

[0056] Figure 3Ais a flowchart of an embodiment of a method 300 for manufacturing a microelectronic device package according to the present disclosure. In operation 302, active circuit systems (e.g., DDRx DRAM with a master / slave architecture) without TSVs are fabricated at die locations on the active surfaces of respective semiconductor substrates (e.g., wafers) configured for a master architecture and a slave architecture. In operation 304, each of the master wafer and the slave wafer is probed to determine the locations of known good dies (KGDs). In operation 306, the master wafer is a post-processed wafer with conductive (e.g., copper) elements in the form of pillars configured for direct chip attachment (DCA). In operation 308, the wafer is thinned, e.g., from an initial thickness of about 600 μm to about 700 μm, e.g., to a thickness of about 5 μm to about 50 μm, and as a specific example, to a thickness approximating about 30 μm. However, it should be noted that embodiments of the method are not limited to any particular die thickness. Then, at operation 310, conventional processes (saw blade, laser, stealth (i.e., laser-induced street-like defects followed by fracture caused by radial expansion of a carrier film), etc.) are used to singulate (i.e., cut) the master wafer and the slave wafer. In operation 312, a reconstructed wafer or panel of the master die KGDs is then formed by placing and adhering the singulated master KGDs through their backs in a spaced-apart relationship on a panel or wafer including a polymer film, such as a non-conductive film (NCF), a b-stage polyimide film, a polytetrafluoroethylene (PTFE) film, or other polymer films. In operation 314, a reconstructed wafer or panel of the slave KGDs is then formed by placing and adhering the singulated slave KGDs through their fronts (i.e., active surfaces) in a spaced-apart relationship at die mounting locations of a panel or wafer configured as a plurality of fan-out package (FOP) redistribution layers (RDLs), each having one or more layers of conductive (e.g., copper) traces carried by a dielectric material and extending beyond at least one side periphery of the associated die mounting location. In operation 316, a film, such as a wafer-level film, e.g., a non-conductive film (NCF), a b-stage polyimide film, a polytetrafluoroethylene (PTFE) film, or other polymer films, is laminated over the back of each of the reconstructed master and slave KGD wafers or panels. In operation 318, the reconstructed master wafer and the slave wafer are singulated into segments between the master KGD locations and between the RDLs of the FOP configuration, each segment carrying an individual master KGD or slave KGD, where the FOP RDL is associated with each slave KGD. In operation 320, the master KGD segments are placed in a spaced-apart relationship on a wafer-level substrate with their conductive pillars inverted in a DCA orientation opposite to conductive pads or traces of the substrate and thermocompression bonded. In operation 322, the slave KGDs are then stacked on the master KGDs in a spaced-apart relationship.In operation 324, openings are formed through conductive traces of the RDL of the FOP configuration of the KGD through a polymer film and through conductive pads or traces extending to the substrate (e.g., by laser ablation or anisotropic etching), and the openings may be referred to as TPVs. In operation 326, the vias are filled with an Ag or Cu paste or other conductive material, for example using an inkjet-type applicator. As another example, the vias may be filled with Sn solder in a wave soldering process. In operation 328, the assembly may be (optionally) encapsulated with an epoxy molding compound (EMC), conductive elements (e.g., solder bumps in a ball grid array (BGA) format) are applied or formed on the substrate opposite the KGD stack, testing is performed, and the KGD stack is singulated through the EMC (if present) and the substrate to form a package. In operation 330, the top of the die stack may be covered with EMC or it may be exposed, for example, for attaching a heat sink with a thermal interface material (TIM).

[0057] Figure 3B is a side cross-sectional schematic view of a microelectronic device package 350 according to an embodiment of the present disclosure, and the microelectronic device package may be according to Figure 3AManufactured by the method. The microelectronic device package 350 includes a substrate 352 having traces (not shown) carried in a dielectric material and extending from conductive pads 354a and 354b on its upper surface to conductive elements 356 on its opposite lower surface. The conductive elements 356 may include, for example, solder balls formed on or applied to the under bump metallization (UBM) layer of the substrate 352. A plurality of semiconductor dies 360A - 360D (e.g., dies configured as dual data rate (DDRx) DRAMs in a master / slave architecture) are stacked on the upper surface of the substrate 352. Each semiconductor die 360A - 360D is laminated on its back surface to a polymer film 362, such as a non-conductive film (NCF), a class b polyimide film, a polytetrafluoroethylene (PTFE) film, extending beyond the lateral periphery of the respective die 360A - 360D on one or more of its sides (two sides are shown). The semiconductor die 360A is inverted in a flip-chip orientation above the substrate 352, and conductive elements in the form of columns P are connected to the conductive pad 354a in a DCA arrangement by thermocompression (i.e., diffusion) bonding. An RDL 366 in a FOP configuration carrying conductive traces 368 is fixed to the active surface 370 of each semiconductor die 260B - 260D, and the conductive traces 368 extend laterally outward from bonding pad locations (not shown) on the active surface 370 of each semiconductor die 360B - 360D through or over the RDL 366, at least to the location of vias 374 filled with conductive material 376, which extend between the semiconductor dies 360A - 360D and to the conductive pad 354b of the substrate 352. As shown, the semiconductor dies 360A - 360D are encapsulated in an EMC 378 that extends, for example, at least around the lateral periphery of the die stack 380 and abuts the upper surface of the substrate 352. As shown, the EMC 378 may extend above the topmost semiconductor die 360D. Alternatively, the EMC 378 may cover the uncovered active surface 370 and the conductive traces 368 with a thin dielectric layer, which may include a thermal interface material (TIM) 382 and a heat sink 384, both shown in dashed lines, for enhancing heat transfer from the microelectronic device package 350.

[0058] While the three embodiments shown and described above provide a TPV on opposite sides of the die stack, embodiments of the present disclosure are not limited thereto. For example, an RDL in a FOP configuration or other dielectric films including conductive traces extending to the TPV ( Figure 1A1 , 1A2 and 1B) may extend beyond the lateral periphery of the die stack DS on the substrate S on one side, two sides, three sides, or four sides of the die stack, respectively, as shown in Figure 4A - 4D as shown.

[0059] Additionally, although the three embodiments shown and described above provide single-row TPVs, embodiments of the present disclosure are not limited thereto. For example, Figure 5A shows a substrate S having a die stack DS, the substrate having an RDL or other dielectric film including conductive traces ( Figure 1A1 , 1A2 and 1B), the RDL or other dielectric film having two rows of aligned TPVs on each of four sides, while Figure 5B shows a substrate S having a die stack DS, the substrate having an RDL or other dielectric film including conductive traces ( Figure 1A1 , 1A2 and 1B), the RDL or other dielectric film having three rows of staggered TPVs on each of four sides. Of course, the number of TPVs on one side of the die stack can be different from the number of TPVs on one or more other sides. In addition to moving signal, power, and ground (e.g., bias) paths to locations external to the semiconductor dies of the die stack DS, if one or more semiconductor dies (different from NAND flash memories) of the die stack DS are susceptible to electromagnetic interference (EMI), an outer ring of ground TPVs (TPVg) can provide a ground stitching function for the die stack DS. Similarly, a ground plane or ground grid, trace array, or other ground structure GS extending over the top of the die stack DS and operatively coupled to the ground TPVg can provide a complete Faraday cage that protects the die stack DS from EMI and serves as an EMI shield, as Figure 5C shown. The ground structure GS can include a conductive (e.g., metal) grid or conductive film. In the former case, the size of the grid and the thickness of the grid material can be adjusted to isolate desired EMI frequencies. Of course, the ground structure GS is electrically isolated from the conductive traces on the top of the die stack DS that are operatively coupled to the semiconductor dies by a dielectric material. In Figure 5C an alternative embodiment of the structure, as shown by the dashed lines, a radio frequency antenna RF can be disposed over the dielectric film D and electrically isolated from the ground structure GS through the dielectric film D, and operatively coupled to one or more semiconductor dies of the die stack DS. The radio frequency antenna RF can be formed in situ in a configuration and thickness tuned to the expected operating wavelength.

[0060] Furthermore, it is contemplated that each layer of conductive traces extending from bond pad locations on various semiconductor dies can be the same and extend to all conductive vias of each layer as shown in Figure 1A1 , 1A2 , 2A, and 3A, or can be customized such that some or all of the conductive trace patterns in a given semiconductor die layer can be the same as or different from the conductive trace patterns of one or more other semiconductor die layers in the stack. For example, asFigure 6A As shown, the conductive traces T of the third layer SD3 and the fourth layer SD4 of the semiconductor dies SD1-SD4 can be operatively coupled to the conductor C of the TPV by physical and electrical contact with the sidewall of the conductor C, while the conductive traces T of the first layer SD1 and the second layer SD2 can be electrically isolated from the TPV by the dielectric material around the conductor C. Thus, in some instances, signals generated by the circuitry of one semiconductor die (e.g., SD4) can be routed through the conductor C of the TPV and received by the circuitry of another die (e.g., SD3) and the circuitry of the substrate S. Similarly, signals can be routed between the circuitry of one semiconductor die (e.g., SD3) and the circuitry of another semiconductor die (e.g., SD1) through the conductor C of one TPV, and between the circuitry of the substrate S through the conductor C of another TPV.

[0061] As Figure 6B shown, in the case of employing multiple rows of TPVs, the conductive traces T can extend from the semiconductor die SD to the conductors C of different rows of TPVs in different layers and be operatively coupled to the conductors C. In Figure 6B the case where, the conductive traces T of the first layer SD1 and the third layer SD3 of the semiconductor dies SD1-SD4 are operatively coupled to the conductors C of the inner row of TPVs, while the second layer SD2 and the fourth layer SD4 are operatively coupled to the conductors C of the outer row of TPVs. As previously described, the rows of TPVs can be aligned, in which case the conductive traces T can extend from the semiconductor die SD and route around the TPVs of the inner row to extend to the TPVs of the outer row, as Figure 6C shown, while in the case where the rows of TPVs are staggered as Figure 6D shown, the conductive traces T can extend directly from the semiconductor die SD between the TPVs of the inner row to reach the TPVs of the outer row and be coupled to their conductors C. In the case of a multiple-row TPV arrangement, through the selective contact and selective electrical isolation of the traces T with a given conductor C, signals can not only be selectively routed between the circuitry of the semiconductor dies SD1-SD4 and between the circuitry of any one of the semiconductor dies SD1-SD4 and the circuitry of the substrate S, but signals can also be routed up or down along a given conductor C of one TPV from the traces T of one semiconductor die to the traces T on another semiconductor die and return through additional traces T of another semiconductor die to the conductors C of different TPVs of different rows, thereby increasing the potential number of available signal paths.

[0062] Figure 7is a block diagram of an illustrative electronic system 700 in accordance with an embodiment of the present disclosure. The electronic system 700 can include, for example, a computer or computer hardware component, a server or other networked hardware component, a cellular phone, a digital camera, a personal digital assistant (PDA), a portable media (e.g., music) player, a Wi-Fi or cellular-enabled tablet computer (e.g., or tablet computer), an e-book, a navigation device, etc. The electronic system 700 includes at least one memory device 702. The memory device 702 can include, for example, an embodiment of a microelectronic device package as previously described herein in accordance with any of the embodiments of Figure 1B 、 2B or 3B. The electronic system 700 can further include at least one electronic signal processor device 704 (commonly referred to as a “microprocessor”). The electronic signal processor device 704 can optionally include an embodiment of a microelectronic device package as previously described herein in accordance with any of the embodiments of Figure 1B 、 2B or 3B. Although the memory device 702 and the electronic signal processor device 704 are depicted as two (2) separate devices in Figure 7 , in additional embodiments, the electronic system 700 includes a single (e.g., only one) memory / processor device having the functionality of the memory device 702 and the electronic signal processor device 704. In such embodiments, the memory / processor device can include an embodiment of a microelectronic device package as previously described herein in accordance with, for example, Figure 3B . The electronic system 700 can further include one or more input devices 706 for a user to input information into the electronic system 700, such as a mouse or other pointing device, a keyboard, a touchpad, a button, or a control panel. The electronic system 700 can further include one or more output devices 708 for outputting information (e.g., visual output or audio output) to the user, such as a monitor, a display, a printer, an audio output jack, a speaker, etc. In some embodiments, the input device 706 and the output device 708 can include a single touchscreen device that can be used both for inputting information into the electronic system 700 and for outputting visual information to the user. The input device 706 and the output device 708 can communicate electrically with one or more of the memory device 702 and the electronic signal processor device 704.

[0063] In the above embodiments, a specific number of semiconductor dies in a given die stack has been mentioned as an example, but the number of semiconductor dies in the stack is not limited thereto. For example, a stack of DRAM memory dies can include thirty-two dies, while a stack of NAND flash memory dies can include up to 128 or even 256 dies.

[0064] In addition, although specific types of semiconductor die were mentioned as examples in the above embodiments, there is no limitation on the one or more types of die that can be stacked in a single die stack. In other words, other types of memory die, such as SRAM, HRAM, MRAM, and FeRAM, etc., can be stacked. Further, in addition to conventional microprocessors, logic die containing memory controller die and processors (e.g., graphics processing unit (GPU), audio processor, and ASICs containing processor cores and memory blocks) can be stacked in combination with die exhibiting other functions, such as logic and memory die. Field programmable gate arrays (FPGAs) are another example of stackable components.

[0065] The customization of each layer of conductive traces obtainable through embodiments of the present disclosure enables the bonding pads at different (e.g., center, multiple rows adjacent to the center line, peripheral on one or more sides) locations of semiconductor die with different patterns and exhibiting different functions to be readily operably coupled to peripherally located TPVs for connection to conductive pads and traces on a substrate for communication with higher levels of the package through conductive paths in the substrate extending to conductive elements. The implementation of an RDL in a FOP configuration carrying multiple layers of conductive traces adds further flexibility to the increasing number of pin connections for state-of-the-art semiconductor die. Additionally, instead of a conventional organic substrate, a silicon substrate including active circuitry can be employed. For example, embodiments of the present disclosure can be used to implement a wide I / O hybrid memory cube architecture using DDR logic in a memory die stack without the need for expensive TSVs while allowing for greater memory density. Similarly, embodiments of the present disclosure can be used to implement a wide I / O high bandwidth memory architecture using device logic in a memory die stack without the need for expensive TSVs while allowing for greater memory density.

[0066] Figure 8Ais a flowchart of an embodiment of a method 800 for manufacturing a microelectronic device package including a stack of multiple microelectronic devices according to the present disclosure. In operation 802, an active circuit system (e.g., DRAM, NAND, 3D Xpoint (e.g., SXP)) without TSVs is fabricated at die locations on the active surface of a semiconductor substrate (e.g., a wafer). In operation 804, the wafer is probed to determine the locations of known good dies (KGDs). In operation 806, the wafer is thinned, e.g., from an initial thickness of about 600 μm to about 700 μm, e.g., to a thickness of about 5 μm to about 200 μm, and as a specific non-limiting example, to a thickness approximating about 100 μm, about 50 μm, or about 30 μm. However, it should be noted that embodiments of the method are not limited to any particular die thickness. Then, at operation 808, the wafer is singulated (i.e., cut) into individual KGDs using conventional processes (saw blade, laser, stealth (i.e., laser-induced street-like defects followed by fracture caused by radial expansion of the carrier film), etc.). In operation 810, the singulated KGDs are then (optionally) formed into a reconstituted wafer or panel of KGDs by placing and adhering them in a spaced-apart relationship to each other through their back sides on an adhesive film (e.g., a die attach film (DAF) or a film-on-die (FOD)-type material). In operation 812, a polymer film is laminated over the front sides (i.e., the active surfaces) of the spaced-apart KGDs of the reconstituted wafer or panel, or over the adhesive film (if present), the polymer film being, for example, a wafer or panel-level film such as a non-conductive film (NCF) including silica-filled epoxy resin, a b-stage polyimide film, a polytetrafluoroethylene (PTFE) film, or other polymer film. In operation 814, openings are formed through the polymer film (e.g., by laser ablation) to expose the bond pad locations on the active surfaces of the KGDs, and subsequently, optionally, a solvent cleaning operation is performed to remove any residues generated by the laser ablation at the bond pad locations, thereby ensuring robust electrical connections between the conductive traces to be formed on the polymer film in operation 816. In operation 816, a conductive material (e.g., Ag or Cu paste) is dispensed to form conductive traces on the polymer film, the conductive traces extending from the bond pads to a predetermined via location outside the lateral periphery of the KGDs, and in some embodiments, extending between adjacent KGDs to be packaged together. Alternatively, the conductive traces can be applied by inkjet technology. In operation 818, the KGDs are singulated laterally using a cutting blade through the polymer film and the optional adhesive film outside the predetermined via location and around groups (e.g., two groups, three groups, four groups, etc.), and multiple groups of KGDs are stacked on a substrate, which can be a wafer-level substrate to be singulated into individual substrates and carry multiple stacks of KGDs in a spaced-apart relationship to each other.In operation 820, vias (which may be referred to as through-poly vias (TPVs)) may be formed, for example, by laser or patterned and anisotropic etching through the films in the KGD stack at the via locations and extending them to conductive pads or traces on adjacent surfaces of the substrate. In operation 822, the vias are filled with a sintered Ag or Cu paste or other conductive material, for example, by using an inkjet-type applicator. As another method, the vias may be filled with Sn solder in a wave soldering process. In operation 824, the assembly may be (optionally) encapsulated with an epoxy molding compound (EMC), conductive elements (e.g., solder bumps in a ball grid array (BGA) format coupled to conductive paths extending to conductive pads or traces on the substrate surface adjacent to the KGD stack) may be applied or formed on the substrate opposite the KGD stack, testing may be performed, and the KGD stacks that are singulated into multiple sets of KGD stacks are operatively coupled to each other through conductive traces that extend between the KGD stacks and through the EMC (if present) and the substrate to form a package. In operation 826, the top of the KGD stack may be covered with EMC or may be left exposed, for example, for attaching a heat sink with an inserted thermal interface material (TIM).

[0067] Figure 8B is a side cross-sectional schematic view of a microelectronic device package 850 according to an embodiment of the present disclosure, and the microelectronic device package may be according to Figure 8AManufactured by the method. The microelectronic device package 850 includes a substrate 852 having traces (not shown) carried in a dielectric material and extending from conductive pads 854 on its upper surface to conductive elements 856 on its opposite lower surface. The substrate 852 may include an organic or inorganic (e.g., silicon) material, with the latter allowing smaller features and closer pitches than the former. The conductive elements 856 may include, for example, solder balls formed on or applied to terminal pads on the bottom surface of the substrate 852. A plurality of semiconductor dies 860A1 - 860D1 and 860A2 - 860D2 (e.g., dies configured as double data rate (DDRx) DRAM, NAND flash memory, or 3D Xpoint (e.g., SXP) memory) to be grouped in the package are stacked on the upper surface of the substrate 852. Each layer of the semiconductor dies 860A1 and 860A2, 860B1 and 860B2, 860C1 and 860C2, and 860D1 and 860D2 is laminated to a polymer film 862, such as a non-conductive film (NCF), a b-stage polyimide film, or a polytetrafluoroethylene (PTFE) film that extends beyond at least one lateral periphery of the corresponding dies 860A1 - 860D1, 860A2 - 860D2 on one or more of their sides (two sides are shown). Each layer of the semiconductor dies 860A1 and 860A2, 860B1 and 860B2, 860C1 and 860C2, and 860D1 and 860D2 may be attached to a DAF 864 on its back surface 866. If an NCF exhibiting sufficient adhesion characteristics is used for lamination purposes, the DAF may be eliminated. Conductive traces 868 in the form of a redistribution layer (RDL) extend laterally outward from bond pad locations (not shown) on the active surfaces 870 of each layer of the semiconductor dies 860A1 and 860A2, 860B1 and 860B2, 860C1 and 860C2, and 860D1 and 860D2 above the upper surface 872 of the polymer film 862 and at least in some cases between adjacent dies in a given layer in different stacks, extending at least to the location of vias 874 filled with a conductive material 876 that extend between the semiconductor dies 860A1 - 860D1 and the semiconductor dies 860A2 and 860D2 and extend to the conductive pads 854 of the substrate 852. As shown by the dashed lines, the semiconductor dies 860A1 - 860D1 and 860A2 - 860D2 may be encapsulated in an EMC 878 that extends, for example, at least around the lateral periphery of the die stacks 880A and 880B, extends between the die stacks, and abuts the upper surface of the substrate 852. As shown, the EMC 878 may extend above the topmost semiconductor dies 860D1 and 860D2.Alternatively, the EMC 878 can cause the active surfaces 870 and conductive traces 868 of the uncovered top semiconductor die of semiconductor dies 860D1 and 860D2 to be covered by a thin dielectric layer, which can include a thermal interface material (TIM) and a heat sink for enhancing heat transfer from the microelectronic device package 850. In one embodiment, there may be only one master die (e.g., semiconductor die 860A1) in the package to control all other slave dies (i.e., 860B1 - 860D1 and 860A2 - 860D2) in the microelectronic device package 850, and this control is achieved through conductive traces extending between die stacks, as Figure 8B depicted and with respect to Figure 8A described. Alternatively, for each respective associated stack of dies 860B1 - 860D1 and 860A2 - 860D2, there may be separate master dies, such as 860A1 and 860A2, and communication between die stacks can be operated through conductive traces 868. Thus, if desired, the master / slave die stacks can be separated across package channels. If the package has height restrictions but a large number of dies are required (e.g., sixteen, thirty-two), then both methods can distribute the dies across a larger coverage area in multiple die stacks, and the first method can allow for multiple and even lower die stacks, with the slave dies in each die stack linked to a single master die in one stack. In another embodiment, a logic die configured as a memory controller can be employed in place of the master die of each semiconductor die stack substrate, or a logic die can be deployed at the bottom of the semiconductor die stack and operatively coupled to the memory dies in multiple stacks.

[0068] Compared to current 3D packaging processes, since through-silicon vias (TSVs) are eliminated and post-wafer fabrication actions for forming complex back-end-of-line (BEOL) structures are not required, Figure 8A and 8B the embodiments of can significantly reduce costs. In the assembly process, DRAM, NAND, or SXP memories can be easily stacked in layers, with each layer including multiple dies. Additionally, this embodiment allows for different conductive trace patterns to be used for each different die layer and allows for separate address pins. Additionally, the power and / or ground of each die can be connected together or be individual. As described above with respect to Figure 5C described, EMI shielding in the form of a Faraday cage or a ground region can be incorporated into the redistribution layer (RDL) only above and between the top dies or for each die layer.

[0069] A conventional die-to-substrate attachment technique for high-power, high-data-rate, high-I / O count devices (e.g., memory controllers, ASICs, etc.) is direct chip attachment (DCA), which allows for optimal signal and power / ground placement between the die and the package substrate, as well as more physical area (conceptually the entire die area) on which to place connections. However, commodity memories are now being pushed into the power / signal space and could benefit from DCA, as described above with respect to Figure 3A and 3B but this is a significant obstacle for the cost of processing and manufacturing. The best solution is to achieve the flexibility of DCA at the expense of wirebonding. Existing options for DCA include chip-scale packaging (CSP) and fan-out packaging (FOP) methods, neither of which can provide the advantages of DCA at low cost. In the embodiments of Figure 9A and 9B , the use of through-silicon vias (TSVs) as described above can be adapted to perform the functions of DCA, but using a die incorporating an iRDL structure formed in a back-end wafer manufacturing process at a lower cost, and including rerouting bond pads to traces suitable for an array pattern for a similar DCA attachment to the substrate.

[0070] Figure 9Ais a flowchart of an embodiment of a method 900 for manufacturing a microelectronic device for direct chip attachment to a substrate according to the present disclosure. In operation 902, an active circuit system (e.g., DRAM, NAND, 3D Xpoint (e.g., SXP)) without TSVs is fabricated at die locations on the active surface of a semiconductor substrate (e.g., a wafer), and iRDLs are formed with traces at each die location to reroute bond pad locations on the active surface of the die into a Cu pad array. In operation 904, the wafer is probed to determine the locations of known good dies (KGDs). In operation 906, the wafer is thinned, e.g., from an initial thickness of about 600 μm to about 700 μm, e.g., to a thickness of about 5 μm to about 200 μm, and as a specific non-limiting example, to a thickness approximating about 100 μm, about 50 μm, or about 30 μm. However, it should be noted that embodiments of the method are not limited to any particular die thickness. Then, at operation 908, the wafer is singulated (i.e., cut) into individual KGDs using a conventional process (saw blade, laser, stealth (i.e., laser-induced street-like defects followed by fracture caused by radial expansion of a carrier film), etc.). In operation 910, then (optionally) a reconstructed wafer or panel of KGDs is formed by placing the singulated KGDs in a spaced-apart relationship through their back sides and adhering them to an adhesive film (e.g., a die attach film (DAF) or a film-on-die (FOD)-type material). In operation 912, a film layer is laminated over the front sides (i.e., the active surfaces) of the spaced-apart KGDs of the reconstructed wafer or panel on the KGDs and the adhesive film (if present), the film being, for example, a wafer or panel-level film such as a non-conductive film (NCF) including silica-filled epoxy, a b-stage polyimide film, a polytetrafluoroethylene (PTFE) film, or other polymer film. In operation 914, vias are formed through the polymer film (e.g., by laser ablation) to expose the iRDL pads on the active surfaces of the KGDs, and subsequently, optionally, a solvent cleaning operation is performed to remove any residues generated by the laser ablation on the iRDL pads. In operation 916, a conductive material (e.g., Ag or Cu paste) is dispensed to fill the vias, or another conductive material is filled using inkjet technology. As another method, the vias can be filled with Sn solder in a wave soldering process. In operation 918, the KGDs are singulated laterally using a cutting blade through the polymer film outside the die coverage area and at the predetermined via locations of the TPVs as shown by the dashed lines for connection to other higher dies in a stack to be formed, as described above with respect to Figure 3A and 3BAs described. In operation 920, each singulated KGD can be picked up, inverted, and placed on a substrate, where the vias filled with conductive material in the polymer film are aligned with terminal pads on the upper surface of the substrate. Subsequently, the assembly is heated to attach the die to the substrate by curing the polymer film and bonding the conductive material in the vias to the terminal pads.

[0071] As depicted regarding Figure 9A the process sequence described Figure 9B shown, a semiconductor die 950 carrying iRDL 952 on its active surface 954 has bonding pads (not shown) rerouted to iRDL pads 956 (e.g., Cu), and this structure has a polymer film laminated thereon, such as an NCF, b-stage polyimide film, or PTFE film 958. Then, vias 960 are formed in the polymer film 958 by laser ablation to expose the iRDL pads 956. Ag, Cu, solder, or other conductive fill materials are introduced to fill the vias 960 and form conductive contacts 962. Then, the semiconductor die 950 is inverted and placed on a substrate 964, which can be an organic or inorganic (e.g., silicon) substrate, where the conductive contacts 962 of the semiconductor die 950 are aligned with the terminal pads 966 of the substrate 964. Then, the assembly is heated to attach the semiconductor die 950 to the substrate 964 and the terminal pads 966 through the polymer film 958 and the conductive contacts 962, respectively. For example, a thermocompression bonding tool can be used for die placement accuracy and heated to obtain the adhesion of the polymer film. In the case of NCF, the heating temperature will be higher than the glass transition temperature (T g ). As shown, the terminal pads 966 are connected to conductive elements 968 (e.g., solder balls) on the opposite side of the substrate 964 through traces and vias including conductive paths 970. Although a single die package is shown, if desired, a stacked die assembly can be complete and optionally encapsulated, as described herein regarding Figure 3A and 3B depicted and described, where the bottom main die as described is connected to the substrate. Of course, the processes and resulting dies described can be employed with dies exhibiting any functionality and are not limited to memories.

[0072] As Figure 9A and 9B potential additional embodiments, and as Figure 9CAs depicted, a die stack DS can be fabricated using multiple semiconductor dies 950' beneath the topmost semiconductor die 950. The multiple semiconductor dies are equipped with TSVs 972 and then provided with a dielectric (e.g., polymer) film 958 having vias 960 that are aligned with the TSVs 972 and filled with a conductive fill material to form conductive contacts 962. The semiconductor dies 950 and 950' can then be stacked on a base wafer or other substrate 974 in a laterally spaced relationship, and physical and electrical connections can be made by heating to cure the polymer film in the bond lines between the dies and between the bottommost die and the substrate. After that, the assembly can be encapsulated with EMC 976, and solder bumps 978 can be applied to the base wafer or substrate as shown by the dashed lines. Thereafter, the complete package can be singulated as is known in the art. Using this method, the conventional use of Cu pillars (capped with solder in some cases) and thermocompression bonding of die stacks can be avoided.

[0073] Now referring to Figure 10A - 10D , in an additional embodiment, the architecture of the previously described die assembly can be further adapted to provide additional advantages in terms of packaging and performance by incorporating surface mount components at each layer of the semiconductor dies in the die stack outside the coverage area of the stacked dies. Figure 10AFIG. 0 is a flowchart of an embodiment of a method 1000 for fabricating a microelectronic device assembly incorporating surface-mounted components in accordance with the present disclosure. In operation 1002, an active circuitry (e.g., DRAM, NAND, 3DXPoint (e.g., SXP)) without TSVs is fabricated at die locations on the active surface of a semiconductor substrate (e.g., a wafer). In operation 1004, the wafer is probed to determine the locations of known good dies (KGDs). In operation 1006, the wafer is thinned, e.g., from an initial thickness of about 600 μm to about 700 μm, e.g., to a thickness of about 5 μm to about 200 μm, and as a specific non-limiting example, to a thickness approximating about 100 μm, about 50 μm, or about 30 μm. However, it should be noted that embodiments of the method are not limited to any particular die thickness. The wafer is then singulated (i.e., cut) into individual KGDs at operation 1008 using conventional processes (saw blade, laser, stealth (i.e., laser-induced street-like defects followed by fracture caused by radial expansion of a carrier film), etc.). In operation 1010, the singulated KGDs are then (optionally) formed into a reconstructed wafer or panel of KGDs by placing and adhering the singulated KGDs in a spaced-apart relationship through their active surfaces onto an RDL panel or wafer in a fan-out package (FOP) configuration, the panel or wafer having traces extending from bond pads of the die to regions beyond the die coverage area. In operation 1012, surface-mounted components (e.g., capacitors, resistors, inductors) may be placed or already pre-formed on the RDL panel or wafer in the FOP configuration, the panel or wafer being adjacent to but outside the coverage area of the semiconductor die at a location where no vias will be formed. In operation 1014, a polymer film is laminated over the back sides of the spaced-apart KGDs of the reconstructed wafer or panel, the polymer film being, e.g., a wafer or panel-level film such as a non-conductive film (NCF) including silica-filled epoxy, a b-stage polyimide film, a polytetrafluoroethylene (PTFE) film, or other polymer film. In operation 1016, the polymer film carrying the KGDs and the RDL in the FOP configuration is singulated with a dicing blade, and each individual KGD with the RDL is inverted and stacked on a base wafer or other substrate. In operation 1018, vias (which may be referred to as through-polycrystalline vias (TPVs)) may be formed, e.g., by laser or patterned and anisotropic etching, through the RDL and the polymer film in the KGD stack at via locations and extending to conductive pads or traces on an adjacent surface of the substrate. In operation 1020, a sintered Ag or Cu paste is dispensed, or other conductive materials are employed, to fill the vias, e.g., using an inkjet-type dispenser, and form through-polycrystalline vias (TPVs). As an alternative method, the vias may be filled with Sn solder in a wave soldering process.In operation 1022, surface mount components (e.g., capacitors, resistors, inductors) can be placed or have been pre-formed and operatively coupled to the RDL of the top die of each KGD stack, and to other dies as needed via the conductive material of one or more TPVs. In operation 1024, the KGD stack and substrate assembly can optionally be encapsulated with an epoxy molding compound (EMC), conductive elements (e.g., solder bumps in a ball grid array (BGA) format coupled to conductive paths that are coupled to conductive pads or traces extending onto the substrate surface adjacent to the KGD stack) are applied or formed on the substrate opposite the KGD stack, testing is performed, and the KGD stack is singulated through the EMC (if present) and the substrate to form a package. In operation 1026, the top of the die stack can be covered with EMC or can be left exposed, e.g., for attaching a heat sink with a thermal interface material (TIM) if the surface mount components are mounted inside the die stack rather than on top of the top die).

[0074] As Figure 10B1 - 10D depicted, the manufacturing processes described with respect to Figure 10A can be implemented to form different die assemblies. For example, Figure 10B1 is a side cross-sectional schematic elevation view of a microelectronic device package 1050B according to an embodiment of the present disclosure and Figure 10B2 is a top schematic elevation view thereof, and the microelectronic device package can be manufactured according to the method of Figure 10A . Although shown as a memory device package including a memory die stack, the structure is not limited thereto. The microelectronic device package 1050B includes a substrate 1052 having traces (not shown) carried in a dielectric material and extending from conductive pads 1054 on its upper surface to conductive elements 1056 on its opposite lower surface. The conductive elements 1056 can include, for example, solder balls formed on or applied to the terminal pads of the substrate 1052. A plurality of semiconductor dies 1060A - 1060D (e.g., dies configured as double data rate (DDRx) DRAM, NAND flash memory, or 3D XPoint (e.g., SXP) memory) are stacked on the upper surface of the substrate 1052. Each semiconductor die 1060A - 1060D is laminated to a polymer film 1062 on its back surface, e.g., on one or more sides ( Figure 10B1 Two sides are shown, Figure 10B2shows a non-conductive film (NCF), a class b polyimide film, a polytetrafluoroethylene (PTFE) film, or other polymer film that extends beyond the lateral periphery of the corresponding die 1060A - 1060D on four sides). The FOP-configured RDL 1066 carrying the conductive traces 1068 is fixed to the active surface 1070 of each semiconductor die 1060A - 1060D. The conductive traces 1068 extend laterally outward from the bonding pad locations (not shown) on the active surface 1070 of each semiconductor die 1060A - 1060D through or over the RDL 1066, at least to the location of the vias 1074 filled with a conductive material 1076 (i.e., TPV). The vias extend between the semiconductor dies 1060A - 1060D and to the conductive pads 1054 of the substrate 1052. In this embodiment, one or more surface-mounted components (e.g., capacitors, resistors, inductors) SM (one shown), such as decoupling capacitors, are mounted to the topmost RDL 1066 and operatively coupled to the topmost RDL, and optionally coupled to one or more TPVs. As Figure 10B2 depicted, the surface-mounted component SM can be mounted above one or more TPV locations and connected to the conductive traces 1068 of the topmost RDL. As shown by the dashed lines, the semiconductor dies 1060A - 1060D can then be encapsulated in, for example, an EMC 1078 that extends at least around the lateral periphery of the die stack 1080 and abuts the upper surface of the substrate 1052. As shown, the EMC 1078 can extend above the topmost semiconductor die 1060D.

[0075] Figure 10C1 is a side cross-sectional schematic elevation view of a microelectronic device package 1050C according to an embodiment of the present disclosure and Figure 10C2 is a top schematic elevation view thereof, and the microelectronic device package can be manufactured according to the method of Figure 10A . Although shown as a memory device package including a memory die stack, the structure is not limited thereto. The microelectronic device package 1050C includes a substrate 1052 having traces (not shown) that are carried in a dielectric material and extend from conductive pads 1054 on its upper surface to conductive elements 1056 on its opposite lower surface. The conductive elements 1056 can include, for example, solder balls formed on or applied to the under bump metallization (UBM) layer of the substrate 1052. A plurality of semiconductor dies 1060A - 1060D (e.g., dies configured as double data rate (DDRx) DRAM, NAND flash memory, or 3D XPoint (e.g., SXP) memory) are stacked on the upper surface of the substrate 1052. Each semiconductor die 1060A - 1060D is laminated to a polymer film 1062 on its back surface, e.g., on one or more of its sides (Figure 10C1 shows two sides, Figure 10C2 a non-conductive film (NCF), a class-b polyimide film, a polytetrafluoroethylene (PTFE) film, or other polymer film extending beyond the lateral periphery of the corresponding die 1060A-1060D on four sides (shows four sides). The FOP-configured RDL 1066 carrying the conductive traces 1068 is fixed to the active surface 1070 of each semiconductor die 1060A-1060D, and the conductive traces 1068 extend laterally outward from the bonding pad positions (not shown) on the active surface 1070 of each semiconductor die 1060A-1060D through or over the RDL 1066, at least extending to the position of the vias 1074 filled with conductive material 1076 (i.e., TPV), the vias extending between the semiconductor dies 1060A-1060D and extending to the conductive pads 1054 of the substrate 1052. In this embodiment, one or more surface-mounted components (e.g., capacitors, resistors, inductors) SM (two shown), such as decoupling capacitors, are each mounted to the RDL 1066 outside the assembly and operatively coupled to its traces 1068, and optionally coupled to one or more TPVs through the RDL traces 1068 extending from the surface-mounted component SM positions to the TPV positions. As Figure 10C2 depicted, the internally positioned surface-mounted components SM can be spaced from the TPV positions. As shown by the dashed lines, the semiconductor dies 1060A-1060D can then be encapsulated in, for example, an EMC 1078 that extends at least around the lateral periphery of the die stack 1080 and abuts the upper surface of the substrate 1052. As shown, the EMC 1078 can extend above the uppermost semiconductor die 260D. Alternatively, the EMC 1078 can cover the uppermost uncovered RDL 1066 with a thin dielectric layer that can include a thermal interface material (TIM) and a heat sink for enhancing heat transfer from the microelectronic device package 1050C.

[0076] Figure 10D is a side cross-sectional schematic elevation view of a microelectronic device package 1050D according to an embodiment of the present disclosure, and the microelectronic device package can be according to Figure 10AManufactured by the method. Although shown as a memory device package including a stack of a memory die and a controller die, it can be configured, for example, as a managed NAND (mNAND) package, but the structure is not limited thereto. The microelectronic device package 1050D includes a substrate 1052 having traces (not shown) carried in a dielectric material and extending from conductive pads 1054 on its upper surface to conductive elements 1056 on its opposite lower surface. The conductive elements 1056 can include, for example, solder balls formed on or applied to the under bump metallization (UBM) layer of the substrate 1052. A plurality of semiconductor dies 1060A - 1060E (e.g., dies configured as NAND flash memories or 3DXPoint (e.g., SXP) memories (dies 1060A and 1060D), low power DRAM (LPDRAM) dies 1060C and 1060D, and a controller die (die 1060E)) are stacked on the upper surface of the substrate 1052. However, other numbers and combinations of dies exhibiting different functions incorporating surface - mounted components can be manufactured. Additionally, if a controller die, ASIC, or other relatively high - power - density device is deployed on top of the die stack, a thermal conductive material (such as a copper plate or other heat sink structure (not shown)) can be placed between the top die and the relatively lower - power - density memory dies below. This method applies to all embodiments of the present disclosure. Each semiconductor die 1060A - 1060E is laminated to a polymer film 1062 on its back surface, for example, on one or more sides ( Figure 10Dshows a non-conductive film (NCF), a class b polyimide film, a polytetrafluoroethylene (PTFE) film, or other polymer film that extends beyond the lateral periphery of the corresponding die 1060A - 1060D on two sides. The FOP-configured RDL 1066 carrying the conductive traces 1068 is fixed to the active surface 1070 of each semiconductor die 1060A - 1060E, and the conductive traces 1068 extend laterally outward from the bond pad locations (not shown) on the active surface 1070 of each semiconductor die 1060A - 1060E through or over the RDL 1066, at least to the location of the vias 1074 filled with a conductive material 1076 (i.e., TPV), which vias extend between the semiconductor dies 1060A - 1060E and to the conductive pads 1054 of the substrate 1052. In this embodiment, one or more surface-mounted components (e.g., capacitors, resistors, inductors) SM (two are shown), such as decoupling capacitors, are each mounted to the topmost RDL 1066 (more than one, less than one) and are operatively coupled to its traces 1068. Two other surface-mounted components SM are mounted to the RDL 1066 outside the assembly and are operatively coupled to its traces 1068, and are optionally coupled to one or more TPVs through the RDL traces 1068 extending from the surface-mounted component SM locations to the TPV locations. As Figure 10B2 and 10C2 depicted, the internally located surface-mounted components SM can be spaced from the TPV locations, while the top-mounted surface-mounted components can be mounted anywhere above the topmost RDL. As shown by the dashed lines, the semiconductor dies 1060A - 1060E can then be encapsulated in, for example, an EMC 1078 that extends at least around the lateral periphery of the die stack 1080 and abuts the upper surface of the substrate 1052. As shown, the EMC 1078 can extend above the topmost semiconductor die 1060E.

[0077] Figure 10A - 10DEmbodiments use additional surface area of the RDL in a FOP configuration outside the cover region of each die to incorporate surface mount components (e.g., capacitors, resistors, inductors) near each die of a stacked die package. If within a die stack on an internal RDL, the surface mount components do not increase the package height, and additional vertical spacing between die bond wires provided by the die thickness can allow the use of larger (i.e., thicker) surface mount components. Additionally, the placement of the surface mount components can be optimized relative to each die, and it is particularly beneficial to place decoupling capacitors for stable power delivery close to the die due to the reduction in loop inductance and resistance. In contrast, it is not possible to place substrate-mounted decoupling capacitors near die bond pads due to manufacturing design rule check (DRC) regulations. Additionally, removing surface mount components from the substrate of the package provides more signal routing space on the substrate.

[0078] Now referring to yet another embodiment, Figure 11A and 11B depict, respectively, a process sequence for fabricating a microelectronic device package employing an inductive coupling loop for data signal transmission and a TPV for power and ground / bias signal transmission in accordance with an embodiment of the present disclosure, and a side view cross-sectional schematic elevation of the microelectronic device package.

[0079] Figure 11AFIG. 1100 is a flowchart of an embodiment of a method 1100 for fabricating a microelectronic device assembly incorporating an inductive coupling link (ICL) for data signal transmission and a TPV for power and ground / bias signal transmission in accordance with an embodiment of the present disclosure. In operation 1102, an active circuit system (e.g., DRAM, NAND, 3D XPoint (e.g., SXP)) without TSVs is fabricated at die locations on the active surface of a semiconductor substrate (e.g., a wafer). In one implementation, the inductive coupling link (ICL) transmitter and ICL receiver may be fabricated in the metallization of the die during back-end-of-line (BEOL) processing as part of the BEOL structure. In operation 1104, the wafer is probed to determine the locations of known good dies (KGDs). In operation 1106, the wafer is thinned, e.g., from an initial thickness of about 600 μm to about 700 μm, e.g., to a thickness of about 5 μm to about 200 μm, and as a specific non-limiting example, to a thickness approximating about 100 μm, about 50 μm, or about 30 μm. However, it should be noted that embodiments of the method are not limited to any particular die thickness that does not jeopardize inductive coupled data signal transmission or cause crosstalk. Then, at operation 1108, the wafer is singulated (i.e., diced) into individual KGDs using conventional processes (saw blade, laser, stealth (i.e., laser-induced street-like defects followed by fracture caused by radial expansion of a carrier film), etc.). In operation 1110, the singulated KGDs are then adhered and operatively coupled in a fan-out package (FOP) configuration on an RDL panel or wafer through their active surfaces in a spaced-apart relationship, the panel or wafer having traces extending from bond pads of the die to regions outside the die coverage area. If the ICL transmitter and ICL receiver are not fabricated on the die, the RDL wafer or panel in the FOP configuration may incorporate the ICL transmitter and ICL receiver therein. In operation 1112, a polymer film is laminated over the back sides of the spaced-apart KGDs of the reconstructed wafer or panel, the polymer film being, e.g., a wafer- or panel-level film such as a non-conductive film (NCF) including silica-filled epoxy, a b-stage polyimide film, a polytetrafluoroethylene (PTFE) film, or other polymer film. In operation 1114, the polymer film carrying the die having the ICL transmitter and ICL receiver and the RDL in the FOP configuration is singulated, and the individual dies each having the RDL and the ICL transmitter and ICL receiver are inverted and stacked on a base wafer or other substrate to a desired stack height (e.g., four, eight, twelve, sixteen dies). In operation 1116, vias (which may be referred to as through-polysilicon vias (TPVs)) may be formed, e.g., by laser or patterned and anisotropic etching, through the RDL and the polymer film in the KGD stack at via locations and extended to conductive pads or traces on an adjacent surface of the substrate.In operation 1118, sintered Ag or Cu paste is dispensed, or other conductive materials are employed, to fill the vias, for example, by using an inkjet-type applicator, and to form through-polycrystalline vias (TPVs). As an alternative method, the vias can be filled with Sn solder in a wave soldering process. In operation 1120, the assembly can be (optionally) encapsulated with an epoxy molding compound (EMC), conductive elements (e.g., solder bumps in a ball grid array (BGA) format that are coupled to conductive paths that extend to conductive pads or traces on the substrate surface adjacent to the KGD stack) are applied or formed on the substrate opposite the KGD stack, testing is performed, and the KGD stack is singulated through the EMC (if present) and the substrate to form a package. In operation 1122, the top of the die stack can be covered with EMC, or it can be exposed to attach a heat sink with a thermal interface material (TIM).

[0080] Figure 11B is a side cross-sectional schematic elevation view of a microelectronic device package 1150 according to an embodiment of the present disclosure, and the microelectronic device package can be manufactured according to Figure 11A the method. Although shown as a memory device package including a memory die stack, the structure is not limited thereto. The microelectronic device package 1150 includes a substrate 1152 having traces (not shown) that are carried in a dielectric material and extend from conductive pads 1154 on its upper surface to conductive elements 1156 on its opposite lower surface. The conductive elements 1156 can include, for example, solder balls formed on or applied to the terminal pads of the substrate 1152. A plurality of semiconductor dies 1160A - 1160D (e.g., dies configured as double data rate (DDRx) DRAM, NAND flash memory, or 3D XPoint (e.g., SXP) memory) are stacked on the upper surface of the substrate 1152. Each semiconductor die 1160A - 1160D is laminated to a polymer film 1162 on its back surface, for example, on one or more of its sides (by way of non-limiting example, Figure 10B1 and 10B2Shows a non-conductive film (NCF), a class b polyimide film, a polytetrafluoroethylene (PTFE) film, or other polymer film extending beyond the lateral periphery of the corresponding die 1160A - 1160D on two sides. The RDL 1166 of the FOP configuration carrying the conductive traces 1168 is fixed to the active surface 1170 of each semiconductor die 1160A - 1160D, and the conductive traces 1168 (i.e., power and ground / bias traces) extend laterally outward from the power and ground / bias bond pad locations (not shown) on the active surface 1170 of each semiconductor die 1160A - 1160D through or over the RDL 1166, at least extending to the location of the vias 1174 filled with a conductive material 1176 (i.e., TPV), which vias extend between the semiconductor dies 1160A - 1160D and extend to the conductive pads 1154 of the substrate 1152. For all semiconductor dies 1160A - 1160D, the power and ground / bias signals can be combined, or for at least some or all semiconductor dies 1160A - 1160D, they can be individual. The ICL transmitters 1172T and ICL receivers 1172R of the RDL 1166 or incorporated into the die metallization are operatively coupled through the data signal conductive traces 1168 to the data signal pin leads on the active surface 1170 of each semiconductor die 1160A - 1160D. The ICL transmitters 1172T and ICL receivers 1172R can be mounted anywhere within the coverage area of each semiconductor die 1160A - 1160D, where the ICL transmitter 1172T of one die is vertically aligned in cooperation with the ICL receivers 1172R of one or more vertically adjacent dies, as shown. Similarly, ICL transmitters 1172T and ICL receivers 1172R can be provided on the upper surface of the substrate 1152, again vertically aligned in cooperation with the ICL receivers 1172R and ICL transmitters 1172T of the lowermost semiconductor die 1160A. Notably, the semiconductor dies 1160A - 1160D are sufficiently thinned (e.g., thinned to about 50 μm or less) such that ICL signals can be transmitted and received between the ICL transmitters and ICL receivers on the active surfaces of vertically adjacent dies, eliminating any need to place ICL transmitters and ICL receivers on both sides of each die. The substrate 1152 can further include a conversion integrated circuit system 1190 operatively coupled to the ICL transmitters 1172T and ICL receivers 1172R of the substrate 1152, which conversion integrated circuit system is for converting inductive data signals (i.e., inductive current) into electrical signals for communication with higher-level packages.Alternatively, another bottom die (not shown) (e.g., a controller die) equipped with an ICL transmitter 1172T and an ICL receiver 1172R on its upper surface for communicating with semiconductor dies 1160A - 1160D can be incorporated into such a conversion circuit system and connected via DCA or as described above. Figure 9A and 9B The connections depicted and described as DCA connections are operably coupled to substrate 1152. As shown by the dashed lines, semiconductor dies 1160A - 1160D can then be encapsulated in, for example, an EMC 1178 that extends at least laterally around the periphery of die stack DS and abuts the upper surface of substrate 1152. As shown, EMC 1178 can extend over the topmost semiconductor die 1060D or can only cover the sides of die stack DS.

[0081] Inductive - coupled loop signal transmission implemented using embodiments of the present disclosure as described above presents a low - power solution for transmitting data signals from one location to another without the need for continuous physical connections, thus eliminating the need for expensive TSVs or other physical interconnect devices (such as bond wires) that pose problems of package height and chip pitch to avoid short - circuits. Since ICL cannot provide power or ground / bias, using ICL communication in combination with through - polysilicon vias (TPV) enables easy vertical alignment of ICL transmitters and ICL receivers within the coverage area of the die stack while routing physical power and ground / bias outside the coverage area to the support substrate through TPVs. Thus, for ICL communication, not only are TSVs eliminated, but also potential tiled or stepped die stacks, which would require complex design practices and limit the die - face - to - face area.

[0082] Reference Figure 12 Another embodiment of the present disclosure is shown and described. In this embodiment, both TSVs and TPVs are employed in the microelectronic device. Figure 12FIG. 0 is a side cross-sectional schematic elevation view of a microelectronic device assembly 1200 in accordance with an embodiment of the present disclosure. Although shown as a memory device package including a memory die stack, the structure is not limited thereto. The microelectronic device assembly includes a substrate 1202 having traces (not shown) carried in a dielectric material and extending from conductive pads 1204 on its upper surface to conductive elements 1206 on its opposite lower surface. The conductive elements 1206 may include, for example, solder balls formed on or applied to the terminal pads of the substrate 1202. A plurality of semiconductor dies 1208A-1208D (e.g., dies configured as double data rate (DDRx) DRAM, NAND flash memory, or 3D XPoint (e.g., SXP) memory) are stacked on the upper surface of the substrate 1202. Each semiconductor die 1208A-1208D is surrounded by EMC 1210 at its lateral periphery. An FOP-configured RDL 1212 carrying conductive traces 1214 is secured to the active surface 1216 of each semiconductor die 1208A-1208D, and the conductive traces 1214 (i.e., power and ground / bias traces) extend laterally outward from power and ground / bias bonding pad locations (not shown) on the active surface 1216 of each semiconductor die 1208A-1208D through or over the RDL 1212, at least to the location of vias 1218 filled with conductive material 1220 (i.e., TPV), which vias extend between the semiconductor dies 1208A-1208D and to the conductive pads 1204 of the substrate 1202 for power and ground / bias signal communication. Of course, an FOP-configured RDL is not required as a dielectric film carrying conductive traces may be employed. As needed, the power and ground / bias connections may be combined for all of the semiconductor dies 1208A-1208D, or may be individual for each or at least some of the semiconductor dies 1208A-1208D. All of the semiconductor dies 1208A-1208C (but not the topmost semiconductor die 1208D) have been fabricated with TSVs 1222 as shown in dashed lines, which TSVs extend through their respective thicknesses from alignment bonding pads (not shown) of the integrated circuit system on the active surface 1216 to conductive pads (not shown) on their backs 1224. The topmost semiconductor die 1208D has bonding pads on its active surface that are aligned with the TSVs of the next lower semiconductor device 1208C. Conductive elements such as pillars 1226 (e.g., solder-capped copper pillars) extend between the bonding pads and the terminal pads through the polymer film 1211 and the RDL 1212, interconnecting the semiconductor dies 1208A-1208D via the TSVs 1222 for data signal communication with conductive pads (not shown) of the substrate 1202 within the covered area of the die stack.A conductive material that fills the vias in the polymer film in the bonding line can be used instead of the columnar conductive elements, as described above with respect to. Figure 9A and 9B As described. As shown by the dashed lines, the semiconductor dies 1208A - 1208D can then be encapsulated in another EMC 1228 that extends, for example, at least laterally around the periphery of the die stack 1230 and abuts the upper surface of the substrate 1202. As shown, the EMC 1228 can extend over the topmost semiconductor die 1060D, or can only cover the sides of the die stack 1230, leaving the topmost semiconductor die 1208D exposed for applications such as (for example) TIM and heat sink structures.

[0083] Now referring to the Figure 13A - 14B drawings, further embodiments of the present disclosure employing an RDL with an FOP configuration in combination with a TPV are shown and described. Figure 13AFIG. 1300 is a flowchart of an embodiment of a method 1300 for manufacturing a microelectronic device package using an RDL in a FOP configuration. In operation 1302, an active circuit system (e.g., DRAM, NAND, 3D XPoint (e.g., SXP)) without TSVs is fabricated at die locations on the active surface of a semiconductor substrate (e.g., a wafer). In operation 1304, the wafer is probed to determine the locations of known good dies (KGDs). In operation 1306, the wafer is thinned, e.g., from an initial thickness of about 600 μm to about 700 μm, e.g., to a thickness of about 5 μm to about 50 μm, and as a specific example, to a thickness approximating about 30 μm. However, it should be noted that embodiments of the method are not limited to any particular die thickness. Then, in operation 1308, the wafer is singulated (i.e., cut) using a conventional process (saw blade, laser, stealth (i.e., laser-induced street-like defects followed by fracture caused by the radial expansion of a carrier film), etc.). In operation 1310, a reconstructed wafer or panel of KGDs is then formed by placing the singulated KGDs in a spaced-apart relationship through their front sides (i.e., the active surfaces) and adhering them to die mounting locations on a panel or wafer configured as a plurality of fan-out package (FOP) redistribution layers (RDLs), each layer having one or more conductive (e.g., copper) traces optionally coupled to bonding pads corresponding to the respective KGDs and carried by a dielectric material, the conductive traces extending to via locations beyond at least one lateral periphery of the associated die coverage area. In operation 1312, the reconstructed panel or wafer of KGDs is then encapsulated in an EMC, adhered to a die attach film (DAF) on the side opposite the RDL, and each KGD, the associated FOP-configured RDL, and the DAF are singulated to form a FOP-configured RDL package. A plurality of packages are then stacked. In operation 1314, openings are formed at via locations (e.g., by laser ablation or anisotropic etching) through the DAF, the EMC, and through the conductive traces of the FOP-configured RDL. In operation 1316, Ag or Cu paste or other conductive material is dispensed, e.g., using an inkjet-type applicator, to fill the vias to form TPVs. As another example, the vias can be filled with Sn solder in a wave soldering process. In operation 1318, the stack of FOP packages is placed on a substrate, where the TPVs are in conductive contact with terminal pads on the upper surface of the substrate. If desired, the stack of FOP packages can be placed on the substrate before forming the TPVs. In operation 1320, the assembly can be (optionally) encapsulated with another epoxy molding compound (EMC), conductive elements (e.g., solder bumps in a ball grid array (BGA) format) are applied or formed on the substrate opposite the KGD stack, testing is performed, and the KGD stack is singulated through the other EMC (if present) and the substrate to form packages.In operation 1322, the top of the die stack may be covered with additional EMC (if present), or it may be left exposed, e.g., for attaching a heat sink with a thermal interface material (TIM).

[0084] Figure 13B is a side cross-sectional schematic view of a microelectronic device package 1350 in accordance with an embodiment of the present disclosure, and the microelectronic device package may be fabricated in accordance with Figure 13A the method of. The microelectronic device package 1350 includes a substrate 1352 having traces (not shown) carried in a dielectric material and extending from conductive pads 1354 on its upper surface to conductive elements 1356 on its opposing lower surface. The conductive elements 1356 may include, for example, solder balls formed on or applied to terminal pads on the bottom surface of the substrate 1352. A plurality of semiconductor dies 1360A - 1360D (e.g., dies configured as double data rate (DDRx) DRAM, NAND flash memory, or 3D Xpoint (e.g., SXP) memory, all of which do not have TSVs) are stacked on the upper surface of the substrate 1352. Each semiconductor die 1360A - 1360D is laminated to an FOP-configured RDL 1364 on its active surface 1362, and the FOP-configured RDL extends beyond at least one lateral periphery of the respective die 1360A - 1360D on one or more of its sides (two sides are shown). Each semiconductor die 1360A - 1360D is attached to a DAF segment 1366 on its backside 1368. Conductive traces 1370 of the RDL 1364 extend laterally outward from bonding pad locations (not shown) on the active surface 1362 of each semiconductor die 1360A - 1360D above the upper surface 1372 of the EMC 1374 surrounding each semiconductor die 1360A - 1360D, extending at least to the location of vias 1376 filled with conductive material 1378, which vias extend between the semiconductor dies 1360A - 1360D and to the conductive pads 1354 of the substrate 1352. As shown in dashed lines, the semiconductor dies 1360A - 1360D may be encapsulated in another EMC 1380, e.g., that extends at least around the lateral periphery of the die stack and abuts the upper surface of the substrate 1352. As shown, the EMC 1380 may extend above the uppermost semiconductor die 1360D. Alternatively, additional EMC 1380 may cause the active surface 1362 and conductive traces 1370 of the uppermost uncovered semiconductor die 1360D to be covered with a thin dielectric layer, which may include a thermal interface material (TIM) and a heat sink for enhancing heat transfer from the microelectronic device package 1350.

[0085] Figure 14AFIG. 1400 is a flowchart of an embodiment of a method 1400 for manufacturing a microelectronic device package for an RDL employing a FOP configuration in combination with a TPV. In 1402, an active circuit system (e.g., DRAM, NAND, 3D XPoint (e.g., SXP)) without TSVs is fabricated at die locations on an active surface of a semiconductor substrate (e.g., a wafer). In act 1404, the wafer is probed to determine the locations of known good dies (KGDs). In act 1406, the wafer is thinned, e.g., from an initial thickness of about 600 μm to about 700 μm, e.g., to a thickness of about 5 μm to about 50 μm, and as a specific example, to a thickness approximating about 30 μm. However, it should be noted that embodiments of the method are not limited to any particular die thickness. The wafer is then singulated (i.e., cut) at act 1408 using conventional processes (saw blade, laser, stealth (i.e., laser-induced street-like defects followed by fracture caused by radial expansion of a carrier film), etc.). In act 1410, a reconstructed wafer or panel of KGDs is then formed by adhesively and operatively coupling the singulated KGDs in spaced-apart relation to die mounting locations on a panel or wafer through their front sides (i.e., active surfaces), the panel or wafer being configured as a plurality of fan-out package (FOP) redistribution layers (RDLs), each layer having one or more layers of conductive (e.g., copper) traces optionally coupled to corresponding bonding pads of the respective KGDs and carried by a dielectric material, the conductive traces extending to via locations beyond at least one lateral periphery of an associated die coverage area. In act 1412, the reconstructed panel or wafer of KGDs is then encapsulated in an EMC. In act 1414, a polymer film is then laminated over the RDLs of the active surfaces of the spaced-apart KGDs of the reconstructed wafer or panel, as well as over each KGD, the surrounding EMC, and the RDLs of the associated FOP configuration, the polymer film being, e.g., a wafer or panel-level film, such as a non-conductive film (NCF) including silica-filled epoxy, a b-stage polyimide film, a polytetrafluoroethylene (PTFE) film, or other polymer film, and the polymer film is singulated to form a package. In act 1416, which may be implemented prior to applying the polymer film and singulating, the KGDs to be placed at the bottom of the die stack are bumped with conductive elements in the form of copper pillars or solder bumps, or may be bumped with conductive material (e.g., Ag or Cu paste) disposed in vias in the polymer film. In act 1418, the bottom (i.e., bumped) KGDs of the stack are inverted and placed face-down on a substrate in a flip-chip orientation, with the active surfaces down, connecting through the polymer film to terminal pads on the substrate. In act 1420, the remaining KGDs of the stack are then inverted and placed face-down on top of the bottom-most KGDs. In act 1422, openings are formed at via locations (e.g., by laser ablation or anisotropic etching) through the EMC, through the conductive traces of the FOP configuration RDL, and through the polymer film.In operation 1424, the vias are filled and the TSVs are formed using an Ag or Cu paste or other conductive material, such as using an inkjet-type applicator. As another example, the vias can be filled with Sn solder in a wave soldering process. In operation 1426, the assembly can be (optionally) encapsulated with another epoxy molding compound (EMC), conductive elements (e.g., solder bumps in a ball grid array (BGA) format) are applied or formed on the substrate opposite the KGD stack, testing is performed, and the KGD stack is singulated through other EMC (if present) and the substrate to form a package. In operation 1428, the top of the die stack can be covered with other EMC (if present) or it can be left exposed, e.g., for attaching a heat sink with a thermal interface material (TIM).

[0086] Figure 14B is a side cross-sectional schematic view of a microelectronic device package 1450 in accordance with an embodiment of the present disclosure, and the microelectronic device package can be in accordance with Figure 14AManufactured by the method. The microelectronic device package 1450 includes a substrate 1452 having traces (not shown) carried in a dielectric material and extending from conductive pads 1454 on its upper surface to conductive elements 1456 on its opposite lower surface. The conductive elements 1456 can include, for example, solder balls formed on or applied to the under bump metallization (UBM) layer of the substrate 1452. A plurality of semiconductor dies 1460A - 1460D (e.g., dies configured as double data rate (DDRx) DRAM, NAND flash memory, or 3D Xpoint (e.g., SXP) memory) are stacked on the upper surface of the substrate 1452. Each semiconductor die 1460A - 1460D is laminated to an RDL 1464 in a FOP configuration on the active surface 1462, and the RDL in the FOP configuration extends beyond at least one side periphery of the corresponding die 1460A - 1460D on one or more of its sides (two sides are shown). The conductive traces 1466 of the RDL 1464 extend laterally outward from the bonding pad positions (not shown) on the active surface 1462 of each semiconductor die 1460A - 1460D above the lower surface 1468 of the EMC 1470 around each semiconductor die 1460A - 1460D, extending at least to the position of vias 1472 filled with conductive material 1474, which extend between the semiconductor dies 1460A - 1460D and to the conductive pads 1454 of the substrate 1452. A polymer film 1476 is laminated over the RDL 1464 on each semiconductor die 1460A - 1460D, and the polymer film is, for example, a wafer or panel - level film, such as a non - conductive film (NCF) including silica - filled epoxy resin, a b - stage polyimide film, a polytetrafluoroethylene (PTFE) film, or other polymer films. Alternatively, capillary underfill (CUF) can be disposed between the semiconductor dies 1460A - 1460D. Conductive elements 1478 in the form of copper pillars or solder bumps extend through the polymer film 1476 between the lowermost semiconductor die 1460A and the substrate 1452 to contact the terminal pads (not shown) of the substrate 1452. The lowermost semiconductor die 1460A is connected to the substrate through the conductive elements 1478 and to the other semiconductor dies 1460B - 1460D through the conductive traces 1466 of its associated RDL1464 and TPV. The die stack can be encapsulated in another EMC 1480, for example, that extends at least around the lateral periphery of the die stack and abuts the upper surface of the substrate 1452. As shown, the EMC 1480 can extend over the uppermost semiconductor die 1460D. Alternatively, the EMC 1480 can cover the back surface of the uncovered semiconductor die 1460D with a thin dielectric layer. Embodiments of the present disclosure include the microelectronic device package 1450.

[0087] Figure 13A - 14B Embodiments reduce the cost of multi-die stacks and packages significantly by eliminating conventional post-wafer fabrication processes on the TSVs and dies. Additionally, these embodiments provide the ability to use different conductive trace designs for each RDL, allowing individual address pins to be used for each die in the stack. Further, the power and ground / bias of the semiconductor dies in the stack can be connected together, or for each die, it can be individual. Additionally, customizing the trace pattern for each layer of RDL facilitates configuring multi-die packages with the same or different die functions.

[0088] Embodiments of the present disclosure include a microelectronic device assembly that includes: a substrate having a conductor exposed on its surface; a stack of two or more microelectronic devices on the substrate, each microelectronic device including an active surface having bond pads operatively coupled to conductive traces that extend over a dielectric material to a via location outside of at least one side of the stack; and vias that extend through the dielectric material at the via location and include conductive material that contacts at least some of the conductive traces of each of the two or more microelectronic devices and extends to the exposed conductor of the substrate.

[0089] Embodiments of the present disclosure include an electronic system that includes an input device, an output device, a processor device, and at least one memory device. At least one of the processor device, the at least one memory device, or a combination thereof is configured to include an assembly of a stack of two or more semiconductor dies on a substrate, each semiconductor die including an active surface operatively coupled to conductive traces that extend over a dielectric material toward conductive vias located outside of at least one side of the stack, wherein the vias extend through the dielectric material to the conductor of the substrate, and at least some of the conductive traces of each of the two or more semiconductor dies are operatively coupled to at least some of the conductive vias.

[0090] Embodiments of the present disclosure include a method that includes: providing singulated semiconductor dies on a dielectric material, the singulated semiconductor dies having conductive traces that extend over their active surfaces and outside of at least one lateral periphery thereof; forming a stack of the singulated semiconductor dies on a substrate in a spaced-apart relationship; forming vias at locations that extend through the conductive traces and the dielectric material to conductive pads or traces on an adjacent surface of the substrate outside of at least one lateral periphery of the semiconductor dies in the stack; and filling the vias with conductive material.

[0091] Embodiments of the present disclosure include a method that includes: forming a reconstructed wafer or panel of semiconductor dies by adhering the semiconductor dies in a spaced-apart relationship through an active surface to a redistribution layer wafer or panel in a fan-out package configuration (FOP-configured RDL) having traces extending from bonding pads to regions on the RDL beyond a coverage area of each semiconductor die; laterally encapsulating the reconstructed wafer or panel of semiconductor dies in an epoxy molding compound (EMC); adhering the reconstructed wafer or panel of semiconductor dies to a die attach film (DAF) on one side of the EMC opposite the FOP-configured wafer or panel; singulating the semiconductor dies, the FOP-configured RDL wafer or panel, the EMC, and the DAF; stacking the singulated semiconductor dies, FOP-configured RDL, EMC, and DAF; forming openings through the singulated RDL, EMC, and DAF at via locations; and filling the openings with a conductive material.

[0092] Embodiments of the present disclosure include a method that includes: forming a reconstructed wafer or panel of semiconductor dies by adhering singulated semiconductor dies in a spaced-apart relationship through an active surface to a redistribution layer wafer or panel in a fan-out package configuration (FOP-configured RDL) having traces extending from bonding pads to regions on the RDL beyond a coverage area of each semiconductor die; encapsulating the reconstructed wafer or panel of semiconductor dies in an epoxy molding compound (EMC); laminating a polymer film over the FOP-configured RDL; singulating the semiconductor dies, the EMC, the FOP-configured RDL wafer or panel, and the polymer film; inverting and stacking the singulated semiconductor dies, FOP-configured RDL, EMC, and polymer film; forming openings through the singulated RDL, EMC, and polymer film at via locations; and filling the openings with a conductive material.

[0093] Additional non-limiting example embodiments of the present disclosure are described below.

[0094] Example 1: A method that includes:

[0095] forming a reconstructed wafer or panel by placing semiconductor dies in a spaced-apart relationship and laminating a polymer film over an active surface of the dies;

[0096] forming openings through the polymer film to expose bonding pads on the active surface;

[0097] forming conductive traces on the polymer film from the bonding pads to via locations outside a lateral periphery of the semiconductor die and between the semiconductor dies;

[0098] Singulate multiple sets of two or more semiconductor die through the polymer film and stack the singulated multiple sets of two or more semiconductor die on a substrate;

[0099] Form vias through the polymer film at the via locations on the stacked semiconductor die; and

[0100] Fill the vias with a conductive material.

[0101] Example 2: The method according to Example 1, further comprising, before forming the reconstructed wafer or panel:

[0102] Fabricate an active circuit system at the die locations on the active surface of a semiconductor substrate without TSVs;

[0103] Perform testing to determine the die locations of known good die (KGD);

[0104] Thin the semiconductor substrate from an initial thickness to a thickness of about 5 μm to about 200 μm;

[0105] Singulate the semiconductor substrate into individual KGD.

[0106] Example 3: The method according to Example 1 or 2, further comprising, after filling the vias with the conductive material:

[0107] Encapsulate the stack of the singulated multiple sets of two or more semiconductor die on the substrate with an epoxy molding compound (EMC);

[0108] Apply or form conductive elements on the substrate opposite the stack of the singulated multiple sets of two or more semiconductor die;

[0109] Test the stack of the singulated multiple sets of two or more semiconductor die; and

[0110] Singulate the stack of the singulated multiple sets of two or more semiconductor die through the EMC and the substrate.

[0111] Example 4: The method according to Example 3, wherein encapsulating the stack of the singulated multiple sets of two or more semiconductor die includes exposing the top of the stack and applying a thermal interface material (TIM) and a heat sink to the top of each stack.

[0112] Example 5: The method according to any one of Examples 1 to 4, wherein providing singulated semiconductor die includes providing DRAM, NAND flash memory, or 3D XPoint (SXP) memory die.

[0113] Example 6: The method according to Example 1 further includes placing the semiconductor die on a bonding film in a spaced-apart relationship through its back surface before laminating the polymer film on the spaced-apart semiconductor die.

[0114] Example 7: The method according to Example 6, wherein placing the semiconductor die on a bonding film in a spaced-apart relationship through its back surface includes placing the semiconductor die on a die attach film (DAF) or a film on die (FOD) material.

[0115] Example 8: The method according to any one of Examples 1, 5 or 6, wherein laminating the polymer film includes laminating a non-conductive film (NCF), a class b polyimide film or a polytetrafluoroethylene (PTFE) film.

[0116] Example 9: The method according to Example 2, wherein:

[0117] Fabricating an active circuit system at a die location on an active surface of a semiconductor substrate without TSVs includes:

[0118] Fabricating an active circuit system that exhibits a first function at a die location on an active surface of a first semiconductor substrate includes fabricating a memory die configured to operate as a slave die in a master / slave memory architecture; and

[0119] Fabricating an active circuit system that exhibits at least one second different function at a die location on an active surface of a second semiconductor substrate includes fabricating a memory die configured to operate as a master die in a master / slave memory architecture.

[0120] Example 10: The method according to Example 9 further includes singulating multiple sets of two or more master dies and placing the multiple sets of two or more master dies on a substrate; and

[0121] Stacking multiple sets of two or more slave dies on the multiple sets of two or more master dies.

[0122] Example 11: The method according to Example 9, wherein forming a reconstituted panel or wafer includes:

[0123] Forming a first reconstituted wafer by placing master dies in a spaced-apart relationship near one or more slave dies;

[0124] Singulating multiple sets of two or more semiconductor dies through the polymer film includes singulating master dies grouped with one or more slave dies;

[0125] Forming a second reconstituted wafer by placing slave dies in a spaced-apart relationship;

[0126] A single cut of multiple groups of two or more semiconductor die includes a single cut of multiple groups of two or more slave die; the method further includes:

[0127] Placing a single cut of multiple groups of master die having one or more slave die on a substrate; and

[0128] Stacking a single cut of multiple groups of two or more slave die respectively on the multiple groups of master die having one or more slave die.

[0129] Example 12: The method according to Example 2, wherein:

[0130] Fabricating an active circuit system at a die location on an active surface of a semiconductor substrate without TSVs includes:

[0131] Fabricating an active circuit system that exhibits a first function at a die location on an active surface of a first semiconductor substrate includes fabricating a memory die; and

[0132] Fabricating an active circuit system that exhibits at least one second different function at a die location on an active surface of a second semiconductor substrate includes fabricating a logic die configured to operate as a memory controller.

[0133] Example 13: The method according to Example 12, further comprising singulating multiple groups of two or more logic die and placing the multiple groups of two or more logic die on a substrate; and

[0134] Stacking multiple groups of two or more memory die respectively on the multiple groups of two or more logic die.

[0135] Example 14: The method according to Example 12, wherein forming a reconfigured panel or wafer includes:

[0136] Forming a first reconfigured wafer by placing logic die in a spaced-apart relationship relative to one or more memory die;

[0137] A single cut of multiple groups of two or more semiconductor die includes singulating logic die grouped with one or more memory die;

[0138] Forming a second reconfigured wafer by placing memory die in a spaced-apart relationship;

[0139] A single cut of multiple groups of two or more semiconductor die includes a single cut of multiple groups of two or more memory die; the method further includes:

[0140] Placing a single cut of multiple groups of logic die having one or more memory die on a substrate; and stacking a single cut of multiple groups of two or more memory die respectively on the multiple groups of one or more master die.

[0141] Example 15: A microelectronic device assembly, comprising:

[0142] A substrate having a conductor exposed on its surface;

[0143] Two or more stacks of two or more microelectronic devices on the substrate, each microelectronic device including an active surface having bonding pads, the bonding pads being operatively coupled to a first conductive trace that extends above a dielectric material to a via location outside at least one side of the microelectronic devices of the stack, and coupled to a second conductive trace that extends between at least some of the microelectronic devices in the two or more stacks of two or more microelectronic devices; and

[0144] A via that extends through the dielectric material at the via location and includes a conductive material that contacts at least some of the conductive traces of each of the two or more stacks of two or more microelectronic devices and extends to the exposed conductor of the substrate.

[0145] Example 16: The microelectronic device assembly according to Example 15, wherein at least some of the vias including the conductive material are configured to route signals between different stacks of microelectronic devices in combination with the conductive traces of a selected microelectronic device of the two or more microelectronic devices of the stack.

[0146] Example 17: The microelectronic device assembly according to Example 15 or 16, wherein the microelectronic device includes a semiconductor die.

[0147] Example 18: The microelectronic device assembly according to Example 17, wherein the semiconductor die includes a main memory die on a substrate at the base of at least one stack of microelectronic devices, and the remaining portion of the semiconductor die included in the microelectronic device assembly includes slave memory dies, wherein the microelectronic device assembly is configured with a master / slave DDR architecture.

[0148] Example 19: The microelectronic device assembly according to Example 18, further including a main memory die on the substrate at the base of each stack of microelectronic devices.

[0149] Example 20: The microelectronic device assembly according to Example 17, wherein the semiconductor die is configured as a memory die and a logic die, and the logic die is positioned at the base of at least one stack.

[0150] Example 21: The microelectronic device assembly according to Example 20, wherein the logic die is positioned at each of the stacked substrates.

[0151] Example 22: The microelectronic device assembly according to Example 17, wherein the microelectronic device includes semiconductor dies that exhibit at least two different functions.

[0152] Example 23: A method, comprising:

[0153] Forming a reconstituted panel or wafer by placing singulated semiconductor dies in a spaced-apart relationship and laminating a polymer film over the active surfaces of the dies, the singulated semiconductor dies including iRDLs that include traces for rerouting bond pad locations to an array of iRDL pads;

[0154] Forming vias through the polymer film to expose the iRDL pads on the active surfaces;

[0155] Filling the vias with a conductive material;

[0156] Singulating the semiconductor dies through the polymer film; and

[0157] Inverting at least one of the semiconductor dies and placing the at least one inverted semiconductor die on a substrate, wherein the vias filled with the conductive material are aligned with terminal pads on the substrate; and

[0158] Bonding the polymer film to the substrate and bonding the conductive material to the terminal pads.

[0159] Example 24: The method according to Example 23, further comprising, before forming the reconstituted wafer or panel:

[0160] Fabricating active circuitry at die locations on an active surface of a semiconductor substrate and forming iRDLs at each die location by traces for rerouting bond pad locations into the iRDL pads;

[0161] Testing the semiconductor substrate to determine die locations of known good dies (KGDs);

[0162] Thinning the semiconductor substrate from an initial thickness to a thickness of about 5 μm to about 200 μm; and

[0163] Singulating the semiconductor substrate into individual KGDs.

[0164] Example 25: The method according to Example 1 or 2, further comprising stacking additional semiconductor dies on the respective semiconductor dies placed on the substrate, and operably coupling the additional semiconductor dies to the terminal pads of the substrate through conductive vias, the conductive vias extending through the dielectric material outside the periphery of the additional semiconductor dies and being in electrical communication with the additional semiconductor dies through traces, the traces being carried by the dielectric material and extending to bonding pads on the active surface of the additional semiconductor dies.

[0165] Example 26: A microelectronic device assembly, comprising:

[0166] A microelectronic device, the surface of the microelectronic device facing the substrate;

[0167] A hole filled with a conductive material, the hole filled with the conductive material extending through a dielectric film between an array of iRDL pads on the active surface of the microelectronic device and terminal pads on the substrate; and

[0168] Additional microelectronic devices, the additional microelectronic devices being stacked on the semiconductor die, each of the additional microelectronic devices having a dielectric film extending above its surface and outside at least one periphery, each of the dielectric films carrying a conductive trace extending from a bonding pad on the surface of the microelectronic device to and in contact with a via filled with a conductive material in the dielectric film, the via extending to a terminal pad on the substrate.

[0169] Example 27: A microelectronic device assembly, comprising:

[0170] A stack of microelectronic devices on a substrate, each microelectronic device including a TSV extending through its thickness between a bonding pad on the active surface and a terminal pad on its back surface;

[0171] A dielectric film, the dielectric film being inserted between adjacent microelectronic devices in the stack, the dielectric film including holes aligned between the bonding pads and terminal pads of adjacent microelectronic devices in the stack;

[0172] The holes filled with a conductive material are in contact with the aligned bonding pads and terminal pads of adjacent microelectronic components.

[0173] Example 28: The microelectronic device assembly according to Example 27, wherein the dielectric film comprises a prefabricated polymer film, and the conductive material comprises a conductive metal paste.

[0174] Example 29: The microelectronic device assembly according to Example 27, wherein the dielectric film extends beyond at least one side of the stack and carries conductive traces from misaligned bond pads or terminal pads to conductive vias positioned beyond the at least one side of the stack, the conductive vias extending to terminal pads on the substrate, the conductive traces and conductive vias being operatively coupled for power and ground or bias transfer between the substrate and the microelectronic devices of the stack.

[0175] Example 30: The microelectronic device assembly according to Example 29, wherein the TSVs and the conductive material in contact with the aligned bond pads and terminal pads are operatively coupled for data signal transfer between the microelectronic devices of the stack and between the microelectronic devices of the stack and the substrate.

[0176] Example 31: A method, comprising:

[0177] Forming a reconstituted wafer or panel of semiconductor dies by adhering semiconductor dies in a spaced-apart relationship to an RDL wafer or panel in FOP configuration through active surfaces, the RDL wafer or panel in FOP configuration having traces extending from bond pads to areas on the RDL beyond the coverage regions of each semiconductor die;

[0178] Placing one or more surface-mounted components on the RDL in FOP configuration outside the coverage regions of laterally associated semiconductor dies at locations where vias will not be formed;

[0179] Laminating a polymer film over the back sides of the semiconductor dies of the reconstituted wafer or panel;

[0180] Singulating the polymer film and the RDL wafer or panel between the semiconductor dies;

[0181] Inverting the semiconductor dies and stacking the inverted semiconductor dies on a substrate, wherein the one or more surface-mounted components are within the die stack;

[0182] Forming vias through the polymer film and the RDL at via locations extending to conductive pads on the substrate; and

[0183] Filling the vias with a conductive material.

[0184] Example 32: The method according to Example 31, wherein placing one or more surface-mounted components includes placing one or more capacitors, inductors, or resistors.

[0185] Example 33: The method according to Example 31 or 32, further comprising placing one or more surface-mounted components on the top RDL of the inverted semiconductor die stack.

[0186] Example 34: The method according to any one of Examples 31, 32, or 33, wherein placing at least one surface-mounted component on the top RDL of the semiconductor die stack includes at least one of the following: placing at least one surface-mounted component above the top RDL of the semiconductor die stack or placing at least one surface-mounted component below the top RDL of the stack and outside the coverage area of the semiconductor die of the stack.

[0187] Example 35: The method according to any one of Examples 31 to 34, wherein the semiconductor die has at least two different sizes, and wherein, when stacking the inverted semiconductor die, at least one surface-mounted component is positioned within the coverage area of vertically adjacent semiconductor dies.

[0188] Example 36: A method, comprising:

[0189] forming a reconstructed wafer or panel of semiconductor dies by adhesively attaching semiconductor dies in a spaced-apart relationship through their active surfaces to an RDL panel or wafer in a FOP configuration, the RDL panel or wafer in a FOP configuration having traces extending from bonding pads to areas on the RDL beyond the coverage area of each semiconductor die;

[0190] laminating a polymer film over the back sides of the semiconductor dies of the reconstructed wafer or panel;

[0191] singulating the polymer film and the RDL between the semiconductor dies;

[0192] inverting the semiconductor dies and stacking the inverted semiconductor dies on a substrate;

[0193] forming vias through the polymer film and the RDL at via locations to conductive pads extending on the substrate;

[0194] filling the vias with a conductive material; and

[0195] placing one or more surface-mounted components on the top RDL of the semiconductor die stack.

[0196] Example 37: The method according to Example 36, wherein placing one or more surface-mounted components includes placing one or more capacitors, inductors, or resistors.

[0197] Example 38: A microelectronic device assembly, comprising:

[0198] A substrate having a conductor exposed on its surface;

[0199] A stack of two or more microelectronic devices on the substrate, each microelectronic device including an active surface having bonding pads operatively coupled to conductive traces that extend over a dielectric material to a via location outside the coverage area of the associated microelectronic device;

[0200] A via that extends through the dielectric material at the via location and includes conductive material that contacts at least some of the conductive traces of each of the two or more microelectronic devices and extends to the exposed conductor of the substrate; and

[0201] One or more surface-mounted components operatively coupled to conductive traces of at least one dielectric material.

[0202] Example 39: The microelectronic device assembly according to Example 38, wherein the one or more surface-mounted components are mounted to the at least one dielectric material at a location outside the coverage area of the microelectronic device associated with the dielectric material.

[0203] Example 40: The microelectronic device assembly according to Example 38 or 39, wherein the one or more surface-mounted components are mounted to the upper surface of the at least one dielectric material.

[0204] Example 41: The microelectronic device assembly according to Example 38 or 39, wherein the one or more surface-mounted components are mounted to the lower surface of the at least one dielectric material.

[0205] Example 42: The microelectronic device assembly according to any one of Examples 38, 39, or 40, wherein the one or more surface-mounted components are positioned on the topmost dielectric material above at least one via.

[0206] Example 43: The microelectronic device assembly according to Example 38, wherein the one or more surface-mounted components are positioned on a dielectric material within a stack where no via is located.

[0207] Example 44: The microelectronic device assembly according to any one of Examples 38, 39, 40, or 43, wherein at least one microelectronic device of the stack is smaller than at least one other adjacent microelectronic device of the stack, and the one or more surface-mounted components are mounted to the at least one dielectric material within the coverage area of the at least one other adjacent microelectronic device of the stack.

[0208] Example 45: The microelectronic device assembly according to any one of Examples 38 to 44, wherein the conductive traces at the via positions extending beyond the coverage regions of the associated microelectronic devices on the dielectric material include a redistribution layer (RDL) structure in a fan-out package configuration (FOP configuration).

[0209] Example 46: The microelectronic device assembly according to any one of Examples 38 to 45, wherein the microelectronic device includes a semiconductor die.

[0210] Example 47: The microelectronic device assembly according to any one of Examples 38 to 46, wherein the one or more surface-mounted components include one or more capacitors, inductors, or resistors.

[0211] Example 48: A method, comprising:

[0212] Forming a reconstructed wafer or panel of semiconductor dies by adhesively attaching semiconductor dies in a spaced-apart relationship through an active surface to an FOP configuration RDL panel or wafer having traces extending from bonding pads of each semiconductor die to regions on the associated RDL beyond the coverage region of the semiconductor die, wherein at least one of each semiconductor die or the associated RDL includes at least one ICL transmitter and at least one ICL receiver;

[0213] Laminating a polymer film over the back sides of the semiconductor dies of the reconstructed wafer or panel;

[0214] Singulating the polymer film and the RDL panel or wafer between the semiconductor dies;

[0215] Inverting the semiconductor dies and stacking the inverted semiconductor dies on a substrate, wherein the at least one ICL transmitter of each semiconductor die or the associated RDL is vertically aligned with the at least one ICL receiver of an adjacent semiconductor die or the associated RDL, and the at least one ICL receiver of each semiconductor die or the associated RDL is vertically aligned with the at least one ICL transmitter of an adjacent semiconductor die or the associated RDL;

[0216] Forming vias through the polymer film and the RDL at via positions to conductive pads extending onto the substrate; and

[0217] Filling the vias with a conductive material.

[0218] Example 49: The method according to Example 48, further comprising forming the at least one ICL emitter and the at least one ICL receiver on the semiconductor die in the BEOL processing of the wafer before singulating the semiconductor die from the wafer.

[0219] Example 50: The method according to Example 48, further comprising forming or placing the at least one ICL emitter and the at least one ICL receiver of each semiconductor die on the RDL panel or wafer in the FOP configuration before forming the reconstructed panel or wafer of the semiconductor die.

[0220] Example 51: The method according to any one of Examples 48, 49 or 50, further comprising providing at least one ICL emitter and at least one ICL receiver for the substrate before stacking the inverted semiconductor die on the substrate, and vertically aligning the at least one ICL emitter of the adjacent semiconductor die or associated RDL with the at least one ICL receiver of the substrate and the at least one ICL receiver of the adjacent semiconductor die or associated RDL with the at least one ICL emitter of the substrate.

[0221] Example 52: The method according to Example 48 or 51, further comprising providing a plurality of ICL emitters and a plurality of ICL receivers for each semiconductor die or associated RDL, and stacking the inverted semiconductor die, wherein the ICL emitters of the stacked semiconductor die or associated RDL are vertically aligned with the ICL receivers of the adjacent stacked semiconductor die or associated RDL, and the ICL receivers of the stacked semiconductor die or associated RDL are vertically aligned with the ICL emitters of the adjacent stacked semiconductor die or associated RDL.

[0222] Example 53: A microelectronic device assembly, comprising:

[0223] A substrate having a conductor exposed on its surface;

[0224] A stack of two or more microelectronic devices on the substrate, each microelectronic device including an active surface having bonding pads operatively coupled to conductive traces that extend over a dielectric material to via locations outside the coverage area of the associated microelectronic device;

[0225] A via for power and ground / bias signal communication, the via extending through the dielectric material at the via location and including conductive material in contact with at least some of the conductive traces of each of the two or more microelectronic devices; and

[0226] The microelectronic device or associated RDL includes at least one ICL transmitter and at least one ICL receiver within the coverage area of the corresponding microelectronic device. The at least one ICL transmitter of each microelectronic device or associated RDL is vertically aligned with the at least one ICL receiver of an adjacent microelectronic device or associated RDL, and the at least one ICL receiver of each microelectronic device or associated RDL is vertically aligned with the at least one ICL transmitter of an adjacent microelectronic device or associated RDL for data signal communication.

[0227] Example 54: The microelectronic device assembly according to Example 53, wherein the at least one ICL transmitter and the at least one ICL receiver are located within the BEOL structure of the corresponding microelectronic device.

[0228] Example 55: The microelectronic device assembly according to Example 53, wherein the at least one ICL transmitter and the at least one ICL receiver are located on the RDL associated with the corresponding microelectronic device.

[0229] Example 56: The microelectronic device assembly according to any one of Examples 53, 54, or 55, wherein the substrate includes at least one ICL transmitter and at least one ICL receiver, and the at least one ICL transmitter of an adjacent microelectronic device or associated RDL is vertically aligned with the at least one ICL receiver of the substrate, and the at least one ICL receiver of the adjacent microelectronic device or associated RDL is vertically aligned with the at least one ICL transmitter of the substrate.

[0230] Example 57: The microelectronic device assembly according to Example 53 or 56, wherein each microelectronic device or associated RDL includes a plurality of ICL transmitters and a plurality of ICL receivers, and the ICL transmitters of stacked microelectronic devices or associated RDLs are vertically aligned with the ICL receivers of adjacent stacked microelectronic devices or associated RDLs, and the ICL receivers of the stacked microelectronic devices or associated RDLs are vertically aligned with the ICL transmitters of adjacent stacked microelectronic devices or associated RDLs.

[0231] Example 58: The microelectronic device assembly according to any one of Examples 53 to 57, wherein the conductive traces at the via locations extending beyond the coverage area of the associated microelectronic device on the dielectric material include a redistribution layer in a fan-out package configuration (RDL in FOP configuration) structure.

[0232] Example 59: The microelectronic device assembly according to any one of Examples 53 to 58, wherein the microelectronic device includes a semiconductor die.

[0233] Example 60: The microelectronic device assembly according to any one of Examples 53 to 59, wherein the power and ground / bias signal communication through the conductive traces and vias is combined for all the microelectronic devices.

[0234] Example 61: The microelectronic device assembly according to any one of Examples 53 to 59, wherein the power and ground / bias communication through the conductive traces and vias is separate for at least some of the microelectronic devices.

[0235] Example 62: A microelectronic device assembly, comprising:

[0236] A substrate having conductors exposed on its surface;

[0237] A stack of two or more microelectronic devices on the substrate, each microelectronic device including an active surface having power and ground / bias pads operatively coupled to conductive traces, the conductive traces extending on a dielectric material to via locations outside the coverage area of the associated microelectronic device, and TSVs for data signal communication, the TSVs extending through the microelectronic device aligned with the TSVs of at least one of the adjacent microelectronic devices;

[0238] Vias for power and ground / bias communication, the vias extending through the dielectric material at the via locations and including conductive material in contact with at least some of the conductive traces of each of the two or more microelectronic devices, and extending to at least some of the exposed conductors of the substrate; and

[0239] Conductive elements extending through the dielectric material between adjacent microelectronic devices aligned with the TSVs for data signal communication.

[0240] Example 63: The microelectronic device assembly according to Example 62, wherein the power and ground / bias signal communication through the conductive traces and vias is combined for all the microelectronic devices.

[0241] Example 64: The microelectronic device assembly according to Example 62, wherein the power and ground / bias communication through the conductive traces and vias is separate for at least some of the microelectronic devices.

[0242] Example 65: The microelectronic device assembly according to any one of Examples 62 to 64 further includes an additional, topmost microelectronic device in the stack that does not have TSVs and has bonding pads aligned with the TSVs of the next lower microelectronic device in the stack.

[0243] Example 66: The microelectronic device assembly according to any one of Examples 62 to 65, wherein each microelectronic device is laterally surrounded by an EMC through which the vias extend.

[0244] Example 67: The microelectronic device assembly according to any one of Examples 62 to 66 further includes a conductive element that extends through the dielectric material between the TSVs of the lowermost microelectronic device and the conductor on the upper surface of the substrate for data signal communication.

[0245] Example 68: A method includes:

[0246] Forming a reconstituted wafer or panel of semiconductor dies by adhering semiconductor dies in a spaced-apart relationship through their active surfaces to an RDL wafer or panel in a FOP configuration that has traces extending from bonding pads to areas on the RDL beyond the coverage regions of each semiconductor die;

[0247] Laterally encapsulating the reconstituted wafer or panel of semiconductor dies in an EMC;

[0248] Adhering the reconstituted wafer or panel of semiconductor dies to a DAF on one side of the EMC opposite the FOP-configured wafer or panel;

[0249] Singulating the semiconductor dies, the FOP-configured RDL wafer or panel, the EMC, and the DAF;

[0250] Stacking the singulated semiconductor dies, FOP-configured RDL, EMC, and DAF;

[0251] Forming openings through the singulated RDL, EMC, and DAF at via locations that communicate with traces beyond the coverage regions of the stacked semiconductor dies; and

[0252] Filling the openings with a conductive material.

[0253] Example 69: The method according to Example 68 further includes stacking the singulated semiconductor dies, FOP-configured RDL, EMC, and DAF on a substrate; and

[0254] wherein filling the openings with a conductive material includes filling the openings with a conductive material to contact a conductor on the upper surface of the substrate.

[0255] Example 70: A microelectronic device assembly, comprising:

[0256] A substrate having a conductor exposed on its surface;

[0257] A stack of two or more microelectronic devices on the substrate, each microelectronic device including an active surface having bonding pads operatively coupled to conductive traces that extend over a dielectric material to a via location outside the coverage area of the associated microelectronic device;

[0258] An EMC laterally surrounding each of the two or more microelectronic devices;

[0259] DAF on each of the microelectronic devices and the surrounding EMC; and

[0260] A via that extends through the dielectric material, the EMC, and the DAF at the via location and includes conductive material that contacts at least some of the conductive traces of each of the two or more microelectronic devices and extends to the exposed conductor of the substrate.

[0261] Example 71: The microelectronic device assembly according to Example 70, wherein the conductive traces that extend over the dielectric material to a via location outside the coverage area of the associated microelectronic device include a redistribution layer in a fan-out package configuration (RDL in FOP configuration) structure.

[0262] Example 72: A method, comprising:

[0263] Forming a reconstructed wafer or panel of semiconductor dies by adhesively attaching singulated semiconductor dies to an RDL wafer or panel in FOP configuration through their active surfaces in a spaced-apart relationship, the RDL wafer or panel in FOP configuration having traces that extend from bonding pads to areas on the RDL outside the coverage area of each semiconductor die;

[0264] Laterally encapsulating the reconstructed wafer or panel of semiconductor dies in an EMC;

[0265] Laminating a polymer film over the RDL;

[0266] Singulating the semiconductor dies, the EMC, the RDL wafer or panel, and the polymer film;

[0267] Inverting and stacking the singulated semiconductor dies, the RDL in FOP configuration, the EMC, and the polymer film;

[0268] Form an opening through the singulated RDL, EMC, and polymer film at the via location; and

[0269] Fill the opening with a conductive material.

[0270] Example 73: The method according to Example 72, further comprising:

[0271] Before inverting and stacking the singulated semiconductor die, FOP-configured RDL, EMC, and polymer film, cause selected microelectronic devices to have conductive elements protruding on their active surfaces;

[0272] Wherein inverting and stacking the singulated semiconductor die, FOP-configured RDL, EMC, and polymer film includes inverting and stacking the protruding microelectronic devices on a substrate, wherein the conductive elements pass through the polymer film and contact the conductors of the substrate; and

[0273] Invert and stack the remaining microelectronic devices.

[0274] Example 74: A microelectronic device assembly, comprising:

[0275] A substrate having conductors exposed on its surface;

[0276] A stack of two or more microelectronic devices over the substrate, each microelectronic device including an active surface facing the substrate and having bonding pads operatively coupled to conductive traces that extend over a dielectric material to a via location outside the coverage area of the associated microelectronic device;

[0277] A polymer film over the dielectric material and the conductive traces;

[0278] EMC laterally surrounding each of the two or more microelectronic devices;

[0279] A via extending through the dielectric material, the polymer film, and the EMC at the via location, and including conductive material contacting at least some of the conductive traces of each of the two or more microelectronic devices and extending to the exposed conductors of the substrate; and

[0280] Another microelectronic device below the stack, adjacent to the substrate and having an active surface facing the substrate, the bonding pads of the another microelectronic device communicating with and contacting the conductors of the substrate through conductive elements extending through the polymer film.

[0281] Example 75: The microelectronic device assembly according to Example 74, wherein the conductive traces extending above the dielectric material to via locations outside the coverage areas of the associated microelectronic devices include a redistribution layer (RDL) structure in a fan-out package configuration (FOP configuration).

[0282] Example 76: A microelectronic device assembly, comprising:

[0283] A substrate having conductors exposed on its surface;

[0284] A stack of two or more microelectronic devices on the substrate, each microelectronic device including an active surface having bonding pads operatively coupled to conductive traces, the conductive traces extending above a dielectric material to via locations outside all sides of the stack;

[0285] A via extending through the dielectric material at the via location and including conductive material in contact with at least some of the conductive traces of each of the two or more microelectronic devices and extending to the exposed conductors of the substrate;

[0286] The combined vias include a ground stitch structure providing electromagnetic interference (EMI) protection;

[0287] A ground structure extending above the topmost microelectronic device and operatively coupled to the ground stitch structure, the ground structure and the ground stitch structure together providing a Faraday cage; and

[0288] A radio frequency antenna disposed above the Faraday cage and dielectrically isolated from the Faraday cage and operatively coupled to one or more of the microelectronic devices in the stack.

[0289] Example 77: A microelectronic device assembly, comprising:

[0290] A substrate having conductors exposed on its surface;

[0291] A stack of two or more microelectronic devices on the substrate, each microelectronic device including an active surface having bonding pads operatively coupled to conductive traces, the conductive traces extending above a dielectric material to via locations outside the coverage areas of the associated microelectronic devices;

[0292] The topmost microelectronic device of the stack, the topmost microelectronic device being configured as a relatively high power density device compared to the power density of one or more other microelectronic devices in the stack;

[0293] A heat sink structure positioned between the uppermost microelectronic device of the stack and the remainder of the stack of microelectronic devices; and

[0294] A via hole that extends through the dielectric material at the via hole location and includes conductive material that contacts at least some of the conductive traces of each of the two or more microelectronic devices and extends to the exposed conductor of the substrate.

[0295] Although certain illustrative embodiments have been described in connection with the accompanying drawings, those of ordinary skill in the art will recognize and understand that the embodiments covered by the present disclosure are not limited to those expressly shown and described herein. Instead, many additions, deletions, and modifications may be made to the embodiments described herein without departing from the scope of the embodiments covered by the present disclosure, as claimed hereinafter, including legal equivalents. In addition, features from one disclosed embodiment may be combined with features of another disclosed embodiment while still remaining within the scope of the present disclosure.

Claims

1. A microelectronic device assembly, which comprises: a substrate having conductors exposed on its surface; a stack of two or more microelectronic devices on the substrate, each microelectronic device having a polymer film on its active surface and on its sides, bonding pads exposed through openings in the polymer film on the active surface being operably coupled to conductive traces, the conductive traces being carried by the polymer film on its surface opposite the active surface and extending laterally outwardly above the polymer film to via positions outside at least one side of the stack; and conductive vias extending through the polymer film on the two or more microelectronic devices of the stack at the via positions, at least some of the conductive vias contacting at least some of the conductive traces carried by the polymer film of at least some of the two or more microelectronic devices of the stack and extending to the exposed conductors of the substrate; wherein the polymer film is a wafer or panel-level film and comprises a non-conductive film (NCF) having silica-filled epoxy resin, a b-stage polyimide film, or a polytetrafluoroethylene (PTFE) film.

2. The microelectronic device assembly according to claim 1, wherein at least some of the conductive vias are configured to route signals between at least two of the two or more microelectronic devices of the stack in combination with the conductive traces carried by the polymer film of the two or more microelectronic devices of the stack.

3. The microelectronic device assembly according to claim 1, wherein the conductive traces extend above the polymer film of the two or more microelectronic devices to the via positions outside a plurality of sides of the stack.

4. The microelectronic device assembly according to claim 1, wherein the via positions are arranged in one or more rows parallel to at least one side of the stack.

5. The microelectronic device assembly according to claim 4, wherein at least some of the conductive vias are configured to route signals between at least two of the two or more microelectronic devices of the stack in combination with the conductive traces of a selected microelectronic device of the two or more microelectronic devices of the stack through a signal path extending through at least two conductive vias.

6. The microelectronic device assembly according to claim 5, wherein the via positions are arranged in at least two rows, and the signal path between the at least two of the two or more microelectronic devices of the stack extends through conductive vias in different rows.

7. The microelectronic device assembly according to claim 3, wherein the via positions are arranged in at least two rows, and the via positions between the at least two rows are aligned or staggered with the via positions in at least one adjacent row.

8. The microelectronic device assembly according to claim 1, wherein the conductive trace carried by the polymer film and extending to a via location outside at least one side of the stack includes a redistribution layer (RDL) structure in a fan-out package configuration (FOP configuration).

9. The microelectronic device assembly according to claim 1, wherein the microelectronic device includes a semiconductor die.

10. The microelectronic device assembly according to claim 1, wherein the microelectronic device includes a semiconductor die exhibiting at least two different functions.

11. A microelectronic device assembly, which comprises: a substrate having a conductor exposed on its surface; a stack of two or more microelectronic devices on the substrate, each microelectronic device having a polymer film on its active surface and on its sides, bonding pads exposed through openings in the polymer film on the active surface being operably coupled to conductive traces, the conductive traces being carried by the polymer film on its surface opposite the active surface and laterally extending outwardly above the polymer film to a via location outside at least one side of the stack; conductive vias extending through the polymer film on the two or more microelectronic devices of the stack at the via location, at least some of the conductive vias contacting at least some of the conductive traces carried by the polymer film of at least some of the two or more microelectronic devices of the stack and extending to the exposed conductor of the substrate; and at least some of the conductive vias are configured to route signals between at least two of the two or more microelectronic devices of the stack through a signal path of conductive material extending through at least two conductive vias in combination with the conductive traces carried by the polymer film of the two or more microelectronic devices of the stack; and the via locations are arranged on all sides of the stack, and the outermost row of the via locations includes a ground stitch structure providing electromagnetic interference (EMI) protection; wherein the polymer film is a wafer or panel-level film and includes a non-conductive film (NCF) having silica-filled epoxy resin, a b-stage polyimide film, or a polytetrafluoroethylene (PTFE) film.

12. The microelectronic device assembly according to claim 11, further comprising a ground structure extending above the topmost microelectronic device of the stack, operably coupled to the ground stitch structure, and the ground structure and the ground stitch structure providing a Faraday cage.

13. The microelectronic device assembly according to claim 12, further comprising a radio frequency antenna disposed above the ground structure and electrically isolated from the ground structure, and operably coupled to one or more microelectronic devices of the stack.

14. A microelectronic device assembly, which comprises: a substrate having a conductor exposed on its surface; A stack of two or more microelectronic devices on the substrate, each microelectronic device having a polymer film on its active surface and its sides, bonding pads exposed through openings in the polymer film on the active surface being operably coupled to conductive traces, the conductive traces being carried by the polymer film and laterally extending outwardly over the polymer film to a via location beyond at least one side of the stack; Conductive vias extending through the polymer films of two or more microelectronic devices of the stack at the via location, at least some of the conductive vias contacting at least some of the conductive traces carried by the polymer films of at least some of the two or more microelectronic devices of the stack and extending to an exposed conductor of the substrate; And The conductive traces extending to a via location beyond at least one side of the stack over the polymer film include Ag or Cu traces on the polymer film; Wherein the polymer film is a wafer or panel-level film and includes a non-conductive film (NCF) having silica-filled epoxy resin, a b-stage polyimide film, or a polytetrafluoroethylene (PTFE) film.

15. A microelectronic device assembly, which Comprises: A substrate having an exposed conductor on its surface; A stack of two or more microelectronic devices on the substrate, each microelectronic device having a polymer film on its active surface and its sides, bonding pads exposed through openings in the polymer film on the active surface being operably coupled to conductive traces, the conductive traces being carried by the polymer film on its surface opposite to the active surface and laterally extending outwardly over the polymer film to a via location beyond at least one side of the stack; Conductive vias extending through the polymer films on the two or more microelectronic devices of the stack at the via location, at least some of the conductive vias contacting at least some of the conductive traces carried by the polymer films of at least some of the two or more microelectronic devices of the stack and extending to an exposed conductor of the substrate; And A dielectric thermal interface material TIM on the topmost microelectronic device of the stack and a heat sink structure on the TIM; Wherein the polymer film is a wafer or panel-level film and includes a non-conductive film (NCF) having silica-filled epoxy resin, a b-stage polyimide film, or a polytetrafluoroethylene (PTFE) film.

16. A microelectronic device assembly, which Comprises: A substrate having an exposed conductor on its surface; A stack of two or more microelectronic devices on the substrate, each microelectronic device having a polymer film on its active surface and on its sides, the bonding pads exposed through the openings in the polymer film on the active surface being operably coupled to conductive traces, the conductive traces being carried by the polymer film on its surface opposite the active surface and extending laterally outwardly above the polymer film to a via location outside of at least one side of the stack; Conductive vias that extend through the polymer films of the two or more microelectronic devices of the stack at the via location, at least some of the conductive vias being in contact with at least some of the conductive traces carried by the polymer films of at least some of the two or more microelectronic devices of the stack and extending to the exposed conductors of the substrate; And Another microelectronic device that is below the two or more microelectronic devices of the stack and is operably coupled to the conductors exposed on the substrate surface by conductive elements extending from its active surface in a direct chip attach (DCA) configuration; Wherein the polymer film is a wafer or panel-level film and includes a non-conductive film (NCF) having silica-filled epoxy resin, a b-stage polyimide film, or a polytetrafluoroethylene (PTFE) film.

17. The microelectronic device assembly according to claim 16, wherein the two or more microelectronic devices of the stack include slave memory dies, and the other microelectronic device includes a main memory die, the microelectronic device assembly being configured with a master / slave DDR architecture.

18. The microelectronic device assembly according to claim 16, wherein the two or more microelectronic devices of the stack are configured as memory dies, and the other microelectronic device is a logic die configured as a memory controller.

19. A microelectronic device assembly that Comprises: A substrate having conductors exposed on its surface; A stack of two or more microelectronic devices on the substrate, each microelectronic device having a polymer film on its active surface and on its sides, the bonding pads exposed through the openings in the polymer film on the active surface being operably coupled to conductive traces, the conductive traces being carried by the polymer film on its surface opposite the active surface and extending laterally outwardly above the polymer film to a via location outside of at least one side of the stack; Conductive vias that extend through the polymer films of the two or more microelectronic devices of the stack at the via location, at least some of the conductive vias being in contact with at least some of the conductive traces carried by the polymer films of at least some of the two or more microelectronic devices of the stack and extending to the exposed conductors of the substrate; And An epoxy molding compound EMC that laterally surrounds each of the two or more microelectronic devices, and the conductive vias extend through the EMC; wherein the polymer film is a wafer or panel-level film and includes a non-conductive film (NCF) having silica-filled epoxy resin, a b-stage polyimide film, or a polytetrafluoroethylene (PTFE) film.

20. The microelectronic device assembly according to claim 19, further comprising a die attach film DAF on the back surface of each of the two or more stacked microelectronic devices opposite the active surface, and the conductive vias extend through the DAF.

21. The microelectronic device assembly according to claim 19, further comprising another microelectronic device below the stack, adjacent to the substrate and having an active surface facing the substrate, and bonding pads of the another microelectronic device communicate with conductors of the substrate through conductive elements extending through the polymer film and contact the exposed conductors of the substrate.

22. The microelectronic device assembly according to claim 19, wherein the conductive traces at the via positions extending beyond the coverage area of the associated microelectronic device above the polymer film include a redistribution layer (RDL) structure of a fan-out package configuration (FOP configuration).

23. An electronic system, which comprises: an input device; an output device; a microelectronic device configured as a processor; and at least one microelectronic device configured as a memory, wherein at least one of the microelectronic device configured as a processor, the at least one microelectronic device configured as a memory, or a combination thereof is configured as an assembly, and the assembly includes: a stack of two or more microelectronic devices located on a substrate, the substrate having conductors exposed on its surface, each microelectronic device having a polymer film on its active surface and its side surfaces, and bonding pads exposed through openings in the polymer film on the active surface are operably coupled to conductive traces, the conductive traces are carried by the polymer film and laterally extend outward above the polymer film to via positions beyond at least one side of the stack; and conductive vias that extend through the polymer films of the two or more microelectronic devices of the stack at the via positions, at least some of the conductive vias contact at least some of the conductive traces carried by the polymer films of at least some of the two or more microelectronic devices of the stack, and extend to the exposed conductors of the substrate; wherein the polymer film is a wafer or panel-level film and includes a non-conductive film (NCF) having silica-filled epoxy resin, a b-stage polyimide film, or a polytetrafluoroethylene (PTFE) film.

24. The electronic system according to claim 23, further comprising at least one other microelectronic device below the stack of two or more microelectronic devices, the at least one other microelectronic device having an active surface facing the substrate and being operatively coupled to its conductors in a direct chip attach (DCA) configuration.

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