Semiconductor chip having dual chip pad structure and semiconductor package including same

Abstract

A semiconductor chip having a dual chip pad structure includes: a chip body; a first chip pad disposed on a first edge of the top surface of the chip body and a second edge of the top surface of the chip body; and a second chip pad disposed at a central portion in the first direction of the top surface between the first edge of the top surface of the chip body and the second edge of the top surface of the chip body along the second direction. The second edge of the top surface is opposite the first edge of the top surface in the first direction. The first die pad is disposed along a second direction perpendicular to the first direction. The first die pad includes a first signal pad coupled to the second die pad.

Description

[0001] This application claims the benefit of priority to Korean Patent Application No. 10-2023-0180104, filed with the Korean Intellectual Property Office on Dec. 12, 2023, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0002] The present disclosure generally relates to semiconductor chips, and more particularly, to semiconductor chips having a dual chip pad structure and semiconductor packages including the semiconductor chips. Background Art

[0003] Due to the development of the electronics industry and / or due to an increase in demand from users of electronic devices, electronic devices may become smaller and / or lighter. As electronic devices potentially become smaller and / or lighter, semiconductor packages used in semiconductor devices may also need to become smaller and / or lighter. Additionally, semiconductor packages may need to have relatively high reliability, relatively high and / or improved performance, and / or relatively large and / or increased capacity. Accordingly, signal transmission paths to semiconductor packages may become more complex in order to potentially meet the reliability, performance, and / or capacity requirements of semiconductor packages. Therefore, the importance of the structure of semiconductor packages corresponding to the size and / or performance of semiconductor packages and stably sending signals to semiconductor packages may be increasing. Summary of the Invention

[0004] One or more example embodiments of the present disclosure provide a semiconductor chip and a semiconductor package including the semiconductor chip, the semiconductor chip having an efficient chip pad arrangement structure and capable of reducing the size of the semiconductor package.

[0005] According to an aspect of the present disclosure, a semiconductor chip having a dual chip pad structure includes: a chip body; a first chip pad disposed on a first edge of a top surface of the chip body and a second edge of the top surface of the chip body, and a second chip pad disposed at a central portion in a first direction of the top surface between the first edge of the top surface of the chip body and the second edge of the top surface of the chip body along a second direction. The second edge of the top surface is opposite the first edge in the first direction. The first chip pad is disposed along a second direction perpendicular to the first direction. The first chip pad includes a first signal pad bonded to the second chip pad.

[0006] According to one aspect of the present disclosure, a semiconductor package includes: a package substrate; a first semiconductor chip disposed on the package substrate, having a first dual chip pad structure, and including a chip body, a first chip pad and a second chip pad disposed on a top surface of the chip body; and a first chip stack structure disposed on the package substrate adjacent to the first semiconductor chip in a first direction, and including a first plurality of memory chips stacked therein. The first chip pad is disposed on a first edge of the top surface of the chip body and a second edge of the top surface of the chip body. The second edge of the top surface is opposite to the first edge of the top surface in the first direction. The first chip pad is disposed along a second direction perpendicular to the first direction. The second chip pad is disposed along the second direction at a central portion in the first direction of the top surface between the first edge of the top surface of the chip body and the second edge of the top surface of the chip body. The first chip pad includes a first signal pad bonded to the second chip pad.

[0007] According to one aspect of the present disclosure, a semiconductor package includes: a package substrate; a first semiconductor chip on the package substrate, having a first dual chip pad structure, and including a chip body, a first chip pad and a second chip pad disposed on a top surface of the chip body; a second semiconductor chip adjacent to the first semiconductor chip in a first direction on the package substrate, and having a second dual chip pad structure identical to the first dual chip pad structure of the first semiconductor chip; and a chip stack structure disposed on the first semiconductor chip and the second semiconductor chip, and including a plurality of memory chips stacked therein. The first chip pad of each of the first semiconductor chip and the second semiconductor chip is disposed on a first edge of the top surface of the chip body and a second edge of the top surface of the chip body. The second edge of the top surface is opposite to the first edge of the top surface in the first direction. The first chip pad is disposed along a second direction perpendicular to the first direction. The second chip pad of each of the first semiconductor chip and the second semiconductor chip is disposed along the second direction at a central portion in the first direction of the top surface between the first edge of the top surface of the chip body and the second edge of the top surface of the chip body. The first chip pad of each of the first semiconductor chip and the second semiconductor chip includes a first signal pad bonded to the second chip pad.

[0008] Additional aspects will be set forth in part in the description which follows, and in part will be obvious from the description, and / or may be learned by practice of the presented embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] The above and other aspects, features and advantages of specific embodiments of the present disclosure will become more apparent from the following description taken in conjunction with the accompanying drawings.

[0010] Figure 1 is a plan view schematically showing a semiconductor chip according to an embodiment.

[0011] Figure 2A is a plan view showing a semiconductor chip according to a comparative example.

[0012] Figure 2B and Figure 2C is a perspective view showing the structure in which a semiconductor chip according to an embodiment Figure 1 and a semiconductor chip Figure 2A are connected to a package substrate through wires.

[0013] Figure 3A 、 Figure 3B and Figures 4A to 4C is a conceptual diagram showing the connection relationship between a second chip pad and a first signal pad of a semiconductor chip according to an embodiment Figure 1 of.

[0014] Figure 5A and Figure 5B is a cross-sectional view showing a semiconductor package including a semiconductor chip according to an embodiment Figure 1 of.

[0015] Figure 6A and Figure 6B is a cross-sectional view showing a semiconductor package including a semiconductor chip according to an embodiment Figure 1 of.

[0016] Figure 7A and Figure 7B is a cross-sectional view showing a semiconductor package including a semiconductor chip according to an embodiment Figure 1 of.

[0017] Figure 8 is a cross-sectional view showing a semiconductor package including a semiconductor chip according to an embodiment Figure 1 of.

[0018] Figure 9A and Figure 9B is a cross-sectional view showing a semiconductor package including a semiconductor chip according to an embodiment. DETAILED DESCRIPTION

[0019] The following description with reference to the accompanying drawings is provided to assist in a comprehensive understanding of embodiments of the present disclosure defined by the claims and their equivalents. Various specific details are included to assist in the understanding, but these details are only considered exemplary. Thus, those of ordinary skill in the art can recognize that various changes and modifications can be made to the embodiments described herein without departing from the scope and spirit of the disclosure. Additionally, descriptions of well-known functions and structures are omitted for clarity and conciseness.

[0020] Regarding the description of the accompanying drawings, like reference numerals may be used to represent like or related elements. It will be understood that unless the relevant context clearly indicates otherwise, the singular form of a noun corresponding to an item may include one or more things. As used herein, each of the phrases such as "A or B", "at least one of A and B", "at least one of A or B", "A, B, or C", "at least one of A, B, and C", and "at least one of A, B, or C" may include any possible combination of the items enumerated together in the corresponding phrase. As used herein, terms such as "first" and "second" or "1st" and "2nd" may be used simply to distinguish a corresponding component from another component and do not otherwise limit the component (e.g., in terms of importance or order). It will be understood that if an element (e.g., a first element) is referred to as "coupled", "coupled to", "connected to", or "connected to" another element (e.g., a second element), with or without the terms "operatively" or "communicatively", it means that the element can be coupled to the other element directly (e.g., wired), wirelessly, or via a third element.

[0021] It will be understood that when an element or layer is referred to as "on", "above", "over", "under", "beneath", "below", "connected to", or "coupled to" another element or layer, it can be directly "on", "above", "over", "under", "beneath", "below", directly connected to, or coupled to the other element or layer, or there may be intervening elements or layers. In contrast, when an element is referred to as "directly on", "directly above", "directly over", "directly under", "directly beneath", "directly below", "directly connected to", or "directly coupled to" another element or layer, there are no intervening elements or layers.

[0022] Terms such as "upper", "middle", "lower", etc. may be replaced with terms such as "first", "second", "third", etc. for describing the relative positions of elements. The terms "first", "second", "third" may be used to describe various elements, but the elements are not limited by the terms, and a "first element" may be referred to as a "second element". Optionally or additionally, the terms "first", "second", "third", etc. may be used to distinguish components from each other and do not limit the present disclosure. For example, the terms "first", "second", "third", etc. may not necessarily involve any form of order or numerical meaning.

[0023] As used herein, when an element or layer is referred to as "covering" another element or layer, the element or layer may cover at least a portion of the other element or layer, where the portion may include a part of the other element or may include the entirety of the other element. Similarly, when an element or layer is referred to as "penetrating" another element or layer, the element or layer may penetrate at least a portion of the other element or layer, where the portion may include a part of the other element or may include the overall dimensions (e.g., length, width, depth) of the other element.

[0024] References throughout this disclosure to "one embodiment", "an embodiment", "example embodiment", or similar language may indicate that a particular feature, structure, or characteristic described in connection with the indicated embodiment is included in at least one embodiment of the present solution. Thus, the phrases "in one embodiment", "in an embodiment", "in an example embodiment", and similar language throughout this disclosure may, but do not necessarily, all refer to the same embodiment. The embodiments described herein are example embodiments, and thus, this disclosure is not limited thereto and may be implemented in various other forms.

[0025] As used herein, each of the terms "GaAs", "InAs", "InP", "SiC", "SiGe", etc. may represent a material composed of the elements included in each term and is not a chemical formula representing a stoichiometric relationship.

[0026] Hereinafter, various embodiments of the present disclosure will be described with reference to the accompanying drawings.

[0027] Figure 1 is a plan view schematically showing a semiconductor chip according to an embodiment.

[0028] Referring to Figure 1 , the semiconductor chip 100 of the present disclosure may include a chip body 110, a first chip pad 120, a second chip pad 130, and a third chip pad 140.

[0029] The chip body 110 may form the main body of the semiconductor chip 100. The top surface of the chip body 110 may have a rectangular shape with a long side in one direction. However, the shape of the chip body 110 is not limited thereto. For example, according to an embodiment, the top surface of the chip body 110 may have a shape similar to a square shape.

[0030] The chip body 110 may include a substrate and an active layer. The substrate may include, but is not limited to, silicon (Si). For example, silicon (Si) may be in the form of single-crystalline Si, polycrystalline Si (poly Si), amorphous Si, etc. However, the material of the substrate is not limited to silicon. For example, in some embodiments, the substrate may include group-IV semiconductors (e.g., germanium (Ge)), group-IV-IV compound semiconductors (e.g., silicon germanium (SiGe) or silicon carbide (SiC)), or group-III-V compound semiconductors (e.g., gallium arsenide (GaAs), indium arsenide (InAs), or indium phosphide (InP)).

[0031] In one embodiment, the substrate may be based on a silicon (Si) bulk substrate. Optionally or additionally, the substrate may be based on a silicon-on-insulator (SOI) substrate or a germanium-on-insulator (GeOI) substrate. However, the present disclosure is not limited in this regard, and the substrate may be based on an epitaxial wafer, a polished wafer, an annealed wafer, etc.

[0032] The active layer may be and / or may include an integrated circuit layer and a multi-wiring layer. The integrated circuit layer may be formed by using impurity regions in the upper portion of the substrate. For example, the integrated circuit layer may be and / or may include transistors, which include gate electrodes and impurity regions (such as source / drain regions). However, the elements included in the integrated circuit layer are not limited to transistors. The multi-wiring layer may be located on the integrated circuit layer and may include internal wirings of multiple layers. The internal wirings may be electrically connected to the integrated circuit layer through contacts. Optionally or additionally, the internal wirings of different layers in the multi-wiring layer may be connected to each other through vertical vias.

[0033] The top surface of the active layer may correspond to the active surface, and the bottom surface of the substrate facing away from the active surface may correspond to the passive surface. In one embodiment, the first chip pad 120 to the third chip pad 140 may be located on the top surface of the active layer. Figure 1 The quadrilateral surface shown may correspond to the top surface of the chip body 110 and may correspond to the top surface of the active layer. In one embodiment, a passivation layer (such as, but not limited to, an oxide film, a nitride film, or a nitride oxide film) may be located on the top surface of the active layer to protect the semiconductor chip 100.

[0034] The semiconductor chip 100 of the present disclosure may be and / or may include, for example, a buffer chip and may include logic elements therein. In one embodiment, the buffer chip may be located on a package substrate together with a chip stack structure to form a semiconductor package. The buffer chip may integrate signals of memory chips in the chip stack structure, may send the signals to the outside, and may also send signals and power from the outside to the memory chips. According to an embodiment, the buffer chip may be referred to as a control chip. Refer to Figure 5ADescribe the buffer chip further.

[0035] The first chip pad 120 may be located on the edge of the top surface of the chip body 110. For example, when the top surface of the chip body 110 has a rectangular shape that is long in the y direction, the first chip pad 120 may be located on two edges in the x direction (e.g., the first edge and the second edge) along the y direction.

[0036] The first chip pad 120 may include a plurality of signal pads. The plurality of signal pads may represent pads for sending signals (such as, but not limited to, read, write, and erase signals) to the memory chips of the chip stack structure. As Figure 1 shown, the pads with names starting with "S" may correspond to the signal pads.

[0037] The first chip pad 120 may include a first signal pad 120S1 and second signal pads (e.g., a right second signal pad 120S2R and a left second signal pad 120S2L). The first signal pad 120S1 may be located on the left edge in the x direction along the y direction. In some embodiments, the first signal pad 120S1 may be located on the right edge in the x direction along the y direction. The left second signal pad 120S2L among the second signal pads 120S2R and 120S2L may be located on the left edge in the x direction along the y direction. The right second signal pad 120S2R among the second signal pads 120S2R and 120S2L may be located on the right edge in the x direction along the y direction.

[0038] As Figure 1 shown, the first signal pad 120S1 may correspond to the pads with names ending with "_U" (e.g., names S0_U to S6_U), and may be connected to the upper memory chips of the chip stack structure. Additionally, the right second signal pad 120S2R may correspond to the pads with names ending with "_L" (e.g., names S0_L to S6_L), and may be connected to the lower memory chips of the chip stack structure. Continuing to refer to Figure 1 , the left second signal pad 120S2L may correspond to the pads with names ending with "_0" (e.g., names S0_0 to S6_0).

[0039] The second chip pad 130 may be located at a central portion between two edges in the x-direction on the top surface of the chip body 110 along the y-direction. The second chip pad 130 may be located at a central portion on the top surface of the chip body 110 while being offset toward any one edge (e.g., the left edge) in the x-direction. However, according to an embodiment, the second chip pad 130 may be located at a central portion on the top surface of the chip body 110 while being offset toward the right side in the x-direction, or may be located at an exact center in the x-direction on the top surface of the chip body 110. In the x-direction, a first distance D1 between the first chip pad 120 and the second chip pad 130 may be maintained. The first distance D1 may be, for example, 75 micrometers (μm) or more. However, the first distance D1 is not limited to this numerical range.

[0040] The second chip pad 130 may include a plurality of signal pads. The second chip pad 130 may be connected to an upper memory chip of the chip stack structure. As Figure 1 shown, the second chip pad 130 may be connected to the upper memory chip and thus may have a name ending with “_U” (e.g., names S0_U to S6_U). Additionally, as Figure 1 marked by the dashed line in, the second chip pad 130 may be electrically connected to a first signal pad 120S1 of the first chip pad 120. The connection between the second chip pad 130 and the first signal pad 120S1 may be implemented through internal wiring i-W of a multi-wiring layer or a redistribution layer (RDL). Refer to Figures 3A to 4C to further describe the connection structure between the second chip pad 130 and the first signal pad 120S1.

[0041] When the second chip pad 130 and the first signal pad 120S1 are connected to each other, it may indicate that the second chip pad 130 and the first signal pad 120S1 send substantially similar and / or the same signals. Thus, the memory chips connected to the second chip pad 130 and the first signal pad 120S1 may be the same. As referred to Figure 5AFurther described, when used in a semiconductor package, the second chip pad 130 and the first signal pad 120S1 of the semiconductor chip 100 may correspond to chip pads having substantially similar and / or identical functions and may be selectively used. That is, when the second chip pad 130 is used, the first signal pad 120S1 may not be used. Optionally or additionally, when the first signal pad 120S1 is used, the second chip pad 130 may not be used. When a chip pad is used, it may indicate that the chip pad is connected to a wire in a connection structure by wire bonding, and when a chip pad is not used, it may indicate that the chip pad is not connected to a wire. Since the second chip pad 130 and the first signal pad 120S1 may have the same function, the semiconductor chip 100 of the present disclosure may have a dual chip-pad structure.

[0042] In some embodiments, the unused chip pad among the second chip pad 130 and the first signal pad 120S1 may be deactivated. Refer to Figures 3A to 4C The deactivation of the second chip pad 130 and the first signal pad 120S1 is further described.

[0043] The third chip pads 140 may be located on two edges of the top surface of the chip body 110 along the y direction. That is, the third chip pads 140 may be located on each of the right edge and the left edge in the x direction on the top surface of the chip body 110 along the y direction. The third chip pads 140 may include a power pad 140P and a ground pad 140G. The power pad 140P may supply a power voltage to the memory chips of the chip stack structure, and the ground pad 140G may supply a ground voltage to the memory chips of the chip stack structure. In Figure 1 it, the pad named VCC may correspond to the power pad 140P, and the pad named VSS may correspond to the ground pad 140G.

[0044] The semiconductor chip 100 of the present disclosure may include first chip pads 120 on both sides and a second chip pad 130 in the central portion between two edges, and the first chip pads 120 may include first signal pads 120S1 electrically connected to the second chip pad 130. In one embodiment, such a chip pad arrangement structure of the semiconductor chip 100 of the present disclosure, which can be used as a buffer chip of a semiconductor package, may allow for an efficient wire bonding structure with the memory chips of the chip stack structure of the semiconductor package. Therefore, the chip pad arrangement structure may significantly reduce the overall size of the semiconductor package.

[0045] Figure 2A is a plan view showing a semiconductor chip according to a comparative example. Figure 2B is a perspective view showing the structure of a semiconductor chip according to an embodiment Figure 1 connected to a package substrate by wires.Figure 2C A perspective view showing the structure in which a semiconductor chip according to an embodiment is connected to a package substrate through wires. Figure 2A

[0046] Referring to Figure 2A , the semiconductor chip Com may include chip pads located on the top surface of the chip body C-B. The chip pads may include signal pads (e.g., lower signal pad SP_L, common signal pad SP_C, and upper signal pad SP_U), power pads PP, and ground pads GP. The lower signal pad SP_L and the common signal pad SP_C may be located on the edge of the top surface of the chip body C-B. Optionally or additionally, the upper signal pad SP_U may be located at the central portion on the top surface of the chip body C-B. As shown in Figure 2A , the semiconductor chip Com may be used as a buffer chip of a semiconductor package, and when connected to a memory chip of a chip stack structure, the lower signal pad SP_L may be connected to the lower memory chip of the chip stack structure, and the upper signal pad SP_U may be connected to the upper memory chip of the chip stack structure. In the semiconductor chip Com, there may be no signal pad connected to the upper signal pad SP_U on the edge of the top surface of the chip body C-B.

[0047] Referring to Figure 2B and Figure 2C , in the semiconductor chip 100 of the present disclosure, the second chip pad 130 may be connected to the first signal pad 120S1 of the first chip pad 120 located on the edge through the RDL 145 and / or the internal wiring 150. Therefore, it is not necessary to directly connect the second chip pad 130 to the substrate pad 210 of the package substrate 200, and the second chip pad 130 may be indirectly connected to the substrate pad 210 of the package substrate 200 by using the first signal pad 120S1 and the wire 300.

[0048] Optionally, in the semiconductor chip Com as shown in Figure 2C , the signal pad corresponding to the upper signal pad SP_U is not located on the edge. Therefore, the common signal pad SP_C located on the edge may be connected to the first substrate pad S-P1 of the package substrate P-S near (e.g., within a specific threshold) the semiconductor chip Com through the first wire W1. Optionally, the upper signal pad SP_U at the central portion may be connected to the second substrate pad S-P2 of the package substrate P-S located away from the semiconductor chip Com through the second wire W2.

[0049] That is, compared with the case where the semiconductor chip 100 of the present disclosure is used as a buffer chip of a semiconductor package, when the semiconductor chip Com is used as a buffer chip of a semiconductor package, the size of the package substrate 200 may increase by a part where the second substrate pad S-P2 is located (i.e., Figure 2BPart A marked by a dashed line), and the overall size of the semiconductor package may also increase correspondingly. In addition, the use of relatively long second wires W2 may lead to potential waste of wire materials and / or problems of deterioration in wire connection reliability and signal reliability.

[0050] However, since the semiconductor chip 100 of the present disclosure includes first chip pads 120 located on two edges and second chip pads 130 located at the central portion between the two edges, and the first chip pads 120 include first signal pads 120S1 electrically connected to the second chip pads 130, potential problems of the semiconductor chip Com can be prevented.

[0051] Figures 3A to 4C is a conceptual diagram showing the connection relationship between the second chip pad and the first signal pad of the first chip pad in the semiconductor chip according to an embodiment. Figure 1 The semiconductor chips 100, 100a, 100b, and 100c may include the semiconductor chip 100 referred to above with reference to Figures 3A to 4C and Figure 1 and Figure 2B described, and may be similar to the semiconductor chip 100 referred to above with reference to Figure 1 and Figure 2B described in many aspects, and may include additional features not mentioned above. Therefore, for the sake of brevity, the repeated descriptions of the semiconductor chips 100, 100a, 100b, and 100c described above with reference to Figure 1 and Figure 2B may be omitted.

[0052] Referring to Figure 3A , in the semiconductor chip 100 of the present disclosure, the second chip pad 130 and the first signal pad 120S1 of the first chip pad 120 may be connected to each other through RDL 145. Optionally or additionally, the second chip pad 130 may be connected to the internal wiring 150 of the multi-wiring layer of the chip body 110. In the semiconductor chip 100 of the present disclosure, whether the second chip pad 130 and the first signal pad 120S1 are used or not, both may be maintained in an enabled state.

[0053] Referring to Figure 3B , in the semiconductor chip 100a of the present disclosure, the second chip pad 130 and the first signal pad 120S1 of the first chip pad 120 may be connected to each other through RDL 145. Optionally or additionally, the second chip pad 130 may be connected to the internal wiring 150 of the multi-wiring layer of the chip body 110. The semiconductor chip 100a of the present disclosure may further include a switching element 160 located on the RDL 145. The switching element 160 may include, for example, a transistor. However, the type of the switching element 160 is not limited to a transistor.

[0054] In the semiconductor chip 100a of the present disclosure, when the first signal pad 120S1 is not in use, the first signal pad 120S1 can be deactivated by the switching element 160. That is, when a wire is not connected to the first signal pad 120S1, the first signal pad 120S1 can be disconnected from the second chip pad 130 by turning off the switching element 160. In this way, since the unused first signal pad 120S1 is deactivated, a short circuit between another first chip pad 120 or a wire adjacent to the first signal pad 120S1 can be prevented.

[0055] Although the internal wiring 150 is depicted as directly connected to the second chip pad 130 in Figure 3B , the present disclosure is not limited thereto. For example, the internal wiring 150 can be directly connected to the first signal pad 120S1. In such an example, when the second chip pad 130 is not in use, the second chip pad 130 can be deactivated by the switching element 160.

[0056] Referring to Figure 4A , in the semiconductor chip 100 of the present disclosure, the second chip pad 130 and the first signal pad 120S1 of the first chip pad 120 can be connected to each other through the internal wiring 150 of a multi-wiring layer. In the semiconductor chip 100 of the present disclosure, whether the second chip pad 130 and the first signal pad 120S1 are in use or not, both can be maintained in an enabled state. Although in Figure 4A two internal wirings 150 are depicted as branching from one internal wiring 150 and connecting to the second chip pad 130 and the first signal pad 120S1, the present disclosure is not limited thereto. For example, the internal wiring 150 can be connected to any one of the second chip pad 130 and the first signal pad 120S1, and the second chip pad 130 and the first signal pad 120S1 can be connected to each other through another internal wiring 150.

[0057] Referring to Figure 4B , in the semiconductor chip 100b of the present disclosure, the second chip pad 130 and the first signal pad 120S1 of the first chip pad 120 can be connected to each other through the internal wiring 150 of a multi-wiring layer. Optionally or additionally, the semiconductor chip 100b of the present disclosure can further include a switching element 160a located on the internal wiring 150. The switching element 160a can include a first switching element 160-1 located near the first signal pad 120S1 (e.g., within a threshold proximity) and a second switching element 160-2 located near the second chip pad 130. The switching element 160a can include, for example, a transistor. However, the type of the switching element 160a is not limited to a transistor.

[0058] In the semiconductor chip 100b of the present disclosure, unused chip pads among the second chip pad 130 and the first signal pad 120S1 can be deactivated by the switching element 160a. That is, the "chip pad not connected to the wire" can be electrically disconnected by turning off the switching element 160a. In this way, since the unused chip pads are deactivated, short circuits between another chip pad or wire adjacent to the chip pad can be prevented.

[0059] Referring to Figure 4C , in the semiconductor chip 100c of the present disclosure, the second chip pad 130 and the first signal pad 120S1 of the first chip pad 120 can be connected to each other through the internal wiring 150 of the multi-wiring layer. Optionally or additionally, the second chip pad 130 can be connected to the internal wiring 150 of the multi-wiring layer of the chip body 110. The semiconductor chip 100c of the present disclosure may further include a switching element 160 located on the internal wiring 150 between the second chip pad 130 and the first signal pad 120S1. The switching element 160 can include, for example, a transistor. However, the type of the switching element 160 is not limited to a transistor.

[0060] In the semiconductor chip 100c of the present disclosure, when the first signal pad 120S1 is not in use, the first signal pad 120S1 can be deactivated by the switching element 160. That is, when the wire is not connected to the first signal pad 120S1, the first signal pad 120S1 can be disconnected from the second chip pad 130 by turning off the switching element 160. In this way, since the unused first signal pad 120S1 is deactivated, short circuits between another first chip pad 120 or wire adjacent to the first signal pad 120S1 can be prevented.

[0061] Although the internal wiring 150 is depicted as being directly connected to the second chip pad 130 in Figure 4C , the present disclosure is not limited thereto, and the internal wiring 150 can be directly connected to the first signal pad 120S1. In such an embodiment, when the second chip pad 130 is not in use, the second chip pad 130 can be deactivated by the switching element 160.

[0062] Figure 5A and Figure 5B are cross-sectional views of a semiconductor package including a semiconductor chip according to an embodiment. Together with Figure 1 , it is described Figure 1 and Figure 5A and Figure 5B . For the sake of brevity, repeated descriptions of the elements described with reference to Figures 1 to 4C can be omitted.

[0063] Referring to Figure 5A, the semiconductor package 1000 of the present disclosure may include a semiconductor chip 100, a package substrate 200, wires 300, a chip stack structure CSS, a sealing member 500, and external connection terminals 600.

[0064] The semiconductor chip 100 may be and / or may include Figure 1 the semiconductor chip 100. Thus, for the sake of brevity, the repeated description of the elements described with reference to Figure 1 may be omitted. As Figure 5A shown in, in the semiconductor package 1000 of the present disclosure, the semiconductor chip 100 may be stacked on the package substrate 200 through an adhesive layer 170. The adhesive layer 170 may be and / or may include, for example, a die attach film (DAF). However, the adhesive layer 170 is not limited to DAF. The connection relationship of the semiconductor chip 100 through the wires 300 is described when the chip stack structure CSS is described.

[0065] The package substrate 200 may be located below the semiconductor chip 100 and the chip stack structure CSS, and may support the semiconductor chip 100 and the chip stack structure CSS. In the semiconductor package 1000 of the present disclosure, the package substrate 200 may be and / or may include, for example, a printed circuit board (PCB). However, the package substrate 200 is not limited to PCB.

[0066] The package substrate 200 may include a substrate body, a substrate wiring layer, and a protective layer. The substrate body may include glass fiber and resin (such as FR4). However, the material of the substrate body is not limited thereto. For example, the substrate body may include a bismaleimide triazine (BT) resin, a polycarbonate (PC) resin, a build-up film (such as an Ajinomoto Build-Up Film®, ABF), or other laminated resins.

[0067] The substrate wiring layer may be located in the substrate body. For example, the substrate wiring layer may include a substrate wiring having a structure of 8 to 20 layers. However, the number of layers of the substrate wiring is not limited to the above range. The substrate wirings of different layers may be connected to each other through vertical vias. The protective layer may be and / or may include a layer for protecting the substrate body and the substrate wiring layer from external physical and chemical damage. The protective layer may include an upper protective layer and a lower protective layer. The protective layer may include, for example, a solder resist (SR). However, the material of the protective layer is not limited to SR.

[0068] As Figure 5AAs shown in [FIGURE], the chip stack structure CSS may include a plurality of memory chips 400 stacked in a vertical direction (e.g., along the z-direction) on a package substrate 200. In the semiconductor package 1000 of the present disclosure, each of the memory chips 400 of the chip stack structure CSS may be and / or may include a flash memory chip (e.g., a NAND flash memory chip). However, the type of the memory chip 400 is not limited to a flash memory chip.

[0069] As Figure 5A shown in [FIGURE], in the chip stack structure CSS, the memory chips 400 may be stacked in a stepped structure. For example, the chip stack structure CSS may have a stepped structure in which the positions of the memory chips 400 are offset upward and offset to the right in the x-direction. In the semiconductor package 1000 of the present disclosure, as an example, the chip stack structure CSS may include eight (8) memory chips 400. However, the number of the memory chips 400 included in the chip stack structure CSS is not limited to eight (8). In the chip stack structure CSS, the eight (8) memory chips 400 may be divided into a lower memory chip LMC and an upper memory chip UMC. The lower memory chip LMC includes four (4) memory chips 400 located at a low position (e.g., the first memory chip 400-1 to the fourth memory chip 400-4), and the upper memory chip UMC includes four (4) memory chips 400 located at a high position (e.g., the fifth memory chip 400-5 to the eighth memory chip 400-8). For example, the lower memory chip LMC may exchange signals through a lower channel, and the upper memory chip UMC may exchange signals through an upper channel.

[0070] Each memory chip 400 may be stacked on the package substrate 200 or the lower memory chip LMC through an adhesive layer 450. The adhesive layer 450 may be, for example, DAF. However, the material of the adhesive layer 450 is not limited to DAF. The lowermost first memory chip 400-1 among the lower memory chips LMC and the lowermost fifth memory chip 400-5 among the upper memory chips UMC may be stacked through the adhesive layer 450, and the adhesive layer 450 may be thicker than the adhesive layers corresponding to the other memory chips 400 (e.g., the memory chips other than the first memory chip 400-1 and the fifth memory chip 400-5). However, in some embodiments, the adhesive layer 450 may all have substantially similar and / or the same thickness.

[0071] The connection relationship through the wire 300 among the semiconductor chip 100, the memory chip 400 of the chip stack structure CSS, and the package substrate 200 may be implemented as follows.

[0072] The semiconductor chip 100 can be connected to a first substrate pad 210 of the package substrate 200 through a first wire 310. That is, a right chip pad 120R located on the right edge of the semiconductor chip 100 in the x direction can be connected to the first substrate pad 210 on the right side of the package substrate 200 in the x direction through the first wire 310. Optionally or additionally, a left chip pad 120L located on the left edge of the semiconductor chip 100 in the x direction can be connected to the first substrate pad 210 on the left side of the package substrate 200 in the x direction through the first wire 310. As Figure 1 shown, the right chip pad 120R and the left chip pad 120L can include a first chip pad 120 and a third chip pad 140. However, for convenience, in Figures 5A to 9B it, only the first chip pad 120 may be shown, and the third chip pad 140 may not be shown. The first chip pad 120 of the right chip pad 120R can include a right second signal pad 120S2R, and the first chip pad 120 of the left chip pad 120L can include a first signal pad 120S1 and a left second signal pad 120S2L.

[0073] The semiconductor chip 100 can be directly connected to an upper memory chip UMC of a chip stack structure CSS through a second wire 320. That is, a second chip pad 130 located in the central portion of the semiconductor chip 100 can be connected to a chip pad 420 of a fifth memory chip 400-5 among the upper memory chips UMC through the second wire 320. The chip stack structure CSS can be connected to a second substrate pad 220 of the package substrate 200 through a third wire 330. That is, a chip pad 420 of a first memory chip 400-1 of the chip stack structure CSS can be connected to the second substrate pad 220 of the package substrate 200 through the third wire 330.

[0074] The right second signal pad 120S2R of the first chip pad 120 of the semiconductor chip 100 can be and / or can include a lower channel pad, and can be connected to a chip pad 420 of a lower memory chip LMC through the first wire 310, the first substrate pad 210, the second substrate pad 220, and the third wire 330 to exchange signals with the lower memory chip LMC. The first substrate pad 210 and the second substrate pad 220 can be connected to each other through substrate wiring of the package substrate 200. However, in some embodiments, the first substrate pad 210 and the second substrate pad 220 can be integrated into one substrate pad, and in such embodiments, the first substrate pad 210 and the second substrate pad 220 can be directly connected without substrate wiring.

[0075] The second chip pad 130 of the semiconductor chip 100 may be and / or may include an upper channel pad, and may be connected to the chip pad 420 of the upper memory chip UMC through the second wire 320 to exchange signals with the upper memory chip UMC. When using the second chip pad 130 of the semiconductor chip 100, the first signal pad 120S1 of the first chip pad 120 may not be used. That is, the wire may not be connected to the first signal pad 120S1. Optionally or additionally, according to Figures 3A to 4C the various wiring connection structures, the first signal pad 120S1 may be deactivated or maintained in an enabled state.

[0076] The left second signal pad 120S2L of the first chip pad 120 of the semiconductor chip 100 may be and / or may include a common channel pad, and may be connected to the external connection terminal 600 of the package substrate 200 through the substrate wiring of the package substrate 200. Optionally or additionally, the third chip pad 140 of the semiconductor chip may also be connected to the chip pad 420 of the memory chip 400 through the first wire 310, the first substrate pad 210, the second substrate pad 220, and the third wire 330 to supply a power voltage and / or a ground voltage to the memory chip 400.

[0077] The sealing member 500 may cover and seal the semiconductor chip 100, the chip stack structure CSS, and the wires 300 on the package substrate 200. The sealing member 500 may seal the semiconductor chip 100 and the memory chip 400 of the chip stack structure CSS to protect the semiconductor chip 100 and the memory chip 400 from external physical and chemical damage. The sealing member 500 may include an insulating material (such as, but not limited to, a thermosetting resin (such as, epoxy resin) or a thermoplastic resin (such as, polyimide)). Optionally or additionally, the sealing member 500 may include a thermosetting resin or a thermoplastic resin containing a reinforcing material (such as, but not limited to, an inorganic filler (such as, ABF, flame retardant 4 (FR-4), or BT resin)). Optionally or additionally, the sealing member 500 may include, but not be limited to, a molding material (such as, epoxy molding compound (EMC)) or a photosensitive material (such as, photosensitive encapsulant (PIE)). In the semiconductor package 1000 of the present disclosure, the sealing member 500 may include, for example, EMC. However, the material of the sealing member 500 is not limited to the above materials.

[0078] The external connection terminals 600 may be located on the bottom surface of the package substrate 200. For example, the external connection terminals 600 may be located on the external pads on the bottom surface of the package substrate 200. The external connection terminals 600 may be electrically connected to the substrate wiring of the package substrate 200 through the external pads. The external connection terminals 600 may include solder balls. However, according to an embodiment, the external connection terminals 600 may include pillars and solder. The semiconductor package 1000 of the present disclosure may be mounted on an external substrate (such as an interposer or a base substrate) through the external connection terminals 600.

[0079] Referring to Figure 5B , the semiconductor package 1000a of the present disclosure may be different from Figure 5A the semiconductor package 1000 in the connection structure of the wire 300a between the semiconductor chip 100 and the chip stack structure CSS. That is, the semiconductor package 1000a of the present disclosure may include a semiconductor chip 100, a package substrate 200, a wire 300a, a chip stack structure CSS, a sealing member 500, and external connection terminals 600. The semiconductor chip 100, the package substrate 200, the chip stack structure CSS, the sealing member 500, and the external connection terminals 600 may include Figure 5A those in the semiconductor package 1000 of Figure 5A and / or may be similar to those in the semiconductor package 1000 of

[0080] The connection relationship between the semiconductor chip 100, the memory chip 400 of the chip stack structure CSS, and the package substrate 200 through the wire 300a may be described as follows.

[0081] The connection relationship between the second signal pads 120S2R and 120S2L of the first chip pad 120 of the semiconductor chip 100 and the third chip pad 140 and the chip stack structure CSS through the wire 300a may be substantially similar and / or the same as the connection relationship in Figure 5A the semiconductor package 1000 of

[0082] In the semiconductor package 1000a of the present disclosure, the first signal pad 120S1 of the first chip pad 120 of the semiconductor chip 100 may be used as an upper channel pad, and may be connected to the chip pad 420 of the upper memory chip UMC through a first wire 310, a first substrate pad 210, a third substrate pad 230, and a second wire 320a to exchange signals with the upper memory chip UMC. The first substrate pad 210 and the third substrate pad 230 may be connected to each other through the substrate wiring of the package substrate 200.

[0083] As Figure 1As shown, the first signal pad 120S1 may be included in the left chip pad 120L and may be located on the left edge of the semiconductor chip 100 in the x direction. However, in some embodiments, the first signal pad 120S1 may be included in the right chip pad 120R and may be located on the right edge of the semiconductor chip 100 in the x direction. When the first signal pad 120S1 is located on the right edge, the first substrate pad 210 and the third substrate pad 230 connected to the first signal pad 120S1 may be integrated into one and may be connected to each other without substrate wiring.

[0084] When the first signal pad 120S1 of the first chip pad 120 of the semiconductor chip 100 serves as the upper channel pad, the second chip pad 130 may not be used. That is, the wire may not be connected to the second chip pad 130. According to Figures 3A to 4C various wiring connection structures, the second chip pad 130 may be deactivated or may be maintained in an enabled state.

[0085] Since the semiconductor packages 1000 and 1000a of the present disclosure selectively use the second chip pad 130 and the first signal pad 120S1 of the first chip pad 120 of the semiconductor chip 100 as the upper channel pad based on the chip pad arrangement structure of the semiconductor chip 100, a more flexible wire connection structure can be achieved between the semiconductor chip 100 and the chip stack structure CSS. Optionally or additionally, as in the structure of the semiconductor package 1000a in Figure 5B even when the second wire 320a for the upper channel is connected to the package substrate 200, it may not necessarily be required to use the second chip pad 130 at the central portion of the semiconductor chip 100. Therefore, as described with reference to Figures 2A to 2C compared with the semiconductor package 1000 in Figure 5A the size of the semiconductor package 1000a may not increase significantly.

[0086] Figure 6A and Figure 6B are cross-sectional views showing semiconductor packages including semiconductor chips according to embodiments. Together with Figure 1 describe Figure 1 Figure 5A and Figure 5B For the sake of brevity, repeated descriptions of the elements described above with reference to Figure 6A and Figure 6B may be omitted. In Figures 1 to 5B names ending with "-1" may represent components, wires, pads, etc. located in the left half, and names ending with "-2" may represent components, wires, pads, etc. located in the right half. Figure 6A and Figure 6B Refer to

[0087] Refer to Figure 6A, the semiconductor package 1000b of the present disclosure may have two Figure 5A structures in which the semiconductor packages 1000 are arranged along the x direction. That is, the semiconductor package 1000b of the present disclosure may include a first semiconductor chip 100-1, a second semiconductor chip 100-2, a package substrate 200, wires 300b, a first chip stack structure CSS-1, a second chip stack structure CSS-2, a sealing member 500, and external connection terminals 600.

[0088] The left half of the first semiconductor chip 100-1, the package substrate 200, and the wires 300b, the first chip stack structure CSS-1, and the left half of the sealing member 500 and the external connection terminals 600 may be substantially similar and / or identical to those in Figure 5A the semiconductor package 1000. Optionally or additionally, when rotated 180° about the z-axis, the right half of the second semiconductor chip 100-2, the package substrate 200, and the wires 300b, the second chip stack structure CSS-2, and the right half of the sealing member 500 and the external connection terminals 600 may be substantially similar and / or identical to those in Figure 5A the semiconductor package 1000.

[0089] Each of the first semiconductor chip 100-1 and the second semiconductor chip 100-2 may have a dual-chip pad structure, and / or may be substantially similar or identical to the Figure 1 first semiconductor chip 100. For reference, in Figure 6A , the second semiconductor chip 100-2 may be rotated 180° about the z-axis relative to the first semiconductor chip 100-1 and may be located on the package substrate 200. Optionally or additionally, the memory chip 400 of the second chip stack structure CSS-2 may be rotated 180° about the z-axis relative to the memory chip 400 of the first chip stack structure CSS-1 and may be stacked and located on the package substrate 200.

[0090] Referring to Figure 6B , the semiconductor package 1000c of the present disclosure may have two Figure 5B structures in which the semiconductor packages 1000a are arranged along the x-axis. That is, the semiconductor package 1000c of the present disclosure may include a first semiconductor chip 100-1, a second semiconductor chip 100-2, a package substrate 200, wires 300c, a first chip stack structure CSS-1, a second chip stack structure CSS-2, a sealing member 500, and external connection terminals 600.

[0091] The left half of the first semiconductor chip 100-1, the package substrate 200, and the wire 300c, the first chip stack structure CSS-1, and the left half of the sealing member 500 and the external connection terminal 600 can be substantially similar and / or identical to those in Figure 5B the semiconductor package 1000a. Optionally or additionally, when rotated 180° about the z-axis, the right half of the second semiconductor chip 100-2, the package substrate 200, and the wire 300c, the second chip stack structure CSS-2, and the right half of the sealing member 500 and the external connection terminal 600 can be substantially similar and / or identical to those in Figure 5B the semiconductor package 1000a.

[0092] Each of the first semiconductor chip 100-1 and the second semiconductor chip 100-2 can have a dual-chip pad structure and can be substantially similar and / or identical to the semiconductor chip 100 in Figure 1 . Optionally or additionally, in Figure 6B , the second semiconductor chip 100-2 can be rotated 180° about the z-axis relative to the first semiconductor chip 100-1 and can be located on the package substrate 200. In one embodiment, the memory chip 400 of the second chip stack structure CSS-2 can be rotated 180° about the z-axis relative to the memory chip 400 of the first chip stack structure CSS-1 and can be stacked and located on the package substrate 200.

[0093] Since the semiconductor packages 1000b and 1000c of the present disclosure selectively use the second chip pads 130-1 and 130-2 and the first signal pads 120S1 of the first chip pads 120-1 and 120-2 as the upper channel pads based on the chip pad arrangement structures of the first semiconductor chip 100-1 and the second semiconductor chip 100-2, a more flexible wire connection structure can be achieved between the first semiconductor chip 100-1 and the second semiconductor chip 100-2 and the first chip stack structure CSS-1 and the second chip stack structure CSS-2. Optionally or additionally, as in the structure of the semiconductor package 1000c in Figure 6B , even when the second wires 320a-1 and 320a-2 for the upper channel are connected to the package substrate 200, it may not necessarily be required to use the second chip pads 130-1 and 130-2 at the central portions of the first semiconductor chip 100-1 and the second semiconductor chip 100-2. Therefore, compared with the semiconductor package 1000b in Figure 6A , the size of the semiconductor package 1000c in Figure 6B may not increase significantly.

[0094] Figure 7A And Figure 7B are diagrams showing a semiconductor package including an embodimentFigure 1 Cross-sectional view of a semiconductor package of a semiconductor chip. Together with Figure 1 , Figure 5A and Figure 5B described together Figure 7A and Figure 7B . For the sake of brevity, repeated descriptions of the components described above with reference to Figures 1 to 6B may be omitted.

[0095] Referring to Figure 7A , the semiconductor package 1000d of the present disclosure may have a structure in which two semiconductor chips 100 and two chip stack structures CSS are stacked with Figure 5B . That is, the semiconductor package 1000d of the present disclosure may include a first semiconductor chip 100-1, a second semiconductor chip 100-2, a package substrate 200, wires 300d, a first chip stack structure CSS-1, a second chip stack structure CSS-2, a sealing member 500, and external connection terminals 600. The package substrate 200, the sealing member 500, and the external connection terminals 600 may be substantially similar and / or identical to those in the Figure 5A semiconductor package 1000.

[0096] Each of the first semiconductor chip 100-1 and the second semiconductor chip 100-2 may have a dual-chip pad structure and may be substantially similar and / or identical to the Figure 1 semiconductor chip 100. Optionally or additionally, the second semiconductor chip 100-2 may be stacked on the first semiconductor chip 100-1 through an adhesive layer 170-2.

[0097] Each of the first chip stack structure CSS-1 and the second chip stack structure CSS-2 may be substantially similar and / or identical to the Figure 5A chip stack structure CSS. Thus, the first chip stack structure CSS-1 may include a lower memory chip LMC-1 and an upper memory chip UMC-1, and the second chip stack structure CSS-2 may include a lower memory chip LMC-2 and an upper memory chip UMC-2. Optionally or additionally, the second chip stack structure CSS-2 may be stacked on the first chip stack structure CSS-1 through an adhesive layer 450 to form an overall chip stack structure CSSa together with the first chip stack structure CSS-1.

[0098] The connection relationship between the first semiconductor chip 100-1 and the second semiconductor chip 100-2, the memory chips 400 of the first chip stack structure CSS-1 and the second chip stack structure CSS-2, and the package substrate 200 through the wires 300d may be described as follows.

[0099] The connection relationship between the second signal pads 120S2R and 120S2L of the first chip pad 120-1 of the first semiconductor chip 100-1, the third chip pad 140-1, and the first chip stack structure CSS-1 through the wire 300d can be substantially similar and / or the same as that in Figure 5B the semiconductor package 1000a. The first substrate pad 210-1, the second substrate pad 220-1, the third substrate pad 230-1, the first wire 310-1, the second wire 320a-1, and the third wire 330-1 can respectively correspond to Figure 5B the first substrate pad 210, the second substrate pad 220, the third substrate pad 230, the first wire 310, the second wire 320a, and the third wire 330 in the semiconductor package 1000a. Since the second semiconductor chip 100-2 is stacked on the first semiconductor chip 100-1 through the adhesive layer 170-2, at least a part of the connection of the first wire 310-1 to the first semiconductor chip 100-1 can be covered by the adhesive layer 170-2.

[0100] The connection relationship between the second signal pads 120S2R and 120S2L of the first chip pad 120-2 of the second semiconductor chip 100-2, the third chip pad 140-2, and the second chip stack structure CSS-2 through the wire 300d can be substantially similar and / or the same as that in Figure 5B the semiconductor package 1000a. The first substrate pad 210-2, the second substrate pad 220-2, the third substrate pad 230-2, the first wire 310-2, the second wire 320a-2, and the third wire 330-2 can respectively correspond to Figure 5B the first substrate pad 210, the second substrate pad 220, the third substrate pad 230, the first wire 310, the second wire 320a, and the third wire 330 in the semiconductor package 1000a.

[0101] In the semiconductor package 1000d of the present disclosure, the first signal pads 120S1 of the first chip pads 120-1 and 120-2 of the first semiconductor chip 100-1 and the second semiconductor chip 100-2 can be used as upper channel pads, and can be connected to the chip pads 420 of the upper memory chips UMC-1 and UMC-2 of the first chip stack structure CSS-1 and the second chip stack structure CSS-2 through the first wires 310-1 and 310-2, the first substrate pads 210-1 and 210-2, the third substrate pads 230-1 and 230-2, and the second wires 320a-1 and 320a-2 to exchange data with the upper memory chips UMC-1 and UMC-2.

[0102] When the first signal pads 120S1 of the first chip pads 120-1 and 120-2 of the first semiconductor chip 100-1 and the second semiconductor chip 100-2 are used as the upper channel pads, the second chip pads 130-1 and 130-2 may not be used. That is, the wires may not be connected to the second chip pads 130-1 and 130-2. According to Figures 3A to 4C the various wiring connection structures, the second chip pads 130-1 and 130-2 may be deactivated or may be maintained in an enabled state.

[0103] Referring to Figure 7B , the semiconductor package 1000e of the present disclosure may have a structure of " Figure 5A the semiconductor chip 100 and the chip stack structure CSS of the semiconductor package 1000 may be stacked on Figure 5B the semiconductor chip 100 and the chip stack structure CSS of the semiconductor package 1000a". That is, the semiconductor package 1000e of the present disclosure may include a first semiconductor chip 100-1, a second semiconductor chip 100-2, a package substrate 200, wires 300e, a first chip stack structure CSS-1, a second chip stack structure CSS-2, a sealing member 500, and external connection terminals 600. The package substrate 200, the sealing member 500, and the external connection terminals 600 may be substantially similar and / or identical to those in Figure 5A the semiconductor package 1000.

[0104] Each of the first semiconductor chip 100-1 and the second semiconductor chip 100-2 may have a dual-chip pad structure and / or may be substantially similar and / or identical to the Figure 1 semiconductor chip 100. Optionally or additionally, the second semiconductor chip 100-2 may be stacked on the first semiconductor chip 100-1 through an adhesive layer 170-2.

[0105] Each of the first chip stack structure CSS-1 and the second chip stack structure CSS-2 may be substantially similar and / or identical to the Figure 5A chip stack structure CSS. Thus, the first chip stack structure CSS-1 may include a lower memory chip LMC-1 and an upper memory chip UMC-1, and the second chip stack structure CSS-2 may include a lower memory chip LMC-2 and an upper memory chip UMC-2. Optionally or additionally, the second chip stack structure CSS-2 may be stacked on the first chip stack structure CSS-1 through an adhesive layer 450 to form an overall chip stack structure CSSa together with the first chip stack structure CSS-1.

[0106] The connection relationship between the first semiconductor chip 100-1 and the second semiconductor chip 100-2, the memory chip 400 of the first chip stack structure CSS-1 and the second chip stack structure CSS-2, and the package substrate 200 through the wire 300e can be described as follows.

[0107] The connection relationship between the second signal pads 120S2R and 120S2L of the first chip pad 120-1 of the first semiconductor chip 100-1, the third chip pad 140-1, and the first chip stack structure CSS-1 through the wire 300e can be substantially similar and / or the same as Figure 5B the connection relationship in the semiconductor package 1000a of Figure 5B . The first substrate pad 210-1, the second substrate pad 220-1, the third substrate pad 230-1, the first wire 310-1, the second wire 320a-1, and the third wire 330-1 can respectively correspond to

[0108] the first substrate pad 210, the second substrate pad 220, the third substrate pad 230, the first wire 310, the second wire 320a, and the third wire 330 in the semiconductor package 1000a of Figure 5A . Since the second semiconductor chip 100-2 is stacked on the first semiconductor chip 100-1 through the adhesive layer 170-2, at least a part of the connection of the first wire 310-1 to the first semiconductor chip 100-1 can be covered by the adhesive layer 170-2. Figure 5A the first substrate pad 210, the second substrate pad 220, the first wire 310, the second wire 320, and the third wire 330 in the semiconductor package 1000 of

[0109] In the semiconductor package 1000e of the present disclosure, the first signal pad 120S1 of the first chip pad 120-1 of the first semiconductor chip 100-1 can be used as an upper channel pad, and the second chip pad 130-2 of the second semiconductor chip 100-2 can be used as an upper channel pad. Optionally or additionally, the first signal pad 120S1 of the first semiconductor chip 100-1 can be connected to the chip pad 420 of the upper memory chip UMC-1 of the first chip stack structure CSS-1 through the first wire 310-1, the first substrate pad 210-1, the third substrate pad 230-1, and the second wire 320a-1, and the second chip pad 130-2 of the second semiconductor chip 100-2 can be connected to the chip pad 420 of the upper memory chip UMC-2 of the second chip stack structure CSS-2 through the second wire 320-2 to exchange signals with the upper memory chips UMC1 and UMC2.

[0110] When the first signal pad 120S1 of the first chip pad 120-1 is used as the upper channel pad in the first semiconductor chip 100-1, the second chip pad 130-1 may not be used. That is, the wire may not be connected to the second chip pad 130-1. According to Figures 3A to 4C various wiring connection structures, the second chip pad 130-1 can be deactivated or can be maintained in an enabled state.

[0111] In the case of the second semiconductor chip 100-2, since the second chip pad 130-2 is used as the upper channel pad, the first signal pad 120S1 of the first chip pad 120-2 may not be used. That is, the wire may not be connected to the first signal pad 120S1 of the first chip pad 120-2. According to Figures 3A to 4C various wiring connection structures, the first signal pad 120S1 of the first chip pad 120-2 can be deactivated or can be maintained in an enabled state.

[0112] Figure 8 is a cross-sectional view of a semiconductor package including a Figure 1 semiconductor chip according to an embodiment. Together with Figure 1 described. Figure 8 For the sake of brevity, the repeated description of the elements described above with reference to Figures 1 to 7B can be omitted.

[0113] Referring to Figure 8 and similar to the semiconductor package 1000d or 1000e of Figure 7A or Figure 7B , the semiconductor package 1000f of the present disclosure can include two semiconductor chips 100-1 and 100-2 and two chip stack structures CSS-1 and CSS-2. However, the arrangement structure on the package substrate 200 can be different from that of Figure 7A or Figure 7Bsemiconductor packages 1000d or 1000e. That is, the semiconductor package 1000f of the present disclosure may include a first semiconductor chip 100-1, a second semiconductor chip 100-2, a package substrate 200, a wire 300f, a first chip stack structure CSS-1, a second chip stack structure CSS-2, a sealing member 500, and external connection terminals 600. The package substrate 200, the sealing member 500, and the external connection terminals 600 may include Figure 5A those in the semiconductor package 1000 and / or may be similar in many aspects to Figure 5A those in the semiconductor package 1000.

[0114] Each of the first semiconductor chip 100-1 and the second semiconductor chip 100-2 may have a dual chip pad structure and may be substantially similar and / or identical to Figure 1 the semiconductor chip 100. The second semiconductor chip 100-2 may be spaced apart from the first semiconductor chip 100-1 in the x direction and may be stacked on the package substrate 200 through an adhesive layer 170.

[0115] Each of the first chip stack structure CSS-1 and the second chip stack structure CSS-2 may be substantially similar and / or identical to Figure 5A the chip stack structure CSS. Thus, the first chip stack structure CSS-1 may include a lower memory chip LMC-1 and an upper memory chip UMC-1, and the second chip stack structure CSS-2 may include a lower memory chip LMC-2 and an upper memory chip UMC-2. The second stack structure CSS-2 may be stacked on the first chip stack structure CSS-1 through an adhesive layer 450 to form an overall chip stack structure CSSb together with the first chip stack structure CSS-1. However, the overall chip stack structure CSSb may be different from Figure 7A or Figure 7B the overall chip stack structure CSSa of the semiconductor package 1000d or 1000e.

[0116] That is, the first chip stack structure CSS-1 may be substantially similar and / or identical to Figure 7A or Figure 7B the first chip stack structure CSS-1 of the semiconductor package 1000d or 1000e. However, the first chip stack structure CSS-1 may not be stacked on the package substrate 200, but may be stacked on the first semiconductor chip 100-1 and the second semiconductor chip 100-2 through an adhesive layer 450. The second chip stack structure CSS-2 may be in the same direction as Figure 7A or Figure 7BThe second chip stack structure CSS-2 of the semiconductor package 1000d or 1000e has a stepped structure in the opposite direction with a stepped structure. That is, the second chip stack structure CSS-2 may have a stepped structure in which the position of the memory chip 400 is offset upward and offset to the left in the x direction. As used herein, a structure that stacks memory chips using two or more semiconductor chips as supports may be referred to as a dolmen structure. Therefore, in the semiconductor package 1000f of the present disclosure, the first chip stack structure CSS-1 or the overall chip stack structure CSSb may have a dolmen structure.

[0117] The connection relationship between the first semiconductor chip 100-1 and the second semiconductor chip 100-2, the memory chip 400 of the first chip stack structure CSS-1 and the second chip stack structure CSS-2, and the package substrate 200 through the wire 300f can be described as follows.

[0118] The connection relationship between the second signal pads 120S2R and 120S2L and the third chip pad 140-1 of the first chip pad 120-1 of the first semiconductor chip 100-1 and the first chip stack structure CSS-1 through the wire 300f can be Figure 5B substantially similar and / or the same as the connection relationship in the semiconductor package 1000a of Figure 5B The first substrate pad 210-1, the second substrate pad 220-1, the third substrate pad 230-1, the first wire 310-1, the second wire 320a-1, and the third wire 330-1 can respectively correspond to Figure 5B the first substrate pad 210, the second substrate pad 220, the third substrate pad 230, the first wire 310, the second wire 320a, and the third wire 330 in the semiconductor package 1000a of

[0119] However, in the semiconductor package 1000a of Figure 5BThe connection relationships in the semiconductor package 1000a are basically similar and / or the same. The first substrate pad 210-2, the second substrate pad 220-2, the third substrate pad 230-2, the first wire 310-2, the second wire 320a-2, and the third wire 330-2 may respectively correspond to Figure 5B the first substrate pad 210, the second substrate pad 220, the third substrate pad 230, the first wire 310, the second wire 320a, and the third wire 330 in the semiconductor package 1000a. However, in the semiconductor package 1000f of the present disclosure, since the second semiconductor chip 100-2 is located below the second chip stack structure CSS-2 and the second chip stack structure CSS-2 has a stepped structure toward the left side, the second wire 320a-2 and the third wire 330-2 may be located on the right side of the second chip stack structure CSS-2. Optionally or additionally, in the x direction, the second substrate pad 220-2 and the third substrate pad 230-2 may be located on the right side of the second chip stack structure CSS-2, and the first substrate pad 210-2 may be located on the left side of the second substrate pad 220-2 and the third substrate pad 230-2.

[0120] In the semiconductor package 1000f of the present disclosure, the first signal pads 120S1 of the first chip pads 120-1 of the first semiconductor chip 100-1 and the first signal pads 120S1 of the first chip pads 120-2 of the second semiconductor chip 100-2 may be upper channel pads, and may be connected to the chip pads 420 of the upper memory chips UMC-1 and UMC-2 of the first chip stack structure CSS-1 and the second chip stack structure CSS-2 through the first wires 310-1 and 310-2, the first substrate pads 210-1 and 210-2, the third substrate pads 230-1 and 230-2, and the second wires 320a-1 and 320a-2 to exchange signals with the upper memory chips UMC1 and UMC2.

[0121] When the first signal pads 120S1 of the first chip pads 120-1 and 120-2 of the first semiconductor chip 100-1 and the second semiconductor chip 100-2 are used as upper channel pads, the second chip pads 130-1 and 130-2 may not be used. That is, the wires may not be connected to the second chip pads 130-1 and 130-2. According to Figures 3A to 4C various wiring connection structures, the second chip pads 130-1 and 130-2 may be deactivated or may be maintained in an enabled state.

[0122] Figure 9A and Figure 9B are cross-sectional views showing a semiconductor package including a Figure 1 semiconductor chip according to an embodiment. It can be described together with Figure 1 , Figure 7A and Figure 7B ​Figure 9A and Figure 9B For the sake of brevity, the repeated description of the components described above with reference to Figures 1 to 8 may be omitted. In Figure 9A and Figure 9B , names ending with "-1" and "-2" may represent components, wires, pads, etc. located in the left half, and names ending with "-3" and "-4" may represent components, wires, pads, etc. located in the right half.

[0123] With reference to Figure 9A , the semiconductor package 1000g of the present disclosure may have a structure in which two Figure 7A semiconductor packages 1000d are arranged along the x-direction. That is, the semiconductor package 1000g of the present disclosure may include semiconductor chips (e.g., first semiconductor chip 100-1, second semiconductor chip 100-2, third semiconductor chip 100-3, and fourth semiconductor chip 100-4), package substrate 200, wire 300d, chip stack structure (e.g., first chip stack structure CSS-1, second chip stack structure CSS-2, third chip stack structure CSS-3, and fourth chip stack structure CSS-4), sealing member 500, and external connection terminals 600. In one embodiment, the second semiconductor chip 100-2 may be stacked on the first semiconductor chip 100-1 through an adhesive layer 170-2, and the fourth semiconductor chip 100-4 may be stacked on the third semiconductor chip 100-3 through an adhesive layer 170-4. The package substrate 200, sealing member 500, and external connection terminals 600 may include Figure 5A those in the semiconductor package 1000 of Figure 5A and / or may be similar in many aspects to those in the semiconductor package 1000 of

[0124] The left half of the first semiconductor chip 100-1 and the second semiconductor chip 100-2, the package substrate 200 and the wire 300d, the first chip stack structure CSS-1 and the second chip stack structure CSS-2, and the left half of the sealing member 500 and the external connection terminals 600 may be substantially similar and / or identical to those in the semiconductor package 1000d of Figure 7A . Optionally or additionally, when rotated 180° about the z-axis, the third semiconductor chip 100-3 and the fourth semiconductor chip 100-4, the right half of the package substrate 200 and the wire 300d, the third chip stack structure CSS-3 and the fourth chip stack structure CSS-4, and the right half of the sealing member 500 and the external connection terminals 600 may be substantially similar and / or identical to those in the semiconductor package 1000d of Figure 7A .

[0125] Each of the first semiconductor chip 100-1 to the fourth semiconductor chip 100-4 may have a dual chip pad structure and may be substantially similar and / or identical to Figure 1 the semiconductor chip 100. Referring to Figure 9A , the stacked structure of the third semiconductor chip 100-3 and the fourth semiconductor chip 100-4 may be rotated 180° about the z-axis relative to the stacked structure of the first semiconductor chip 100-1 and the second semiconductor chip 100-2 and may be located on the package substrate 200. The memory chips 400 of the third chip stacked structure CSS-3 and the fourth chip stacked structure CSS-4 may be rotated 180° about the z-axis relative to the memory chips 400 of the first chip stacked structure CSS-1 and the second chip stacked structure CSS-2 and may be stacked and located on the package substrate 200.

[0126] Referring to Figure 9B , the semiconductor package 1000h of the present disclosure may have a structure in which two Figure 7B of the semiconductor packages 1000e may be arranged along the x-direction. That is, the semiconductor package 1000h of the present disclosure may include the first semiconductor chip 100-1 to the fourth semiconductor chip 100-4, the package substrate 200, the wire 300e, the first chip stacked structure CSS-1 to the fourth chip stacked structure CSS-4, the sealing member 500, and the external connection terminal 600. The package substrate 200, the sealing member 500, and the external connection terminal 600 may include Figure 5A those in the semiconductor package 1000 and / or may be similar in many aspects to Figure 5A those in the semiconductor package 1000.

[0127] The left halves of the first semiconductor chip 100-1 and the second semiconductor chip 100-2, the package substrate 200 and the wire 300e, the first chip stacked structure CSS-1 and the second chip stacked structure CSS-2, and the sealing member 500 and the external connection terminal 600 may be substantially similar and / or identical to Figure 7B those in the semiconductor package 1000e. Optionally or additionally, when rotated 180° about the z-axis, the right halves of the third semiconductor chip 100-3 and the fourth semiconductor chip 100-4, the package substrate 200 and the wire 300e, the third chip stacked structure CSS-3 and the fourth chip stacked structure CSS-4, and the sealing member 500 and the external connection terminal 600 may be substantially similar and / or identical to Figure 7B those in the semiconductor package 1000e.

[0128] Each of the first semiconductor chip 100-1 to the fourth semiconductor chip 100-4 may have a dual chip pad structure and may be substantially similar and / or identical to Figure 1The semiconductor chips 100 are substantially similar and / or identical. Refer to Figure 9B , the stacked structure of the third semiconductor chip 100-3 and the fourth semiconductor chip 100-4 can be rotated 180° about the z-axis relative to the stacked structure of the first semiconductor chip 100-1 and the second semiconductor chip 100-2, and can be located on the package substrate 200. Optionally or additionally, the memory chips 400 of the third chip stack structure CSS-3 and the fourth chip stack structure CSS-4 can be rotated 180° about the z-axis relative to the memory chips 400 of the first chip stack structure CSS-1 and the second chip stack structure CSS-2, and can be stacked and located on the package substrate 200.

[0129] Although the present disclosure has been specifically shown and described with reference to embodiments of the present disclosure, it will be understood that various changes in form and detail may be made therein without departing from the spirit and scope of the appended claims.

Claims

1. A semiconductor chip having a double chip pad structure, the semiconductor chip comprising: Chip body; A first chip pad is arranged on a first edge of the top surface of the chip body and a second edge of the top surface of the chip body, the second edge of the top surface is opposite to the first edge of the top surface in a first direction, and the first chip pad is arranged along a second direction perpendicular to the first direction; as well as a second chip pad disposed along the second direction at a central portion of the top surface in the first direction between the first edge of the top surface of the chip body and the second edge of the top surface of the chip body, The first chip pad includes a first signal pad combined with the second chip pad.

2. The semiconductor chip according to claim 1, wherein: The second chip pad is combined with the first signal pad through at least one of a redistribution layer of the chip body and an internal wiring of a multi-wiring layer of the chip body.

3. The semiconductor chip according to claim 1, wherein: The semiconductor chip is included in a semiconductor package, and The second chip pad and the first signal pad are selectively combined with the memory chip of the semiconductor package.

4. The semiconductor chip according to claim 3, wherein: At least one of the second chip pad and the first signal pad that is not combined with the memory chip of the semiconductor package is configured to be deactivated by the switching element.

5. The semiconductor chip according to any one of claims 1 to 4, wherein: The semiconductor chip includes a buffer chip disposed on a package substrate of a semiconductor package, The semiconductor package includes a chip stacking structure, which is disposed adjacent to the semiconductor chip on a package substrate and includes a plurality of memory chips stacked therein. Wherein, the first chip pad also includes a second signal pad, wherein the second chip pad and the first signal pad are selectively combined with an upper memory chip disposed at a first position in the chip stacking structure among the plurality of memory chips, wherein the second signal pad is combined with a lower memory chip disposed at a second position in the chip stacking structure among the plurality of memory chips, and Among them, the second position is lower than the first position.

6. A semiconductor package, comprising: A package substrate; A first semiconductor chip is disposed on a package substrate, has a first double chip pad structure, and includes a chip body, a first chip pad and a second chip pad disposed on a top surface of the chip body; as well as a first chip stack structure disposed adjacent to the first semiconductor chip on the package substrate in a first direction and including a first plurality of memory chips stacked therein, The first chip pad is arranged on a first edge of the top surface of the chip body and a second edge of the top surface of the chip body, the second edge of the top surface is opposite to the first edge of the top surface in a first direction, and the first chip pad is arranged along a second direction perpendicular to the first direction, wherein the second chip pad is disposed along the second direction at a central portion of the top surface in the first direction between a first edge of the top surface of the chip body and a second edge of the top surface of the chip body, and The first chip pad includes a first signal pad combined with the second chip pad.

7. The semiconductor package according to claim 6, wherein: The first chip pad also includes a second signal pad, wherein the second chip pad and the first signal pad are selectively combined with a first memory chip disposed at a first position in the first chip stacking structure among the first plurality of memory chips, wherein the second signal pad is combined with a second memory chip disposed at a second position in the first chip stacking structure among the first plurality of memory chips, and Among them, the second position is lower than the first position.

8. The semiconductor package according to claim 6, further comprising: a second chip stack structure adjacent to the first chip stack structure in the first direction on the package substrate and including a second plurality of memory chips stacked therein; as well as a second semiconductor chip disposed adjacent to the second chip stack structure on the package substrate in the first direction and having a second double chip pad structure identical to the first double chip pad structure of the first semiconductor chip, wherein the first semiconductor chip is combined with the first plurality of memory chips of the first chip stack structure, and The second semiconductor chip is combined with the second plurality of memory chips of the second chip stack structure.

9. The semiconductor package according to claim 6, further comprising: a second semiconductor chip stacked on the first semiconductor chip and having a second double chip pad structure that is the same as the first double chip pad structure of the first semiconductor chip, The first chip stacking structure includes a lower chip stacking structure and an upper chip stacking structure. wherein the first semiconductor chip is combined with the lower memory chip of the lower chip stacking structure, and The second semiconductor chip is combined with the upper memory chip of the upper chip stacking structure.

10. The semiconductor package according to claim 9, wherein: The first chip pad of the first semiconductor chip further includes a second signal pad, The second semiconductor chip includes a first chip pad and a second chip pad, and the first chip pad of the second semiconductor chip includes a first signal pad and a second signal pad. wherein the first signal pad of the first semiconductor chip is combined with the upper memory chip at a first position in the lower chip stacking structure, wherein the second signal pad of the first semiconductor chip is combined with the lower memory chip at the second position in the lower chip stacking structure, Among them, the second position is lower than the first position, wherein the second chip pad and the first signal pad of the second semiconductor chip are selectively combined with the upper memory chip at the third position in the upper chip stacking structure, wherein the second signal pad of the second semiconductor chip is combined with the lower memory chip at the fourth position in the upper chip stacking structure, and Among them, the fourth position is lower than the third position.

11. The semiconductor package according to claim 9, wherein: The first semiconductor chip is connected to the first substrate pad of the package substrate through the first wire. The lower memory chip of the lower chip stacking structure is combined with the second substrate pad of the package substrate through a second wire. The second semiconductor chip is combined with the third substrate pad of the package substrate through a third wire. The upper memory chip of the upper chip stacking structure is combined with the fourth substrate pad of the package substrate through a fourth wire. The first base pad is combined with the second base pad through the base wiring of the package base. The third substrate pad is combined with the fourth substrate pad through the substrate wiring of the package substrate, and At least a portion of the first conductive line is covered by the adhesive layer between the first semiconductor chip and the second semiconductor chip.

12. The semiconductor package according to claim 6, further comprising: a second semiconductor chip stacked on the first semiconductor chip and having a second double chip pad structure that is the same as the first double chip pad structure of the first semiconductor chip; a second chip stack structure on the package substrate adjacent to the first chip stack structure and including a second plurality of memory chips stacked therein; a third semiconductor chip on the package substrate adjacent to the second chip stack structure in the first direction and having a third double chip pad structure identical to the first double chip pad structure of the first semiconductor chip; as well as a fourth semiconductor chip stacked on the third semiconductor chip and having a fourth double chip pad structure that is the same as the first double chip pad structure of the first semiconductor chip, wherein the first semiconductor chip and the second semiconductor chip are combined with the first plurality of memory chips of the first chip stack structure, and The third semiconductor chip and the fourth semiconductor chip are combined with the second plurality of memory chips of the second chip stack structure.

13. The semiconductor package according to claim 12, wherein: Each of the first chip stacking structure and the second chip stacking structure has a lower chip stacking structure and an upper chip stacking structure, wherein the first semiconductor chip is combined with a first lower memory chip of a lower chip stacking structure of the first chip stacking structure, wherein the second semiconductor chip is combined with the first upper memory chip of the upper chip stacking structure of the first chip stacking structure, wherein the third semiconductor chip is combined with the second lower memory chip of the lower chip stacking structure of the second chip stacking structure; and The fourth semiconductor chip is combined with the second upper memory chip of the upper chip stack structure of the second chip stack structure.

14. The semiconductor package according to any one of claims 6 to 13, wherein: The first semiconductor chip includes a buffer chip, and Wherein, the first plurality of memory chips include NAND flash memory chips.

15. The semiconductor package according to any one of claims 6 to 13, wherein: A second chip pad and a first signal pad are selectively combined with the first plurality of memory chips of the first chip stack structure, and Wherein, at least one of the second chip pad and the first signal pad that is not combined with the first plurality of memory chips is configured to be disabled by a switch element.

16. A semiconductor package, comprising: A package substrate; A first semiconductor chip, on a package substrate, has a first double chip pad structure and includes a chip body, a first chip pad and a second chip pad disposed on a top surface of the chip body; a second semiconductor chip on the package substrate adjacent to the first semiconductor chip in the first direction and having a second double chip pad structure identical to the first double chip pad structure of the first semiconductor chip; as well as A chip stack structure is provided on the first semiconductor chip and the second semiconductor chip and includes a plurality of memory chips stacked therein, wherein a first chip pad of each of the first semiconductor chip and the second semiconductor chip is disposed on a first edge of a top surface of a chip body and a second edge of a top surface of the chip body, the second edge of the top surface is opposite to the first edge of the top surface in a first direction, and the first chip pad is disposed along a second direction perpendicular to the first direction, wherein the second chip pad of each of the first semiconductor chip and the second semiconductor chip is disposed along the second direction at a central portion of the top surface in the first direction between a first edge of the top surface of the chip body and a second edge of the top surface of the chip body, and The first chip pad of each of the first semiconductor chip and the second semiconductor chip includes a first signal pad combined with the second chip pad.

17. The semiconductor package according to claim 16, wherein: The chip stacking structure includes a lower chip stacking structure and an upper chip stacking structure. wherein the first semiconductor chip is combined with the lower memory chip of the lower chip stacking structure, and The second semiconductor chip is combined with the upper memory chip of the upper chip stacking structure.

18. The semiconductor package according to claim 17, wherein: The lower chip stacking structure has a stepped structure in which the positions of the memory chips in the lower chip stacking structure are shifted upward and shifted to the right in a first direction, and The upper chip stacking structure has a stepped structure in which the positions of the memory chips in the upper chip stacking structure are shifted upward and shifted to the left in the first direction.

19. The semiconductor package according to claim 17, wherein: The first chip pad of each of the first semiconductor chip and the second semiconductor chip further includes a second signal pad, wherein the first signal pad of the first semiconductor chip is combined with the upper memory chip at a first position in the lower chip stacking structure, wherein the second signal pad of the first semiconductor chip is combined with the lower memory chip at the second position in the lower chip stacking structure, Among them, the second position is lower than the first position, wherein the first signal pad of the second semiconductor chip is combined with the upper memory chip at the third position in the upper chip stacking structure, wherein the second signal pad of the second semiconductor chip is combined with the lower memory chip at the fourth position in the upper chip stacking structure, and Among them, the fourth position is lower than the third position.

20. The semiconductor package according to claim 17, wherein The first semiconductor chip and the second semiconductor chip are spaced apart from each other in a first direction, The first semiconductor chip is combined with a first substrate pad of the package substrate through a first wire, and the first substrate pad of the package substrate is on a first side and a second side of the first semiconductor chip in a first direction. The lower memory chip of the lower chip stacking structure is combined with the second substrate pad of the package substrate through a second wire, and the second substrate pad of the package substrate is on the left side in the first direction of the first semiconductor chip. The second semiconductor chip is combined with the third substrate pad of the package substrate through the third wire, and the third substrate pad of the package substrate is on the third side and the fourth side of the second semiconductor chip in the first direction. The upper memory chip of the upper chip stacking structure is combined with the fourth substrate pad of the package substrate through a fourth wire, and the fourth substrate pad of the package substrate is on the right side of the second semiconductor chip in the first direction, and At least a portion of each of the first conductive line and the third conductive line is covered by the adhesive layer between the first semiconductor chip and the lowermost memory chip and between the second semiconductor chip and the lowermost memory chip.

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