Semiconductor device including circular member and method of manufacturing same

Abstract

The invention relates to a semiconductor device including a circular member and a method of manufacturing the same. A semiconductor device includes an electrically conductive carrier and a semiconductor chip disposed on a first portion of the carrier. The semiconductor device also includes a dielectric material disposed between the first portion of the carrier and the semiconductor chip, where the dielectric material galvanically isolates the first portion of the carrier from the semiconductor chip. At least one of the first portion of the carrier or the semiconductor chip includes at least one of a rounded corner or a rounded edge.

Description

Technical Field

[0001] The present disclosure relates to a semiconductor device including a circular component and a method for manufacturing such a semiconductor device. Background Art

[0002] In a semiconductor device, during device operation, a high voltage difference may occur between various device components. For example, in a current sensor device between a current rail and a sensor chip arranged above the current rail, an increased potential difference may occur. Depending on the material properties and relative positioning of the device components, the increased voltage difference may cause high electric field stress in certain spatial regions of the device. High electric field stress can cause electrical aging of the device components and degradation of the device, which in the worst case can lead to device failure. Manufacturers and developers of semiconductor devices have been striving to improve their products. In view of the above, there may be a particular interest in extending the durability of semiconductor devices and ensuring their continuous safe operation. Summary of the Invention

[0003] One aspect of the present disclosure relates to a semiconductor device. The semiconductor device includes a conductive carrier and a semiconductor chip arranged on a first portion of the carrier. The semiconductor device further includes a dielectric material arranged between the first portion of the carrier and the semiconductor chip, wherein the dielectric material electrically isolates the first portion of the carrier and the semiconductor chip. At least one of the first portion of the carrier or the semiconductor chip includes at least one of a rounded corner or a rounded edge.

[0004] Another aspect of the present disclosure relates to a method for manufacturing a semiconductor device. The method includes the action of forming at least one of a rounded corner or a rounded edge of at least one of the first portion of the conductive carrier or the semiconductor chip. The method further includes the action of arranging a dielectric material on the first portion of the carrier. The method further includes the action of arranging a semiconductor chip on the dielectric material, wherein the dielectric material electrically isolates the first portion of the carrier and the semiconductor chip. Brief Description of the Drawings

[0005] The device and method according to the present disclosure are described in more detail below based on the figures. Similar reference numerals may represent corresponding similar parts. The technical features of the various illustrated examples may be combined as long as they are not mutually exclusive, and / or may be selectively omitted if not described as being necessary.

[0006] Figure 1 A cross-sectional side view of a semiconductor device 100 according to the present disclosure is schematically illustrated.

[0007] Figure 2 A cross-sectional side view of a semiconductor device 200 according to the present disclosure is schematically illustrated.

[0008] Figure 3 A flowchart illustrating a method for manufacturing a semiconductor device according to the present disclosure is shown.

[0009] Figures 4A to 4F A method for manufacturing a semiconductor device according to the present disclosure is schematically illustrated.

[0010] Figures 5A to 5C A method for manufacturing a semiconductor device according to the present disclosure is schematically illustrated.

[0011] Figures 6A to 6C A method for manufacturing a semiconductor device according to the present disclosure is schematically illustrated. Detailed Description

[0012] Figure 1 The semiconductor device 100 may include a conductive carrier 2 having a first portion 4 and a second portion 6. A semiconductor chip 8 may be disposed on the first portion 4 of the carrier 2. The semiconductor device 100 may further include a dielectric material 10 disposed between the first portion 4 of the carrier 2 and the semiconductor chip 8. The dielectric material 10 may be configured to electrically isolate the first portion 4 of the carrier 2 and the semiconductor chip 8. The semiconductor chip 8 may be electrically connected to the second portion 6 of the carrier 2 via an electrical connection element 12. The components of the semiconductor device 100 may be at least partially encapsulated in an encapsulation material 14. At least one of the first portion 4 of the carrier 2 or the semiconductor chip 8 may include at least one of a rounded corner or a rounded edge 16.

[0013] In the example shown, the conductive carrier 2 may be a lead frame. The lead frame may be made of a metal and / or a metal alloy, particularly at least one of copper, copper alloy, nickel, iron-nickel, aluminum, aluminum alloy, steel, stainless steel, etc. During operation of the semiconductor device 100, the first portion 4 of the carrier 2 may be a current-carrying portion. Specifically, the first portion 4 of the lead frame may be a current rail configured to carry the current to be measured by the semiconductor chip 8. Hereinafter, the terms “first portion”, “current-carrying portion” and “current rail” may be used interchangeably. Specifically, the current rail 4 may be integrally formed. The second portion 6 of the lead frame 2 may include one or more leads (or lead fingers or pins). In Figure 1 a cross-sectional side view, only one lead 6 is shown due to the selected perspective. For example, any number of additional leads 6 may be disposed behind the shown lead 6.

[0014] In one example, the semiconductor chip 8 can be a sensor chip configured to sense a magnetic field generated by a current flowing through the current rail 4. Based on the sensed magnetic field (or the sensed magnetic flux density of the induced magnetic field), the intensity of the current can be determined. Specifically, the induced magnetic field can be detected without physical contact (i.e., galvanic isolation) between the sensor chip 8 and the current rail 4. In this case, when viewed in the z-direction, the sensor chip 8 (or more specifically, at least one sensor element of the sensor chip 8) can at least partially overlap with the current rail 4. The physical signal sensed by the sensor chip 8 can be converted into an electrical signal and forwarded to additional components (not shown) via the electrical connection element 12 and the lead 4 for further processing or evaluation. In the example shown, the electrical connection element 12 can include wires. In another example, the electrical connection element 12 can include clips, ribbons, etc.

[0015] The sensor chip 8 can include one or more sensor elements (not shown). In one example, the sensor chip 8 can be a differential magnetic field sensor chip including two sensor elements. For example, the sensor elements of the sensor chip 8 can be Hall sensor elements, magnetoresistive sensor elements, vertical Hall sensor elements, or fluxgate sensor elements. The magnetoresistive xMR sensor elements can be AMR (anisotropic magnetoresistive) sensor elements, GMR (giant magnetoresistive) sensor elements, or TMR (tunnel magnetoresistive) sensor elements. In one example, the (one or more) sensor elements can be arranged on the top surface of the sensor chip 8 facing away from the current rail 4. In another example, the (one or more) sensor elements can be arranged on the bottom surface of the sensor chip 8 facing the current rail 4.

[0016] In the example shown, the dielectric material 10 can include an exemplary number of two stacked dielectric elements (or dielectric layers) 10A and 10B. For example, the dielectric elements 10A and 10B can be mechanically connected to form an integral dielectric part. The upper dielectric element 10A can at least partially overhang the lower dielectric element 10B so that a base for mounting the semiconductor chip 8 can be provided. When measured in the z-direction, the dielectric elements 10A and 10B can have similar thicknesses or different thicknesses. In the example shown, each of the dielectric elements 10A and 10B can have a thickness within an exemplary and non-limiting range of about 50 μm to about 150 μm, typically about 100 μm.

[0017] When viewed in the z - direction, the footprint of the lower dielectric element 10B can be (especially completely) arranged within the footprint of the upper dielectric element 10A. For example, the footprints of the dielectric elements 10A and 10B can be circular, oval, elliptical, square, rectangular, polygonal, etc. The dielectric elements 10A and 10B can be made of the same material or different materials. Each of the dielectric elements 10A and 10B can include one or more of the following materials: ceramics, glass, silicon - based materials, polymer - based materials, etc. In a specific example, one or both of the dielectric elements 10A and 10B can correspond to a chip made of a dielectric material.

[0018] The encapsulation material 14 can at least partially encapsulate one or more components of the semiconductor device 100. Specifically, the current rail 4 and the semiconductor chip 8 can be at least partially embedded in the encapsulation material 14. The encapsulation material 14 can form a housing (or package) for the encapsulated components to protect them from external influences such as, for example, moisture or mechanical shock. The semiconductor device 100 can also be referred to as a semiconductor package. The leads 6 can at least partially protrude from the encapsulation material 14 such that the semiconductor chip 8 can be electrically accessed from outside the encapsulation material 14. In a similar manner, the current rail 4 can at least partially protrude from the encapsulation material 14 to provide inputs and outputs for measuring current.

[0019] The encapsulation material 14 can include or can be made of at least one of epoxy resins, filled epoxies, glass - fiber - filled epoxies, imides, thermoplastics, thermosetting polymers, polymer blends, laminates, etc. Various techniques can be used to encapsulate the components of the semiconductor device 100 with the encapsulation material 14, such as at least one of compression molding, injection molding, powder molding, liquid molding, mapping molding, lamination, etc.

[0020] During operation of the semiconductor device 100, the potential of the current rail 4 can be different from the potential of the semiconductor chip 8. For example, the current rail 4 can be in a high - voltage domain, while the semiconductor chip 8 (and the leads 6 electrically connected thereto) can be in a low - voltage domain. The low - voltage domain can be associated with or can be specified by an exemplary value range of about 0V to about 20V. In this regard, a typical exemplary operating value of the low - voltage domain can be about 3.3V or about 5V. The high - voltage domain can be associated with or can be specified by an exemplary value range of about 50V to about 15000V. In this regard, typical exemplary operating values of the high - voltage domain can be about 600V or about 800V or about 1200V. In a non - limiting example, the potential of the semiconductor chip 8 can be about 0V, while the potential of the current rail 4 can be about 1000V.

[0021] Therefore, during operation of the semiconductor device 100, a large potential difference can occur between the current rail 4 and the semiconductor chip 8. These potential differences can reach values as high as 1000 V or greater. The electrical isolation between the current rail 4 and the semiconductor chip 8 can be provided by the dielectric material 10 disposed therebetween. In this case, a capacitor (or a parallel plate capacitor) can be formed, where each of the current rail 4 and the semiconductor chip 8 can form an electrode of the capacitor, and the dielectric material 10 can form a solid insulation between these electrodes.

[0022] Since the dielectric material 10 can have electrical isolation capabilities, high electric field intensities (or high non-uniform electric field peaks) can occur in certain spatial regions of the semiconductor device 100. Materials located in these regions can be exposed to high electrical stress, which can become particularly problematic for materials with limited insulation capabilities. High electrical stress can cause the materials to age prematurely. During the aging process of the semiconductor device 100, electrical treeing can occur particularly. Generally, electrical treeing can occur and propagate when the dielectric material is subjected to high and divergent electric field stress over a long period of time. Electrical treeing can start from the corners and / or edges of the semiconductor chip and / or lead frame of the corresponding semiconductor device. It may ultimately lead to the formation of one or more unwanted conductive paths between the semiconductor chip and the lead frame, thus causing device failure in the worst case.

[0023] Specifically, in a semiconductor device, high electric field intensities (and thus particularly electrical treeing) can occur at locations where the current rail and / or the semiconductor chip have sharp edges and / or sharp corners. In Figure 1 the illustrated example, a first exemplary region 18A where high electric field intensity can potentially occur can be located at the edge and / or corner 16A of the current rail 4. In the first region 18A of the illustrated example, a first edge of the current rail 4 can extend in the x direction, a second edge of the current rail 4 can extend in the y direction, and a third edge of the current rail 4 can extend in the z direction. The three edges of the current rail 4 can meet at the corner of the current rail 4.

[0024] In the semiconductor device 100, the current rail 4 can include at least one of a rounded corner or a rounded edge 16A in the first region 18A. In this case, at least one of the first edge, the second edge, the third edge, or the corner formed by these three edges can be rounded. Due to the rounded shape of the corner and / or edge, high electric field peaks can be avoided, and a uniform electric field distribution can be provided in the first region 18A. In contrast, conventional semiconductor devices including current rails with sharp edges and / or corners may not be able to achieve such a uniform electric field distribution.

[0025] In the illustrated example, at least one rounded corner or rounded edge 16A of the current rail 4 can be disposed on the top surface of the current rail 4 facing the semiconductor chip 8. The rounded corner and / or rounded edge 16A can be adjacent to the encapsulation material 14. Specifically, the rounded corner and / or rounded edge 16A and the encapsulation material 14 can have a common interface. The rounded corner and / or rounded edge 16A and the encapsulation material 14 can be in direct physical contact. Due to the rounded shape of the corner and / or edge 16A, electrical treeing into the encapsulation material 14 can be avoided.

[0026] A second exemplary region 18B where a high electric field intensity can potentially occur can be located at the edge and / or corner 16B of the semiconductor chip 8. In the second region 18B of the illustrated example, a first edge of the semiconductor chip 8 can extend in the x direction, a second edge of the semiconductor chip 8 can extend in the y direction, and a third edge of the semiconductor chip 8 can extend in the z direction. The three edges of the semiconductor chip 8 can meet at the corner of the semiconductor chip 8.

[0027] In the semiconductor device 100, the semiconductor chip 8 can include at least one of a rounded corner or a rounded edge 16B in the second region 18B. In this regard, at least one of the first edge, the second edge, the third edge, or the corner formed by the three edges can be rounded. In one example, the rounded corner and / or edge 16B can be disposed on the active surface of the semiconductor chip 8. In another example, the rounded corner and / or edge 16B can be disposed on a surface of the semiconductor chip 8 that is disposed opposite to the active surface. Due to the rounded shape of the corner and / or edge, high electric field peaks can be avoided, and a uniform electric field distribution can be provided in the first region 18B. In contrast, a conventional semiconductor device including a semiconductor chip having sharp edges and / or corners may not be able to achieve such a uniform electric field distribution.

[0028] In the illustrated example, the rounded corners and / or rounded edges 16B of the semiconductor chip 8 may be disposed on the bottom surface of the semiconductor chip 8 facing the current rail 4. The rounded corners and / or rounded edges 16B of the semiconductor chip 8 may be adjacent to the dielectric material 10. Specifically, the rounded corners and / or rounded edges 16B and the dielectric material 10 may have a common interface. The material of the rounded corners and / or rounded edges 16B and the dielectric material 10 may be in direct physical contact. Additionally, the rounded corners and / or rounded edges 16B of the semiconductor chip 8 may be adjacent to the encapsulation material 14. Specifically, the rounded corners and / or rounded edges 16B and the encapsulation material 14 may have a common interface. The material of the rounded corners and / or rounded edges 16B and the encapsulation material 14 may be in direct physical contact. Due to the rounded shape of the rounded corners and / or rounded edges 16B, electrical treeing into the dielectric material 10 and / or electrical treeing into the encapsulation material 14 can be avoided. Specifically, the formation of a conductive path between the semiconductor chip 8 and the current rail 4 can be avoided. For example, such a path may extend along the common interface between the dielectric material 10 and the encapsulation material 14.

[0029] A third exemplary region 18C where a high electric field strength may potentially occur may be located at another edge and / or corner 16C of the semiconductor chip 8. In the semiconductor device 100, the semiconductor chip 8 may include at least one of a rounded corner or a rounded edge 16C in the third region 18C. The rounded corner / edge 16C may be similar to the rounded corner / edge 16B so that the previous comments may hold.

[0030] Figure 2 The semiconductor device 200 may include Figure 1 Some or all of the features of the semiconductor device 100. Figure 2 Various dimensions (in μm) are shown for indicating the sizes of the device components. It should be noted that the shown dimensions are exemplary and in no way limiting. In other examples, the dimensions of similar components may vary by up to ±20% from the values given in Figure 2 What is provided.

[0031] The semiconductor device 200 may include similar components as described previously in connection with Figure 1 For simplicity, the leads 6 and the electrical connection elements 12 of the semiconductor device 200 are not shown. The semiconductor device 200 may include a first adhesive layer 20A configured to mechanically connect the semiconductor chip 8 and the dielectric material 10. Additionally, the semiconductor device 200 may include a second adhesive layer 20B configured to mechanically connect the dielectric material 10 and the current rail 4. It is worth noting that similar adhesive layers may be present in Figure 1For use in the foregoing examples. In a non-limiting example, at least one of the first adhesive layer 20A and the second adhesive layer 20B may include a die attach film (DAF).

[0032] In the example shown, the dielectric material 10 may extend beyond the profile of the current rail 4. In Figure 2 the exemplary side view, the right end of the dielectric material 10 may at least partially overhang the right end of the current rail 4. The current rail 4 may include at least one of a rounded corner or a rounded edge 16A in the first region 18A. The rounded corner and / or rounded edge 16A of the current rail 4 may be disposed on the top surface of the current rail 4 facing the semiconductor chip 8. Due to the rounded shape of the corner and / or edge 16A, dendrite formation in the dielectric material 10 and / or the encapsulation material 14, as discussed previously in connection with Figure 1 can be avoided.

[0033] For example, the current rail 4 may be stamped in a direction pointing away from the semiconductor chip 8. In the case shown, the current rail 4 may be stamped from top to bottom, i.e., in the negative z direction indicated by the arrow. Due to this stamping of the current rail 4, at least one rounded corner or rounded edge 16A may have been formed. Additionally, the stamping of the current rail 4 may produce burrs 22, which may be disposed at the edges and / or corners of the surface of the current rail 4 facing away from the semiconductor chip 8. A burr may be designated as a raised edge or a small piece of material that remains attached to the workpiece after a modification process such as stamping, for example.

[0034] In the example shown, the semiconductor chip 8 may include a rounded corner / edge 16B in the second region 18B and / or a rounded corner / edge in the third region 18C. The rounded corners / edges 16B, 16C and the associated regions 18B, 18C may be similar to the corresponding technical features described previously in connection with Figure 1 above.

[0035] In Figure 1 and Figure 2 examples, the concept of using rounded edges and / or rounded corners of device components to avoid high electric field peaks in associated spatial regions has been described for the case of a magnetic current sensor device including a current rail and a sensor chip. However, it should be noted that the concepts presented herein may also be applied to other semiconductor devices that may exhibit high potential differences during operation, such as gate drivers, isolation drivers, digital isolators, auxiliary power components, etc.

[0036] Figure 3 FIG. illustrates a flowchart of a method for manufacturing a semiconductor device according to the present disclosure. Figure 3The method is illustrated in a general manner to qualitatively specify aspects of the present disclosure. This method can be used to fabricate any of the semiconductor devices described previously and can thus be interpreted in conjunction with the previous figures. The method can be extended by any aspect described in conjunction with other examples discussed herein. In conjunction with Figures 4A to 6C Examples of more detailed methods for fabricating semiconductor devices in accordance with the present disclosure are shown and discussed.

[0037] In 24, at least one of a first portion of a conductive carrier or a rounded corner or rounded edge of a semiconductor chip can be formed. In 26, a dielectric material can be disposed on the first portion of the carrier. In 28, a semiconductor chip can be disposed on the dielectric material, wherein the dielectric material electrically isolates the first portion of the carrier and the semiconductor chip.

[0038] Figures 4A to 4F An exemplary method for fabricating one or more semiconductor devices in accordance with the present disclosure is illustrated. Figures 4A to 4F The method can be regarded as at least partially Figure 3 a more detailed version of the method. Specifically, the actions of Figures 4A to 4F can be applied to obtain a semiconductor chip including at least one of a rounded corner or a rounded edge.

[0039] In Figure 4A , a semiconductor wafer 30 can be disposed on a carrier 32. For example, the semiconductor wafer 30 can be made of silicon. In the example shown, the semiconductor wafer 30 and the carrier 32 can be mechanically connected to each other through an adhesive layer 34. In one example, the semiconductor wafer 30 can be laminated onto the carrier 32.

[0040] In Figure 4B , a photoresist 36 can be disposed on top of the top surface of the semiconductor wafer 30. The photoresist 36 can include (among other things) a resin. The photoresist 36 can be disposed substantially over the entire top surface of the semiconductor wafer 30. The thickness of the photoresist 36 can be substantially constant. In one example, the photoresist 36 can be spin-coated on the top surface of the semiconductor wafer 30.

[0041] In Figure 4C , the photoresist 36 can be structured. In this regard, the photoresist 36 can be (especially completely) removed at positions where the semiconductor wafer 30 is to be etched later. By removing the photoresist 36, the semiconductor wafer 30 can be exposed at these positions. In one example, the photoresist 36 can be structured based on suitable exposure and development.

[0042] In Figure 4DIn [the process], a dry etching operation (or a plasma etching operation) can be performed. Specifically, the exposed top surface of the semiconductor wafer 30 can be etched, where at least one of the rounded corners or rounded edges 16B, 16C can be formed on the top surface of the semiconductor wafer 30. The acceleration of the reactive ions toward the top surface of the photoresist 36 and the exposed top surface of the semiconductor wafer 30 is indicated by the arrows. During the dry etching operation, a groove can be formed on the exposed top surface of the semiconductor wafer 30. Specifically, the dry etching can be performed through the entire semiconductor wafer 30 until the top surface of the adhesive layer 34 can become exposed.

[0043] In Figure 4E [the process], the dry-etched semiconductor wafer 30 can be singulated, where multiple semiconductor chips 8 can be obtained. In the illustrated example, the semiconductor wafer 30 can be singulated using a saw blade 38 in a sawing operation. In one example, the effective surface of the obtained semiconductor chip 8 can face the carrier 32. Alternatively or additionally, the effective surface of the semiconductor chip 8 can face away from the carrier 32. In the illustrated example, each semiconductor chip 8 can include at least one of the rounded corners or rounded edges 16B and 16C. The dry etching can be performed on at least one side surface of the corresponding singulated semiconductor chip 8.

[0044] In Figure 4F [the process], the photoresist 36 can be removed. Additionally, the carrier 32 and the adhesive layer 34 (not shown) can be removed. For example, the obtained semiconductor chips 8 can be similar to the semiconductor chips 8 of Figure 1 and Figure 2 .

[0045] Figures 4A to 4F The method of Figures 4A to 4F can include additional operations that are not described for simplicity. Specifically, Figure 3 the method of

[0046] Figures 5A to 5C FIG. illustrates an exemplary method for manufacturing one or more semiconductor devices according to the present disclosure. Figures 5A to 5C The method of Figure 3 can be regarded as at least partially a more detailed version of the method of Figures 5A to 5C . Specifically, the operations of

[0047] In Figure 5AIn [description], the semiconductor wafer 30 can be disposed on the carrier 32. For example, the semiconductor wafer 30 can be made of silicon. In the illustrated example, the semiconductor wafer 30 and the carrier 32 can be mechanically connected to each other through the adhesive layer 34. In a non-limiting example, the semiconductor wafer 30 can be attached to the tape 32 using the glue 34. In a further operation, a chamfering cut operation can be performed. Specifically, the top surface of the semiconductor wafer 30 can be chamfered using the blade 40. The blade 40 can only partially penetrate the top surface of the semiconductor wafer 30. Here, at least one of the circular chamfers or circular edges 16B and 16C can be formed on the top surface of the semiconductor wafer 30.

[0048] In Figure 5B [description], the chamfered semiconductor wafer 30 can be singulated, and a plurality of semiconductor chips 8 can be obtained. In the illustrated example, the chamfered semiconductor wafer 30 can be singulated using a saw blade 38 in a sawing operation. The width of the saw blade 38 can be smaller than the width of the previously used blade 40.

[0049] Figure 5C The figure illustrates Figure 5B the arrangement after the sawing operation. Each obtained semiconductor chip 8 can include at least one of the circular corners or circular edges 16B and 16C.

[0050] Figures 5A to 5C The method of [description] can include additional operations not described for simplicity. In a further operation, the carrier 32 and the adhesive layer 34 can be removed. For example, the obtained semiconductor chips 8 can be similar to Figure 1 and Figure 2 the semiconductor chips 8 of [description]. Additionally, Figures 5A to 5C the method of [description] can be extended by Figure 3 the operations 26 and 28 of [description].

[0051] Figures 6A to 6C The figure illustrates an exemplary method for manufacturing one or more semiconductor devices according to the present disclosure. Figures 6A to 6C The method of [description] can be regarded as at least partially Figure 3 a more detailed version of the method of [description]. Specifically, the operations of Figures 6A to 6C [description] can be applied to obtain semiconductor chips including at least one of the circular corners or circular edges.

[0052] In Figure 6AIn this case, the semiconductor wafer can be arranged on the carrier 32. For example, the semiconductor wafer can be made of silicon. The semiconductor wafer and the carrier 32 can be mechanically connected to each other through an adhesive layer 34. In one example, the semiconductor wafer can be laminated onto the carrier 32. In a further operation, the semiconductor wafer can be singulated, where multiple semiconductor chips 8 can be obtained. In the illustrated example, the semiconductor wafer can be singulated in a cutting operation. For example, the effective surface of the obtained semiconductor chip 8 can face the carrier 32. Alternatively or additionally, the effective surface of the semiconductor chip 8 can face away from the carrier 32.

[0053] In Figure 6B a milling (mil) step can be performed. In the illustrated example, the top surface of the semiconductor chip 8 can be milled using a milling tool 42. The milling tool 42 can include at least one beveled end section. In the illustrated example, the beveled end section can have the shape of an arrow. The beveled end section can rotate and can penetrate the top surface of the semiconductor chip 8, where circular corners and / or circular edges 16B and 16C can be formed on the top surface of the semiconductor chip 8.

[0054] It should be noted that Figure 6A and Figure 6B the order of the operations can be reversed. That is, in another example, first the top surface of the semiconductor wafer can be milled to form circular corners and / or circular edges 16B and 16C on the surface of the semiconductor wafer. After that, the milled semiconductor wafer can be singulated, where semiconductor chips 8 including circular corners and / or circular edges can be obtained.

[0055] Figure 6C illustrates the arrangement after the Figure 6B milling operation has been performed. Each of the obtained semiconductor chips 8 can include at least one of the circular corners or circular edges 16B and 16C.

[0056] Figures 6A to 6C The method of Figure 1 and Figure 2 can include additional operations not described for simplicity. In a further operation, the carrier 32 and the adhesive layer 34 can be removed. For example, the obtained semiconductor chips 8 can be similar to the Figures 6A to 6C and Figure 3 semiconductor chips 8 of

[0057] A further exemplary method for manufacturing one or more semiconductor devices according to the present disclosure can be derived from the Figure 2It can be seen in [reference]. Specifically, the actions of this method can be applied to obtain a first portion of a conductive carrier including at least one of a circular corner or a circular edge.

[0058] In the action, a conductive material can be provided. In one example, the conductive material can correspond to the material for manufacturing a lead frame, such as a flat plate or sheet of metal and / or metal alloy, in particular at least one of copper, copper alloy, nickel, iron-nickel, aluminum, aluminum alloy, steel, stainless steel, etc.

[0059] In a further action, the conductive material can be stamped, wherein a first portion of the carrier including at least one of a circular corner or a circular edge can be formed. The first portion of the carrier can be stamped in a direction pointing away from the surface on which the semiconductor chip will be disposed later. Return reference Figure 2 For an example, the stamping direction is indicated by an arrow. In one case, a metal sheet can be stamped, wherein at least one of a current rail and a die pad and leads can be formed. Return reference Figure 2 For an example, the stamping of the metal sheet can (among other things) result in the current rail 4 including circular corners and / or circular edges 16A at the top surface of the current rail 4 and burrs 22 at the bottom surface of the current rail 4.

[0060] In a further action, the stamped first portion of the carrier can be etched, wherein at least part of the burrs of the conductive material obtained during the stamping action can be removed. Return reference Figure 2 For an example, at least part of the burrs 22 located at the bottom surface of the current rail 4 can be removed.

[0061] In one or more further actions, the stamped carrier including at least one circular corner and / or circular edge can be used to manufacture a semiconductor device according to the present disclosure, such as Figure 2 the semiconductor device 200. For example, the method can be extended by Figure 3 the actions 26 and 28.

[0062] Example

[0063] Hereinafter, a semiconductor device according to the present disclosure and its manufacturing method will be illustrated by examples.

[0064] Example 1 is a semiconductor device, including: a conductive carrier; a semiconductor chip disposed on a first portion of the carrier; and a dielectric material disposed between the first portion of the carrier and the semiconductor chip, wherein the dielectric material electrically isolates the first portion of the carrier and the semiconductor chip, and wherein at least one of the first portion of the carrier or the semiconductor chip includes at least one of a circular corner or a circular edge.

[0065] Example 2 is a semiconductor device according to Example 1, wherein during operation of the semiconductor device, the first part of the carrier is a current-carrying part.

[0066] Example 3 is a semiconductor device according to Example 1 or 2, wherein during operation of the semiconductor device, the first part of the carrier is in a high-voltage domain and the semiconductor chip is in a low-voltage domain.

[0067] Example 4 is a semiconductor device according to one of the foregoing examples, wherein: the carrier is a lead frame, the first part of the carrier is a current rail, and the semiconductor chip is a sensor chip configured to sense a magnetic field generated by a current flowing through the current rail.

[0068] Example 5 is a semiconductor device according to one of the foregoing examples, wherein at least one of the rounded corners or rounded edges of the semiconductor chip is arranged on the surface of the semiconductor chip facing the first part of the carrier.

[0069] Example 6 is a semiconductor device according to one of the foregoing examples, wherein at least one of the rounded corners or rounded edges of the semiconductor chip is adjacent to a dielectric material.

[0070] Example 7 is a semiconductor device according to one of the foregoing examples, wherein at least one of the rounded corners or rounded edges of the first part of the carrier is arranged on the surface of the first part of the carrier facing the semiconductor chip.

[0071] Example 8 is a semiconductor device according to one of the foregoing examples, wherein at least one of the rounded corners or rounded edges of the first part of the carrier is adjacent to a dielectric material.

[0072] Example 9 is a semiconductor device according to one of the foregoing examples, further comprising: an encapsulating material, wherein the first part of the carrier and the semiconductor chip are at least partially encapsulated in the encapsulating material.

[0073] Example 10 is a semiconductor device according to Example 9, wherein at least one of the rounded corners or rounded edges of the semiconductor chip is adjacent to a dielectric material and the encapsulating material.

[0074] Example 11 is a semiconductor device according to Example 9 or 10, wherein the dielectric material extends beyond the contour of the first part of the carrier, and at least one of the rounded corners or rounded edges of the first part of the carrier is adjacent to the dielectric layer and the encapsulating material.

[0075] Example 12 is a semiconductor device according to one of the foregoing examples, wherein the first part of the carrier is stamped in a direction away from the direction pointed to by the semiconductor chip.

[0076] Example 13 is a semiconductor device according to one of the foregoing examples, wherein the first part of the carrier includes burrs at the edges of the surface facing away from the semiconductor chip.

[0077] Example 14 is a semiconductor device according to one of the foregoing examples, wherein the side surface of the semiconductor chip is dry-etched.

[0078] Example 15 is a method for manufacturing a semiconductor device, the method comprising: forming at least one of a rounded corner or a rounded edge of at least one of the first part of the conductive carrier or the semiconductor chip; disposing a dielectric material on the first part of the carrier; and disposing the semiconductor chip on the dielectric material, wherein the dielectric material electrically isolates the first part of the carrier and the semiconductor chip.

[0079] Example 16 is the method according to Example 15, wherein forming at least one of the rounded corner or the rounded edge of the semiconductor chip comprises: dry-etching the surface of the semiconductor wafer, wherein at least one of the rounded corner or the rounded edge is formed on the surface of the semiconductor wafer; and singulating the dry-etched wafer, wherein semiconductor chips are obtained.

[0080] Example 17 is the method according to Example 15 or 16, wherein forming at least one of the rounded corner or the rounded edge of the semiconductor chip comprises: chamfering the surface of the semiconductor wafer, wherein at least one of the rounded corner or the rounded edge is formed on the surface of the semiconductor wafer; and singulating the chamfered wafer, wherein semiconductor chips are obtained.

[0081] Example 18 is the method according to one of Examples 15 to 17, wherein forming at least one of the rounded corner or the rounded edge of the semiconductor chip comprises: singulating the semiconductor wafer, wherein semiconductor chips are obtained; and milling the surface of the semiconductor chip, wherein at least one of the rounded corner or the rounded edge is formed on the surface of the semiconductor chip.

[0082] Example 19 is the method according to one of Examples 15 to 18, wherein forming at least one of the rounded corner or the rounded edge of the carrier comprises: providing a conductive material; stamping the conductive material, wherein a first part of the carrier including at least one of the rounded corner or the rounded edge is formed, and wherein the first part of the carrier is stamped in a direction away from the semiconductor chip disposed thereon.

[0083] Example 20 is the method according to Example 19, further comprising: etching the stamped first part of the carrier, wherein burrs of the conductive material obtained during stamping are at least partially removed.

[0084] Although the present disclosure has been described with reference to illustrative examples, such description is not intended to be construed in a limiting sense. Various modifications and combinations of the illustrative examples, as well as other examples of the present disclosure, will be apparent to those of ordinary skill in the art upon reference to the description. Accordingly, the appended claims are intended to embrace any such modifications or examples.

Claims

1. A semiconductor device comprising: A conductive carrier (2); A semiconductor chip (8) arranged on the first part (4) of the carrier (2); as well as a dielectric material (10) arranged between the first portion (4) of the carrier (2) and the semiconductor chip (8), wherein the dielectric material (10) galvanically isolates the first portion (4) of the carrier (2) and the semiconductor chip (8), At least one of the first portion (4) of the carrier (2) or the semiconductor chip (8) comprises at least one of a rounded corner or a rounded edge (16).

2. The semiconductor device according to claim 1, wherein during operation of the semiconductor device, the first portion (4) of the carrier (2) is a current carrying portion.

3. The semiconductor device according to claim 1 or 2, wherein during operation of the semiconductor device, the first portion (4) of the carrier (2) is in a high voltage domain and the semiconductor chip (8) is in a low voltage domain.

4. The semiconductor device according to claim 1, wherein: The carrier (2) is a lead frame, The first portion (4) of the carrier (2) is a current rail, and The semiconductor chip (8) is a sensor chip configured to sense a magnetic field generated by a current flowing through the current rail.

5. The semiconductor device according to claim 1 , wherein at least one of the rounded corners or the rounded edges (16) of the semiconductor chip (8) is arranged on a surface of the first part (4) of the semiconductor chip (8) facing the carrier (2).

6. The semiconductor device according to any of the preceding claims, wherein at least one of a rounded corner or a rounded edge (16) of the semiconductor chip (8) is adjacent to the dielectric material (10).

7. The semiconductor device according to claim 1 , wherein at least one of the rounded corners or the rounded edges ( 16 ) of the first part ( 4 ) of the carrier ( 2 ) is arranged on a surface of the first part ( 4 ) of the carrier ( 2 ) facing the semiconductor chip ( 8 ).

8. The semiconductor device according to one of the preceding claims, wherein at least one of a rounded corner or a rounded edge (16) of the first portion (4) of the carrier (2) is adjacent to the dielectric material (10).

9. The semiconductor device according to claim 1 , further comprising: An encapsulation material (14), wherein the first part (4) of the carrier (2) and the semiconductor chip (8) are at least partially encapsulated in the encapsulation material (14).

10. The semiconductor device according to one of the preceding claims, wherein at least one of rounded corners or rounded edges ((16)) of the semiconductor chip (8) is adjacent to the dielectric material (10) and the encapsulation material (14).

11. A semiconductor device according to claim 9 or 10, wherein the dielectric material (10) protrudes beyond the contour of the first part (4) of the carrier (2), and at least one of the rounded corners or rounded edges (16) of the first part (4) of the carrier (2) is adjacent to the dielectric layer (10) and the encapsulation material (14). 12 . The semiconductor arrangement as claimed in claim 1 , wherein the first part ( 4 ) of the carrier ( 2 ) is punched out in a direction away from the semiconductor chip ( 8 ).

13. The semiconductor device according to claim 1, wherein the first portion (4) of the carrier (2) comprises a burr (22) at an edge of a surface facing away from the semiconductor chip (8).

14. The semiconductor arrangement according to claim 1, wherein side surfaces of the semiconductor chip (8) are dry-etched.

15. A method for manufacturing a semiconductor device, the method comprising: forming at least one of a rounded corner or a rounded edge (16) of at least one of the first portion (4) of the conductive carrier (2) or the semiconductor chip (8); disposing a dielectric material (10) on the first portion (4) of the carrier (2); and The semiconductor chip (8) is arranged on the dielectric material (10), wherein the dielectric material (10) galvanically isolates the first part (4) of the carrier (2) and the semiconductor chip (8).

16. The method of claim 15, wherein forming at least one of rounded corners or rounded edges (16) of the semiconductor chip (8) comprises: dry etching a surface of a semiconductor wafer (30), wherein at least one of rounded corners or rounded edges (16) is formed on the surface of the semiconductor wafer (30), and The dry-etched wafer (30) is singulated, wherein the semiconductor chips (8) are obtained.

17. The method according to claim 15 or 16, wherein forming at least one of rounded corners or rounded edges (16) of the semiconductor chip (8) comprises: Chamfering a surface of a semiconductor wafer (30), wherein at least one of a rounded corner or a rounded edge (16) is formed on the surface of the semiconductor wafer (30), and The chamfered wafer (30) is singulated, wherein the semiconductor chips (8) are obtained.

18. The method according to one of claims 15 to 17, wherein forming at least one of rounded corners or rounded edges (16) of the semiconductor chip (8) comprises: singulating a semiconductor wafer (30), wherein the semiconductor chips (8) are obtained, and The surface of the semiconductor chip (8) is milled, wherein the at least one of a rounded corner or a rounded edge (16) on the surface of the semiconductor chip (8) is formed.

19. The method according to one of claims 15 to 18, wherein forming at least one of a rounded corner or a rounded edge (16) of the first portion (4) of the carrier (2) comprises: Providing conductive materials; The electrically conductive material is stamped, wherein the first portion (4) of the carrier (2) comprising the at least one of a rounded corner or a rounded edge (16) is formed, wherein the first portion (4) of the carrier (2) is stamped in a direction away from the semiconductor chip (8) arranged thereon.

20. The method according to claim 19, further comprising: The punched first portion (4) of the carrier (2) is etched, wherein burrs (22) of the electrically conductive material obtained during punching are at least partially removed.

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