Semiconductor element and manufacturing method thereof
By introducing insulating structures, electric fuse elements and gap walls into semiconductor components, and using manufacturing process variations to form epitaxial structures, the problems of semiconductor components being susceptible to defects and insufficient security of IoT hardware are solved, and random encoding and physical incommendable functions are realized, which improves information security.
Patent Information
- Application Number
- CN202311694278.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-12-11
- Publication Date
- 2025-06-13
AI Technical Summary
Existing semiconductor components are susceptible to defects during production, and in the field of IoT, hardware security is difficult to ensure, especially in preventing counterfeit chips and data security.
By introducing an insulating structure, an electric fuse element and a gap wall into the semiconductor element, the gap wall is partially covered with the semiconductor layer of the electric fuse element by utilizing the manufacturing process variation, and an epitaxial structure is formed to electrically connect adjacent electric fuse elements, realizing the functions of random coding and physical incommensurable.
The purpose of random encoding in semiconductor components is achieved, hardware security is enhanced, counterfeit chips are prevented, and the security of IoT information is improved.
Smart Images
Figure CN120149294A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of semiconductor devices, and particularly to a semiconductor element including an electric fuse element and a manufacturing method thereof. Background Art
[0002] With the miniaturization and increasing complexity of semiconductor manufacturing processes, semiconductor elements become more susceptible to various defects. Therefore, in addition to manufacturing components such as metal interconnects, diodes, or transistors, some fusible or openable connecting lines (fusible links), that is, fuses or electrical fuses (e-fuses), are additionally formed in integrated circuits to ensure the usability of the integrated circuits.
[0003] Generally, fuses / e-fuses are used to electrically connect to redundancy circuits in integrated circuits. Once it is detected that a part of the circuit is defective, the fuses / e-fuses can repair or replace the detected defective circuit. In addition, current e-fuse designs can also provide programming functions. For example, redundant information, batch numbers, or security codes can be stored in the e-fuse, thereby uniquely identifying each chip.
[0004] In addition, with the rise of the Internet of Things (IoT), more and more data is stored and shared digitally, and the security of the architecture has become increasingly important. In the past, information security regarding the IoT mostly focused on software and network encryption connections. However, in fact, in addition to network-level security protection, physical devices also pose threats. Once there are counterfeit chips or other problems, hackers may remotely control devices through the network to obtain keys and other sensitive information, thereby causing losses to enterprises.
[0005] Therefore, hardware-based security technologies have gradually received attention. For example, physically unclonable function (PUF) belongs to a type of hardware security technology. Its principle is to introduce various random variables in the semiconductor manufacturing process, causing slight differences in the microstructures of the manufactured chips. Due to the unpredictable and uncontrollable nature of random variables, it becomes almost impossible to replicate the chip. Such randomness, uniqueness, and non-replicability make the physically unclonable function exist as a kind of chip fingerprint, which can greatly enhance the information security of the IoT. Therefore, how to introduce random variables in the semiconductor manufacturing process to achieve the PUF function has become one of the key points for relevant industries to focus on. Summary of the Invention
[0006] According to an embodiment of the present invention, a semiconductor element is provided, which includes an insulating structure, a first fuse element, a second fuse element, a first spacer, a second spacer, and an epitaxial structure. The insulating structure is disposed in a substrate. The first fuse element and the second fuse element are respectively disposed on two sides of the insulating structure, wherein the first fuse element and the second fuse element respectively include a semiconductor layer and a mask layer. The semiconductor layer is disposed on the substrate, and the mask layer is disposed on the semiconductor layer. The first spacer partially covers a sidewall of the semiconductor layer of the first fuse element adjacent to the insulating structure. The second spacer partially covers a sidewall of the semiconductor layer of the second fuse element adjacent to the insulating structure. The epitaxial structure is disposed above the insulating structure and electrically connects the semiconductor layer of the first fuse element and the semiconductor layer of the second fuse element.
[0007] According to another embodiment of the present invention, a method for manufacturing a semiconductor element is provided, which includes the following steps. Form an insulating structure in a substrate. Form a first fuse element and a second fuse element on two sides of the insulating structure, wherein the first fuse element and the second fuse element respectively include a semiconductor layer and a mask layer. The semiconductor layer is disposed on the substrate, and the mask layer is disposed on the semiconductor layer. Form a first spacer to partially cover a sidewall of the semiconductor layer of the first fuse element adjacent to the insulating structure. Form a second spacer to partially cover a sidewall of the semiconductor layer of the second fuse element adjacent to the insulating structure. Form an epitaxial structure above the insulating structure and electrically connect the semiconductor layer of the first fuse element and the semiconductor layer of the second fuse element.
[0008] Compared with the prior art, when manufacturing the fuse element, the present invention makes use of process variations to enable the spacer to only partially cover the semiconductor layer of the fuse element, which is beneficial to forming an epitaxial structure to electrically connect the semiconductor layers of adjacent fuse elements. When applied to manufacturing a fuse element matrix, some adjacent fuse elements can be randomly electrically connected to each other by an epitaxial structure, while some adjacent fuse elements are not electrically connected to each other by an epitaxial structure, thereby achieving the purpose of random coding and realizing the PUF function. Description of the Drawings
[0009] Figure 1 、 Figure 2 、 Figure 3 、 Figure 4 、 Figure 5 、 Figure 6 、 Figure 7 and Figure 8 , which are schematic cross-sectional views of the steps of manufacturing a semiconductor element according to an embodiment of the present invention;
[0010] Figure 9 is a schematic cross-sectional view of the steps of manufacturing a semiconductor element according to another embodiment of the present invention;
[0011] Figure 10 It is a top view schematic diagram of a semiconductor device according to an embodiment of the present invention.
[0012] Main component symbol description
[0013] 1: First component
[0014] 2: Second component
[0015] 3: Third component
[0016] 10: Region
[0017] 20: Region
[0018] 100: Substrate
[0019] 101, 211, 221, 231: Top surface
[0020] 110: First component region
[0021] 120: Second component region
[0022] 130: Third component region
[0023] 210: First insulating structure
[0024] 212, 222: Depressions
[0025] 213, 223, 233: Flattened portions
[0026] 220: Second insulating structure
[0027] 230: Third insulating structure
[0028] 300: Semiconductor material layer
[0029] 310: Semiconductor layer
[0030] 311, 312, 313, 314, 315, 316: Sidewalls
[0031] 400: Mask material layer
[0032] 410: Mask layer
[0033] 500: Patterned mask
[0034] 610: First electric fuse element
[0035] 611, 621, 631: Sharp corner structures
[0036] 620: Second electric fuse element
[0037] 630: Third electric fuse element
[0038] 640: The fourth electric fuse element
[0039] 642, 652, 662: Flat structures
[0040] 650: The fifth electric fuse element
[0041] 660: The sixth electric fuse element
[0042] 710: The first spacer wall
[0043] 720: The second spacer wall
[0044] 730: The third spacer wall
[0045] 740: The fourth spacer wall
[0046] 750: The fifth spacer wall
[0047] 760: The sixth spacer wall
[0048] 810, 820: Epitaxial structures
[0049] 900: Mask layer
[0050] D1, D3: Horizontal directions
[0051] D2: Vertical direction
[0052] G: Gap
[0053] H1, H2: Height differences
[0054] L1: Length
[0055] P1: Ion implantation fabrication process
[0056] P2, P3: Etching fabrication processes
[0057] W1: Width Detailed implementation manners
[0058] Regarding the foregoing and other technical contents, features and effects of the present invention, they will be clearly presented in the following detailed description of the preferred implementation manners with reference to the accompanying drawings. The directional terms mentioned in the following implementation manners, such as: up, down, left, right, front, back, bottom, top, etc., are only with reference to the directions of the attached drawings. Therefore, the directional terms used are for explanation, rather than limiting the present invention. In addition, in the following implementation manners, the same or similar elements will adopt the same or similar reference numerals.
[0059] In the following description of "the first feature is formed on or above the second feature", it may mean that "the first feature is in direct contact with the second feature", or it may mean that "there are other features between the first feature and the second feature", so that the first feature and the second feature are not in direct contact.
[0060] The present invention uses terms such as first and second to describe elements, regions, layers, and / or sections, but it should be understood that these terms are only used to distinguish one element, region, layer, and / or section from another element, region, layer, and / or section. They do not imply or represent any previous ordinal number of the element itself, nor represent the arrangement order of one element and another element, or the order in the manufacturing method. Therefore, without departing from the scope of the specific implementation of the present invention, the first element, region, layer, and / or section discussed below may also be referred to by the terms of the second element, region, layer, and / or section. These terms in the claims may not be the same as those in the specification, and may be replaced by first, second, third... according to the order of element declarations in the claims.
[0061] Please refer to Figures 1 to 8 , which is a schematic cross-sectional view of the steps of manufacturing a semiconductor device according to an embodiment of the present invention. Figure 1 In, first, a substrate 100 is provided. The substrate 100 may be a silicon substrate, an epitaxial silicon substrate, a silicon carbide substrate, or a silicon on insulator (SOI) substrate. The substrate 100 includes a first element region 110, a second element region 120, and a third element region 130. Then, an insulating structure is formed in the substrate 100. Here, taking the formation of three insulating structures as an example, they are a first insulating structure 210, a second insulating structure 220, and a third insulating structure 230 respectively. The first insulating structure 210 is located in the first element region 110, the second insulating structure 220 is located in the second element region 120, and the third insulating structure 230 is located in the third element region 130. The first insulating structure 210, the second insulating structure 220, and the third insulating structure 230 may be, for example, shallow trench isolation (STI) structures, and the materials of the first insulating structure 210, the second insulating structure 220, and the third insulating structure 230 may be, for example, silicon dioxide. It should be particularly noted that Figure 1 drawing the first element region 110, the second element region 120, and the third element region 130 as adjacent to each other is for the convenience of drawing and description, and is not used to limit the present invention.
[0062] Next, as Figure 2As shown, an ion implantation process P1 is performed, where the energy and / or dose of the ion implantation process P1 in the first device region 110 and the second device region 120 is greater than the energy and / or dose in the third device region 130. Thus, the height (not otherwise labeled) of the first insulating structure 210 and the second insulating structure 220 protruding from the top surface 101 of the substrate 100 is lower than the height (not otherwise labeled) of the third insulating structure 230 protruding from the top surface 101 of the substrate 100, and the top surfaces 211 of the first insulating structure 210 and 221 of the second insulating structure 220 are more likely to form recesses 212 and 222 compared to the top surface 231 of the third insulating structure 230. Here, two recesses 212 are formed on both sides of the top surface 211 of the first insulating structure 210 through the ion implantation process P1, and one recess 222 is formed on one side of the top surface 221 of the second insulating structure 220. However, for illustration only, the present invention is not limited thereto. For example, in other embodiments, recesses 212 are formed on both sides of the top surface 211 of the first insulating structure 210, and recesses 222 are formed on both sides of the top surface 221 of the second insulating structure 220. Or, recesses 212 are formed on only one side of the top surface 211 of the first insulating structure 210, and recesses 222 are formed on both sides of the top surface 221 of the second insulating structure 220. In other words, the present invention can utilize the process variations generated by the ion implantation process P1 to randomly form recesses (such as recesses 212 and 222) in the insulating structures (such as the first insulating structure 210 and the second insulating structure 220) in the device regions (such as the first device region 110 and the second device region 120) where the energy and / or dose of the ion implantation process P1 is higher. The aforementioned "recesses" (such as recesses 212 and 222) may refer to the parts where the top ends of the insulating structures (such as the first insulating structure 210 and the second insulating structure 220) are recessed and lower than the top surface 101 of the substrate 100.
[0063] Figure 2 In [the figure], the top surface 211 of the first insulating structure 210 includes a flat portion 213 and two recesses 212. The flat portion 213 is connected between the two recesses 212. The height difference H1 between the flat portion 213 and one of the recesses 212 in the vertical direction D2 can be 100 angstroms to 140 angstroms. The aforementioned height difference H1 can be defined as the depth of the recess 212. The aforementioned vertical direction D2 can be parallel to the normal direction of the top surface 101 of the substrate 100, for example. Figure 2 In [the figure], the height differences H1 between the two recesses 212 of the first insulating structure 210 and the flat portion 213 in the vertical direction D2 are the same. However, for illustration only, due to process variations, the height differences H1 between the two recesses 212 of the first insulating structure 210 and the flat portion 213 in the vertical direction D2 may be slightly different.
[0064] The top surface 221 of the second insulating structure 220 includes a flat portion 223 and a recessed portion 222. The flat portion 223 is connected to the recessed portion 222, and the height difference H2 between the flat portion 223 and the recessed portion 222 in the vertical direction D2 can be 100 angstroms to 140 angstroms. Figure 2 Among them, the height difference H2 is the same as the height difference H1. However, this is only an example. Due to manufacturing process variations, the height difference H2 may be slightly different from the height difference H1. The top surface 231 of the third insulating structure 230 only includes a flat portion 233 and does not include a recessed portion.
[0065] Furthermore, although the energy and / or dose of the ion implantation manufacturing process P1 in the first element region 110 and the second element region 120 are the same, however, due to manufacturing process variations, the number and / or depth of the recessed portions 212 and 222 formed on the top surface 211 of the first insulating structure 210 and the top surface 221 of the second insulating structure 220 may be different. In addition, since the energy and / or dose of the ion implantation manufacturing process P1 in the third element region 130 are lower, therefore, no recessed portion is formed on the top surface 231 of the third insulating structure 230.
[0066] In some embodiments, the ion implantation manufacturing process P1 can be carried out together with the ion implantation manufacturing process for forming well regions (not shown in the figure) or source / drain regions (not shown in the figure) in the substrate 100 when manufacturing transistors. For example, the semiconductor device may further include a transistor (not shown in the figure). Therefore, the formation of the recessed portions 212 and 222 can be integrated into the manufacturing process of manufacturing the transistor to streamline the manufacturing process, but not limited thereto. In some embodiments, Boolean operations can be used to control the energy and / or dose of the ion implantation manufacturing process P1 in the first element region 110 and the second element region 120 to be different from the energy and / or dose in the third element region 130. How to control the energy and / or dose of the ion implantation manufacturing process P1 in different element regions is well known in the art and will not be elaborated herein.
[0067] Figure 2 Among them, the recessed portions 212 and 222 are formed by the ion implantation manufacturing process P1. However, the present invention is not limited thereto. For example, please refer to Figure 9 which is a schematic cross-sectional view of the steps of manufacturing a semiconductor device according to another embodiment of the present invention, and it continues Figure 1 the steps. Figure 9In this case, first, a mask layer 900 is formed to cover the third element region 130. Then, through an etching process P3, a part of the first insulating structure 210 and the second insulating structure 220 is removed, such that the heights (not otherwise labeled) of the first insulating structure 210 and the second insulating structure 220 protruding from the top surface 101 of the substrate 100 are lower than the height (not otherwise labeled) of the third insulating structure 230 protruding from the top surface 101 of the substrate 100, and recessed portions 212 and 222 are formed on the top surface 211 of the first insulating structure 210 and the top surface 221 of the second insulating structure 220. After that, the mask layer 900 is removed. After the etching process P3, the structures of the first insulating structure 210, the second insulating structure 220, and the third insulating structure 230 can refer to Figure 2 the structure and its related description. The aforementioned etching process P3 can be wet etching. For example, a buffered oxide etch (BOE) can be used to etch the first insulating structure 210 and the second insulating structure 220, but it is not limited thereto. In other words, the present invention can also utilize the process variations generated by the etching process P3 to randomly form recessed portions (such as recessed portions 212 and 222) in the insulating structures (such as the first insulating structure 210 and the second insulating structure 220) in the element regions (such as the first element region 110 and the second element region 120) that have undergone the etching process P3.
[0068] Next, as Figure 3 shown, a semiconductor material layer 300 is formed on the substrate 100, and a mask material layer 400 is formed on the semiconductor material layer 300. Then, the semiconductor material layer 300 and the mask material layer 400 are patterned. For example, as Figure 4 shown, a patterned mask 500 can be formed on the mask material layer 400, and then the parts of the semiconductor material layer 300 and the mask material layer 400 not covered by the patterned mask 500 are removed by using the etching process P2, as Figure 5 shown, such that the top surface 211 of the first insulating structure 210, the top surface 221 of the second insulating structure 220, and the top surface 231 of the third insulating structure 230 are exposed.
[0069] Next, as Figure 6As shown, after removing the patterned mask 500, the first fuse element 610 and the second fuse element 620 are obtained on two sides of the first insulating structure 210, the third fuse element 630 and the fourth fuse element 640 are obtained on two sides of the second insulating structure 220, and the fifth fuse element 650 and the sixth fuse element 660 are obtained on two sides of the third insulating structure 230. Each of the first fuse element 610, the second fuse element 620, the third fuse element 630, the fourth fuse element 640, the fifth fuse element 650, and the sixth fuse element 660 includes a semiconductor layer 310 and a mask layer 410. The semiconductor layer 310 is disposed on the substrate 100, and the mask layer 410 is disposed on the semiconductor layer 310. The material of the semiconductor layer 310 may include, for example, polysilicon or amorphous silicon, and the material of the mask layer 410 may include, for example, silicon dioxide (SiO 2 ), silicon nitride (SiN), silicon carbide (SiC), and / or silicon oxynitride (SiON).
[0070] Since the first insulating structure 210 is formed with a recess 212, the first fuse element 610 has a sharp corner structure 611 on a side adjacent to the first insulating structure 210, and the second fuse element 620 has a sharp corner structure 621 on a side adjacent to the first insulating structure 210. Since the second insulating structure 220 is formed with a recess 222, the third fuse element 630 has a sharp corner structure 631 on a side adjacent to the second insulating structure 220. Corresponding to the flat portion 223 of the second insulating structure 220, the fourth fuse element 640 has a flat structure 642 on a side adjacent to the second insulating structure 220. Corresponding to the flat portion 233 of the third insulating structure 230, the fifth fuse element 650 has a flat structure 652 on a side adjacent to the third insulating structure 230, and the sixth fuse element 660 has a flat structure 662 on a side adjacent to the third insulating structure 230.
[0071] Next, as Figure 7As shown, a first spacer wall 710 partially covers a sidewall 311 of a semiconductor layer 310 of a first fuse element 610 adjacent to a first insulating structure 210, a second spacer wall 720 partially covers a sidewall 312 of a semiconductor layer 310 of a second fuse element 620 adjacent to the first insulating structure 210, a third spacer wall 730 partially covers a sidewall 313 of a semiconductor layer 310 of a third fuse element 630 adjacent to a second insulating structure 220, a fourth spacer wall 740 completely covers a sidewall 314 of a semiconductor layer 310 of a fourth fuse element 640 adjacent to the second insulating structure 220, a fifth spacer wall 750 completely covers a sidewall 315 of a semiconductor layer 310 of a fifth fuse element 650 adjacent to a third insulating structure 230, and a sixth spacer wall 760 completely covers a sidewall 316 of a semiconductor layer 310 of a sixth fuse element 660 adjacent to the third insulating structure 230. A width W1 of the first spacer wall 710 in a horizontal direction D1 may decrease from bottom to top. The aforementioned horizontal direction D1 may be perpendicular to a normal direction of a top surface 101 of the substrate 100, for example. Similarly, a width (not otherwise labeled) of any one of the second spacer wall 720 to the sixth spacer wall 760 in the horizontal direction D1 may also decrease from bottom to top.
[0072] Specifically, the first through sixth spacer walls 710 - 760 can be formed simultaneously, and may include the following steps: depositing a spacer wall material layer (not shown in the figures) to entirely cover the top surfaces (not otherwise labeled) and sidewalls (not otherwise labeled) of the first through sixth fuse elements 610 - 660, as well as the top surfaces 211 of the first insulating structure 210, the top surfaces 221 of the second insulating structure 220, and the top surfaces 231 of the third insulating structure 230. Then, performing one or more etching processes and / or cleaning processes to completely remove the portions of the spacer wall material layer located on the top surfaces of the first through sixth fuse elements 610 - 660 and the top surfaces 211 of the first insulating structure 210, the top surfaces 221 of the second insulating structure 220, and the top surfaces 231 of the third insulating structure 230. During this process, portions of the spacer wall material layer located on the sidewalls of the first through sixth fuse elements 610 - 660 will also be removed, and the remaining spacer wall material layer is the first through sixth spacer walls 710 - 760. Due to the sharp corner structures 611, 621, 631, it is not conducive to the first spacer wall 710, the second spacer wall 720, and the third spacer wall 730 completely covering the sidewalls of the first fuse element 610, the second fuse element 620, and the third fuse element 630, such that the first spacer wall 710, the second spacer wall 720, and the third spacer wall 730 partially cover the sidewalls 311 of the semiconductor layer 310 of the first fuse element 610, the sidewalls 312 of the semiconductor layer 310 of the second fuse element 620, and the sidewalls 313 of the semiconductor layer 310 of the third fuse element 630. More specifically, the height of the semiconductor layer 310 above the recessed portions 212, 222 in the vertical direction D2 is greater than the height of the semiconductor layer 310 above the flat portions 223, 233 in the vertical direction D2, which is not conducive to the first spacer wall 710, the second spacer wall 720, and the third spacer wall 730 completely covering the sidewalls of the first fuse element 610, the second fuse element 620, and the third fuse element 630. The material of the first through sixth spacer walls 710 - 760 may include oxides and / or nitrides, such as silicon dioxide, silicon nitride, silicon oxynitride, or silicon carbonitride.
[0073] Next, as Figure 8 shown, an epitaxial growth process is performed to form an epitaxial structure 810 above the first insulating structure 210 and electrically connecting the semiconductor layer 310 of the first fuse element 610 and the semiconductor layer 310 of the second fuse element 620, and to form an epitaxial structure 820 above the second insulating structure 220 and connecting the semiconductor layer 310 of the third fuse element 630.
[0074] Specifically, since the sidewalls 311 of the semiconductor layer 310 of the first fuse element 610, the sidewalls 312 of the semiconductor layer 310 of the second fuse element 620, and the sidewalls 313 of the semiconductor layer 310 of the third fuse element 630 are only partially covered by the first spacer 710, the second spacer 720, and the third spacer 730, during the epitaxial growth process, the epitaxy will grow from the uncovered parts of the sidewalls 311, 312, and 313. The epitaxy grown from the sidewalls 311 and 312 is connected to form an epitaxial structure 810. The epitaxial structure 810 can electrically connect the semiconductor layer 310 of the first fuse element 610 and the semiconductor layer 310 of the second fuse element 620, thereby forming a path between the first fuse element 610 and the second fuse element 620. Since the sidewall 314 is completely covered by the fourth spacer 740, the epitaxial structure 820 formed by the growth of the sidewall 313 cannot electrically connect the semiconductor layer 310 of the third fuse element 630 and the semiconductor layer 310 of the fourth fuse element 640. Therefore, the third fuse element 630 and the fourth fuse element 640 are in an open circuit state. No epitaxial structure is formed between the fifth fuse element 650 and the sixth fuse element 660, so they are also in an open circuit state.
[0075] Figure 8 In FIG., the epitaxial structure 810 and the first insulating structure 210 have a gap G in the vertical direction D2. The material of the epitaxial structure 810 may include silicon germanium (SiGe). The length L1 of the epitaxial structure 810 in the horizontal direction D1 may be 530 angstroms to 570 angstroms, and the length L1 is substantially the same as the spacing distance between the sidewall 311 and the sidewall 312 in the horizontal direction D1. Thus, it is beneficial for the epitaxy grown from the sidewalls 311 and 312 to be connected to form the epitaxial structure 810.
[0076] In some embodiments, the first spacer 710 to the sixth spacer 760 of the present invention may also be formed together with the spacers (not shown) that form a gate surround structure (not shown) and define a lightly doped drain (LDD) region (not shown) and / or the spacers (not shown) that define a source / drain region (not shown) when manufacturing a transistor. The epitaxial structures 810 and 820 may also be formed together with the epitaxial structures (not shown) formed in the substrate 100 on both sides of the gate structure and used to increase the channel stress when manufacturing a transistor. For example, the semiconductor device may further include a transistor (not shown). Therefore, the formation of the first spacer 710 to the sixth spacer 760 and the epitaxial structures 810 and 820 can be integrated into the manufacturing process of manufacturing a transistor to streamline the manufacturing process, but it is not limited thereto.
[0077] Each of the above-mentioned film layers, such as the semiconductor material layer 300, the mask material layer 400, the patterned mask 500, the mask layer 900, the first spacer 710 to the sixth spacer 760, etc., can be formed by any suitable method, such as but not limited to molecular-beam epitaxy (MBE), chemical vapor deposition (CVD), metal organic chemical vapor deposition (MOCVD), hydride vapor phase epitaxy (HVPE), atomic layer deposition (ALD), etc.
[0078] Please refer to Figure 8 , which is a cross-sectional schematic diagram of a semiconductor device according to an embodiment of the present invention. As shown in the first device region 110, the semiconductor device may include a first device 1, and the first device 1 includes a first insulating structure 210, a first fuse element 610, a second fuse element 620, a first spacer 710, a second spacer 720, and an epitaxial structure 810. The first insulating structure 210 is disposed in the substrate 100. The first fuse element 610 and the second fuse element 620 are respectively disposed on two sides of the first insulating structure 210, wherein the first fuse element 610 and the second fuse element 620 respectively include a semiconductor layer 310 and a mask layer 410. The semiconductor layer 310 is disposed on the substrate 100, and the mask layer 410 is disposed on the semiconductor layer 310. The first spacer 710 partially covers the sidewall 311 of the semiconductor layer 310 of the first fuse element 610 adjacent to the first insulating structure 210. The second spacer 720 partially covers the sidewall 312 of the semiconductor layer 310 of the second fuse element 620 adjacent to the first insulating structure 210. The epitaxial structure 810 is disposed above the first insulating structure 210 and electrically connects the semiconductor layer 310 of the first fuse element 610 and the semiconductor layer 310 of the second fuse element 620. The first device 1 further includes a gap G disposed between the epitaxial structure 810 and the first insulating structure 210 in the vertical direction D2. Other details of the first device 1 can be referred to above and will not be elaborated here.
[0079] As shown in the second element region 120, the semiconductor device may further include a second element 2, which includes a second insulating structure 220, a third fuse element 630, a fourth fuse element 640, a third spacer 730, a fourth spacer 740, and an epitaxial structure 820. The second insulating structure 220 is disposed in the substrate 100. The third fuse element 630 and the fourth fuse element 640 are respectively disposed on two sides of the second insulating structure 220, wherein the third fuse element 630 and the fourth fuse element 640 respectively include a semiconductor layer 310 and a mask layer 410. The semiconductor layer 310 is disposed on the substrate 100, and the mask layer 410 is disposed on the semiconductor layer 310. The third spacer 730 partially covers the sidewall 313 of the semiconductor layer 310 of the third fuse element 630 adjacent to the second insulating structure 220. The fourth spacer 740 completely covers the sidewall 314 of the semiconductor layer 310 of the fourth fuse element 640 adjacent to the second insulating structure 220. The epitaxial structure 820 is disposed above the second insulating structure 220 and is connected to the semiconductor layer 310 of the third fuse element 630. The difference between the second element 2 and the first element 1 is mainly that the semiconductor layer 310 of the fourth fuse element 640 is completely covered by the fourth spacer 740, so that the epitaxial structure 820 cannot be electrically connected to the semiconductor layers 310 of the adjacent third fuse element 630 and fourth fuse element 640. Other details about the second element 2 can be referred to the above, and will not be elaborated here.
[0080] As shown in the third element region 130, the semiconductor device may further include a third element 3, which includes a third insulating structure 230, a fifth fuse element 650, a sixth fuse element 660, a fifth spacer 750, and a sixth spacer 760. The third insulating structure 230 is disposed in the substrate 100. The fifth fuse element 650 and the sixth fuse element 660 are respectively disposed on two sides of the third insulating structure 230, wherein the fifth fuse element 650 and the sixth fuse element 660 respectively include a semiconductor layer 310 and a mask layer 410. The semiconductor layer 310 is disposed on the substrate 100, and the mask layer 410 is disposed on the semiconductor layer 310. The fifth spacer 750 completely covers the sidewall 315 of the semiconductor layer 310 of the fifth fuse element 650 adjacent to the third insulating structure 230. The sixth spacer 760 completely covers the sidewall 316 of the semiconductor layer 310 of the sixth fuse element 660 adjacent to the third insulating structure 230. The difference between the third element 3 and the first element 1 is mainly that the semiconductor layers 310 of the fifth fuse element 650 and the sixth fuse element 660 are respectively completely covered by the fifth spacer 750 and the sixth spacer 760. Therefore, the third element 3 does not have an epitaxial structure electrically connecting the semiconductor layers 310 of the adjacent fifth fuse element 650 and sixth fuse element 660. Other details about the third element 3 can be referred to the above, and will not be elaborated here.
[0081] Please refer to Figure 10 , which is a top view schematic diagram of a semiconductor device according to an embodiment of the present invention. The semiconductor device includes region 10 and region 20. Region 10 can be used as a PUF unit, for example, and region 20 can be a region for arranging components such as transistors (not shown in the figure), diodes (not shown in the figure), metal wirings (not shown in the figure), and fuse elements (such as the fifth fuse element 650 and the sixth fuse element 660 in the third element region 130) that implement the main functions of the semiconductor device.
[0082] The above-mentioned first element region 110 and second element region 120 can be arranged in region 10, and the third element region 130 can be arranged in region 20. The fifth fuse element 650 and the sixth fuse element 660 in the third element region 130 can be used to repair or replace defective circuits detected, etc., to ensure the usability of the semiconductor device.
[0083] For example, region 10 may include a fuse element matrix formed by arranging a plurality of fuse elements (such as the first fuse element 610, the second fuse element 620, the third fuse element 630, and the fourth fuse element 640) along the horizontal direction D1 and the horizontal direction D3. Here, the horizontal direction D3 is perpendicular to the horizontal direction D1. However, this is only an example, and the present invention is not limited thereto. Insulation structures (such as the first insulation structure 210 and the second insulation structure 220) are provided between two adjacent fuse elements. Region 10 may further include a plurality of word lines (not shown in the figure) and a plurality of bit lines (not shown in the figure) for controlling the plurality of fuse elements, such as addressing and reading the individual fuse elements.
[0084] When manufacturing the semiconductor device, after forming a plurality of insulation structures in the substrate 100, as Figure 2 shown, the energy and / or dose of the ion implantation manufacturing process P1 in region 10 is greater than that in region 20, or, as Figure 9 shown, a mask layer 900 is formed in region 20, and a part of the insulation structures in region 10 is removed through the etching manufacturing process P3, so that the height (not otherwise labeled) of the plurality of insulation structures in region 10 protruding from the top surface 101 of the substrate 100 is lower than the height of the plurality of insulation structures in region 20 protruding from the top surface 101 of the substrate 100, and a recess (such as the recesses 212 and 222 in Figure 2 ) is formed on the top surface of the plurality of insulation structures in region 10. In other words, the present invention can use at least one additional ion implantation manufacturing process P1 and / or etching manufacturing process P3 for region 10 to make the insulation structures located in region 10 randomly have unpredictable recesses, so that the plurality of fuse elements formed subsequently have manufacturing process differences and thus the PUF function can be realized.
[0085] Specifically, due to manufacturing process variations, the number and depth of the recesses formed by multiple insulating structures in region 10 are different, resulting in some of the subsequently formed spacer walls partially covering the sidewalls of the semiconductor layer in the fuses (such as the first spacer wall 710, the second spacer wall 720, and the third spacer wall 730), and some completely covering the sidewalls of the semiconductor layer in the fuses (such as the fourth spacer wall 740). As a result, an epitaxial structure for electrically connecting each other is formed between some of the fuses (such as the first element 1 in Figure 8 ), and an epitaxial structure for electrically connecting each other cannot be formed between some of the fuses (such as the second element 2 in Figure 8 ). In addition, through circuit design, it can be defined that when there is an epitaxial structure between two fuses to conduct between them, it represents one of 0 and 1, and when there is no epitaxial structure between two fuses to conduct between them, it represents the other of 0 and 1. That is, the fuse matrix in region 10 can correspond to a logic matrix composed of 0 and 1.
[0086] Due to the randomness of manufacturing process variations, the fuses with an epitaxial structure to conduct between them are randomly distributed in region 10. In other words, 0 and 1 in the logic matrix are also randomly distributed and can be used as the inherent electronic fingerprint of the semiconductor device 1, which can be used as the key to identify the chip or device, thereby realizing the PUF function. Regarding how to control multiple fuses through word lines and bit lines, and how to define the corresponding state of different fuses as one of 0 or 1 through circuit design, these are well-known in the art and will not be elaborated here.
[0087] Compared with the prior art, in the present invention, when manufacturing fuses, by using manufacturing process variations, the spacer walls can only partially cover the semiconductor layer of the fuses, which is beneficial to forming an epitaxial structure to electrically connect the semiconductor layers of adjacent fuses. When applied to manufacturing a fuse matrix, some adjacent fuses can randomly have an epitaxial structure to electrically connect each other, and some adjacent fuses do not have an epitaxial structure to electrically connect each other, thereby achieving the purpose of random coding and realizing the PUF function.
[0088] The above are only the preferred embodiments of the present invention. All equivalent changes and modifications made according to the claims of the present invention shall fall within the scope of the present invention.
Claims
1. A semiconductor device, characterized in that, comprising: an insulating structure disposed in a substrate; a first fuse element and a second fuse element, respectively disposed on two sides of the insulating structure, wherein the first fuse element and the second fuse element respectively comprise a semiconductor layer and a mask layer, the semiconductor layer is disposed on the substrate, and the mask layer is disposed on the semiconductor layer; a first spacer, partially covering a sidewall of the semiconductor layer of the first fuse element adjacent to the insulating structure; a second spacer, partially covering a sidewall of the semiconductor layer of the second fuse element adjacent to the insulating structure; and an epitaxial structure disposed above the insulating structure and electrically connecting the semiconductor layer of the first fuse element and the semiconductor layer of the second fuse element.
2. The semiconductor device according to claim 1, further comprising: a gap disposed between the epitaxial structure and the insulating structure in a vertical direction.
3. The semiconductor device according to claim 1, wherein a top surface of the insulating structure comprises two recessed portions on two sides of the top surface.
4. The semiconductor device according to claim 3, wherein the top surface of the insulating structure further comprises a flat portion connecting between the two recessed portions, and a height difference between the flat portion and the recessed portion in a vertical direction is 100 angstroms to 140 angstroms.
5. The semiconductor device according to claim 1, wherein the first fuse element and the second fuse element respectively have a sharp corner structure on a side adjacent to the insulating structure.
6. The semiconductor device according to claim 1, wherein a width of the first spacer in a horizontal direction decreases from bottom to top.
7. The semiconductor device according to claim 1, wherein a length of the epitaxial structure in a horizontal direction is 530 angstroms to 570 angstroms.
8. The semiconductor device according to claim 1, wherein a material of the semiconductor layer comprises polysilicon or amorphous silicon.
9. The semiconductor device according to claim 1, wherein a material of the epitaxial structure comprises silicon germanium.
10. A method for manufacturing a semiconductor device, characterized in that, comprising: forming an insulating structure in a substrate; forming a first fuse element and a second fuse element on two sides of the insulating structure, wherein the first fuse element and the second fuse element respectively comprise a semiconductor layer and a mask layer, the semiconductor layer is disposed on the substrate, and the mask layer is disposed on the semiconductor layer; forming a first spacer to partially cover a sidewall of the semiconductor layer of the first fuse element adjacent to the insulating structure; forming a second spacer to partially cover a sidewall of the semiconductor layer of the second fuse element adjacent to the insulating structure; and forming an epitaxial structure above the insulating structure and electrically connecting the semiconductor layer of the first fuse element and the semiconductor layer of the second fuse element.
11. The method according to claim 10, wherein there is a gap between the epitaxial structure and the insulating structure in a vertical direction.
12. The method according to claim 10, wherein forming the first fuse element and the second fuse element on two sides of the insulating structure comprises: forming a semiconductor material layer on the substrate; forming a mask material layer on the semiconductor material layer; and Pattern the semiconductor material layer and the mask material layer.
13. The method according to claim 10, further comprising: Form two recesses on two sides of the top surface of the insulating structure.
14. The method according to claim 13, wherein the top surface of the insulating structure further comprises a flat portion connected between the two recesses, and the height difference between the flat portion and the recesses in the vertical direction is 100 angstroms to 140 angstroms.
15. The method according to claim 13, wherein the two recesses are formed by an etching manufacturing process or an ion implantation manufacturing process.
16. The method according to claim 10, wherein the first fusing element and the second fusing element respectively have a sharp corner structure on one side adjacent to the insulating structure.
17. The method according to claim 10, wherein the width of the first spacer in the horizontal direction decreases from bottom to top.
18. The method according to claim 10, wherein the length of the epitaxial structure in the horizontal direction is 530 angstroms to 570 angstroms.
19. The method according to claim 10, wherein the material of the semiconductor layer comprises polysilicon or amorphous silicon.
20. The method according to claim 10, wherein the material of the epitaxial structure comprises silicon germanium.