Demagnetization time successive approximation circuit for improving power supply energy transfer efficiency

Abstract

The invention belongs to the technical field of circuit structures, particularly relates to a demagnetization time successive approximation circuit for improving power supply energy transfer efficiency, and aims to solve the problems of incomplete primary side excitation capability demagnetization energy transfer, man-made noise and unstable circuit in an existing asymmetric half-bridge flyback switching power supply. According to the circuit, the optimal demagnetization time of the low-side power tube is obtained by detecting the optimal demagnetization signal, and the actual conduction time of the low-side power tube is controlled to gradually approach the optimal demagnetization time in a closed-loop manner through circuits such as the integrator which generates a variable slope along with the change of the compensation current. The optimal energy transmission efficiency is achieved, and generation of man-made noise and occurrence of unstable conditions are restrained through gradual linear changes.

Description

Technical Field

[0001] The present invention belongs to the technical field of circuit structures, and particularly relates to a demagnetization time gradually approaching circuit for improving the power energy transfer efficiency. Background Art

[0002] The asymmetric half-bridge flyback converter is a typical power switch. In the asymmetric half-bridge flyback converter system, when the high-side power transistor conducts, it magnetizes and stores energy in the transformer excitation inductor. When the low-side power transistor conducts, it demagnetizes the transformer excitation inductor and transfers the energy to the output capacitor on the secondary side, thereby realizing the transfer of the output capacitor energy through the alternating conduction of the high-side and low-side power transistors to stably output the voltage under different load conditions.

[0003] If the pulse width length of the conduction time LS of the low-side power transistor is too long or too short, there will be a problem of incomplete energy transfer. Specifically, too long LS increases the unnecessary conduction loss of the low-side power transistor and may cause the negative inductor current to reverse magnetize the transformer, resulting in reliability problems; too short LS may cause the current ripple on the secondary side to increase. Due to insufficient energy transfer, the un-demagnetized energy may flow back to the input capacitor, polluting the power grid.

[0004] Currently, to solve this problem, some asymmetric half-bridge flyback converters directly turn off the low-side power transistor after detecting the demagnetization completion signal by sampling the inductor voltage to achieve the best energy transfer efficiency; however, due to the fluctuation of the topology output load, it may cause a large non-linear change in the conduction time LS of the low-side power transistor, artificially introducing circuit noise, thereby affecting the circuit stability.

[0005] Therefore, to solve the above problems, a demagnetization time gradually approaching circuit that can both improve the power energy transfer efficiency and does not affect the circuit stability is proposed. Summary of the Invention

[0006] To solve the above problems existing in the prior art, the present invention provides a demagnetization time gradually approaching circuit for improving the power energy transfer efficiency, which solves the problem that due to the fluctuation of the topology output load in the prior art, the conduction time LS of the low-side power transistor may have a large non-linear change, affecting the circuit stability.

[0007] The object of the present invention can be achieved by the following technical solutions: A demagnetization time gradually approaching circuit for improving the power energy transfer efficiency includes a high-pass filter sampling and amplifying circuit, a main integrator circuit, a sample and hold circuit, a switched capacitor amplifying circuit, a current comparator circuit, and a clock control circuit;

[0008] The high-pass filter sampling and amplifying circuit is connected to the voltage-dividing node of the primary inductor of the flyback switching power supply transformer, detects the voltage-dividing voltage signal as VZCD, filters out the low-frequency components from VZCD and amplifies the high-frequency resonance signal, and outputs the optimal demagnetization time signal LST_e to trigger the clock control circuit to generate the clock control signal LST;

[0009] The switched-capacitor amplifier circuit performs a difference ratio operation on the voltage signal Ve generated by the sampling circuit and the given voltage VH to obtain the voltage signal Vee;

[0010] The current comparator circuit is used to compare the Vee signal and the Ve signal, and then control the charging and discharging of different currents of the subsequent large capacitor. The capacitor compensation voltage Vcom is generated during the charging and discharging. The Vcom is used to dynamically adjust the self-compensation current Icom of the main integrator circuit, control the slope of the integral ramp voltage, and the slope of the integral ramp voltage feedback affects the voltage signal Ve;

[0011] The main integrator circuit generates an integral ramp voltage Vramp with a slope varying with Icom according to the preset self-compensation current Icom. After comparing the Vramp and VH with the current comparator circuit, the pulse signal LS_e is output to trigger the clock control circuit to generate the clock control signal LS;

[0012] The clock control circuit is used to generate three clock control signals LSs, LS, and LST to control the charging and discharging of the main integrator, the sampling and holding functions of the sample-and-hold circuit, and the sampling, amplifying, and holding functions of the switched-capacitor amplifier circuit respectively.

[0013] Preferably, a capacitor multiplier circuit is further included. The capacitor multiplier circuit includes a five-transistor OTA, two resistors R1 and resistor R2, where the resistance value of R1 is greater than that of R2. Through the clamping action of the OTA, the voltage at its positive input terminal is equal to the output terminal voltage, so that the ratio of the currents I1 and I2 flowing through R1 and R2 is equal to the ratio of R1 and R2.

[0014] Preferably, the high-pass filter sampling and amplifying circuit includes a high-pass filter module and a weak signal amplification module;

[0015] The input terminal of the high-pass filter module is connected to the VZCD voltage signal, which is used to sample the tiny high-frequency resonance signal on VZCD to the given voltage Vs1 to obtain the voltage signal Vhp_l, and then obtain the voltage signal Vhp_h after being amplified by the weak signal amplification module. Vhp_h is compared with the given voltage Vs2 through a comparator to obtain the output optimal demagnetization time signal LST_e;

[0016] The calculation formulas for the voltage signals Vhp_l and Vhp_h are:

[0017] Vhp_l = V s1 + V ZCD_ac

[0018]

[0019] Among them, VZCD_ac is the AC voltage amplitude of the high-frequency resonance of the ZCD pin.

[0020] Preferably, the main integrator circuit includes an OTA amplifier, an integration capacitor Cramp, a charge transfer gate switch Sch, a reset transfer gate switch Srst, a fixed current source Ich, a self-compensating current source Icom, and an output capacitor Co.

[0021] Preferably, the clock control circuit includes two SR latches and four Buffers. The externally input pulse signal LS_s is connected to the set terminals of the two SR latches, and the pulse signal LS_e output by the main integrator and the pulse signal LST_e output by the high-pass filter sampling and amplifying circuit are respectively input to the reset terminals of the two SR latches. The output terminals of the two SR latches are each connected to two Buffers to generate two clock control signals LS and LST, so that the rising edges of LS and LST are generated at the same moment; the input terminal of the Buffer before the LS clock signal is the clock signal LSs, aiming to make LSs rise from low level to high level earlier than LS.

[0022] Preferably, the switched-capacitor amplifier circuit includes a high-gain operational amplifier, a sample-and-hold capacitor, and a transfer gate switch. Among them, the voltage signal Ve and the voltage signal VH are respectively connected to the lower plate of the sampling capacitor Cs through the sampling switches S1 and S2. The calculation formula for the output voltage signal Vee of the switched-capacitor amplifier is:

[0023]

[0025] Preferably, a Buffer is inserted between the voltage signal and the sampling switch.

[0026] Preferably, the current comparator circuit includes a voltage-to-current converter composed of two PMOS transistors and a current mirror composed of two NMOS transistors. Ve and Vee are connected to the gates of the two PMOS transistors to generate currents corresponding to the magnitudes of VGS, and the current generated by Vee will be copied by the current mirror composed of NMOS below the current generated by Ve;

[0027] When Ve > Vee, the large capacitor at the subsequent stage is discharged;

[0028] When Ve < Vee, the large capacitor at the subsequent stage is charged.

[0029] Preferably, the output integral ramp voltage Vramp starts from the voltage VL and gradually increases with an initial slope until it rises to VH, where it triggers the pulse signal LS_e to control the generation of the falling edge of LS, causing the main integrator to reset the VL voltage until the start of the next cycle. The pulse width of the clock signal LS is inversely proportional to the integral ramp voltage Vramp. The calculation formulas for the slope of the integral ramp voltage Vramp and the pulse width length of LS are as follows:

[0030]

[0032] The beneficial effects of the present invention are as follows:

[0033] In the present invention, the high-pass filter module and the weak signal amplification module in the high-pass filter sampling and amplification circuit are used to sample and amplify the tiny high-frequency resonance signal of the transformer inductance voltage resistance voltage division VZCD, and then accurately detect it, greatly improving the detection accuracy of the tiny high-frequency resonance signal of VZCD.

[0034] The closed-loop control implemented by circuits such as the integrator, switched-capacitor amplifier, and current comparator in the present invention enables the conduction time of the low-side power transistor to approximately linearly approach the demagnetization completion time corresponding to the high-frequency resonance of VZCD, not only improving the energy transfer efficiency but also greatly reducing the possibility of generating artificial noise and low circuit stability.

[0035] The present invention also uses a capacitor multiplier circuit to not only improve the accuracy of the circuit but also greatly reduce the area of the overall circuit and prevent large capacitors from occupying area. Description of the Drawings

[0036] For the convenience of those skilled in the art to understand, the present invention will be further described below with reference to the accompanying drawings.

[0037] Figure 1 It is the overall framework diagram of the demagnetization time gradually approaching circuit for improving the power energy transfer efficiency provided by the embodiment of the present invention;

[0038] Figure 2 It is the internal circuit diagram of the high-pass filter sampling and amplification circuit provided by the embodiment of the present invention;

[0039] Figure 3 It is the internal circuit diagram of the main integrator circuit provided by the embodiment of the present invention;

[0040] Figure 4 It is the internal circuit diagram of the operational amplifier inside the main integrator circuit provided by the embodiment of the present invention;

[0041] Figure 5 It is the internal circuit diagram of the clock control circuit provided by the embodiment of the present invention;

[0042] Figure 6 Internal circuit diagram of the switched-capacitor amplifier circuit provided by the embodiment of the present invention;

[0043] Figure 7 Internal circuit diagram of the current comparison circuit provided by the embodiment of the present invention;

[0044] Figure 8 Internal circuit diagram of the capacitor multiplier circuit provided by the embodiment of the present invention;

[0045] Figure 9 Overall circuit diagram of the demagnetization time step-by-step approximation circuit for improving the power supply energy transfer efficiency provided by the embodiment of the present invention;

[0046] Figure 10 Working waveform diagram of the demagnetization time step-by-step approximation circuit for improving the power supply energy transfer efficiency provided by the embodiment of the present invention. Detailed implementation manners

[0047] To further elaborate on the technical means and effects adopted by the present invention to achieve the predetermined invention purpose, the following combines the accompanying drawings and preferred embodiments to detail the specific implementation manners, structures, features, and their effects according to the present invention as follows.

[0048] Please refer to Figures 1-10 , this embodiment provides a demagnetization time step-by-step approximation circuit for improving the power supply energy transfer efficiency, including a high-pass filter sampling amplifier circuit, a main integrator circuit, a sample-and-hold circuit, a switched-capacitor amplifier circuit, a current comparator circuit, and a clock control circuit. The high-pass filter sampling amplifier circuit is connected to the voltage-dividing node of the primary inductor of the flyback switching power supply transformer, detects the divided voltage signal as VZCD, filters out the low-frequency components from VZCD and amplifies the high-frequency resonant signal, and outputs the optimal demagnetization time signal LST_e to trigger the clock control circuit to generate the clock control signal LST;

[0049] The switched-capacitor amplifier circuit performs a difference ratio operation on the voltage signal Ve generated by the sampling circuit and the given voltage VH to obtain the voltage signal Vee;

[0050] The current comparator circuit is used to compare the Vee signal and the Ve signal, and further control the charging and discharging control of different currents for the subsequent large capacitor;

[0051] The main integrator circuit generates an integral ramp voltage Vramp with a slope varying with Icom according to the preset self-compensation current Icom. After comparing Vramp and VH with the current comparator circuit, a pulse signal LS_e is output to trigger the clock control circuit to generate the clock control signal LS;

[0052] A clock control circuit for generating three clock control signals LSs, LS, and LST to control the charging and discharging of the main integrator, the sampling and holding functions of the sample and hold circuit, and the sampling and amplified holding functions of the switched-capacitor amplifier circuit respectively.

[0053] A high-pass filter sampling and amplifying circuit includes a high-pass filter module and a weak signal amplification module. The specific circuit composition is designed as shown in Figure 2 one embodiment. The input terminal of the high-pass filter module is connected to the VZCD voltage signal. The high-pass filter module consists of CHP and RHP, and is used to sample the tiny high-frequency resonance signal on the VZCD voltage signal to a given voltage Vs1 to obtain the voltage signal Vhp_l. After being amplified by the weak signal amplification module, the voltage signal Vhp_h is obtained. Vhp_h and the given voltage Vs2 are compared by a comparator to obtain the output optimal demagnetization time signal LST_e, which triggers the clock control circuit to generate the clock control signal LST.

[0054] Among them, the calculation formulas for the voltage signals Vhp_l and Vhp_h are:

[0055] V hp_l =V s1 +V ZCD_ac

[0056]

[0057] Among them, VZCD_ac is the AC voltage amplitude of the high-frequency resonance of the ZCD pin.

[0058] A switched-capacitor amplifier circuit, as shown in Figure 6 one embodiment, is used to perform a difference ratio operation on the voltage signal Ve transmitted in the previous-stage sample and hold circuit and the given voltage VH, and calculate the obtained voltage value Vee. The voltage value Vee and Ve are compared by a current comparator.

[0059] Among them, the specific working principle of the switched-capacitor amplifier is: the switched-capacitor amplifier performs subtraction and amplification operations on the voltage values Ve and VH provided by the previous stage through two capacitors Cs and CH. The specific working process is divided into two stages: sampling and amplification. The output result of the operational amplifier in the sampling stage is Ve, and the output result of the operational amplifier in the holding stage is Ve plus the coefficient of the difference between VH and Ve.

[0060] The calculation formula for the output voltage signal Vee of the switched-capacitor amplifier is:

[0061]

[0062] The switched-capacitor amplifier includes a high-gain operational amplifier, a sample-and-hold capacitor, and transmission gate switches. Among them, the capacitor voltage signal Ve and the given voltage signal VH sent from the previous stage are respectively connected to the lower plate of the sampling capacitor Cs through the sampling switches S1 and S2.

[0063] The specific circuit structure of the switched-capacitor amplifier is as follows: the positive input of the high-gain operational amplifier is connected to the input voltage Ve, and the negative input is connected to the upper plate of the sampling capacitor Cs, the upper plate of the holding capacitor CH, and the right end of the switch S3. The output port Vee of the operational amplifier is connected to the right end of the switch S3 and the lower end of the switch S4; in addition to the positive input terminal of the operational amplifier, the input voltage Ve is also connected to the switch S1 and the switch S5; finally, the upper end of the switch S4 is connected to the lower plate of the holding capacitor CH and the left end of the switch S5.

[0064] The current comparator circuit, such as Figure 7 shown, is used to compare the Vee signal and the Ve signal, and then control the charge and discharge control of different currents of the large capacitor in the subsequent stage.

[0065] The working principle of the current comparator circuit is as follows: it includes a voltage-current converter composed of two PMOS transistors and a current mirror composed of two NMOS transistors. Ve and Vee are connected to the gates of the two PMOS transistors to generate currents corresponding to the magnitudes of VGS, and the current generated by Vee will be copied by the current mirror composed of NMOS below the current generated by Ve.

[0066] When Ve > Vee, the corresponding currents Iee of the two are greater than the current Ie, so the large capacitor in the subsequent stage will be discharged;

[0067] When Ve < Vee, the corresponding current Ie of the two is less than the current Ie, so the large capacitor in the subsequent stage will be charged.

[0068] The main integrator circuit is used to generate an integration ramp voltage Vramp whose slope varies with Icom. The voltage signal Vramp and VH are compared by a current comparator and then the pulse signal LS_e is output to make the subsequent clock control circuit generate the clock signal LS.

[0069] The main integrator circuit, such as Figure 3 shown, specifically includes a folded cascode floating-gate current source Class AB structure OTA amplifier, an integration capacitor Cramp, a charge transfer gate switch Sch, a reset transfer gate switch Srst, a fixed current source Ich, a self-compensating current source Icom, and an output capacitor Co.

[0070] The current comparator circuit generates a capacitance compensation voltage Vcom during charge and discharge. Vcom is used to dynamically adjust the self-compensation current Icom of the main integrator circuit, control the slope of the integral ramp voltage, and the change in the slope of the ramp voltage affects the pre-stage signal Ve through the feedback loop of the circuit system to form a closed-loop control. By adjusting the ramp slope, the duty cycle of the PWM signal is optimized, and the voltage regulation accuracy of the circuit is improved.

[0071] The switched-capacitor amplifier circuit realizes the dynamic closed-loop control of the slope of the ramp voltage, realizes the current feedback of the error signal and the precise matching of the capacitance compensation mechanism, and improves the stability of the circuit.

[0072] The clock control circuit is used to trigger and generate two clock control signals LSs, LS, and LST to control the charge and discharge of the main integrator, the sampling and holding functions of the sample and hold circuit, and the sampling and amplified holding functions of the switched-capacitor amplifier circuit.

[0073] The specific circuit of the clock control circuit is as Figure 5 shown: It includes two SR latches and four Buffers. The externally input pulse signal LS_s is connected to the set terminals of the two SR latches, and the pulse signals LS_e output by the main integrator and LST_e output by the high-pass filter sample amplifier circuit are respectively input to the reset terminals of the two SR latches. The output terminals of the two SR latches are each connected to two Buffers to generate two clock control signals LS and LST, so that the rising edges of LS and LST are generated at the same moment; the input terminal of the Buffer before the LS clock signal is the clock signal LSs, aiming to make LSs pull high from low level earlier than LS.

[0074] For the switched-capacitor amplifier circuit, each transmission gate switch is controlled by the clock signals LS and the inverted signal LSn output by the clock control circuit and the clock signal LSs to be in the on and off states. The transmission gate switches S2 and S5 are both controlled by the clock signal LS, and the transmission gate switches are closed when LS is at a high level; the switches S1 and S4 are both controlled by the clock signal LSn, and the switches are closed when LSn is at a high level. The clock signal LSs controls the on and off of the transmission gate switch S3, and LSs controls S3 to enter the off state earlier than the LS signal, so that the upper plate of the sampling capacitor Cs floats after S3 is turned off, and the characteristic that the voltage across the capacitor cannot change suddenly is applied to prevent the error introduced by the charge injection related to the input signal.

[0075] The specific operation process of the main integrator circuit is as follows: First, the clock control circuit outputs signals LS and LSn to turn on the charge transfer gate switch Sch and turn off the reset transfer gate switch Srst. Then, the current source at the negative input terminal of the OTA amplifier charges the integration capacitor Cramp to generate an integration ramp voltage signal Vramp. As it gradually increases linearly, when it is greater than the constant voltage VH, it is compared with a comparator to output the LS_e pulse signal, which is sent to the clock control circuit to flip the level signals LS and LSn to turn off the charge transfer gate switch Sch and turn on the reset transfer gate switch Srst to perform a reset operation on the output voltage Vramp of the integrator.

[0076] The output integration ramp voltage Vramp starts from the voltage VL and gradually increases with the initial slope until it rises to VH, where it triggers the pulse signal LS_e to control the falling edge of LS to cause the main integrator to reset the VL voltage until the start of the next cycle. The pulse width of the clock signal LS is inversely proportional to the integration ramp voltage Vramp. The calculation formulas for the slope of the integration ramp voltage Vramp and the pulse width of LS are:

[0077]

[0079] In one embodiment, the circuit diagram of the OTA amplifier with a folded cascode floating gate current source ClassAB structure in the main integrator is as Figure 4 shown. This structure has advantages such as high dynamic range, high PSRR, large gain, low power consumption, and high slew rate. The first stage of this OTA amplifier uses a folded cascode with differential input and single-ended output to achieve high gain and high PSRR; the second stage uses a Class-AB output stage, which can achieve rail-to-rail output at a lower quiescent current. The push-pull output method enables the output current during large-signal establishment to be unrestricted by the quiescent current, thereby achieving a better slew rate. Considering system stability, a Miller compensation circuit is added between the two-stage amplifiers to split the primary and secondary poles to improve the phase margin.

[0080] To prevent leakage of the voltage signals Ve and VH during the switching process of the sampling switches S1 and S2, in one embodiment, a Buffer is added between the voltage signal and the sampling switch to isolate the front and rear stages, provide driving ability for charging the sampling capacitor Cs of the rear stage, and shield the error influence caused by the parasitic capacitance connected between the lower plate of the sampling switch and the metal layer.

[0081] To improve the accuracy of the overall circuit, in one embodiment, it also includes a capacitor multiplication circuit, as Figure 8As shown in the figure, it is used to implement the function of approximately amplifying a small capacitor into a large capacitor. It includes a five-transistor OTA, two resistors R1 and R2, where the resistance value of R1 is greater than that of R2. The specific principle is as follows: Through the clamping action of the OTA, the voltages at its positive input terminal and output terminal are made equal. Therefore, the ratio of the currents I1 and I2 flowing through R1 and R2 is approximately equal to the ratio of R1 and R2. This circuit can multiply the capacitance Cm by adjusting the ratio of R1 and R2. It not only improves the accuracy of the circuit but also greatly reduces the area of the overall circuit, preventing the occupation of area by large capacitors.

[0082] A demagnetization time gradually approaching circuit for improving the power energy transfer efficiency, and its overall circuit diagram is as Figure 9 shown.

[0083] A demagnetization time gradually approaching circuit for improving the power energy transfer efficiency, and its working waveform diagram is as Figure 10 shown.

[0084] Combined with Figure 9 Figure 10 , the specific working process of the demagnetization time gradually approaching circuit for improving the power energy transfer efficiency is as follows:

[0085] At time t1, the external input pulse signal LS_s changes from low level to high level. The clock signals LS and LST output by the clock control module are triggered by the LS_s signal and also change from low level to high level. The LS signal starts to control the current Ich to charge the integration capacitor of the main integrator, and the output is an integration ramp voltage Vramp with a slope of k1. The LST signal controls the sample and hold circuit to sample the voltage signal Vramp.

[0086] After a period of time, the circuit reaches time t2. The high-pass filter sampling and amplifying circuit detects the high-frequency harmonic oscillation of the external input voltage signal VZCD and generates a pulse signal LS_e, which causes the clock control circuit to pull the clock signal LST from high level to low level, and then holds the sampled voltage Ve at a fixed voltage V1.

[0087] During the time period when LS is at high level, the switched-capacitor circuit also works in the sampling stage, making the output voltage Vee always equal to the previous-stage input voltage Ve. Therefore, the gate voltages of the two PMOS transistors in the subsequent current comparator circuit remain equal, Ie and Iee are approximately the same, and there is no extra current to charge and discharge the large capacitor in the subsequent stage. The capacitor voltage Vcom remains unchanged, and the VCCS composed of NMOS also does not generate a compensation current Icom to change the slope of the integration ramp voltage Vramp output by the main integrator circuit.

[0088] Until the circuit works until time t3, the integral ramp voltage Vramp of the main integrator is greater than the given fixed voltage VH, generating a pulse LS_e such that the clock control circuit controls the clock signal LS to be pulled down from high level to low level, and the switched-capacitor amplifier circuit changes to the hold amplification mode, amplifying the output voltage Vee to the fixed voltage V2; at this time, the output voltage Vee of the switched-capacitor amplifier circuit is greater than the sample-and-hold voltage Ve, the current Ie output by the current comparator is greater than Iee, and starts to charge the large capacitor generated by the subsequent capacitor multiplier circuit, and the voltage Vcom gradually increases, and the compensation current Icom generated after passing through the VCCS also gradually increases.

[0089] The circuit continues to work until time t4, and the externally input pulse signal LS_s changes from low to high again, and the circuit enters the next cycle. Since the compensation current Icom generated in the previous cycle increases to a certain value, the slope of the integral ramp voltage Vramp output by the main integrator in this cycle increases to k2. Due to the increase in the slope, the ramp voltage Vramp will be greater than the given fixed voltage VH faster, making the clock signal LS generated by the clock control circuit shorter than the previous cycle and closer to the pulse width length of the clock signal LST.

[0090] After the circuit goes through the same working process as the previous cycle, the voltage signal Vcom gradually increases again when the LS signal is at a low level, and the compensation current Icom also increases accordingly, thereby controlling the integral ramp voltage Vramp of the next cycle to continue to increase, and the clock signal LS is further shortened, gradually approaching the clock signal LST.

[0091] The above is only a preferred embodiment of the present invention and does not impose any form of limitation on the present invention. Although the present invention has been disclosed above with a preferred embodiment, it is not intended to limit the present invention. Any person skilled in the art can make some changes or modifications to the above-disclosed technical content to form an equivalent embodiment with equivalent changes, but as long as it does not depart from the technical content of the present invention, any brief modification, equivalent change and modification made to the above embodiment based on the technical essence of the present invention still fall within the scope of the technical solution of the present invention.

Claims

1. A demagnetization time step-by-step approximation circuit for improving power supply energy transfer efficiency, characterized in that: It includes a high-pass filter sampling amplifier circuit, a main integrator circuit, a sampling and holding circuit, a switch capacitor amplifier circuit, a current comparator circuit and a clock control circuit; The high-pass filter sampling amplifier circuit is connected to the voltage-dividing node of the primary inductance of the flyback switching power supply transformer, detects that the voltage-dividing voltage signal is VZCD, filters out the low-frequency component from VZCD and amplifies the high-frequency resonance signal, outputs the optimal demagnetization time signal LST_e, and triggers the clock control circuit to generate the clock control signal LST; The switch capacitor amplifier circuit performs a difference ratio operation on the voltage signal Vee generated by the sampling circuit and the given voltage VH to obtain a voltage signal Vee; The current comparator circuit is used to compare the Vee signal with the Ve signal, thereby controlling the charge and discharge of different currents of the subsequent large capacitor, generating a capacitor compensation voltage Vcom during the charge and discharge, and the Vcom is used to dynamically adjust the self-compensation current Icom of the main integrator circuit, control the integral ramp voltage slope, and the integral ramp voltage slope feedback affects the voltage signal Ve; The main integrator circuit generates an integrated ramp voltage Vramp whose slope varies with Icom according to a preset self-compensation current Icom, and the Vramp and VH are compared by the current comparator circuit to output a pulse signal LS_e, which triggers the clock control circuit to generate a clock control signal LS; The clock control circuit is used to generate three clock control signals LSs, LS and LST to respectively control the charging and discharging of the main integrator, the sampling and holding function of the sampling and holding circuit, and the sampling and amplification and holding function of the switched capacitor amplifier circuit.

2. The demagnetization time step-by-step approximation circuit for improving power supply energy transfer efficiency according to claim 1, characterized in that: It also includes a capacitance multiplication circuit, which includes a five-transistor OTA, two resistors R1 and a resistor R2, wherein the resistance of R1 is greater than the resistance of R2, and the voltages at its positive input and output ends are made equal through the clamping effect of the OTA, so that the ratio of currents I1 and I2 flowing through R1 and R2 is equal to the ratio of R1 and R2.

3. A demagnetization time step-by-step approximation circuit for improving power supply energy transfer efficiency according to any one of claim 2, characterized in that: The high-pass filtering sampling and amplifying circuit comprises a high-pass filtering module and a weak signal amplifying module; The input end of the high-pass filter module is connected to the VZCD voltage signal, which is used to sample the tiny high-frequency resonance signal on the VZCD to the given voltage Vs1 to obtain the voltage signal Vhp_l, and then amplify it through the weak signal amplification module to obtain the voltage signal Vhp_h. Vhp_h is compared with the given voltage Vs2 through a comparator to obtain the output optimal demagnetization time signal LST_e; The calculation formulas of the voltage signals Vhp_l and Vhp_h are: V hp_l =V s1 +V ZCD_ac Wherein, VZCD_ac is the AC voltage amplitude of the high frequency resonance of the ZCD pin.

4. A demagnetization time step-by-step approximation circuit for improving power supply energy transfer efficiency according to any one of claim 3, characterized in that: The main integrator circuit includes an OTA amplifier, an integrating capacitor Cramp, a charging transmission gate switch Sch, a reset transmission gate switch Srst, a fixed current source Ich, a self-compensating current source Icom and an output capacitor Co.

5. The demagnetization time step-by-step approximation circuit for improving power supply energy transfer efficiency according to claim 3, characterized in that: The clock control circuit includes two SR latches and four Buffers. The externally input pulse signal LS_s is connected to the set terminals of the two SR latches. The pulse signal LS_e output by the main integrator and the pulse signal LST_e output by the high-pass filter sampling and amplification circuit are respectively input to the reset terminals of the two SR latches. Two clock control signals LS and LST are generated after connecting two Buffers to the output terminals of the two SR latches, so that the rising edges of LS and LST are generated at the same moment. At the input terminal of the Buffer before the LS clock signal is the clock signal LSs, aiming to make LSs rise from low level to high level earlier than LS.

6. The demagnetization time step-by-step approximation circuit for improving power supply energy transfer efficiency according to claim 5, characterized in that: The switched-capacitor amplifier circuit includes a high-gain operational amplifier, a sample-and-hold capacitor, and transmission gate switches. The voltage signal Ve and the voltage signal VH are respectively connected to the lower plate of the sampling capacitor Cs through the sampling switches S1 and S2. The calculation formula for the output voltage signal Vee of the switched-capacitor amplifier is:

7. The demagnetization time step-by-step approximation circuit for improving power supply energy transfer efficiency according to claim 6, characterized in that: Insert a Buffer between the voltage signal and the sampling switch.

8. The demagnetization time step-by-step approximation circuit for improving power supply energy transfer efficiency according to claim 4, characterized in that: The current comparator circuit includes a voltage-to-current converter composed of two PMOS transistors and a current mirror composed of two NMOS transistors. Ve and Vee are connected to the gates of the two PMOS transistors to generate currents corresponding to the magnitudes of VGS, and the current generated by Vee will be copied by the current mirror composed of NMOS below the current generated by Ve; When Ve > Vee, the large capacitor at the subsequent stage is discharged; When Ve < Vee, the large capacitor at the subsequent stage is charged.

9. The demagnetization time step-by-step approximation circuit for improving power supply energy transfer efficiency according to claim 1, characterized in that: The output integrated ramp voltage Vramp starts from the voltage VL and gradually increases at the initial slope until it rises to VH, triggering the generation of the falling edge of the pulse signal LS_e to control the reset of the VL voltage by the main integrator until the start of the next cycle. The pulse width of the clock signal LS is inversely proportional to the integrated ramp voltage Vramp. The calculation formulas for the slope of the integrated ramp voltage Vramp and the pulse width length of LS are:

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