Peak voltage suppression circuit and inverter

Abstract

The invention provides a peak voltage suppression circuit and an inverter, and relates to the technical field of power electronics, and the circuit comprises an inversion circuit which is used for converting a direct current into an alternating current; the follow current circuit is connected with the inverter circuit and is used for realizing soft switching when a switching tube in the inverter circuit is disconnected so as to carry out follow current; the voltage suppression circuit is used for carrying out voltage clamping on peak voltage generated when a switching tube in the inverter circuit is switched off; the voltage suppression circuit comprises a first clamping circuit and a second clamping circuit, the first end of the first clamping circuit is connected with the first end of the follow current circuit, and the second end of the first clamping circuit is connected with the third end of the second clamping circuit; the first end of the second clamping circuit is connected with the second end of the follow current circuit, and the second end of the second clamping circuit is connected with the third end of the follow current circuit. According to the invention, the peak voltage of the follow current switch tube can be effectively suppressed, and the switching loss of the follow current switch tube is reduced.

Description

Technical Field

[0001] The present invention relates to the field of power electronics technology, and particularly to a spike voltage suppression circuit and an inverter. Background Art

[0002] In an inverter circuit, freewheeling switching tubes mostly adopt hard-switching control. During the switching process of hard-switching, a relatively large spike voltage will be generated. Especially when the inverter circuit operates at a low power factor, the spike voltage not only increases the loss of the switching tube, but also damages the switching tube when the spike voltage is too high. Therefore, how to effectively suppress the spike voltage is an urgent problem to be solved.

[0003] In the prior art, the midpoint of two freewheeling tubes is connected to the DC bus terminal through a diode or a MOS tube for voltage clamping, or a spike voltage is absorbed through an RC absorption circuit. However, if it is clamped to the bus voltage, it will cause the output noise to be introduced back to the input terminal to generate a circulating current problem; while the RC absorption circuit will cause serious heating of the resistor, resulting in a large loss, and cannot fundamentally solve the problem of hard-switching control of the freewheeling switching tube. Summary of the Invention

[0004] The present invention provides a spike voltage suppression circuit and an inverter, which are used to solve the defect that the spike voltage cannot be effectively suppressed in the prior art, effectively suppress the spike voltage of the freewheeling switching tube, and reduce the switching loss of the freewheeling switching tube.

[0005] The present invention provides a spike voltage suppression circuit, including:

[0006] An inverter circuit for converting direct current into alternating current;

[0007] A freewheeling circuit connected to the inverter circuit for achieving soft switching when the switching tube in the inverter circuit is turned off to conduct freewheeling;

[0008] A voltage suppression circuit for voltage clamping the spike voltage generated when the switching tube in the inverter circuit is turned off; the voltage suppression circuit includes a first clamping circuit and a second clamping circuit, where:

[0009] The first end of the first clamping circuit is connected to the first end of the freewheeling circuit, and the second end of the first clamping circuit is connected to the third end of the second clamping circuit; the first clamping circuit is used for voltage clamping the first end of the freewheeling circuit;

[0010] The first end of the second clamping circuit is connected to the second end of the freewheeling circuit, and the second end of the second clamping circuit is connected to the third end of the freewheeling circuit.

[0011] According to the spike voltage suppression circuit provided by the present invention, the first clamping circuit includes a capacitor C3. One end of the capacitor C3 serves as the first end of the first clamping circuit, and the other end of the capacitor C3 serves as the second end of the first clamping circuit. The capacitor C3 is used to clamp the voltage at the first end of the freewheeling circuit.

[0012] According to the spike voltage suppression circuit provided by the present invention, the first clamping circuit further includes an MOS transistor Q7 and a resistor R1, where:

[0013] The drain of the MOS transistor Q7 is connected to one end of the capacitor C3, one end of the resistor R1 is connected to the other end of the capacitor C3, and the source of the MOS transistor Q7 is connected to the other end of the resistor R1.

[0014] According to the spike voltage suppression circuit provided by the present invention, the second clamping circuit includes a diode D1 and a diode D2, where:

[0015] The negative electrode of the diode D1 serves as the first end of the second clamping circuit. The positive electrode of the diode D1 is connected to the positive electrode of the diode D2, and the positive electrode of the diode D1 serves as the third end of the second clamping circuit. The negative electrode of the diode D2 serves as the second end of the second clamping circuit.

[0016] According to the spike voltage suppression circuit provided by the present invention, the second clamping circuit includes an MOS transistor Q8 and an MOS transistor Q9, where:

[0017] The drain of the MOS transistor Q8 serves as the first end of the second clamping circuit. The source of the MOS transistor Q8 is connected to the source of the MOS transistor Q9. The drain of the MOS transistor Q9 serves as the second end of the second clamping circuit.

[0018] According to the spike voltage suppression circuit provided by the present invention, the freewheeling circuit includes a soft-switching freewheeling bridge arm, an inductor L1, an inductor L2, and a capacitor C2, where:

[0019] The first end of the soft-switching freewheeling bridge arm is connected to one end of the inductor L1. The second end of the soft-switching freewheeling bridge arm is connected to one end of the inductor L2. The other end of the inductor L1 is connected to one end of the load and one end of the capacitor C2, and the other end of the inductor L1 serves as the second end of the freewheeling circuit. The other end of the capacitor C2 is connected to the other end of the load and the other end of the inductor L2, and the other end of the capacitor C2 serves as the third end of the freewheeling circuit.

[0020] According to the spike voltage suppression circuit provided by the present invention, the soft-switching freewheeling bridge arm includes an MOS transistor Q5 and an MOS transistor Q6, where:

[0021] The source electrode of the MOS transistor Q5 serves as the first end of the soft-switching freewheeling bridge arm. The drain electrode of the MOS transistor Q5 is connected to the drain electrode of the MOS transistor Q6, and the drain electrode of the MOS transistor Q5 serves as the first end of the freewheeling circuit. The source electrode of the MOS transistor Q6 serves as the second end of the soft-switching freewheeling bridge arm.

[0022] According to the spike voltage suppression circuit provided by the present invention, the inverter circuit includes a DC power supply, a capacitor C1, a first inverter bridge arm, and a second inverter bridge arm, where:

[0023] The capacitor C1, the first inverter bridge arm, and the second inverter bridge arm are connected in parallel with the DC power supply. The first inverter bridge arm is connected to the first end of the soft-switching freewheeling bridge arm. The second inverter bridge arm is connected to the second end of the soft-switching freewheeling bridge arm. The second end of the first inverter bridge arm is connected to the second end of the second inverter bridge arm.

[0024] According to the spike voltage suppression circuit provided by the present invention, the first inverter bridge arm includes MOS transistors Q1 and Q2. The drain electrode of the MOS transistor Q1 serves as the first end of the first inverter bridge arm. The source electrode of the MOS transistor Q1 is connected to the drain electrode of the MOS transistor Q2 and the first end of the soft-switching freewheeling bridge arm.

[0025] The second inverter bridge arm includes MOS transistors Q3 and Q4. The drain electrode of the MOS transistor Q3 serves as the first end of the second inverter bridge arm. The source electrode of the MOS transistor Q3 is connected to the drain electrode of the MOS transistor Q4 and the second end of the soft-switching freewheeling bridge arm. The source electrode of the MOS transistor Q2 is connected to the source electrode of the MOS transistor Q4. The drive signals corresponding to the MOS transistor Q7 are respectively complementary in phase to the drive signals corresponding to the MOS transistors Q1 and Q2. The MOS transistors Q1 and Q4 are turned on synchronously. The MOS transistors Q2 and Q3 are turned on synchronously. The turn-on time of the MOS transistor Q5 is later than the turn-on time of the MOS transistor Q1 to achieve soft switching of the MOS transistor Q5. The turn-on time of the MOS transistor Q6 is later than the turn-on time of the MOS transistor Q2 to achieve soft switching of the MOS transistor Q6.

[0026] The present invention also provides an inverter, including a control circuit and the spike voltage suppression circuit as described in any one of the above. The control circuit is connected to the spike voltage suppression circuit, and the control circuit is used to control the states of the switching transistors in the spike voltage suppression circuit.

[0027] The peak voltage suppression circuit and inverter provided by the present invention can effectively avoid the generation of peak voltage through the soft-switching function of the freewheeling circuit during the AC-DC conversion process of the inverter circuit. During the freewheeling process of the freewheeling circuit, the first clamping circuit in the voltage suppression circuit further clamps the peak voltage generated when the switch of the inverter circuit is turned off, maintaining the peak voltage within a stable range, effectively suppressing the peak voltage, reducing the switching loss, and avoiding overvoltage damage to the switching tube. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] In order to more clearly illustrate the technical solutions in the present invention or the prior art, the following will briefly introduce the drawings required for use in the description of the embodiments or the prior art. Obviously, the drawings in the following description are some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0029] Figure 1 is a schematic connection diagram of the peak voltage suppression circuit provided by an embodiment of the present invention;

[0030] Figure 2 is a schematic circuit diagram of the inverter circuit provided by an embodiment of the present invention;

[0031] Figure 3 is a schematic circuit diagram of the freewheeling circuit provided by an embodiment of the present invention;

[0032] Figure 4 is a waveform diagram of the drive signals of different MOS tubes provided by an embodiment of the present invention;

[0033] Figure 5 is one of the schematic circuit diagrams of the voltage suppression circuit provided by an embodiment of the present invention;

[0034] Figure 6 is one of the schematic circuit diagrams of the peak voltage suppression circuit provided by an embodiment of the present invention;

[0035] Figure 7 is the second schematic circuit diagram of the peak voltage suppression circuit provided by an embodiment of the present invention;

[0036] Figure 8 is the second schematic circuit diagram of the voltage suppression circuit provided by an embodiment of the present invention.

[0037] Reference numerals:

[0038] 110: Inverter circuit; 111: First inverter bridge arm; 112: Second inverter bridge arm; 120: Freewheeling circuit; 121: Soft-switching freewheeling bridge arm; 130: Voltage suppression circuit; 131: First clamping circuit; 132: Second clamping circuit. Detailed implementation manners

[0039] To make the objectives, technical solutions and advantages of the present invention clearer, the technical solutions in the present invention will be clearly and completely described below with reference to the accompanying drawings in the present invention. Obviously, the described embodiments are some but not all of the embodiments of the present invention. All other embodiments obtained by those of ordinary skill in the art based on the embodiments in the present invention without creative efforts shall fall within the protection scope of the present invention.

[0040] In view of the problem that the peak voltage cannot be effectively suppressed in the prior art, an embodiment of the present invention provides a peak voltage suppression circuit Figure 1 is a connection schematic diagram of the peak voltage suppression circuit provided by an embodiment of the present invention, as Figure 1 shown, the circuit includes:

[0041] An inverter circuit 110 for converting direct current into alternating current;

[0042] A freewheeling circuit 120, the freewheeling circuit 120 is connected to the inverter circuit 110 and is used to achieve soft switching when the switching tube in the inverter circuit 110 is turned off for freewheeling;

[0043] A voltage suppression circuit 130, the voltage suppression circuit 130 is used to perform voltage clamping on the peak voltage generated when the switching tube in the inverter circuit 110 is turned off; the voltage suppression circuit 130 includes a first clamping circuit 131 and a second clamping circuit 132, wherein:

[0044] The first end of the first clamping circuit 131 is connected to the first end of the freewheeling circuit 120, and the second end of the first clamping circuit 131 is connected to the third end of the second clamping circuit 132; the first clamping circuit 131 is used to perform voltage clamping on the first end of the freewheeling circuit 120;

[0045] The first end of the second clamping circuit 132 is connected to the second end of the freewheeling circuit 120, and the second end of the second clamping circuit 132 is connected to the third end of the freewheeling circuit 120.

[0046] Specifically, in the inverter circuit 110, direct current can be converted into alternating current to achieve the inversion of direct current. By modulating the switching tubes in the inverter circuit 110, that is, adjusting the states of the switching tubes in the inverter circuit 110, an output with a specific frequency and waveform can be achieved. During the modulation process of the switching tubes in the inverter circuit 110, since the switching tubes in the inverter circuit 110 operate in the hard-switching state, a large peak voltage will be generated at the moment when the switching tubes in the inverter circuit 110 are turned off. Therefore, in the embodiment of the present invention, after the switching tubes in the inverter circuit 110 are turned off, on the one hand, the freewheeling circuit 120, through the soft-switching function, while providing freewheeling for the load RL, effectively avoids the generation of new peak voltages during the modulation process of the switching tubes in the freewheeling circuit 120. On the other hand, the first clamping circuit 131 in the voltage suppression circuit 130 clamps the peak voltage, that is, by absorbing the peak voltage through the first clamping circuit 131, the peak voltage is limited within a specific range to prevent the switching tubes in the peak voltage suppression circuit 130 from being damaged due to excessive peak voltage.

[0047] It should be noted that the inverter circuit 110 and the freewheeling circuit 120 can form an improved Heric (High-efficient and reliable inverter concept topology). That is, in the prior art, both the freewheeling switching tube in Heric and the switching tubes in the full-bridge circuit operate in the hard-switching state, while in the embodiment of the present invention, the freewheeling switching tube in Heric in the prior art operates in the soft-switching state. Compared with the prior art, the generation of peak voltages during the switching process of the freewheeling switching tube is effectively avoided, that is, the peak voltage is reduced. In addition, the inverter circuit 110 can be the full-bridge circuit in the improved Heric. That is, the inverter circuit 110 includes four switching tubes, and all four switching tubes operate in the hard-switching state, and peak voltages will be generated during the switching process of the switching tubes.

[0048] Furthermore, Figure 2 is a schematic circuit diagram of the inverter circuit provided by the embodiment of the present invention. As Figure 2 shown, the inverter circuit 110 includes a DC power supply DC_BUS, a capacitor C1, a first inverter bridge arm 111, and a second inverter bridge arm 112, where:

[0049] The capacitor C1, the first inverter bridge arm 111, and the second inverter bridge arm 112 are connected in parallel with the DC power supply DC_BUS. The first inverter bridge arm 111 is connected to the first end of the soft-switching freewheeling bridge arm 121, the second inverter bridge arm 112 is connected to the second end of the soft-switching freewheeling bridge arm 121, and the second end of the first inverter bridge arm 111 is connected to the second end of the second inverter bridge arm 112.

[0050] Further, the first inverter bridge arm 111 includes an MOS transistor Q1 and an MOS transistor Q2. The drain of the MOS transistor Q1 serves as the first end of the first inverter bridge arm 111, and the source of the MOS transistor Q1 is connected to the drain of the MOS transistor Q2 and the first end of the soft-switching freewheeling bridge arm 121;

[0051] The second inverter bridge arm 112 includes an MOS transistor Q3 and an MOS transistor Q4. The drain of the MOS transistor Q3 serves as the first end of the second inverter bridge arm 112, and the source of the MOS transistor Q3 is connected to the drain of the MOS transistor Q4 and the second end of the soft-switching freewheeling bridge arm 121. The source of the MOS transistor Q2 is connected to the source of the MOS transistor Q4. The driving signals corresponding to the MOS transistor Q7 are respectively complementary in phase to the driving signals corresponding to the MOS transistor Q1 and the MOS transistor Q2. The MOS transistor Q1 and the MOS transistor Q4 are turned on synchronously. The MOS transistor Q2 and the MOS transistor Q3 are turned on synchronously. The turn-on moment of the MOS transistor Q5 is later than the turn-on moment of the MOS transistor Q1 to achieve soft switching of the MOS transistor Q5. The turn-on moment of the MOS transistor Q6 is later than the turn-on moment of the MOS transistor Q2 to achieve soft switching of the MOS transistor Q6.

[0052] Specifically, each of the first inverter bridge arm 111 and the second inverter bridge arm 112 includes two MOS transistors. The four MOS transistors are all N-channel MOS transistors, and body diodes are provided between the source and the drain of each of the four MOS transistors, and the body diodes point from the source to the drain. That is, as Figure 2As shown, a body diode DQ1 is provided between the source and drain of MOS transistor Q1. The positive electrode of body diode DQ1 is connected to the source of MOS transistor Q1, and the negative electrode of body diode DQ1 is connected to the drain of MOS transistor Q1; the positive electrode of body diode DQ2 is connected to the source of MOS transistor Q2, and the negative electrode of body diode DQ2 is connected to the drain of MOS transistor Q2; the positive electrode of body diode DQ3 is connected to the source of MOS transistor Q3, and the negative electrode of body diode DQ3 is connected to the drain of MOS transistor Q3; the positive electrode of body diode DQ4 is connected to the source of MOS transistor Q4, and the negative electrode of body diode DQ4 is connected to the drain of MOS transistor Q4. At the same time, in the first inverter leg 111 and the second leg, MOS transistors Q1 and Q4 are turned on synchronously, and MOS transistors Q2 and Q3 are turned on synchronously, that is, when MOS transistors Q1 and Q4 are turned on synchronously, MOS transistors Q2 and Q3 are both in the off state, and when MOS transistors Q2 and Q3 are turned on synchronously, MOS transistors Q1 and Q4 are both in the off state. When MOS transistors Q1 to Q4 are all in the off state, a continuous current is provided to load RL through freewheeling circuit 120 to avoid damage to load RL or data loss caused by sudden current interruption. It should be noted that the body diode between the source and drain of the MOS transistor is a characteristic of the MOS transistor itself, rather than a diode with an additional circuit connection designed.

[0053] Further, Figure 3 is a circuit schematic diagram of the freewheeling circuit provided by an embodiment of the present invention. As Figure 3 shown, the freewheeling circuit 120 includes a soft-switching freewheeling leg 121, an inductor L1, an inductor L2, and a capacitor C2, where:

[0054] The first end of the soft-switching freewheeling leg 121 is connected to one end of the inductor L1, the second end of the soft-switching freewheeling leg 121 is connected to one end of the inductor L2, the other end of the inductor L1 is connected to one end of the load RL and one end of the capacitor C2, and the other end of the inductor L1 serves as the second end of the freewheeling circuit 120. The other end of the capacitor C2 is connected to the other end of the load RL and the other end of the inductor L2, and the other end of the capacitor C2 serves as the third end of the freewheeling circuit 120.

[0055] Further, as Figure 3 shown, the soft-switching freewheeling leg 121 includes MOS transistors Q5 and Q6, where:

[0056] The source of the MOS transistor Q5 serves as the first end of the soft-switching freewheeling leg 121. The drain of the MOS transistor Q5 is connected to the drain of the MOS transistor Q6, and the drain of the MOS transistor Q5 serves as the first end of the freewheeling circuit 120. The source of the MOS transistor Q6 serves as the second end of the soft-switching freewheeling leg 121.

[0057] Specifically, both MOS transistors in the soft-switching freewheeling leg 121 are N-channel MOS transistors. Moreover, body diodes are provided between the source and drain of both MOS transistors, and the body diodes point from the source to the drain. That is, as Figure 3 shown, the positive electrode of the body diode DQ5 is connected to the source of the MOS transistor Q5, and the negative electrode of the body diode DQ5 is connected to the drain of the MOS transistor Q5; the positive electrode of the body diode DQ6 is connected to the source of the MOS transistor Q6, and the negative electrode of the body diode DQ6 is connected to the drain of the MOS transistor Q6. Meanwhile, in the soft-switching freewheeling leg 121, the MOS transistor Q5 and the MOS transistor Q6 do not conduct synchronously. That is, when the MOS transistor Q5 conducts, the MOS transistor Q6 is in the off state, and when the MOS transistor Q6 conducts, the MOS transistor Q5 is in the off state. After the MOS transistors Q1 and Q4 are in the off state, the MOS transistor Q6 uses the body diode DQ6 together with the voltage suppression circuit 130 to form a freewheeling path to freewheel for the load RL. After the MOS transistors Q2 and Q3 are in the off state, the MOS transistor Q5 uses the body diode DQ5 together with the voltage suppression circuit 130 to form a freewheeling path to freewheel for the load RL.

[0058] It should be noted that in the prior art, the MOS transistors Q1, Q4, and Q5 conduct synchronously. At this time, the MOS transistor Q5 operates in a hard-switching state, and a spike voltage will be generated during the switching process of the MOS transistor Q5. In the embodiment of the present invention, the drive signals corresponding to each MOS transistor are all rectangular pulse waves in the form of SPWM, and when the drive signals corresponding to the MOS transistors Q1, Q4, and Q5 are all output in the positive half cycle, Figure 4 is the drive signal waveform diagram of different MOS transistors provided by the embodiment of the present invention. As Figure 4As shown, after the MOS transistors Q1 and Q4 are turned on synchronously, the body diode DQ5 of the MOS transistor Q5 is turned on first, causing the voltage across the MOS transistor Q5 to drop to the diode voltage drop, enabling the MOS transistor Q5 to achieve zero-voltage turn-on. That is, the turn-on time of the MOS transistor Q5 is later than the turn-on times of the MOS transistors Q1 and Q4 by a time duration T1, causing the MOS transistor Q5 to operate in a soft-switching state, which can effectively avoid the generation of new spike voltages. After the MOS transistors Q2 and Q3 are turned on synchronously, the body diode DQ6 of the MOS transistor Q6 is turned on first, causing the voltage across the MOS transistor Q6 to drop to the diode voltage drop, enabling the MOS transistor Q6 to achieve zero-voltage turn-on. That is, the turn-on time of the MOS transistor Q6 is later than the turn-on times of the MOS transistors Q2 and Q3 by a time duration T3, causing the MOS transistor Q6 to operate in a soft-switching state, which can effectively avoid the generation of new spike voltages.

[0059] In addition, since it takes a certain amount of time for charge accumulation or dissipation during the state transition of the MOS transistor Q5 or Q6, there is a time delay during the transition from the on state to the off state, or from the off state to the on state. That is, there is a dead time T2 between the MOS transistors Q5 and Q6. For example, when the MOS transistor Q5 switches from the on state to the off state, the moment when the MOS transistor Q5 is completely turned off or the moment when the MOS transistor Q6 is turned on is the sum of the moment corresponding to the turn-off action of the MOS transistor Q5 and the dead time T2.

[0060] Furthermore, Figure 5 is one of the circuit schematic diagrams of the voltage suppression circuit provided by the embodiment of the present invention. As Figure 5 shown, the first clamping circuit 131 includes a capacitor C3. One end of the capacitor C3 serves as the first end of the first clamping circuit 131, and the other end of the capacitor C3 serves as the second end of the first clamping circuit 131. The capacitor C3 is used to clamp the voltage at the first end of the freewheeling circuit.

[0061] Specifically, after the MOS transistor Q1 is turned off and a spike voltage is generated, when there is a high voltage between the drain of the MOS transistor Q5 and the drain of the MOS transistor Q6, part of the spike voltage can be absorbed by the capacitor C3. And during the positive half-cycle when the MOS transistor Q5 is in the conducting state, the capacitor C3 can release part of the voltage through the MOS transistor Q5 to clamp the spike voltage after the MOS transistor Q1 is turned off, effectively suppressing the spike voltage. At the same time, the current released by the capacitor C3 can charge the inductor L1 for the load RL to use. In addition, after the MOS transistor Q2 is turned off and a spike voltage is generated, when there is a high voltage between the drain of the MOS transistor Q5 and the drain of the MOS transistor Q6, part of the spike voltage can be absorbed by the capacitor C3. And during the negative half-cycle when the MOS transistor Q6 is in the conducting state, the capacitor C3 can release part of the voltage through the MOS transistor Q6 to clamp the spike voltage after the MOS transistor Q2 is turned off, effectively suppressing the spike voltage. At the same time, the current released by the capacitor C3 can charge the inductor L2 for the load RL to use.

[0062] Further, as Figure 5 shown, the first clamping circuit 131 further includes an MOS transistor Q7 and a resistor R1, where:

[0063] The drain of the MOS transistor Q7 is connected to one end of the capacitor C3, one end of the resistor R1 is connected to the other end of the capacitor C3, and the source of the MOS transistor Q7 is connected to the other end of the resistor R1.

[0064] Specifically, in the first clamping circuit 131, the MOS transistor Q7 is an N-channel MOS transistor, and a body diode DQ7 is provided between the source and the drain of the MOS transistor Q7. The positive electrode of the body diode DQ7 is connected to the source of the MOS transistor Q7, and the negative electrode of the body diode DQ7 is connected to the drain of the MOS transistor Q7. In addition, as Figure 4 shown, the Q7 drive signal corresponding to the MOS transistor Q7 is output in the full cycle. When the MOS transistors Q1 to Q4 are all in the off state, while clamping the spike voltage through the voltage suppression circuit 130, the freewheeling path is extended, further improving the freewheeling efficiency, and at the same time, improving the quality of the output waveform.

[0065] Further, as Figure 5 shown, the second clamping circuit 132 includes a diode D1 and a diode D2, where:

[0066] The negative electrode of the diode D1 serves as the first end of the second clamping circuit 132, the positive electrode of the diode D1 is connected to the positive electrode of the diode D2, and the positive electrode of the diode D1 serves as the third end of the second clamping circuit 132, and the negative electrode of the diode D2 serves as the second end of the second clamping circuit 132.

[0067] For example, MOS transistor Q1 and MOS transistor Q2 control their respective states according to Figure 4 the SPWM waveform shown, and MOS transistors Q3, Q4, Q5, and Q6 control their respective states according to Figure 4 the sine period shown. The spike voltage suppression circuit 130 has four operating modes during the inversion process, where:

[0068] (1) Figure 6 is one of the circuit schematic diagrams of the spike voltage suppression circuit provided by the embodiment of the present invention. As Figure 6 shown, during the positive half cycle of the inverter output, that is, when MOS transistor Q1 and MOS transistor Q4 are turned on, and MOS transistors Q2 and Q3 are turned off, after the DC power supply DC_BUS outputs current, there are two current paths. One is that the output current flows through MOS transistor Q1, inductor L1, load RL, and inductor L2 in sequence, and the other is that the output current flows through MOS transistor Q1, body diode DQ5, capacitor C3, diode D2, and inductor L2 in sequence. Among them, the body diode DQ5, capacitor C3, and diode D2, and inductor L1 and capacitor C2 form a π-type filter. In addition, after MOS transistor Q1 is turned on, the body diode DQ5 is turned on first, so that the voltage across MOS transistor Q5 is the conduction voltage of the body diode DQ5, making MOS transistor Q5 turn on with zero voltage. And after MOS transistor Q5 is turned on, it charges capacitor C3, and the maximum charging voltage value of capacitor C3 is the output voltage value of the DC power supply DC_BUS. For example, if the output voltage of the DC power supply DC_BUS is 400V, then when charging capacitor C3, the maximum charging voltage value of capacitor C3 is 400V.

[0069] (2) Figure 7 is the second circuit schematic diagram of the spike voltage suppression circuit provided by the embodiment of the present invention. As Figure 7As shown, when MOS transistor Q1 and MOS transistor Q4 are turned off, in order to avoid damage to the device of load RL or data loss, freewheeling can be carried out through freewheeling circuit 120 and voltage suppression circuit 130. Among them, when inductor L2 freewheels, body diode DQ6 and MOS transistor Q7 are turned on. MOS transistor Q6 uses body diode DQ6 to form a freewheeling path, that is, body diode DQ6, MOS transistor Q7, resistor R1 and diode D1 form a freewheeling path. At the same time, body diode DQ6, MOS transistor Q7, resistor R1 and diode D2 form a supplementary freewheeling path for inductor L2. At this time, if a spike voltage is generated when MOS transistor Q1 is turned off, causing a high voltage at the drain of MOS transistor Q6, on the one hand, part of the spike voltage can be reduced through MOS transistor Q7 and resistor R1. On the other hand, capacitor C3 absorbs part of the spike voltage, and when the drain voltage of MOS transistor Q6 is relatively small, through the loop formed by capacitor C3, MOS transistor Q7 and resistor R1, the voltage in capacitor C3 is released, so that the voltage of capacitor C3 is within a stable voltage range, that is, the drain voltage of MOS transistor Q6 is clamped through capacitor C3, MOS transistor Q7, resistor R1 and diode D2, that is, the spike voltage generated when MOS transistor Q1 is turned off is clamped, realizing effective suppression of the spike voltage. In addition, the clamping voltage can also be adjusted by adjusting the values of capacitor C3 and resistor R1, that is, adjusting the suppression effect of the spike voltage, so as to ensure the smooth realization of the soft-switching state of the soft-switching freewheeling bridge arm 121 in freewheeling circuit 120 during switch switching.

[0070] For example, taking the case where capacitor C3 is charged to 400V in the positive half-cycle and the voltage range of capacitor C3 is [340V, 380V] as an example, if no spike voltage is generated after MOS transistor Q1 is turned off, during freewheeling, MOS transistor Q7 is turned on, and capacitor C3 releases part of the voltage through MOS transistor Q7 and resistor R1. After releasing the voltage, the voltage of capacitor C3 is 350V. In the next positive half-cycle, capacitor C3 is charged to 400V again. If a spike voltage is generated after MOS transistor Q1 is turned off, during freewheeling, the drain voltage of MOS transistor Q6 is relatively high, and part of the spike voltage is absorbed by capacitor C3, making the voltage of capacitor C3 reach 430V. At the same time, after the spike voltage becomes smaller, capacitor C3 releases part of the voltage through MOS transistor Q7 and resistor R1. After releasing the voltage, the voltage of capacitor C3 decreases to 370V. Repeating the above steps, the voltage of capacitor C3 can be stabilized within the range of [340V, 380V], and the spike voltage is less than or equal to the maximum value of the voltage of capacitor C3 and the output voltage after being absorbed and released by capacitor C3 and resistor R1. The clamped spike voltage is equal to the sum of the voltage of capacitor C3 and λV, and the magnitude of this λV is determined by the energy absorbed and released by capacitor C3 and resistor R1.

[0071] (3) During the negative half-cycle of the inverter output, when MOS transistor Q1 and MOS transistor Q4 are turned off, and MOS transistor Q2 and MOS transistor Q3 are turned on, after the DC power supply DC_BUS outputs current, there are two current paths. One is that the output current flows through MOS transistor Q3, inductor L2, load RL, and inductor L1 in sequence. The other is that the output current flows through MOS transistor Q3, body diode DQ6, capacitor C3, diode D1, and inductor L1 in sequence. Among them, the body diode DQ6, capacitor C3, and diode D1, as well as inductor L2 and capacitor C2 form a π-type filter. In addition, after MOS transistor Q2 is turned on, the body diode DQ6 is turned on first, making the voltage across MOS transistor Q6 the conduction voltage of the body diode DQ6, so that MOS transistor Q6 is turned on with zero voltage. And after MOS transistor Q6 is turned on, it charges capacitor C3, and the maximum charging voltage value of capacitor C3 is the output voltage value of the DC power supply DC_BUS. It should be noted that during the zero-crossing switching between the positive and negative half-cycles of the inverter output, due to the need for a certain time for charge accumulation or dissipation, therefore, MOS transistor Q6 will not be turned on until MOS transistor Q5 is turned off and after the dead time T2.

[0072] (4) When MOS transistor Q2 and MOS transistor Q3 are turned off, to avoid damage to the equipment of load RL or data loss, a freewheeling circuit 120 and a voltage suppression circuit 130 can be used for freewheeling. Among them, when inductor L1 freewheels, body diode DQ5 and MOS transistor Q7 are turned on. MOS transistor Q5 uses the body diode DQ5 to form a freewheeling path, that is, the body diode DQ5, MOS transistor Q7, resistor R1, and diode D2 form a freewheeling path. At the same time, the body diode DQ5, MOS transistor Q7, resistor R1, and diode D1 form a supplementary freewheeling path for inductor L1. At this time, if a spike voltage is generated when MOS transistor Q2 is turned off, causing a high voltage at the drain of MOS transistor Q5, on the one hand, part of the spike can be reduced through MOS transistor Q7 and resistor R1. On the other hand, capacitor C3 absorbs part of the spike voltage, and when the drain voltage of MOS transistor Q5 is small, through the loop formed by capacitor C3, MOS transistor Q7, and resistor R1, the voltage in capacitor C3 is released, so that the voltage of capacitor C3 is within a stable voltage range, that is, the drain voltage of MOS transistor Q5 is clamped through capacitor C3, MOS transistor Q7, resistor R1, and diode D1, that is, the spike voltage generated when MOS transistor Q2 is turned off is clamped, realizing effective suppression of the spike voltage. In addition, the clamping voltage can also be adjusted by adjusting the values of capacitor C3 and resistor R1, that is, adjusting the suppression effect of the spike voltage, so as to ensure the smooth realization of the soft-switching state of the soft-switching freewheeling bridge arm 121 in the freewheeling circuit 120 during switch switching.

[0073] In addition, Figure 8 is the second circuit schematic diagram of the voltage suppression circuit provided by the embodiment of the present invention, as Figure 8As shown, the second clamping circuit 132 includes MOS transistor Q8 and MOS transistor Q9, where:

[0074] The drain of the MOS transistor Q8 serves as the first end of the second clamping circuit 132. The source of the MOS transistor Q8 is connected to the source of the MOS transistor Q9, and the drain of the MOS transistor Q9 serves as the second end of the second clamping circuit 132.

[0075] Specifically, the second clamping circuit 132 in combination with the first clamping circuit 131 can clamp the spike voltage. The second clamping circuit 132 may further include MOS transistor Q8 and MOS transistor Q9. Both MOS transistor Q8 and MOS transistor Q9 are N-channel MOS transistors, and body diodes are provided between the source and the drain of both transistors. Moreover, the orientation of the body diode DQ8 corresponding to the MOS transistor Q8 is the same as that of the diode D2, and the orientation of the body diode DQ9 corresponding to the MOS transistor Q9 is the same as that of the diode D1. That is, the positive electrode of the body diode DQ8 is connected to the source of the MOS transistor Q8, the negative electrode of the body diode DQ8 is connected to the drain of the MOS transistor Q8, the positive electrode of the body diode DQ9 is connected to the source of the MOS transistor Q9, and the negative electrode of the body diode DQ9 is connected to the drain of the MOS transistor Q9.

[0076] In the spike voltage suppression circuit 130 provided by the present invention, during the AC-DC conversion process of the inverter circuit 110, through the soft-switching function of the freewheeling circuit 120, the generation of spike voltage is effectively avoided. And during the freewheeling process of the freewheeling circuit 120, through the first clamping circuit 131 in the voltage suppression circuit 130, the spike voltage generated when the switch of the inverter circuit 110 is turned off is further voltage-clamped, so that the spike voltage is maintained within a stable range, effectively suppressing the spike voltage, reducing the switching loss while avoiding overvoltage damage to the switching tube. In addition, by adding a freewheeling path to the inverter through the voltage suppression circuit 130, the freewheeling efficiency can be improved and the output waveform quality can be improved.

[0077] The embodiment of the present invention further provides an inverter, which includes a control circuit and the spike voltage suppression circuit 130 as described in any one of the above. The control circuit is connected to the spike voltage suppression circuit 130, and the control circuit is used to control the state of the switching tube in the spike voltage suppression circuit 130 to achieve the purpose of converting direct current into alternating current.

[0078] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that they can still modify the technical solutions described in the foregoing embodiments, or perform equivalent replacements for some of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A peak voltage suppression circuit, characterized in that, it includes: an inverter circuit for converting direct current into alternating current; a freewheeling circuit, the freewheeling circuit is connected to the inverter circuit and is used to achieve soft switching when the switching tube in the inverter circuit is turned off for freewheeling; a voltage suppression circuit for voltage clamping the peak voltage generated when the switching tube in the inverter circuit is turned off; the voltage suppression circuit includes a first clamping circuit and a second clamping circuit, where: the first end of the first clamping circuit is connected to the first end of the freewheeling circuit, and the second end of the first clamping circuit is connected to the third end of the second clamping circuit; the first clamping circuit is used to voltage clamp the first end of the freewheeling circuit; the first end of the second clamping circuit is connected to the second end of the freewheeling circuit, and the second end of the second clamping circuit is connected to the third end of the freewheeling circuit.

2. The peak voltage suppression circuit according to claim 1, characterized in that, the first clamping circuit includes a capacitor C3, one end of the capacitor C3 is used as the first end of the first clamping circuit, and the other end of the capacitor C3 is used as the second end of the first clamping circuit. The capacitor C3 is used to voltage clamp the first end of the freewheeling circuit.

3. The peak voltage suppression circuit according to claim 2, characterized in that, the first clamping circuit further includes a MOS transistor Q7 and a resistor R1, where: the drain of the MOS transistor Q7 is connected to one end of the capacitor C3, one end of the resistor R1 is connected to the other end of the capacitor C3, and the source of the MOS transistor Q7 is connected to the other end of the resistor R1.

4. The peak voltage suppression circuit according to any one of claims 1-3, characterized in that, the second clamping circuit includes a diode D1 and a diode D2, where: the negative electrode of the diode D1 is used as the first end of the second clamping circuit, the positive electrode of the diode D1 is connected to the positive electrode of the diode D2, and the positive electrode of the diode D1 is used as the third end of the second clamping circuit, and the negative electrode of the diode D2 is used as the second end of the second clamping circuit.

5. The peak voltage suppression circuit according to any one of claims 1-3, characterized in that, the second clamping circuit includes a MOS transistor Q8 and a MOS transistor Q9, where: the drain of the MOS transistor Q8 is used as the first end of the second clamping circuit, the source of the MOS transistor Q8 is connected to the source of the MOS transistor Q9, and the drain of the MOS transistor Q9 is used as the second end of the second clamping circuit.

6. The peak voltage suppression circuit according to claim 3, characterized in that, the freewheeling circuit includes a soft-switching freewheeling bridge arm, an inductor L1, an inductor L2 and a capacitor C2, where: One end of the soft-switching freewheeling bridge arm is connected to one end of the inductor L1, and the second end of the soft-switching freewheeling bridge arm is connected to one end of the inductor L2. The other end of the inductor L1 is connected to one end of the load and one end of the capacitor C2, and the other end of the inductor L1 serves as the second end of the freewheeling circuit. The other end of the capacitor C2 is connected to the other end of the load and the other end of the inductor L2, and the other end of the capacitor C2 serves as the third end of the freewheeling circuit.

7. The spike voltage suppression circuit according to claim 6, wherein, the soft-switching freewheeling bridge arm includes MOS transistor Q5 and MOS transistor Q6, where: the source electrode of the MOS transistor Q5 serves as the first end of the soft-switching freewheeling bridge arm, the drain electrode of the MOS transistor Q5 is connected to the drain electrode of the MOS transistor Q6, and the drain electrode of the MOS transistor Q5 serves as the first end of the freewheeling circuit, and the source electrode of the MOS transistor Q6 serves as the second end of the soft-switching freewheeling bridge arm.

8. The spike voltage suppression circuit according to claim 7, wherein, the inverter circuit includes a DC power supply, a capacitor C1, a first inverter bridge arm, and a second inverter bridge arm, where: the capacitor C1, the first inverter bridge arm, and the second inverter bridge arm are connected in parallel with the DC power supply, and the first inverter bridge arm is connected to the first end of the soft-switching freewheeling bridge arm, the second inverter bridge arm is connected to the second end of the soft-switching freewheeling bridge arm, and the second end of the first inverter bridge arm is connected to the second end of the second inverter bridge arm.

9. The spike voltage suppression circuit according to claim 8, wherein, the first inverter bridge arm includes MOS transistor Q1 and MOS transistor Q2. The drain electrode of the MOS transistor Q1 serves as the first end of the first inverter bridge arm, and the source electrode of the MOS transistor Q1 is connected to the drain electrode of the MOS transistor Q2 and the first end of the soft-switching freewheeling bridge arm; the second inverter bridge arm includes MOS transistor Q3 and MOS transistor Q4. The drain electrode of the MOS transistor Q3 serves as the first end of the second inverter bridge arm, and the source electrode of the MOS transistor Q3 is connected to the drain electrode of the MOS transistor Q4 and the second end of the soft-switching freewheeling bridge arm. The source electrode of the MOS transistor Q2 is connected to the source electrode of the MOS transistor Q4. The drive signals corresponding to the MOS transistor Q7 are respectively complementary in phase to the drive signals corresponding to the MOS transistor Q1 and the MOS transistor Q2; the MOS transistor Q1 and the MOS transistor Q4 are turned on synchronously, the MOS transistor Q2 and the MOS transistor Q3 are turned on synchronously, and the turn-on moment of the MOS transistor Q5 is later than the turn-on moment of the MOS transistor Q1 to achieve soft switching of the MOS transistor Q5; the turn-on moment of the MOS transistor Q6 is later than the turn-on moment of the MOS transistor Q2 to achieve soft switching of the MOS transistor Q6.

10. An inverter, wherein, it includes a control circuit and the spike voltage suppression circuit according to any one of claims 1-9. The control circuit is connected to the spike voltage suppression circuit, and the control circuit is used to control the states of the switching transistors in the spike voltage suppression circuit.

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