Digital peak current control method of three-level flying capacitor buck converter

Abstract

The invention discloses a digital peak current control method for a three-level flying capacitor buck converter, and the method comprises the following steps: analyzing the working mechanism of a three-level flying capacitor buck converter circuit, including the on-off logic of a switching device, four static working modes, and two dynamic working switching modes; taking one static working mode point (1, 0) as an example to analyze the influence of flying capacitor voltage balance on the normal operation of the circuit; the invention provides a pure digital control strategy aiming at an inductive current peak value aiming at the voltage balance problem of two ends of a flying capacitor of a three-level flying capacitor buck converter circuit. An improved digital control strategy is provided; carrying out stability analysis on the algorithm; for the problem of sub-harmonic oscillation, a digital slope compensation technology is introduced to eliminate the problem of sub-harmonic oscillation in the algorithm.

Description

Technical Field

[0001] The present invention belongs to the technical field of power electronics, and particularly relates to a digital peak current control method for a three-level flying capacitor buck converter. Background Art

[0002] Compared with the traditional two-level Buck circuit, the three-level flying capacitor buck converter (3L-FCBC) has the direct advantages of halving the stress borne by the switching devices, halving the voltage swing of the filter inductor, doubling the output voltage frequency, and reducing the volume of magnetic components. The problem of flying capacitor voltage imbalance is a major challenge in the topology design of 3L-FCBC. Currently, there has emerged a technology for balancing the flying capacitor voltage of 3L-FCBC based on the inductor current ripple, but its control is still analog control. Analog control will lead to an increase in the required hardware devices, an increase in circuit complexity, and limited control diversity. Summary of the Invention

[0003] In view of the fact that the peak current control currently used to balance the flying capacitor voltage is mostly analog control, the present invention proposes a digital peak current control method for a three-level flying capacitor buck converter, which reduces the circuit complexity and makes it possible to enhance control diversity.

[0004] To solve the above technical problems, the present invention adopts the following technical solutions:

[0005] A digital peak current control method for a three-level flying capacitor buck converter includes the following steps:

[0006] Analyze the working mechanism of the three-level flying capacitor buck converter circuit, including the on-off logic of each switching device during normal circuit operation, 4 static working modes, and 2 dynamic working switching modes. Among them, the on-off logic of each switching device during normal operation includes: the first switching device Q 1 and the fourth switching device Q 4 conduct complementarily, the second switching device Q 2 and the third switching device Q 3 conduct complementarily, and the first switching device Q 1 and the second switching device Q 2 exhibit an interleaved conduction characteristic with a phase difference of 180°; the 4 static working modes include: taking the coordinate sequence (Q 1 , Q 2 ) composed of the first switching device and the second switching device as a reference, and are respectively denoted as state Ⅰ, state Ⅱ, state Ⅲ, and state Ⅳ. The coordinate sequence (Q 1 , Q 2Correspond to (1, 0), (0, 0), (0, 1), and (1, 1) respectively; the two dynamic working switching modes include: dividing the dynamic switching process of the circuit operation into two working modes according to the range of the voltage conversion ratio G, where the voltage conversion ratio G is the ratio of the output voltage V o to the input voltage V g respectively. Specifically, in Mode 1 where G < 0.5, the static working modes of the circuit sequentially switch in the order of Ⅰ→Ⅱ→Ⅲ→Ⅱ; in Mode 2 where G > 0.5, the static working modes of the circuit sequentially switch in the order of Ⅳ→Ⅰ→Ⅳ→Ⅲ;

[0007] Taking one of the static working mode points (1, 0) as an example, analyze the influence of the flying capacitor voltage balance on the normal operation of the circuit;

[0008] Regarding the voltage balance problem at both ends of the flying capacitor in the three-level flying capacitor buck converter circuit, a pure digital control strategy for the peak inductor current is proposed, that is, the peak current control technology based on the digital voltage outer loop and digital current inner loop feedback;

[0009] And to overcome the delay in one output change cycle, an improved digital control strategy is proposed; then the stability of the algorithm is analyzed;

[0010] Regarding the digital control algorithm with sub-harmonic oscillation, a solution strategy is proposed, introducing the digital ramp compensation technology to eliminate the sub-harmonic oscillation problem existing in the algorithm; further analyze whether the digital peak current has the characteristic of self-balancing of the flying capacitor after the sub-harmonic oscillation is eliminated.

[0011] In a possible implementation manner, the three-level flying capacitor buck converter includes a DC input voltage source V g , a flying capacitor C fly , a bridge arm composed of switching devices, a filter inductor L o , an output capacitor C o , and a DC output terminal. The DC input voltage source V g is connected in parallel with a bridge arm composed of four switching devices Q 1 , Q 2 , Q 3 , Q 4 connected in series. The flying capacitor C fly is connected in parallel across the series branch composed of Q 2 and Q 3 . The series branch composed of the filter inductor L o and the output capacitor C o is connected in parallel with the series branch composed of Q 3 and Q 4 . The output capacitor C o is connected in parallel with the DC output terminal. Brief Description of the Drawings

[0012] Figure 1 is the basic circuit architecture of a three-level flying capacitor buck converter;

[0013] Figure 2 are the 4 static operating modes of the three-level flying capacitor buck converter and the corresponding equivalent circuit diagrams;

[0014] Figure 3 are the output waveform diagrams under 2 dynamic operating switching modes of the three-level flying capacitor buck converter;

[0015] Figure 4 is the digital control system architecture of the three-level flying capacitor buck converter described in the present invention;

[0016] Figure 5 is the digital peak current control waveform diagram under the leading-edge modulation method when G < 0.5;

[0017] Figure 6 is the digital peak current control waveform diagram under the trailing-edge modulation method when G < 0.5;

[0018] Figure 7 is the digital peak current control waveform diagram under the triangular leading-edge modulation method when G < 0.5;

[0019] Figure 8 is the digital peak current control waveform diagram under the triangular trailing-edge modulation method when G < 0.5;

[0020] Figure 9 is the schematic diagram of the digital circuit timing of the leading-edge modulation;

[0021] Figure 10 is the improved digital peak current control waveform diagram under the leading-edge modulation method when G < 0.5;

[0022] Figure 11 is the improved digital peak current control waveform diagram under the trailing-edge modulation method when G < 0.5;

[0023] Figure 12 is the improved digital peak current control waveform diagram under the trailing-edge modulation method with slope compensation when G < 0.5;

[0024] Figure 13 is the output waveform diagram of the improved digital peak current control with slope compensation under the leading-edge modulation method when G < 0.5 and there is a small disturbance in the flying capacitor voltage. Specific implementation manners

[0025] Next, the technical solutions in the embodiments of the present invention will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, rather than all of the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts belong to the scope of protection of the present invention.

[0026] A digital peak current control method for a three-level flying capacitor buck converter according to an embodiment of the present invention includes the following steps:

[0027] Analyze the working mechanism of the three-level flying capacitor buck converter circuit, including the on-off logic of each switching device during normal circuit operation, 4 static working modes, and 2 dynamic working switching modes: the on-off logic of each switching device during normal operation, characterized in that the first switching device Q 1 and the fourth switching device Q 4 conduct complementarily, the second switching device Q 2 and the third switching device Q 3 conduct complementarily, and the first switching device Q 1 and the second switching device Q 2 exhibit an interleaved conduction characteristic with a phase difference of 180°; 4 static working modes, characterized in that, described with the coordinate sequence (Q 1 , Q 2 ) formed by the first switching device and the second switching device as the standard, are respectively denoted as state I, state II, state III, and state IV, and the coordinate sequence (Q 1 , Q 2 ) corresponds to (1, 0), (0, 0), (0, 1), and (1, 1) respectively; 2 dynamic working switching modes, characterized in that according to the range of the voltage conversion ratio G, the dynamic switching process of the circuit operation is divided into two working modes, and the voltage conversion ratio G is the ratio of the output voltage V o to the input voltage V g , which are respectively mode 1, that is, when G < 0.5, the static working modes of the circuit are sequentially switched in the order of I → II → III → II; mode 2, that is, when G > 0.5, the static working modes of the circuit are sequentially switched in the order of IV → I → IV → III;

[0028] Taking one of the static working mode points (1, 0) as an example, analyze the influence of the flying capacitor voltage balance on the normal operation of the circuit. If the voltage across the flying capacitor cannot reach the steady-state value, the voltage imbalance problem of the series devices will be highlighted;

[0029] Aiming at the voltage balance problem of the flying capacitor at both ends of the three-level flying capacitor buck converter circuit, a pure digital control strategy for the peak inductor current is proposed, that is, a peak current control technology based on digital voltage outer loop and digital current inner loop feedback;

[0030] To overcome the delay in one output change cycle, an improved digital control strategy is proposed; then the stability of the algorithm is analyzed.

[0031] For a digital control algorithm with sub - harmonic oscillation, a solution strategy is proposed. The digital ramp compensation technique is introduced to eliminate the sub - harmonic oscillation problem in the algorithm; further analyze whether the digital peak current has the characteristic of flying - capacitor self - balancing after the sub - harmonic oscillation is eliminated.

[0032] In a specific embodiment of the present invention, as Figure 1 shown, the basic circuit structure of the three - level flying - capacitor buck converter is as follows. The circuit mainly includes a DC input voltage source V g , a flying capacitor C fly , a bridge arm composed of switching devices, a filter inductor L o , an output capacitor C o and a DC output terminal. The DC input voltage source V g is connected in parallel with a bridge arm composed of four switching devices Q 1 , Q 2 , Q 3 , Q 4 connected in series. The flying capacitor C fly is connected in parallel across the series branch composed of Q 2 and Q 3 . The series branch composed of the filter inductor L o and the output capacitor C o is connected in parallel with the series branch composed of Q 3 and Q 4 . The output capacitor C o is connected in parallel with the DC output terminal. In an exemplary embodiment of the present invention, the DC output terminal takes a parallel pure - resistive load R as an example, and the voltage across the pure - resistive load R is denoted as the output voltage v o . For the convenience of subsequent description, Figure 1 key measurement points are marked: the voltage across the series branch composed of the switching devices Q 3 and Q 4 is defined as the switching - node voltage V sw . At the same time, the reference current directions of the flying capacitor C fly and the filter inductor L o are as shown in Figure 1 to assist in explaining the operation principle and dynamic behavior of the circuit.

[0033] In a specific application example, for the above-mentioned three-level flying capacitor buck converter circuit, analyzing its working mechanism includes the conduction logic of each switching device when the circuit is operating normally; four static operating modes; and two dynamic operating switching modes. Among them, analyzing the conduction logic of each switching device when the three-level flying capacitor buck converter circuit is operating normally specifically includes that the first switching device Q 1 and the fourth switching device Q 4 conduct complementarily, the second switching device Q 2 and the third switching device Q 3 conduct complementarily. Complementary conduction means that when one device in a pair conducts, the other is in the off state, and vice versa. In addition, when the three-level flying capacitor buck converter circuit reaches a steady state, the first switching device Q 1 and the second switching device Q 2 exhibit an interleaved conduction characteristic with a phase difference of 180°.

[0034] Furthermore, analyzing Figure 1 the four static operating modes existing in the three-level flying capacitor buck converter circuit shown specifically includes that due to the complementary conduction characteristic of the switching devices in the three-level flying capacitor buck converter, there are two degrees of freedom in controlling the conduction and cutoff of the four switching devices. For example, when the on-off states of the first switching device Q 1 and the second switching device Q 2 are determined, the on-off states of the third switching device Q 3 and the fourth switching device Q 4 are also determined immediately. If a certain switching device conducts, it is denoted as Q n =1 (where n = 1, 2, 3, 4); if a certain switching device is cutoff, it is denoted as Q n =0 (where n = 1, 2, 3, 4). In an example of the present invention, the first switching device Q 1 and the second switching device Q 2 are taken as examples for illustration, but the embodiments of the present invention are not limited thereto. Q 1 has two on-off states, namely Q 1 =1 or Q 1 =0. At the same time, Q 2 has two on-off states, namely Q 2 =1 or Q 2 =0. If the conduction state of the first switching device Q 1 is taken as the abscissa and the conduction state of the second switching device Q 2 is taken as the ordinate to form a coordinate sequence (Q 1 , Q 2 ), and the circuit is described based on this coordinate sequence, there are four static operating modes, which are respectively denoted as state I, state II, state III, and state IV. The coordinate sequence (Q 1 , Q2 ) respectively correspond to (1, 0), (0, 0), (0, 1), (1, 1), and the equivalent circuit diagrams corresponding to the four static working modes are as Figure 2 shown.

[0035] Furthermore, analyzing Figure 1 the two dynamic working switching modes existing in the three-level flying capacitor buck converter circuit shown specifically include, defining the ratio of the output voltage V o to the input voltage V g as the voltage conversion ratio G, that is Ideally, G is equal to the conduction duty cycles D 1 and D 2 of Q 1 and Q 2 . Due to the interleaved conduction characteristics of the switching devices in the three-level flying capacitor buck converter, the circuit will exhibit two different dynamic working switching modes because the range of the voltage conversion ratio G is within one switching period T s . As Figure 3 shown, the two dynamic working switching modes are respectively: Mode 1: When G < 0.5, Figure 2 the static working modes of the circuit described are sequentially switched in the order of I → II → III → II; Mode 2: When G > 0.5, Figure 2 the static working modes of the circuit described are sequentially switched in the order of IV → I → IV → III. When working in both modes, the output voltage will change twice within one switching period (T s ), and the output voltage change period is denoted as T s .

[0036] In a specific application example, taking one of the static working mode points (1, 0) as an example to analyze the impact of the flying capacitor voltage balance on the normal operation of the circuit specifically includes, taking the circuit working mode of (Q 1 , Q 2 ) = (1, 0) as an example for detailed description, but the embodiments of the present invention are not limited thereto. For Figure 1 the three-level flying capacitor buck converter circuit, the input voltage V g forms a first switching loop with the first switching device Q 1 , the flying capacitor C fly and the fourth switching device Q 4 ; at the same time, the flying capacitor C fly forms a second switching loop with the second switching device Q 2 and the third switching device Q 3 . Referring to Figure 2 the static working state at the (1, 0) coordinate point, that is, when the first switching device Q 1 is conducting and the second switching device Q 2When turned off, correspondingly, the fourth switching device Q 4 is turned off and the third switching device Q 3 is turned on. The equivalent circuit is as shown in Figure 2 State Ⅰ. In the first switching loop, the following equation exists for the voltage relationship. Denote the voltage across the flying capacitor C fly as v fly , and the voltage across the fourth switching device Q 4 as

[0037]

[0038] In the second switching loop, the following equation exists for the voltage relationship. Denote the voltage across the second switching device Q 2 as

[0039]

[0040] It can be seen from Equation (1) and Equation (2) that if the voltage v fly across the flying capacitor C fly can reach the steady-state value, that is then the voltage drops of the second switching device Q 2 and the fourth switching device Q 4 are equal and only half of the input voltage V g . Conversely, if the voltage v fly across the flying capacitor C fly cannot reach the steady-state value, that is, the situation of or occurs, it will all lead to not being equal to . If the voltage imbalance problem of the series devices exists for a long time, it will not only exacerbate the instability of the flying capacitor voltage, cause charge and discharge imbalance, and ultimately lead to the imbalance of the three-level flying capacitor buck converter system and the loss of its circuit function. Therefore, for the three-level flying capacitor buck converter circuit shown in Figure 1 , controlling the voltage v fly across the flying capacitor C fly to reach balance is particularly important for realizing the normal operation of this circuit and giving full play to the key advantages of this topology.

[0041] In specific application examples, for the problem of voltage balance across the flying capacitor of the three-level flying capacitor buck converter circuit shown in Figure 1 , a pure digital control strategy for the peak inductor current is proposed, that is, the peak current control technology based on digital voltage outer loop and digital current inner loop feedback, which specifically includes the control system architecture, control principle, control process, and control algorithm.

[0042] Furthermore, the present invention proposes a digital control system architecture for a three-level flying capacitor buck converter, characterized in that as shown in Figure 4 , it is composed of a three-level flying capacitor buck converter circuit and a digital controller. An analog-to-digital converter (ADC), a discrete proportional-integral-derivative (D-PID) compensator, and a digital pulse width modulator (DPWM) are integrated in the digital controller. Specifically, the output voltage port of the three-level flying capacitor buck converter circuit and the drive signal port for controlling the states of four switching devices are respectively connected to the digital controller.

[0043] Furthermore, the control principle of the present invention is based on the analysis shown in Figure 4 , which is an extension of the basic circuit of the three-level flying capacitor buck converter shown in Figure 1 . Specifically, when the equivalent series resistance R on the branch of the output capacitor C o is significantly smaller than the load resistance R, that is, R e << R, then the high-frequency varying inductor current ripple Δi on the inductor e completely flows through the output capacitor C L and discharges the output capacitor C o through the series resistance R e , thereby generating a voltage drop Δi o on R e that is the same as the slope of the inductor current. When the capacitance of C L is very large, its voltage V e can be considered constant, then the output voltage is composed of a constant quantity and a ripple quantity, that is, V o = V cap + Δi o R cap . The ripple change trend of the output voltage V L will change with the change of the inductor current ripple Δi e . The digital controller senses the change of the output voltage V o ripple and reacts accordingly by combining the algorithm proposed in the present invention to generate corresponding drive signals to control the on / off of the switching devices in the circuit, thereby achieving the target output.

[0044] Furthermore, the control process of the present invention specifically includes the following steps: The analog-to-digital conversion (ADC) module in the digital controller samples the output voltage V L to obtain a digitized sampled value v o . A reference voltage V o stored in digital form is preset in the system. This reference voltage and the sampled output voltage v o obtained by sampling ref o ​Compare them to generate an error signal. This error signal is then fed into a discrete proportional integral derivative (D-PID) control module to generate a corresponding voltage control signal v pi . Then, a digital pulse width modulation (DPWM) module, based on the sampled value v o of the output voltage at the current moment and the voltage control signal v pi generated by the D-PID module, combines with the specific algorithm proposed in the present invention to calculate the switching duty cycle required by the circuit. Based on this calculation result, the DPWM module outputs drive signals with high and low levels at different time intervals to precisely control the on and off states of four switching devices, thereby effectively regulating the output voltage.

[0045] Furthermore, the present invention elaborates on the control algorithm, specifically including the implementation of the digital peak current control algorithm under leading edge, trailing edge, triangular leading edge, and triangular trailing edge modulations, and taking the three-level flying capacitor buck converter operating in Mode 1, i.e., G < 0.5 as an example, but the embodiments of the present invention are not limited thereto.

[0046] As Figure 5 shown, when the inductor current operates in the continuous conduction mode (within one switching period, the inductor current does not reach 0), the control waveforms of the digital peak current control three-level flying capacitor buck converter under the leading edge modulation mode when operating under the condition of G < 0.5 are presented. Among them, m 1 , m 2 are respectively the rising slope and falling slope magnitudes of the output voltage ripple v o detected by the digital controller. According to the operating principle of the three-level flying capacitor buck converter, within the range of G < 0.5, m 1 and m 2 are respectively:

[0047]

[0048] d n-1 , d n are respectively the conduction duty cycles of the switching devices corresponding to the change of two adjacent output voltages. I L is the average value of the output current at steady state. The solid line is the steady-state waveform, and the dotted line is the change trend of the output current after the disturbance appears. The output current is sampled once at the beginning of each output current change cycle to obtain the sampled value i s . The values of two successive samplings are defined as i s (n - 1) and i s (n). The digital controller generates a peak current control signal i c through its built-in discrete proportional integral derivative (D-PID) controller., Since the inherent natural frequency of the system is much lower than the switching frequency, it can be considered that the peak current control signal i does not change significantly within two adjacent output current change cycles, that is, i c (n) = i c (n - 1). The current disturbance Δi c (n - 1) that appears at the beginning of the (n - 1)th cycle is reflected in i s (n - 1). If no other disturbance occurs in the current cycle, there is Δi s (n - 1) = Δi s (n). DPWM calculates the duty cycle d s according to i s (n - 1), i c , the duty cycle d n-1 , the circuit parameters pre - stored inside the digital controller, and different modulation methods, so that within the nth cycle, the detected peak value of the output current ripple is equal to i n . According to c , the digital peak current control principle under the leading - edge modulation method when G < 0.5, at the beginning of the nth switching cycle, Q Figure 5 , Q 1 are both turned off, and i 2 decreases. After a time of (0.5 - d s )T n-1 , Q s is turned on, and i 1 increases. After conducting for a time of d s T n-1 , Q s is turned off again, entering the (n + 1)th switching cycle, and i 1 decreases. After a time of (0.5 - d s )T n , Q s is turned on, and i 2 increases, and it remains until the end of the current switching cycle (T s ). In this way, Q s and Q 1 are turned on with a phase difference of 2 . Denote the peak value of the ripple voltage in the nth switching cycle as i (n). From spk , we get: Figure 5

[0049] i c = i spk (n) = i s (n - 1)-m 2 d' n-1 T s +m 1 d n-1 T s -m2 d' n T s +m 1 d n T s (4)

[0050] Among them, d' n = 0.5 - d n , d' n-1 = 0.5 - d n-1 . Further, from Equation (4), the duty cycle algorithm of the leading-edge modulation digital peak current control three-level flying capacitor buck converter when the voltage conversion ratio G < 0.5 is

[0051]

[0052] Similarly, referring to Figure 6 , the digital peak current control waveform diagram under the trailing-edge modulation mode when G < 0.5 is given. In the trailing-edge modulation, the sampling points in each output change period appear at the valley positions of the ripple. From Figure 6 it can be obtained that:

[0053] i c = i spk (n) = i s (n - 1) + m 1 d n-1 T s -m 2 d n ' -1 T s +m 1 d n T s (6)

[0054] Further, from Equation (6), the duty cycle algorithm of the trailing-edge modulation mode digital peak current control three-level flying capacitor buck converter when the voltage conversion ratio G < 0.5 is:

[0055]

[0056] Similarly, referring to Figure 7 , the triangular leading-edge modulation digital peak current control when G < 0.5 is given. At the beginning of the nth cycle, Q 1 and Q 2 are turned off, and i s drops. After a time of Q 1 is turned on, and i s rises. After a time of d n-1 T s , Q 1 is turned off again until the end of the current cycle. At the beginning of the (n + 1)th cycle, Q1 , Q 2 remains continuously off, i s continues to decrease. After time Q 1 turns on, i s rises. After d n T s time, Q 1 turns off again until the end of the current cycle. Thus, Q 2 and Q 1 are staggered by time to turn on. In the leading-edge triangle modulation, the sampling point of each switching cycle appears at the middle position of the output current ripple falling stage; the switching transistors Q 2 , Q 1 have equal off times at the start and end segments of each output voltage change cycle (T sw in the figure). From Figure 7 it can be obtained that:

[0057]

[0058] Further, from Equation (8), the duty cycle algorithm of the digital peak control three-level flying capacitor buck converter under the leading-edge triangle modulation mode when G < 0.5 can be obtained:

[0059]

[0060] Similarly, referring to Figure 8 , the digital peak current control under the trailing-edge triangle modulation when G < 0.5 is given. From Figure 8 it can be obtained that:

[0061]

[0062] Further, from Equation (10), the duty cycle algorithm of the digital peak control three-level flying capacitor buck converter under the trailing-edge triangle modulation mode when G < 0.5 is:

[0063]

[0064] In a specific application example, for the above derivations which are all within the range of G < 0.5, the present invention extends the applicable range of digital control to the range of G > 0.5. It is characterized in that, as analyzed above, Equations (5), (7), (9), and (11) respectively give the duty cycle algorithms of the digital peak control three-level flying capacitor buck converter under the leading-edge, trailing-edge, symmetric leading-edge triangle, and symmetric trailing-edge triangle modulations when G < 0.5. When G > 0.5, the above algorithms are still applicable, and the difference is that the rising and falling slopes of the output current ripple are different in the two operating modes. Equation (12) gives m 1 , m 2Expression:

[0065]

[0066] Observing the duty cycles of equations (5), (7), (9), and (11), the duty cycles obtained by the above algorithm are all calculated based on the quantities in the previous output change cycle, resulting in a delay of one output change cycle. If the delay of one output change cycle can be overcome to calculate the duty cycle required for the current switch according to the state quantity of the current output change cycle.

[0067] In specific application examples, the present invention overcomes the delay of one output change cycle and proposes an improved digital control strategy. Specifically, for a digital control circuit, there are usually the following time intervals: sampling time and circuit delay interval t s , algorithm calculation time interval t c (including the time of D-PID and DPWM), duty cycle update time t r . For the digital peak current controlled three-level flying capacitor buck converter of the present invention, there is The key to overcoming the switch cycle delay is to maximize t r , so as to have sufficient time to update the duty cycle, while t s is usually determined by the circuit hardware structure and remains basically unchanged. Therefore, minimizing t c increases the feasibility of overcoming the switch cycle delay. Taking the timing diagram of the front-edge modulation digital circuit as an example, as Figure 9 , if the timing t r > dT s can be satisfied, the improved front-edge modulation digital peak control algorithm can be realized. As Figure 10 shown, the control waveforms of the improved digital peak controlled three-level flying capacitor buck converter in the front-edge modulation mode are given. According to Figure 10 , it can be obtained that:

[0068] i c = i spk (n - 1) = i s (n - 1) - m 2 (0.5 - d n-1 )T s + m 1 d n-1 T s (13) Further from equation (13), the duty cycle algorithm of the improved digital peak controlled three-level flying capacitor buck converter in the front-edge modulation mode is:

[0069]

[0070] From Figure 10It can be seen that after a perturbation appears at the beginning of the (n - 1)-th period, the peak value of the output current ripple can reach the control target i in the (n - 1)-th period c .

[0071] Similarly, equations (15), (16), and (17) respectively give the duty cycle calculation algorithms of the improved digital peak current control three-level flying capacitor buck converter under trailing edge modulation, triangular leading edge modulation, and triangular trailing edge modulation modes:

[0072]

[0073] In a specific application example, the present invention conducts a stability analysis on the algorithm, specifically including that the improved digital control algorithm overcomes the delay of one output change period existing in the traditional digital control algorithm, and the two have the same stability. Taking the improved digital control algorithm as an example for stability analysis, it is studied through the ratio . According to Figure 10 , for the improved digital peak current control waveform under leading edge modulation, from the geometric relationships of the triangle and parallelogram in the figure, it can be obtained that:

[0074]

[0075] From Figure 10 the output current waveform of the improved digital peak current control three-level flying capacitor buck converter under leading edge modulation shown, it can be seen that the output current disturbance amount that appears at the beginning of the (n - 1)-th period disappears at the end of the (n - 1)-th period. Therefore, leading edge modulation eliminates the possible subharmonic oscillation problem in the improved digital peak current control three-level flying capacitor buck converter from the modulation principle. Therefore, the stable region of the improved digital peak current control three-level flying capacitor buck converter under leading edge modulation is 0 < G < 1. According to Figure 11 , for the improved digital peak current control waveform under trailing edge modulation, the stable region needs to satisfy |K| < 1. Substituting m 1 , m 2 when 0 < G < 0.5 and 0.5 < G < 1 respectively, the stable region of the improved digital peak current control three-level flying capacitor buck converter under trailing edge modulation is obtained:

[0076]

[0077]

[0078] Finally, similar to the principle of deriving the stable region by leading-edge modulation, the stable range of the improved digital peak current control three-level flying capacitor buck converter with triangular leading-edge modulation is 0 < G < 1; the improved digital peak current control three-level flying capacitor buck converter with triangular trailing-edge modulation will generate subharmonic oscillations within the full range of voltage conversion ratio, i.e., 0 < G < 1.

[0079] For the above digital control algorithms with subharmonic oscillations, the digital ramp compensation technique is introduced to eliminate the subharmonic oscillation problems existing in the algorithms. The output and control waveforms of the improved digital peak current control three-level flying capacitor buck converter with trailing-edge modulation using the digital ramp compensation technique are as Figure 12 shown, where k comp is the slope of the digital ramp compensation. It can be obtained that:

[0080]

[0081] Substitute m 1 and m 2 when 0 < G < 0.5 and 0.5 < G < 1 respectively, and get

[0082]

[0083] Therefore, the minimum ramp slope required for the algorithm of the improved digital peak control three-level flying capacitor buck converter with trailing-edge modulation using the digital ramp compensation technique is Similarly, the minimum ramp slope required for the algorithm of the improved digital peak control three-level flying capacitor buck converter with triangular trailing-edge modulation using the digital ramp compensation technique is

[0084] Furthermore, for the pure digital voltage-current double-loop feedback control technique proposed in the present invention, the above are all derivations based on the digital peak current control technique. Specifically, Table 1 summarizes the duty cycle calculation methods of the pure digital voltage-current double-loop feedback control technique under different modulation methods, including leading-edge modulation, trailing-edge modulation, triangular leading-edge modulation, and triangular trailing-edge modulation, which are applicable to the digital peak current control technique. In addition, the present invention also proposes an improved digital peak current control technique, and lists the corresponding duty cycle algorithm expressions of this improved technique in Table 1.

[0085]

[0086] Meanwhile, since the improved digital control algorithm has the same stability as the traditional digital control algorithm, Table 2 details the stable regions of the pure digital voltage-current double-loop feedback control technology under different modulation methods, which are applicable to the (improved) digital peak current control technology. Among them, the digital peak current control technology is stable in the full range under the leading-edge modulation and triangular leading-edge modulation methods, unstable in the full range under the triangular trailing-edge modulation method, and stable in a partial range under the trailing-edge modulation method; similar conclusions can be drawn for the digital peak voltage control technology. In addition, for the case of generating subharmonic oscillations, a ramp compensation is superimposed on the original control current signal (i c ), and the minimum slope of the compensating ramp varies according to different single-edge modulations (leading-edge modulation, trailing-edge modulation) and double-edge modulations (triangular leading-edge modulation, triangular trailing-edge modulation).

[0087]

[0088]

[0089] Furthermore, after using the digital ramp compensation technology to eliminate the subharmonic oscillations of the inductor current, the influence on the stability of the flying capacitor voltage is analyzed. Specifically, for example Figure 13 , taking the digital peak control three-level flying capacitor buck converter operating in the mode of G < 0.5 under the trailing-edge modulation method as an example, assuming that there is a perturbation on the flying capacitor , that is, the flying capacitor voltage Due to the existence of the perturbation on the flying capacitor, the resulting influence will surely be reflected in the unbalanced charging and discharging of the flying capacitor, and at the same time cause different duty cycles of the two switching devices, which are respectively set as D 1 , D 2 . From the geometric relationship of the waveforms, the following are obtained respectively:

[0090]

[0091] The formula for the average current flowing through the flying capacitor is:

[0092]

[0093] Among them, A pos and A neg are respectively the positive and negative areas of the flying capacitor current curve. Solved by the geometric relationship and substituting equations (24) and (25) into equation (26), the formula for the average current of the flying capacitor in the range of G < 0.5 is obtained:

[0094]

[0095] From equation (27), it can be seen that in the range of G < 0.5, when the slope of the compensating ramp satisfies will cause the average current I of the flying capacitor fly to have a sign opposite to that of the perturbation of the flying voltage . Therefore, it can be concluded that in the digital peak control three-level flying capacitor buck converter under trailing-edge modulation, once the subharmonic oscillation of the converter inductor current is suppressed, this technique will inherently stabilize the flying capacitor voltage and make it finally reach an equilibrium state. Similarly, a similar conclusion can be obtained for the digital peak control method under triangular trailing-edge modulation. Therefore, after the subharmonic oscillation is eliminated, digital peak control has the characteristic of self-balancing the flying capacitor voltage.

[0096] Differently, after the subharmonic oscillation is eliminated, digital peak control does not have the characteristic of self-balancing the flying capacitor voltage. Only when the peak-to-peak ripple is large enough will the flying capacitor voltage be stable.

[0097] It should be understood that the exemplary embodiments described herein are illustrative rather than restrictive. Although one or more embodiments of the present invention have been described in conjunction with the accompanying drawings, those of ordinary skill in the art should understand that various changes in form and detail may be made without departing from the spirit and scope of the present invention as defined by the appended claims.

Claims

1. A digital peak current control method for a three-level flying capacitor buck converter, characterized in that: The following steps are involved: The working mechanism of the three-level flying capacitor buck converter circuit is analyzed, including the on-off logic of each switch device during normal operation of the circuit, four static working modes, and two dynamic working switching modes. The on-off logic of each switch device during normal operation includes: the first switch device Q1 and the fourth switch device Q4 are complementary turned on, the second switch device Q2 and the third switch device Q3 are complementary turned on, and the first switch device Q1 and the second switch device Q2 present a staggered conduction characteristic with a phase difference of 180°; the four static working modes include: based on the coordinate sequence (Q1, Q2) composed of the first switch device and the second switch device, they are described as state I, state II, state III, and state IV respectively, and the coordinate sequence (Q1, Q2) corresponds to (1, 0), (0, 0), (0, 1), and (1, 1) respectively; the two dynamic working switching modes include: the circuit working dynamic switching process is divided into two working modes according to the range of the voltage conversion ratio G, and the voltage conversion ratio G is the output voltage V o With input voltage V g The ratio is: mode 1, i.e., when G<0.5, the circuit static working modes are switched in the order of Ⅰ→Ⅱ→Ⅲ→Ⅱ; mode 2, i.e., when G>0.5, the circuit static working modes are switched in the order of Ⅳ→Ⅰ→Ⅳ→Ⅲ; Taking one of the static operating mode points (1,0) as an example, the influence of flying capacitor voltage balance on the normal operation of the circuit is analyzed; Aiming at the voltage balance problem across the flying capacitor in the three-level flying capacitor buck converter circuit, a pure digital control strategy for the inductor current peak is proposed, namely, a peak current control technology based on digital voltage outer loop and digital current inner loop feedback. And overcome the delay of one output change cycle, and propose an improved digital control strategy; then conduct stability analysis on the algorithm; For the digital control algorithm with subharmonic oscillation, a solution strategy is proposed, and digital slope compensation technology is introduced to eliminate the subharmonic oscillation problem in the algorithm; further analysis is conducted to see whether the digital peak current has the self-balancing characteristics of the flying capacitor after the subharmonic oscillation is eliminated.

2. The digital peak current control method of the three-level flying capacitor buck converter according to claim 1, characterized in that: The three-level flying capacitor buck converter comprises a DC input voltage source V g 、Flying capacitor C fly , bridge arm composed of switching devices, filter inductor L o , output capacitor C o As well as the DC output terminal, the DC input voltage source V g Connected in parallel with the bridge arm consisting of four switching devices Q1, Q2, Q3, Q4 in series, the flying capacitor C fly Connected in parallel at both ends of the series branch composed of Q2 and Q3, the filter inductor L o and output capacitor C o The series branch composed of Q3 and Q4 is connected in parallel with the series branch composed of Q3 and Q4. The output capacitor C o Connect in parallel with the DC output terminal.

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