Fast flying capacitor pre-charge circuit

Abstract

The invention provides a fast flying capacitor pre-charge circuit. Effective, efficient and compact circuits and corresponding methods enable activation of a multi-level (M-level) converter cell to ensure that a driver circuit for a power transistor is sufficiently powered so as to be able to switch the power transistor on and off, and ensuring that all of the flying capacitors are pre-charged to a target voltage level prior to enabling the switching of the operating mode of the multilevel converter cell. Embodiments utilize power available from a battery connected to a multi-level converter cell, and operate the converter cell in a boost mode to repeatedly transfer charge from the battery to one or more flying capacitors until each flying capacitor reaches a respective target voltage.

Description

Technical Field

[0001] The present invention relates to electronic circuits, and more particularly to a pre-charge circuit for a multi-level power converter. Background Art

[0002] Many electronic devices, particularly mobile computing and / or communication products and components (e.g., laptop computers, ultrabook computers, and tablet devices), can be powered from multiple sources, including batteries, solar cells, and rectified AC sources (e.g., USB chargers or wireless charging circuits). A DC power converter is typically used to generate a lower or higher voltage from a selected power source, such as a rectified AC source, to both power the electronic device and charge a battery within the electronic device.

[0003] A power converter that generates a lower output voltage level from a higher input voltage power source is typically referred to as a buck converter, so named because the output voltage V OUT is less than the input voltage V IN , and thus the converter "bucks down" the input voltage. A power converter that generates a higher output voltage level from a lower input voltage power source is typically referred to as a boost converter because V OUT is greater than V IN . Some power converters can be either buck or boost converters, depending on which terminals are used for input and output. Some power converters can provide an inverted output.

[0004] Figure 1 is a block diagram of a prior art power converter 100. In the example shown, the power converter 100 includes a multi-level (M-level) converter unit 102 and a controller 104. The multi-level converter unit 102 is configured to receive an input voltage V IN across terminals V1+ and V1- (common) from a voltage source 106 (e.g., a rectified AC source), and to convert the input voltage V IN into an output voltage V OUT across terminals V2+ and V2- (common). The output voltage V OUT is typically coupled across an output capacitor C OUT , and the output capacitor C OUT can be connected to a load 108 (e.g., a battery and / or an electronic device).

[0005] Controller 104 receives a set of input signals and generates a set of output signals. Some of these input signals arrive along signal path 110 connected to converter unit 102. Some input signals carry information indicating the operating state of converter unit 102. Controller 104 typically also receives a clock / timing signal CLK and one or more external input / output signals I / O, which can be analog, digital (encoded or direct signal lines), or a combination of both. Based on the received input signals, controller 104 provides a set of control signals (including clock signal φ 1 …φ n ) back to converter unit 102 via signal path 110. This set of control signals controls the internal components of converter unit 102 (e.g., internal power switches such as FETs, especially MOSFETs) so that converter unit 102 converts V IN into V OUT . Each power switch typically has a level shifter and a driver circuit that are coupled to a control input (e.g., the gate of the FET implementing the power switch) to enable the power switch to be turned on or off based on logic-level clocks and / or control signals. In some embodiments, an auxiliary circuit (not shown) can provide various signals such as clock signal CLK, input / output signal I / O to controller 104 (and optionally directly to converter unit 102), as well as various voltages such as a general system supply voltage V DD and a transistor bias voltage V BIAS .

[0006] One type of multilevel converter unit 102 includes charge transfer capacitors as energy storage elements coupled by controlled power switches to transfer charge from V IN to V OUT . Such charge transfer capacitors are commonly referred to as "flying capacitors" or "pump capacitors". Each time a flying capacitor is used (i.e., not bypassed), the electrical energy flowing through the flying capacitor will typically charge or discharge the flying capacitor.

[0007] One design challenge of multilevel converter unit 102 is to charge its flying capacitors to a target voltage at startup before normal switching operation begins. The present invention provides an effective, efficient, and compact circuit to address this design challenge. SUMMARY OF THE INVENTION

[0008] The present invention includes effective, efficient, and compact circuits and corresponding methods that enable starting a multi-level (M-level) converter unit to ensure that a driver circuit for a power transistor is adequately powered to be able to switch the power transistor ON and OFF, and to ensure that all flying capacitors are pre-charged to a target voltage level before allowing a change in the operating mode of the multi-level converter unit.

[0009] Embodiments of the present invention utilize power available from a battery connected to the multi-level converter unit and operate the converter unit in a boost mode to repeatedly transfer charge from the battery to one or more flying capacitors C Fx , until each flying capacitor reaches its corresponding target voltage. The multi-level converter unit includes at least two "high-side" power FETs serially coupled between a V IN node and an intermediate node Lx, and at least two "low-side" power FETs serially coupled between the node Lx and a reference potential (e.g., circuit ground).

[0010] For example, all flying capacitors C of a multi-level power converter Fx can be pre-charged using the following process for power FET state configuration: during the pre-charge duration, the outermost low-side power FET (i.e., the one closest to the reference potential) is set to the conducting state but in a reduced current limit gate drive (RGD) mode; all high-side power FETs are set to the off state; all low-side power FETs except the innermost low-side power FET (the one closest to the node Lx) are set to the conducting state; the innermost low-side power FET is set to switch, which begins charging all flying capacitors C Fx ; the switching of the selected low-side power FET continues until the associated flying capacitor is fully pre-charged to its corresponding target voltage level; and if any remaining flying capacitors C Fx need to be fully pre-charged, the next low-side power FET further from the node Lx is selected to switch together with the previously switched one or more low-side power FETs until the flying capacitor associated with the next low-side power FET is fully pre-charged. This last step is repeated until all flying capacitors are fully pre-charged to their corresponding target voltage levels. Once full pre-charge of all flying capacitors has occurred, the multi-level converter unit can continue any additional start-up processes that may be required, and normal switching operation can begin, where the multi-level power converter is configured for boost or buck operation as may be required for a particular application or situation.

[0011] Details of one or more embodiments of the invention are set forth in the accompanying drawings and the following description. Other features, objects, and advantages of the invention will be apparent from the description, the drawings, and the claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 is a block diagram of a prior art power converter.

[0013] Figure 2 is a schematic diagram of a prior art three-level converter unit.

[0014] Figure 3A is Figure 2 a schematic diagram of the three-level converter unit of in a first switching configuration, which represents the first half of the charging clock cycle in the case of V BAT >V IN / 2.

[0015] Figure 3B is Figure 2 a schematic diagram of the three-level converter unit of in a second switching configuration, which represents the second half of the charging clock cycle in the case of V BAT >V IN / 2.

[0016] Figure 4 is BAT >V IN / 2 and V FLY =V IN / 2, and the voltage V F1 at node Lx and the current I Lx through inductor L during the first half and the second half of the charging period of the flying capacitor C L versus time.

[0017] Figure 5 is BAT >V IN / 2 and V FLY =0V, and the voltage V F1 at node Lx and the current I Lx through inductor L during the first half and the second half of the charging period of the flying capacitor C L versus time.

[0018] Figure 6A is a block diagram of an improved three-level converter unit according to the present invention.

[0019] Figure 6B is a block diagram of the improved three-level converter unit in a second pre-charge configuration.

[0020] Figure 6C is a graph showing Figure 6A the voltages of different nodes of a converter unit varying with time during a specific startup sequence of the converter unit.

[0021] Figure 6D is a first flowchart showing a process for precharging the V IN and V INT nodes and then precharging a single flying capacitor C F1 of a three-level power converter in another startup sequence.

[0022] Figure 6E is a second flowchart showing the steps for precharging the V IN and V INT nodes and then precharging multiple flying capacitors C Fx of a four-level or higher-level power converter unit.

[0023] Figure 7 is a schematic diagram of a level shifter / driver circuit that can be used with Figure 6A the converter unit.

[0024] Figure 8 is a schematic diagram of an example low dropout (LDO) circuit that can be used for Figure 6A the low dropout circuit LDOn of the converter unit.

[0025] Figure 9 is a schematic diagram of an example RGD circuit that can be used to power at least a portion of Figure 6A the outermost low-side level shifter / driver circuit LS / D3 of

[0026] Figure 10 is Figure 6A a schematic diagram of one embodiment of a peak current sensor of

[0027] Figure 11 is a block diagram of one embodiment of a control circuitry of a multilevel converter unit coupled to an output block including an inductor L and an output capacitor C OUT of.

[0028] Figure 12 is a top plan view of a substrate that can be, for example, a printed circuit board or a chip module substrate (e.g., a thin film tile).

[0029] Figure 13 is a process flowchart showing a method for precharging at least one flying capacitor coupled to a multilevel converter unit.

[0030] Figure 14It is a process flow diagram showing one method for pre-charging the voltage nodes of a multilevel converter unit.

[0031] Unless the context otherwise requires, like reference numerals and names in the various figures indicate like elements. Detailed Description

[0032] The present invention includes efficient, effective, and compact circuits and corresponding methods that enable starting a multilevel converter unit to ensure that the driver circuits of power transistors are adequately powered to be able to turn the power transistors on and off, and to ensure that all flying capacitors are pre-charged to a target voltage level before enabling operation mode switching of the multilevel converter unit.

[0033] It may be useful to better understand the challenges of power converter circuit startup before normal switching operation begins in an example multilevel converter unit. Figure 2 It is a schematic diagram of a prior art three-level converter unit 200. The conductive channels (drain to source) of power field effect transistors (FETs) M0 - M3 are serially coupled between an input voltage V IN and a reference potential (e.g., circuit ground). Each power FET M0 - M3 is shown to have corresponding inherent body diodes D0b - D3b connected in parallel with the associated FET. Clock signals φ0 to φ3 applied to the respective power FETs M0 - M3 control the on (ON) or off (OFF) state of the power FETs. (Note that for simplicity, level shifters, drivers, and control circuitry are omitted).

[0034] Energy storage flying capacitor C F1 is coupled between a high side node HS1 (between power FETs M0 and M1) and a low side node LS1 (between power FETs M2 and M3). Energy storage inductor L is coupled between battery B and node Lx, which separates the high side power FETs M0, M1 from the low side power FETs M2, M3. The voltage across battery B is V BAT . Output capacitor C OUT is coupled between inductor L and the reference potential. In some embodiments, for the purpose of pre-charging the flying capacitor C F1 as described below, output capacitor C OUT can be pre-charged by other circuitry (not shown) or retain charge from a previous power converter unit operation and thus act like battery B.

[0035] Figure 2The three-level converter unit enables the generation of three instantaneous voltage levels at node Lx during normal operation according to the ON-OFF states of the power FETs M0 - M3: V IN , V IN / 2 or 0V. For example, if V IN = 5V, then during normal operation, Lx can have values of 5V, 2.5V, or 0V. By switching the clock signals φ0 - φ3 in a specific pattern, the average voltage at node Lx can be maintained between approximately 0V and 2.5V or between approximately 2.5V and 5V. Note that a conventional buck converter would lack capacitor C F1 and power FETs M0 and M3, and during normal operation, it may generate only two instantaneous voltage levels at node Lx: V IN or 0V. In the three-level converter unit, the switching levels of the Lx node are reduced by half compared to a conventional buck converter. Compared to a conventional buck converter, the three-level converter unit offers the following advantages: lower switching losses, higher efficiency, higher output current, and smaller inductor requirements (which results in a reduction in circuit size).

[0036] The following is Figure 2 an example of the normal operation of the three-level converter unit, which assumes that V BAT < V IN / 2 and the voltage V F1 across the flying capacitor C FLY is V IN / 2: (1) In the charged state of the flying capacitor C F1 , during the first half of the clock cycle, power FETs M0 and M2 will be ON and power FETs M1 and M3 will be OFF, and during the second half of the clock cycle, power FETs M0 and M1 will be OFF and power FETs M2 and M3 will be ON; and (2) In the discharged state of the flying capacitor C F1 , during the first half of the clock cycle, power FETs M0 and M2 will be OFF and power FETs M1 and M3 will be ON, and during the second half of the clock cycle, power FETs M0 and M1 will be OFF and power FETs M2 and M3 will be ON.

[0037] The following is Figure 2 an example of the normal operation of the three-level converter unit, which assumes that V BAT > V IN / 2 and the voltage V F1 across the flying capacitor C FLY is V IN / 2: (1) In the charged state of the flying capacitor C F1In the charging state, during the first half of the clock cycle, power FETs M0 and M1 will be ON and power FETs M2 and M3 will be OFF, and during the second half of the clock cycle, power FETs M0 and M2 will be ON and power FETs M1 and M3 will be OFF; and (2) in the discharging state of the flying capacitor C F1 In the discharging state, during the first half of the clock cycle, power FETs M0 and M1 will be ON and power FETs M2 and M3 will be OFF, and during the second half of the clock cycle, power FETs M0 and M2 will be OFF and power FETs M1 and M3 will be ON.

[0038] Figure 2 The normal operation of the three-level converter unit depends critically on maintaining the voltage V F1 across the flying capacitor C FLY at V IN / 2; otherwise, the current through inductor L may reach overcurrent or negative current limits, which may damage the circuit.

[0039] As an example of the importance of maintaining the voltage V F1 across the flying capacitor C FLY at V IN / 2, consider the switching configuration of the three-level converter unit during the charging clock cycle as shown in Figure 3A and Figure 3B The switching configuration of the three-level converter unit during the charging clock cycle is shown in Figure 3A is Figure 2 a schematic diagram of the three-level converter unit in the first switching configuration, which represents the first half of the charging clock cycle when V BAT > V IN / 2. Figure 3B is Figure 2 a schematic diagram of the three-level converter unit in the second switching configuration, which represents the second half of the charging clock cycle when V BAT > V IN / 2. Therefore, during the first half of the clock cycle, power FETs M0 and M1 are ON and power FETs M2 and M3 are OFF, and during the second half of the clock cycle, power FETs M0 and M2 are ON and power FETs M1 and M3 are OFF.

[0040] Figure 4 is when V BAT > V IN / 2 and V FLY = V IN / 2 (i.e., the target voltage level), the flying capacitor C F1The voltage V at node Lx during the first and second halves of the charging cycle Lx and the current I through inductor L L Combined graph 400 versus time. As indicated by graph line 402, the current I L increases during the first half of the charging cycle and decreases during the second half of the charging cycle. The operation of the 3-level converter unit is as desired.

[0041] Figure 5 is at V BAT > V IN / 2 and V FLY = 0V (i.e., away from the target voltage level), the flying capacitor C F1 The voltage V at node Lx during the first and second halves of the charging cycle Lx and the current I through inductor L L Combined graph 500 versus time. As indicated by graph line 502, since the flying capacitor C F1 has no charge (V FLY = 0V), node Lx remains at V during the second half of the charging cycle IN . Therefore, the inductor L will always have a positive voltage across it, causing current to build up in the inductor L and eventually reaching an over-current limit. This problem extends to other categories of multi-level converter units (e.g., 4-level and 5-level converter units).

[0042] Therefore, in a 3-level converter unit, before multi-level switching begins, the flying capacitor C F1 should be pre-charged so that V FLY = V IN / 2, and V FLY should be maintained at this same level during switching. One way to pre-charge V FLY could be to add a circuit such as a current mirror to the multi-level converter to pre-charge each flying capacitor to the appropriate target voltage (e.g., V IN / 2 for a 3-level converter unit) before normal switching operation begins. However, if the power-up time is a critical specification, the required pre-charge current is higher, and the current mirror will consume a large area of the integrated circuit (IC). For example, charging a 20 μF flying capacitor C F1 to 10V in 10 mS requires 20 mA of current (i = c * dv / dt). If the IC die area is a critical specification, the pre-charge current value can be smaller, but the power-up time will increase. For example, the time to charge a 20 μF flying capacitor to 10V with 1 mA of current is 200 mS.

[0043] The present disclosure teaches a new and fast pre - charge technique that can be implemented in a smaller area than conventional solutions, rather than adding large - area circuitry to pre - charge the flying capacitors of a multilevel converter unit (remember, such circuitry is not used for anything else after startup). As an example, Figure 6A is a block diagram of an improved three - level converter unit 600 according to the present invention.

[0044] In Figure 6A , the conductive channels (drain - to - source) of power field - effect transistors (FETs) M0 - M3 are serially coupled between an internal voltage node V INT and a reference potential (e.g., circuit ground). The internal voltage node V INT is coupled to the V IN node through an internal disconnect switch S1, and this V IN node is in turn coupled to an external voltage source V EXT , such as a wired charging source (e.g., USB) or a wireless charging source, through an external disconnect switch S2. The voltage at node V INT is substantially the voltage at the node V IN after passing through the disconnect switch S1, and the voltage at node V IN is substantially the voltage at the node V EXT after passing through the disconnect switch S2. The disconnect switches S1, S2 allow the power FETs M0 - M3 to be isolated from the V EXT voltage source until the converter unit 600 is ready for normal switching operation. Note that in the following description, depending on the context, "V IN " and "V INT " can be used to refer to the node or the voltage at that node.

[0045] Each power FET M0 - M3 is shown to have a corresponding intrinsic body diode D0b - D3b connected in parallel with the associated FET. The gate of each power FET Mn is coupled to a corresponding level - shifter / driver circuit LS / Dn, an example of which is shown in Figure 7 . Note that in some embodiments, the outermost low - side power FET (M3 in this example) may not require a level - shifter and only requires a driver circuit; however, if the clock signal φ3 is in a different voltage domain from V BAT , then the clock signal φ3 needs to be level - shifted to the V BAT voltage domain before it is applied to the gate of the power FET M3. The signals applied to the corresponding level - shifter / driver circuits LS / D1 to LS / D3 from a controller (see, e.g., Figure 11) The clock signals φ0 to φ3 control the ON (conducting) or OFF (blocking) states of the power FETs M0 - M3.

[0046] The level shifter / driver circuits LS / D0, LS / D1, and LS / D2 are coupled in parallel with respective bootstrap capacitors Cn and optional protective Zener diode clamps Dn, and are coupled to the outputs of respective low - dropout circuits LDO0, LDO1, and LDO3. An example of the low - dropout circuits LDO0, LDO1, and LDO3 is shown in Figure 8 . The outermost low - side level shifter / driver circuit LS / D3 is coupled to the output of a Reduced Gate Drive circuit (RGD) 602. An example of the Reduced Gate Drive circuit (RGD) is shown in Figure 9 . In the example shown, the innermost low - side level shifter / driver circuit LS / D2 is coupled to V BAT through a diode Dp to provide sufficient power to activate the power FET M2 when V INT = 0V.

[0047] In the example shown, the energy storage inductor L is coupled between the battery B and the node Lx, which separates the high - side power FETs M0, M1 from the low - side power FETs M2, M3. The voltage across the battery B is V BAT . The output capacitor C OUT is coupled between the inductor L and the reference potential. The energy storage flying capacitor C F1 is coupled between the high - side node (between the power FETs M0 and M1) and the low - side node (between the power FETs M2 and M3).

[0048] An important aspect of the present invention is the concept of establishing a current in the inductor L through the battery B (or through an output capacitor C OUT ) having sufficient available charge, and then transferring the current in a controlled manner to pre - charge one or more flying capacitors through the intrinsic body diodes of the power FETs. Thus, for a three - level power converter, with the low - side power FET M3 always ON in a current - limited reduced gate drive mode, when the low - side power FET M2 is switched ON, the current from V BAT flows through the inductor L to circuit ground through the low - resistance path provided by the power FETs M2 and M3. Thus, energy is stored in the inductor L. When it is detected that the current through the inductor L has reached a specific threshold level, the power FET M2 is switched OFF. Then, the energy stored in the inductor L is transferred to the flying capacitor C F1Since the resistance of the current path through power FETs M2 and M3 to circuit ground is less than the forward threshold voltage of body diode D1b, no current flows through the intrinsic body diode D1b of power FET M1 when M2 is ON. Repeatedly switching power FET M2 between ON and OFF allows incremental current to accumulate in inductor L and then be transferred to flying capacitor C F1 , until the target voltage is reached on each flying capacitor (e.g., V F1 / 2 for flying capacitor C IN ). Importantly, the current through inductor L and the charging current to flying capacitor C F1 are limited by the reduced gate drive mode of the outermost low-side power FET (power FET M3 in this 3-level power converter example), thus protecting circuit components from overcurrent damage.

[0049] In more general detail, embodiments of the present invention utilize power available from battery B connected to a multi-level converter unit and operate the converter unit in a boost mode (asynchronous, meaning that before normal switching begins, the low-side power FETs are switched ON and OFF, but the high-side power FETs are set to OFF; the body diodes of the high-side power FETs assist in ramping down the inductor current) to repeatedly transfer charge from the battery to one or more flying capacitors C Fx , until each flying capacitor reaches its corresponding target voltage. For example, the following procedure configured for the power FET states can be used to pre-charge all flying capacitors C Fx of a multi-level power converter (note that for power converters with 4 levels or more, all flying capacitors should be initially discharged to start from 0V):

[0050] a. During the pre-charge duration, the outermost low-side power FET (i.e., the one closest to the reference potential, which is power FET M3 in this example) is set to a current-limiting reduced gate drive (RGD)

[0051] mode (see Figure 9 for details on the RGD mode and implementation circuit);

[0052] b. All high-side power FETs (M0 and M1 in this example) are set to the off state;

[0053] c. All low-side power FETs except the innermost low-side power FET are set to the on state (there are no other FETs in this 3-level example), and these low-side power FETs can be in full gate drive or reduced gate drive;

[0054] d. The innermost low-side power FET (i.e., the one closest to node Lx, which is M2 in this example)

[0055] is set to switch (cycle between ON and off states, possibly with different duty cycles), which begins charging all the flying capacitors C by periodically storing charge in the inductor L; Fx charging;

[0056] e. The switching of the innermost low-side power FET continues until the associated flying capacitor is fully pre-charged to the corresponding target voltage level; and

[0057] f. If any remaining flying capacitors C Fx need to be fully pre-charged, the next low-side power FET further from the node Lx is selected for switching together with one or more previously switched low-side power FETs until the flying capacitor associated with the next low-side power FET is fully pre-charged. By switching the power FET associated with the fully pre-charged flying capacitor, the capacitor is floating whenever the associated power FET is in the off state, thus preserving the charge of the capacitor when charge flows from the inductor L to other flying capacitors. This step is repeated until all flying capacitors are fully pre-charged to the corresponding target voltage levels.

[0058] Once the full pre-charging of all flying capacitors has occurred, the multilevel converter unit can proceed with any additional start-up steps that may be required, and in the case where the converter unit 600 is configured for boost or buck operations that may be required for a particular application or situation, normal switching operations can commence.

[0059] Referring again to Figure 6A , when pre-charging the flying capacitors C F1 , the states of the power FETs M0 - M3 are shown in bold next to each power FET and are set by appropriate values of the clock signals φ0 to φ3: M0 and M1 are OFF, M2 is switching, and M3 is ON in the current-limiting RGD mode. Note that the level shifter / driver circuit LS / D2 for switching the power FET M2 is powered by V BAT (through the diode Dp) during this operation phase. Similarly, the RGD circuit 602 is powered by V BAT , thus allowing the power FET M3 to be turned ON in the RGD mode. The dashed line 604 shows the flow of charge from V BAT through the inductor L and the node Lx and continuing through the power FETs M2 and M3 to the reference potential (e.g., circuit ground) when the power FET M2 switches to the conducting state. The dashed lines 606a and 606b show the flow of charge from V BATFlows through inductor L and node Lx and continues to flow through the intrinsic body diode D1b of power FET M1 to flying capacitor C F1 to the top plate of and charge from flying capacitor C F1 flows to the reference potential through the always-ON power FET M3 to the bottom plate of.

[0060] In some embodiments, to ensure a known starting state, it may be useful to discharge the V EXT node (e.g., USB or wireless charging circuit) to the V IN node before coupling an external voltage source to the V INT node and the V IN node to a target voltage level. The target voltage level can be 0V, but to not waste stored energy and thus increase the efficiency of converter unit 600, the target voltage level can be set to no greater than V BAT . For example, the V INT node and the V IN node can be at some unknown voltage (e.g., somewhere between 5V and 6V), while the V BAT can be 3V. Discharging the V INT and the V IN to approximately V BAT produces known voltages at these nodes.

[0061] For similar reasons, if all flying capacitors C Fx are overcharged, in some embodiments (especially multi-level power converters with more than 3 levels) it may be useful to discharge the overcharged flying capacitors C Fx to the corresponding target voltage levels (in this case, precharging is unnecessary).

[0062] In alternative embodiments, for example, in cases where a suitable power supply is available to power the gate-side control circuit of the high-side power FET at startup, then one or more high-side power FETs (e.g., Figure 6A M1 in the example of ) can be turned on to transfer charge from inductor L (as initially provided by V BAT ) to the flying capacitor for precharging purposes, rather than using the body diode of the high-side power FET. For example, the high-side power FET M1 can be switched in a phase opposite to that of the low-side power FET M2 such that charge is transferred from inductor L to flying capacitor C F1 through the source-to-drain conduction channel of power FET M1. In higher-order multi-level power converters, in flying capacitor C F1After being fully charged, the power FET M1 and the next higher high-side power FET can be switched in a phase opposite to that of the next switching low-side power FET, such that charge is transferred from the inductor L to the next flying capacitor C through the source-to-drain conduction channel of the high-side power FET. Fx Overall, the processing steps outlined above for body-diode-based charge transfer will be the same, except that: the high-side power FET will be switched as described rather than being turned off.

[0063] In some embodiments, after discharging the V INT node and the V IN node to a known target voltage (e.g., V BAT ), it may be useful to pre-charge the V INT node and the V IN node back up to a desired voltage level that will be at or near the expected voltage of the external voltage V EXT source (e.g., about 4.8V). In such cases, a variant of the technique described above for pre-charging the flying capacitor C EXT source (e.g., about 4.8V) can be used. For example, F1 is a block diagram of an improved three-level converter unit 600 in a second pre-charging configuration. When pre-charging the V Figure 6B node and the V INT node, the states of the power FETs M0 - M3 are shown in bold adjacent to each power FET and will be set by appropriate values of the clock signals φ0 to φ3: M0 and M1 are OFF, M2 is switching, and M3 is ON or switching in synchronization with M2, but in either case operating in a current-limiting RGD mode. The dashed line 612 shows that when the power FETs M2 and M3 are in the conducting state, charge flows from V IN through the inductor L and the node Lx and continues through the power FETs M2 and M3 to the reference potential. The dashed line 612 shows that when the power FET M2 switches to the off state, charge flows from V BAT through the inductor L and the node Lx and continues through the respective intrinsic body diodes D1b and D0b of the power FETs M1 and M0 to the V BAT node. If the switch S1 is closed, charge is also conveyed to the V INT node - the voltages on the V IN node and the V INT node will be substantially equal. IN node will be substantially equal.

[0064] One process for pre-charging the V INT node and the V IN node can be summarized as follows:

[0065] a. Set the outermost low-side power FET to a current-limiting reduced gate drive mode;

[0066] b. Set all of the plurality of high-side power FETs to an off state; and

[0067] c. Set all of the plurality of low-side power FETs to switch to start charging the V INT node (and the V IN node, if switch S1 is closed), and continue switching until the V INT node (and the V IN node, if switch S1 is closed) is fully pre-charged to the target voltage level.

[0068] Figure 6C is a graph showing Figure 6A the voltage variations over time of different nodes of the converter unit 600 during a specific start-up sequence of the converter unit 600.

[0069] During the time span 630, if the node V INT is overcharged, the node V INT (graph curve 632) is discharged to the target voltage level, e.g., V BAT (graph curve 634; in this example, V BAT is at a constant 3V). Optionally, in some embodiments, the node V IN (graph curve 636) can likewise be discharged (in this example, the node V IN is already at 0V).

[0070] During the time span 638, the node V INT and the node V IN are connected by closing the open switch S1, thus substantially equalizing the voltages at the two nodes.

[0071] During the time span 640, by setting the converter unit 600 to the Figure 6B second pre-charge configuration shown in, the node V INT (and thus the node V IN likewise) is pre-charged to the target voltage level (4.8V in this example). Accordingly, the gate voltages V GS of the gates of the power FET M2 (graph curve 642) and the power FET M3 (graph curve 644) start to switch between the on state and the off state, causing the node V IN and the node V INTThe voltage at [location] ramps up to approximately the target voltage level. Note that the frequencies of graph lines 642 and 644 are not to scale - the actual ON - OFF cycles will typically be much higher in terms of frequency than depicted in the drawing.

[0072] During time span 646, if the flying capacitor C F1 is not overcharged, the level converter unit 600 is set to Figure 6A the first pre - charge configuration shown in [figure / reference] to pre - charge the flying capacitor C F1 to V IN / 2. Thus, the power FET M2 continues to switch between the on - state and the off - state, but the power FET M3 stops switching and instead enters a stable current - limiting (RGD mode) on - state. During time span 646, the voltage across the flying capacitor C F1 (graph line 648) starts to ramp up to V IN / 2 (about 2.32V in this example) while the power FET M2 is switching. When the voltage across the flying capacitor C F1 reaches approximately V IN / 2, the power FET M2 returns to the off - state, ending time span 646. Any remaining steps in the startup sequence of the converter unit 600 can proceed, after which the normal switching operation of the converter unit 600 can begin.

[0073] Some startup sequences can include steps to discharge the flying capacitor C Fx to a known voltage state before starting the pre - charge, which is typically required for multi - level power converters with more than 3 levels (and thus more than one flying capacitor).

[0074] Figure 6D Figure 650 is a first flowchart which shows another startup sequence for pre - charging the V IN node and the V INT node and then pre - charging a single flying capacitor C of a 3 - level power converter. The process generally follows the sequence of actions described above with respect to F1 If it is determined that the V Figure 6C node and the V INT node are overcharged (step 652), then both are discharged to a target voltage such as V IN node and the V BAT (step 654), otherwise (and in any case) the circuit configuration shown in Figure 6B is used to pre - charge the two nodes (step 656).

[0075] In the example shown, if it is determined that the flying capacitor C F1is overcharged (step 658), the flying capacitor C F1 is discharged to V IN / 2 (step 660), otherwise use the Figure 6A circuit configuration shown in F1 to precharge the flying capacitor C (step 662). In any case, the startup sequence continues to completion (step 664), and multilevel switching can begin (step 666).

[0076] Figure 6E is a second flowchart 670, which shows the steps for precharging the V IN node and the V INT node and then precharging the multiple flying capacitors C of the power converter unit with more than 4 levels Fx . Specifically, if it is determined that the V INT node and the V IN node are overcharged (step 672), then both are discharged to a target voltage such as V BAT , otherwise (and in any case) use the Figure 6B circuit configuration shown in

[0077] to precharge the two nodes (step 676). Fx In the example shown, before starting the precharge (step 678), all the flying capacitors C Figure 6A are discharged to 0V to ensure a known voltage state, and then use the Fx circuit configuration shown in

[0078] to precharge the flying capacitors C sequentially (step 680). Thereafter, the startup sequence continues to completion (step 682), and multilevel switching can begin (step 684).

[0079] It should be recognized that other startup sequences including fewer or more sequence events can be used. BAT In a multilevel power converter where the target voltage of one or more of the flying capacitors is actually less than V Figure 6A , different switch configurations can be used that bypass the requirement of repeatedly pumping charge into the inductor L and then discharging it into the flying capacitor. For example, referring to F1 , if the target voltage of the flying capacitor C IN is V BAT / 2 and V IN / 2, the following switch states can be set by appropriate values of clock signals φ0 to φ3: M0 is OFF, M1 is OFF (but can be ON if sufficient power is available to activate the gate-side control circuit of M1), M2 is OFF, and M3 is ON in the current-limiting RGD mode. Then, the charge will directly transfer from V through the intrinsic body diode D1b or the conductive channel of M1 to the flying capacitor C BAT transfer to the flying capacitor C F1 , where the current is limited by the power FET M3. When the voltage across the flying capacitor C F1 is measured as V IN / 2, the power FET M3 is turned into OFF, thus floating the bottom plate of the flying capacitor C F1 and preventing further charging.

[0080] As described above, when the switching power FET starts the conduction-state half-cycle, the current in the inductor L ramps up. To protect the inductor L from overcurrent conditions, an optional peak current sensor can be used to determine when to end the ON duration of one or more switching low-side power FETs. The peak current sensor can be voltage-based or current-based.

[0081] For example, referring to Figure 6A , one type of peak current sensor can be the voltage comparator 608, which has a first input coupled to the bottom plate of the flying capacitor C F1 (see the dashed line, indicating the optional state of the voltage comparator 608) and a second input coupled to the reference voltage V REF . When the switching power FET M2 is ON and the current through the inductor L starts to increase above the value limited by the RGD power FET M3, the differential current starts to flow into the bottom plate of the flying capacitor C F1 and sharply raises the voltage on the bottom plate of the flying capacitor C F1 . This results in a difference between the bottom plate voltage and V REF , triggering the output Pk_I_Limit of the comparator 608, which can be provided to the control system and used to switch the power FET M2 into OFF. Similar comparator-based peak current sensors can be used for each flying capacitor in other categories of multilevel converter units (e.g., 4-level and 5-level converter units).

[0082] Figure 6AAn alternative implementation of optional peak current sensing in the form of a peak current sensor 610 is also shown, which is coupled to the node above the outermost low-side power FET (M3 in this example). As the current through the outermost low-side power FET increases, this current can be sensed and compared with a fixed reference to generate a control signal Pk_I_Limit, which can be provided to the control system and used to switch the power FET M2 to OFF. Details of one implementation of the peak current sensor 610 are shown in Figure 10 in.

[0083] Figure 7 is a level shifter / driver circuit 700 that can be used with the Figure 6A converter unit. The input clock signal φ n is applied to the input of the level shifter 702, which has a first power input coupled between the general system supply voltage V DD and circuit ground and a second power input coupled between the local voltages +V, -V, which represent the potential across the associated bootstrap capacitor Cn; thus, the -V power input represents the local reference potential that is also coupled to the source of the associated power FET Mn. The level shifter 702 converts the input signal from one voltage domain (e.g., digital logic voltage) to another voltage domain (e.g., transistor control voltage). Thus, the output of the level shifter 702 follows the input clock signal φ n , but in a different voltage range.

[0084] The output of the level shifter 702 is applied to the input of the driver 704, which has power terminals coupled to the local voltages +V, -V. The driver 704 can have a non-inverting or inverting output (as indicated by the dashed circle 706) coupled to the gate of the associated power FET Mn (note that high-side and low-side power FETs typically receive complementary control clock signals during synchronous operation and thus require different output polarities). In some implementations, the driver 704 can include one or more inverters or buffers, and the number of constituent inverters and / or buffers within the driver 704 can be adjusted to accommodate the signal delay requirements of a particular application. Generally, it is useful to design the driver 704 such that it can be placed in a high-impedance (high-Z) output state.

[0085] The optional resistor Rn can be coupled between the output of driver 704 (and thus also to the gate of the associated power FET Mn) and the local reference potential (and thus also to the source of the associated power FET Mn). The resistor Rn preferably has a reasonably high resistance (e.g., 100 kΩ or greater), which does not interfere with the normal control of the associated power FET Mn by the LS / Dn circuit 700, but allows charge to be drained from the gate of the associated power FET Mn to maintain the power switch in the off state. This capability is useful by creating a known system state (i.e., the default off state of the power FET Mn) if driver 704 is not fully powered and operational or if the corresponding LS / Dn circuit 700 is placed in a high-Z state.

[0086] As described above, the power for each LS / Dn circuit 700 is provided by the charge stored on the corresponding bootstrap capacitor Cn (in this example, n = 0…2) coupled to the +V, -V voltage inputs associated with the LS / Dn circuit 700. The size of each bootstrap capacitor Cn is preferably set to provide at least enough charge with a minimum voltage drop to allow the associated LS / Dn circuit 700 to switch the state of the associated power FET Mn (whose control gate is a relatively large capacitive structure). Typically, each bootstrap capacitor Cn loses charge in switching the gate of the associated power FET Mn. In addition, the bootstrap capacitor Cn loses charge even when not switching the associated power switch, e.g., through DC current leakage from other connected circuits (e.g., the bias current of an analog circuit). Thus, the bootstrap capacitor Cn typically needs to be charged during startup and periodically recharged during normal operation to replenish the lost charge.

[0087] Figure 8 is a schematic diagram of an example low dropout (LDO) circuit 800, which can be used for Figure 6A the low dropout circuit LDOn of the converter unit. In the case where M1b and M2b are coupled between V INT and the +V output terminal, the LDO circuit 800 includes a source follower (common drain) amplifier circuit, which includes a regulated nFET M1b, whose conductive channel is serially coupled with the conductive channel of a second nFET M2b. A current source 802 is serially coupled with a Zener diode Dz1 between the boost voltage source V INT _CP and the -V output terminal. In the example shown, V INT _CP can be generated by a charge pump (not shown) coupled to V INT and is slightly larger in magnitude than V INT。A variety of circuits known in the art can be used, and a current source can be configured by transistors and / or diodes. The output of the current source 802 before the Zener diode Dz1 provides a substantially constant bias voltage to the gate of the FET M1b. A bias current flows through the Zener diode Dz1, and ensures that the diode is always reverse-biased. When the FET M2b is set to the ON (conductive) state by a corresponding control signal P0B from a separate control logic (such as the controller circuit 1100 below) Figure 11 in the controller circuit 1100), the drain of the FET M1b provides a bootstrap voltage to the local level shifter / driver circuit LS / Dn. The FET M2b serves as a disconnect switch for the outermost high-side LDO. For the lower LDO, the FET M2b supports the electrostatic discharge current through its body diode, and the FET M2b can be configured as a diode-connected FET (in other words, no control signal needs to be coupled to the gate of the FET M2b).

[0088] Figure 9 is a schematic diagram of an exemplary RGD circuit 602, which can be used to power Figure 6A at least a portion of the outermost low-side level shifter / driver circuit LS / D3. More specifically, at least the final driver 902 of the LS / D3 is powered by the RGD circuit 602. The final driver 902 in this example includes a pFET and an nFET coupled in series in a conventional inverter configuration. In this example, the output of the final driver 902 is coupled to the gate of the power FET M3. The input of the final driver 902 can include one or more initial driver stages 904. The input of the initial driver stage 904 can come from an optional level shifter 906, which receives a clock signal corresponding to the power FET M3 If the level shifter 906 is omitted, the clock signal is applied directly to the initial driver stage 904.

[0089] In the illustrated example, the RGD circuit 602 includes a FET M LDO , and the conductive channel of this FET M LDO is coupled between V BAT and the final driver 902. The gate of the FET M LDO is coupled to node A. The main function of the RGD circuit 602 is to enable at least two different voltage levels at node A to be coupled to the gate of the FET M LDO , which in turn determines the output voltage level V GATE provided by the final driver 902 that drives the gate of the associated power FET M3. Therefore, the associated power FET M3 can be placed in (1) a low R for normal power converter operation ONan over-driven or “full-gate drive” conduction state, or (2) at least one current-limiting reduced-gate drive conduction state having a relatively high R ON and / or in a saturation mode in which current is limited. The saturation mode appears as an increased resistance R ON , but is not exactly the same - in the saturation mode, the power FET M3 acts like an ON-OFF switch and allows only a maximum fixed current to pass regardless of the applied voltage, while a true resistance means that a greater voltage allows a greater current. The current-limiting state is selected to provide protection against potentially damaging events such as inrush current or charge-transfer current. For example, during the start-up of a power converter, when balancing the charge between the flying capacitors within the power converter, or during a fault event such as a short-circuit event, potentially damaging events may occur.

[0090] FET M LDO 's gate driver circuit includes a current source 908 serially coupled between V BAT and a floating reference potential GND in series with a Zener diode Dz2. The gate of FET M LDO is coupled to a node A between the current source 908 and the Zener diode Dz2. The output I BIAS of the current source 908 before the Zener diode Dz2 at node A LDO provides a substantially constant bias voltage V GS_SF to the gate of FET M LDO . The source of FET M LDO_OUT provides a drive voltage V

[0091] In parallel with the Zener diode Dz2 is a voltage control circuit 910 that includes a reduced-gate drive switch Sw RGD that is serially coupled to a first diode-connected FET M RGD and at least one additional diode-connected FET M D0 where N≥1. As shown, one terminal of the switch Sw DN is coupled to node A and one terminal is connected to the conductive channel of the first diode-connected FET M RGD . The conductive channel of the first diode-connected FET M D0 is coupled to the conductive channels of the additional diode-connected FET M D0 where the conductive channel of the last additional diode-connected FET M DN is coupled to the floating reference potential GND. A control signal EN_RGD from a controller (e.g., see DN ) controls the switch Sw Figure 11 ), and one terminal is coupled to the conductive channel of the first diode-connected FET M RGDOpen and closed states. Note that switch Sw RGD can be positioned anywhere along the voltage control circuit 910 to interrupt or allow current to flow through the circuit. For example, the switch Sw from node A to the floating reference potential GND RGD and FET M D0 and M DN can be in the order of (1) Sw RGD , M D0 , M DN (as shown), (2) M D0 , Sw RGD , M DN or (3) M D0 , M DN , Sw RGD . However, positioning the switch Sw as shown in Figure 9 can reduce the parasitic effects on FET M RGD due to the capacitance of, for example, FET M D0 and / or M DN . The decoupling capacitor C LDO is coupled between the source of FET M O and the floating reference potential GND.

[0092] Because the threshold voltages of FET M LDO and FET M D0 effectively cancel each other out, the function of the diode-connected FET M LDO is to offset FET M D0 . The function of the additional diode-connected FET M LDO is to set the current I DN through the power FET M3 in proportion to the ratio of the sizes of the power FET M3 and FET M RGD when the switch Sw DN is closed and the current mirror function of the voltage control circuit 910 is engaged. More specifically, the current I MAIN through the power FET M3 is proportional to the current I MAIN from the current source 908 and the ratio of the sizes of FET M BIAS and the power FET M3. For example, if the current source 908 outputs 1 mA and the power FET M3 is 1,000 times the size of FET M DN (W / LM3 = 1000 × W / L M DN ), then the maximum current through the power FET M3 is 1,000 × 1 mA = 1 A. This ensures that the gate-to-source voltage V DN of FET M DN is GSTo achieve the same as the gate-to-source voltage V of the power FET M3. The maximum gate voltage of the power FET M3 is the voltage at node A minus the threshold voltage V of FET M GS . Including FET M LDO to increase the voltage at node A by the second threshold voltage V TH . Therefore, the voltage at node A = (V of FET M D0 ) + (V of FET M GS ), or 2V DN . If FET M GS and FET M D0 match (proportionally), then the maximum value that the V of the power FET M3 can reach is the same as the V of FET M TH , and this equation varies with process, temperature, etc. GS . If FET M LDO and FET M D0 match (proportionally), then the maximum value that the V of the power FET M3 can reach is the same as the V of FET M GS , and this equation varies with process, temperature, etc. DN . The V of the power FET M3 can reach the maximum value that is the same as the V of FET M GS , and this equation varies with process, temperature, etc.

[0093] As described above, an important function of the voltage control circuit 910 is that it provides a selectable amount of the regulated gate bias voltage V LDO to FET M GS_SF , which also controls the power supply to the final inverter 902 and the voltage output of the final inverter 902. When the switch Sw RGD is open, then the voltage control circuit 910 is disconnected from node A - and thus from the gate of FET M LDO - and thus has substantially no effect on the output of FET M LDO ; therefore, the final inverter 902 can overdrive the gate of the power FET M3 to the selected level determined by the Zener diode Dz2.

[0094] When the switch Sw RGD is closed - for example, during the startup of the power converter, when the outermost low-side power FET is configured in the RGD mode during the energization or precharging of the flying capacitor, or when rebalancing the charge amount of the flying capacitor - then the voltage control circuit 910 operates as a bypass to divert the current around the Zener diode Dz2 and lower the voltage at node A, thus reducing the drive voltage at FET M LDO . The reduced gate drive voltage at FET M LDO also reduces the power at the final inverter 902, and thus reduces the gate drive voltage V GATE at the power FET M3. If the drain-to-source voltage V across the power FET M3 DSHigh enough to keep power FET M3 in saturation, the power FET M3 acts as a controlled current limiting source. If V DS is below the level that would keep power FET M3 in saturation, the power FET M3 should be in the linear range of its operation, having an increased R ON value compared to the R ON value when in the normal overdrive state. In either case - saturation mode controlled current limiting source or linear mode increased R ON - the power FET M3 should limit the current through power FETs M0 - M3 of converter unit 600 and thus suppress excessive current spikes, thereby protecting the power FETs (and other coupled circuits) from large voltage spikes. Selectively varying the I BIAS current controls the V GATE value applied to power FET M3, thus allowing selection of different increased R ON values.

[0095] It should be recognized that while the RGD circuit 602 shown in Figure 9 is preferred because of its simple implementation, low power requirement, and small circuit area, other devices or circuits providing the same or similar functionality may be used in other embodiments. For example, node A may be coupled through switch Sw RGD to an amplifier having a level - shifted reference voltage as an input; the gate voltage at FET M LDO would be more accurate, but at the cost of complexity, circuit area, and power (and thus efficiency).

[0096] Figure 10 is Figure 6A a schematic diagram of one embodiment of a current - based peak current sensor 610. The peak current sensor 610 basically includes a current comparator that senses the power FET current and compares the sensed value with a fixed reference current. Example peak current sensor 610 includes (1) FET M1m having a conductive channel coupled between V BAT and a first current source 612, which in turn is coupled to the reference potential GND, and (2) FET M2m having a conductive channel coupled between V BAT and a second current source 614, which in turn is coupled to the reference potential GND. The gates of FETM1m and M2m are coupled together and also to the source of FET M1m. The reference potential GND is coupled to the conductive channel of the outermost low - side power FET (M3 in this example) of converter unit 600.

[0097] In operation, when power FET M2 is in the on - state, the current I M3Flows through power FET M3, which represents the current I flowing through inductor L L . Reference current I REF Flows through FET M1m and mirrors the sense current I SENSE Flows through FET M2m. The sense current I SENSE Is equal to K*I M3 , where K is a fractional scaling factor that reflects the relative device sizes of FET M2m and power FET M3. The peak current sensor 610 provides a control signal Pk_I_Limit at the node between power FET M2m and the second current source 614. When I SENSE Is equal to I REF , the control signal Pk_I_Limit changes state (e.g., from high to low), where I REF Is set to the maximum (scaled) current limit for the amount of current allowed to pass through inductor L. When the control signal Pk_I_Limit is generated, the control signal Pk_I_Limit can be provided to the control system and used to switch power FET M2 to OFF. It is noted that only one peak current sensor 610 is needed to monitor converter unit 600.

[0098] The current through inductor L can be monitored by a similar circuit to control how long power FET M2m is switched to OFF before switching back to the conducting state. Generally, it is desirable that little or no stored energy remains in inductor L before power FET M2m is switched back to ON, so preferably, power FET M2m remains in the off state until the inductor current I L Is zero or close to zero, and then power FET M2m is only switched back to ON.

[0099] Figure 11 Is a block diagram of a control circuitry 1100 of a multilevel converter unit 1102 for coupling to an output block 1104 including inductor L and output capacitor C OUT . Note that conceptually, as in Figure 6AIn the example, inductor L may also be considered to be included within the multilevel converter unit 1102. This example control circuitry 1100 is adapted from the teachings set forth in U.S. Patent Application Ser. No. 17 / 560,767, filed Dec. 23, 2021, entitled “Controlling Charge-Balance and Transients in a Multi-Level Power Converter,” which is assigned to the assignee of the present invention and the contents of which are incorporated herein by reference. However, the present invention may be used in conjunction with other types of control circuitry for the multilevel converter unit 1102.

[0100] The control circuitry 1100 functions as a control loop that is coupled to the output of the multilevel converter unit 1102 and to the power switch control inputs of the multilevel converter unit 1102. Generally, the control circuitry 1100 is configured to monitor the output (e.g., voltage and / or current) of the multilevel converter unit 1102 and, in view of changes in V IN and the output load, dynamically generate a set of power switch control inputs to the multilevel converter unit 1102 that attempts to stabilize the output voltage and / or current at a specified value. In an alternative embodiment, the control circuitry 1100 may be configured to monitor the input (e.g., voltage and / or current) of the multilevel converter unit 1102 and / or one or more internal nodes of the multilevel converter unit 1102 (e.g., the voltage across one or more flying capacitors or the current through one or more power FETs). Thus, most generally, the control circuitry 1100 may be configured to monitor the voltage and / or current of a node (e.g., input terminal, internal node, or output terminal) of the multilevel converter unit 1102. The control circuitry 1100 may be incorporated into or separated from the overall controller 104 of the power converter 100 that implements the multilevel converter unit 1102, and portions of the control circuitry 1100 may be implemented with a digital microcontroller.

[0101] The first block includes a feedback controller 1106, which may be a conventional controller, such as a fixed-frequency voltage-mode or current-mode controller, a constant-on-time controller, a hysteresis controller, or any other variant. The feedback controller 1106 is shown coupled to V BAT . In an alternative embodiment, the feedback controller 1106 may be configured to monitor the input of the multilevel converter unit 1102 and / or the internal nodes of the multilevel converter unit 1102. The feedback controller 1106 generates a signal that directly or indirectly indicates V BATThe pulse-width modulation (PWM) signal of the voltage at [location], generally speaking, this signal determines what needs to be done in the multilevel converter unit 1102 to maintain V BAT the desired value: charging, discharging, or tri-state (i.e., off, no current flowing).

[0102] In the illustrated example, the feedback controller 1106 includes a feedback circuit 1108, a compensation circuit 1110, and a PWM generator 1112. The feedback circuit 1108 can include, for example, a feedback loop voltage detector that compares V BAT (or a attenuated version of V BAT ) with a reference voltage representing the desired V BAT target voltage (which can be dynamic), and outputs a control signal to indicate whether V BAT is higher or lower than the target voltage. The feedback loop voltage detector can be implemented using a comparison device such as an operational amplifier (op-amp) or a transconductance amplifier (gm amplifier).

[0103] The compensation circuit 1110 is configured to stabilize the closed-loop response of the feedback controller 1106 by the following operations: avoiding inadvertently creating positive feedback that can cause oscillations, and controlling the overshoot and ringing in the step response of the feedback controller 1106. The compensation circuit 1110 can be implemented in a known manner and can include LC and / or RC circuits.

[0104] The PWM generator 1112 generates the actual PWM control signal that ultimately sets the duty cycle of the power switches of the multilevel converter unit 1102. In some embodiments, the PWM generator 1112 can transmit an additional optional control signal CTRL that indicates, for example, the magnitude of the difference between V BAT and the reference voltage (thus indicating that some levels of the multilevel converter unit 1102 should be bypassed to reach a higher or lower level) and the direction of this difference (e.g., V BAT is greater than or less than the reference voltage). In other embodiments, the optional control signal CTRL can be obtained from the output of the compensation circuit 1110, or from the output of the feedback circuit 1108, or from a separate comparator (not shown) coupled to, for example, V BAT . One purpose of the optional control signal CTRL is for advanced control algorithms, where it may be beneficial to know how far V BAT is from the target output voltage, thus allowing for faster charging of the inductor L in the case of severe under-regulation of V BAT .

[0105] The second block includes a multilevel controller 1114, and the main function of the multilevel controller 414 is to select the generation of V each time the output voltage level is selectedBAT while maintaining the charge balance state of the flying capacitors within the multilevel converter unit 1102 for the expected value, regardless of which power switch state or states were used in the past.

[0106] The multilevel controller 1114 includes a voltage level selector 1116 that receives the PWM control signal and an additional control signal CTRL (if available). Additionally, the voltage level selector 1116 may be coupled to V BAT 、V INT and / or V IN (only V IN is shown), and in some embodiments, is coupled to a high / low voltage status signal C Fx_H / L from a voltage detector (not shown), the voltage detector being coupled across the corresponding flying capacitor C Fx within the multilevel converter unit 1102. The function of the voltage level selector 1116 is to convert the received signals into a target output voltage level (e.g., on a cycle-by-cycle basis). The voltage level selector 1116 generally will consider at least V BAT 、V INT and / or V IN to determine which target level should charge or discharge the output of the multilevel converter unit 1102 at a desired rate, and may consider the voltage across each flying capacitor.

[0107] The output of the voltage level selector 1116 is coupled to a multilevel switch state selector 1118, which generally will be coupled to a voltage status signal C Fx from a capacitor voltage detector of the flying capacitor C Fx_H / L . Taking into account the target level generated by the voltage level selector 1116, the multilevel switch state selector 1118 determines which power switch states are preferred for capacitor charge balance for the desired output level. The output of the multilevel switch state selector 1118 is coupled to the power FETs of the multilevel converter unit 1102 (through appropriate level shifter circuits and driver circuits, as may be required for a particular converter unit), and includes a power switch state setting determined by the multilevel switch state selector 1118 that selects the configuration of the power FETs within the multilevel converter unit 1102 corresponding to the selected target level.

[0108] Typically (but not always), the voltage level selector 1116 and the multi-level switch state selector 1118 change their states only when the PWM signal changes. For example, when the PWM signal goes high, the voltage level selector 1116 selects which level causes the inductor L to charge, and the multi-level switch state selector 1118 sets which version of the switch settings to use for that level. Then, when the PWM signal goes low, the voltage level selector 1116 selects which level should cause the inductor L to discharge, and the multi-level switch state selector 1118 sets which version to use for that level. Thus, the voltage level selector 1116 and the multi-level switch state selector 1118 typically change states only when the PWM signal changes (the PWM signal is effectively their clock signal). However, there may be cases or events where it is desirable for the CTRL signal to change the state of the voltage level selector 1116. In some embodiments, it may be useful to include the following timing function: the timing function forces the multi-level switch state selector 1118 to periodically re-evaluate the best version of the power switch state, for example to avoid "sticking" at one level for a long time, which could lead to charge imbalance.

[0109] In an embodiment that utilizes the teachings set forth in the above-referenced patent application entitled "Controlling Charge-Balance and Transients in a Multi-Level Power Converter", the multi-level controller 1114 implements a control method for the multi-level converter unit 1102 that selects the flying capacitor C each time a voltage level at the Lx node is selected Fx to move to the substantially best power switch state for charge balance, regardless of which power switch state or states were used in the past. Thus, such a multi-level converter circuit freely selects a different power switch state or L X voltage level in each switching cycle without having to track any previous power switch state or sequence of power switch states.

[0110] In some embodiments, the multi-level switch state selector 1118 may consider the magnitude and / or polarity of the current I flowing through the inductor L via the optional current measurement input 1120 L which can be implemented in a conventional manner.

[0111] Figure 11 A significant benefit of the control circuitry shown in

[0112] While Figure 11A particular embodiment of a control circuitry for a multilevel converter unit modified in accordance with the present invention is shown, but it should be understood that other control circuits may be adjusted or designed while still being able to use embodiments of the present invention to provide appropriate switching signals for power switches within the converter unit.

[0113] It may be desirable to provide additional control and operating circuitry (or one or more shutdown procedures) that enables a power converter utilizing a multilevel converter unit designed in accordance with the present disclosure to operate reliably and efficiently. For example, in a buck power converter, the output voltage of the converter unit is less than the input voltage of the converter unit. Shutting down or disabling a converter unit having a designed inductor connected to the output (e.g., due to a fault event such as a short circuit) when the output load current is non-zero typically requires some means for discharging the inductor current. In some embodiments, a bypass switch may be connected in parallel with the designed inductor connected to the output of the converter unit, and the bypass switch is controlled to be open during normal operation and closed when the converter unit is shut down or in the event of a fault. Ideally, to prevent transient ringing and to provide a safe discharge of the inductor current, the bypass switch may be closed before disabling the converter unit switching. In an alternative embodiment using MOSFETs for the main power switches of the converter, the inherent body diodes connected between the body and the drain terminals of each MOSFET may also discharge the inductor current. Details of these solutions and alternative shutdown solutions are taught in U.S. Patent No. 10,686,367, entitled “Apparatus and Method for Efficient Shutdown of Adiabatic Charge Pumps,” published on June 16, 2020, which is assigned to the assignee of the present invention and the content of which is incorporated herein by reference.

[0114] Another consideration when combining converter units in parallel is to control multiple parallel power converters to avoid inrush current (e.g., during the soft start period of the power converter) and / or overstress of the power switches in the event that all power converters are not fully operational (such as during startup) or in the event of a fault condition. Conditional control can be achieved by monitoring voltage and / or current using a node status detector coupled to selected nodes within the parallel-connected power converters. In some embodiments, such a node status detector can be configured to operate in parallel with an output status detector that measures the output voltage of the associated power converter during startup. The node status detector ensures that the voltage across critical components (e.g., flying capacitors and / or power switches) within the converter unit of the power converter is within a desired range before allowing full-power steady-state operation of the parallel power converters, and otherwise prevents full-power steady-state operation. The node status detector can be coupled to a master controller that uses one or more common control signals to control one or more of the parallel power converters. In a further implementation of the master controller configuration, when ready to leave the startup phase for full-power steady-state operation, the parallel power converters can each report a power good signal (Pgood). The master controller can essentially "AND" all such Pgood signals, and possibly one or more status signals from other circuits, such that the master controller does not allow full-power steady-state operation of any of the parallel power converters unless all parallel power converters are ready for that state. In essence, the Pgood signals from each of the parallel power converters are all tied together such that the parallel power converters may not transition out of the startup phase until all Pgood signals indicate that they are ready to transition to steady-state operation. Additionally, if the Pgood signal changes due to a fault condition in one or more of the parallel power converters, the parallel power converters can transition from steady-state operation to an auto-restart or shutdown operation. Details of these solutions and alternative shutdown solutions are taught in U.S. Patent No. 10,992,226, entitled "Startup Detection for Parallel Power Converters," published on April 27, 2021, which is assigned to the assignee of the present invention and the content of which is incorporated herein by reference.

[0115] Another solution for balancing capacitor voltages in a multilevel DC-DC converter circuit is to provide a lossless voltage balancing solution, where unordered state transitions of the multilevel DC-DC converter unit are allowed to occur during normal operation. The net effect of the unordered state transitions is to increase or decrease the voltage across a particular flying capacitor, thereby preventing voltage overstress on the main power switches of the DC-DC converter. In some embodiments, a limit is imposed on the overall sequence of state transitions to reduce or avoid transition state switching, thereby allowing each capacitor the opportunity to have its voltage manipulated as needed, rather than allowing voltage balancing for one capacitor and then for another capacitor. The details of this solution and alternative charge balancing solutions are taught in U.S. Patent No. 10,770,974, entitled "Multi-Level DC-DC Converter with Lossless Voltage Balancing," published on September 8, 2020, which is assigned to the assignee of the present invention and the contents of which are incorporated herein by reference.

[0116] An additional consideration in some embodiments is to allow operation of the multilevel converter unit such that a voltage can be generated in the boundary region between voltage levels. The "boundary region" represents an output voltage that cannot be obtained by a conventional multilevel DC-DC converter circuit. To generate an output voltage within the boundary region, some embodiments alternate (switch) substantially between adjacent (or even nearby) regions by setting the states of the converter unit power switches in a boundary region transition mode. For example, a 3-level DC-DC converter circuit can operate in region 1 for a selected time and in an adjacent region 2 for a selected time. Thus, regions 1 and 2 are treated as a single "super region." More generally, in some cases, it may be useful to create super regions using non-adjacent regions or using more than two regions (adjacent and / or non-adjacent). The details of this solution are taught in U.S. Patent No. 10,720,842, entitled "Multi-Level DC-DC Converter with Boundary Transition Control," published on July 21, 2020, which is assigned to the assignee of the present invention and the contents of which are incorporated herein by reference.

[0117] Yet another consideration in some embodiments is to protect the main power switches and other components within the power converter from stress conditions, particularly from voltages that exceed the breakdown voltage of such power switches (especially FET switches). A method for protecting a multilevel power converter uses at least one high-voltage FET power switch while allowing all or most of the other main power switches to be low-voltage FET switches.

[0118] More specifically, the multilevel power converter provides or enables many benefits and advantages, including:

[0119] — Adaptability to applications where the input and / or output voltage can have a wide dynamic range (e.g., different battery input voltage levels, different output voltages);

[0120] — Improved efficiency of the operating time of devices operating on portable electrical energy sources (batteries, generators, or fuel cells using liquid or gaseous fuels, solar cells, etc.);

[0121] — Improved efficiency in cases where efficiency is important for thermal management, especially to protect other components (e.g., displays, nearby ICs) from overheating;

[0122] — Enabling design optimization of the power efficiency, power density, and form factor of the power converter — for example, a smaller-sized multilevel power converter can allow the power converter to be placed closer to the load, thus improving efficiency and / or reducing the overall material cost;

[0123] — The ability to utilize the performance of smaller, low-voltage transistors;

[0124] — Adaptability to applications where the power source (such as batteries, other power converters, generators, or fuel cells using liquid or gaseous fuels, solar cells, line voltage (AC), and DC voltage sources (e.g., USB, USB-C, power over Ethernet, etc.)) can vary widely;

[0125] — Adaptability to applications where the load (such as general ICs (including microprocessors and memory ICs), motors, and actuators, transducers, sensors, and displays (e.g., all types of LCDs and LEDs)) can vary widely;

[0126] — The ability to be implemented in a variety of IC technologies (e.g., MOSFET, GaN, GaAs, and bulk silicon) and packaging technologies (e.g., flip chip, ball grid array, wafer-level chip packaging, wide fan-out packaging, and embedded packaging).

[0127] It should be clear that the multilevel power converter embodiments described in this disclosure can be combined synergistically with the teachings of one or more of the additional control and operation circuits and methods described in this section.

[0128] One advantage of the embodiments of the present invention is the fast turn-on time. For example, the pre-charge process of the present invention allows the start-up of the power converter unit to occur within a few tens of milliseconds at 1 - 2 amperes without the need for additional components, but rather by using the existing power converter circuit in a new way. Other advantages of the embodiments of the present invention include small IC area, limiting inrush current during start-up, and controlling the pre-charge of the flying capacitor. In addition, the embodiments of the present invention improve the power density and / or power efficiency of the incorporated circuit and circuit modules or blocks. As would be understood by one of ordinary skill in the art, using the embodiments of the present invention beneficially affects the system architecture in key aspects, including lower power and / or longer battery life. Thus, the present invention specifically includes system-level embodiments that are creatively implemented by being incorporated into large system designs and applications.

[0129] The circuits and devices according to the present invention can be used alone or in combination with other components, circuits, and devices. Embodiments of the present invention can be fabricated as integrated circuits (ICs), which can be packaged in IC packages and / or modules to facilitate handling, manufacturing, and / or improving performance. In particular, the IC embodiments of the present invention are typically used in modules where one or more such ICs are combined with other circuit components or blocks (e.g., filters, amplifiers, passive components, and possibly additional ICs) in one package. Then typically, the IC and / or module are combined with other components on a printed circuit board to form part of a final product (such as a cellular phone, laptop computer, or electronic tablet), or to form a higher-level module that can be used in a variety of products (such as vehicles, test equipment, medical devices, etc.). Through various configurations of the modules and components, such ICs typically implement communication modes, usually wireless communication.

[0130] The advantages and benefits of multilevel power converters enable their use in a wide range of applications. For example, applications of multilevel power converters include portable and mobile computing and / or communication products and components (e.g., laptop computers, ultrabooks, tablet devices, and telephones), displays (e.g., LCD, LED), radio-based devices and systems (e.g., cellular systems, WiFi, Bluetooth, Zigbee, Z-Wave, and GPS-based devices), wired network devices and systems, data centers (e.g., for power conversion in battery backup systems and / or for processing systems and / or electronic / optical networking systems), Internet of Things (IoT) devices (e.g., smart switches and lights, security sensors, and security camera devices), household appliances and electronic products (e.g., set-top boxes, battery-powered vacuum cleaners, appliances with built-in radio transceivers such as washing machines, dryers, and refrigerators), AC / DC power converters, all types of electric vehicles (e.g., for drivetrain, control systems, and / or infotainment systems), and other devices and systems that use portable power sources and / or require power conversion.

[0131] Radio system uses include wireless RF systems (including base stations, relay stations, and handheld transceivers) that use various technologies and protocols, including various types of orthogonal frequency division multiplexing (“OFDM”), quadrature amplitude modulation (“QAM”), code division multiple access (“CDMA”), time division multiple access (“TDMA”), wideband code division multiple access (“W-CDMA”), global system for mobile communications (“GSM”), long term evolution (“LTE”), 5G, 6G, and WiFi (e.g., 802.11a, b, g, ac, ax, be) protocols, as well as other radio communication standards and protocols.

[0132] As an example of the integration of an embodiment of the present invention with other components, Figure 12 is a top plan view of a substrate 1200 that can be, for example, a printed circuit board or a chip module substrate (e.g., a thin film block). In the example shown, the substrate 1200 includes a plurality of ICs 1202a to IC1202d having terminal pads 1204 that are interconnected by conductive vias and / or traces on and / or within the substrate 1200 or on the opposite (rear) surface of the substrate 1200 (surface conductive traces are not shown to avoid clutter, and not all terminal pads are labeled). The ICs 1202a to 1202d can embody, for example, signal switches, active and / or passive filters, amplifiers (including one or more LNAs), and other circuitry. For example, IC 1202b can include Figure 6A one or more instances of the converter unit 600 shown in

[0133] The substrate 1200 may further include one or more passive devices 1206 embedded in, formed on, and / or fixed to the substrate 1200. Although shown as generally rectangular, the passive devices 1206 may be, for example, filters, capacitors, inductors, transmission lines, resistors, antenna elements, transducers (including, for example, MEMS-based transducers such as accelerometers, gyroscopes, microphones, pressure sensors, etc.), batteries, etc., interconnected to other passive devices 1206 and / or individual ICs 1202a to IC 1202d by conductive traces on or in the substrate 1200. Either the front or back surface of the substrate 1200 may be used as a location for forming other structures.

[0134] Another aspect of the present invention includes a method for pre-charging at least one capacitor coupled to a multilevel converter unit. For example, Figure 13 FIG. 1300 is a process flow diagram showing one method for pre-charging at least one flying capacitor coupled to a multilevel converter unit. In this example, the multilevel converter unit includes a node, a plurality of high-side power FETs serially coupled to the node, a plurality of low-side power FETs serially coupled to the node, and an inductor coupled to the node and configured to be coupled to a battery, wherein the multilevel converter unit is configured to connect to at least one flying capacitor between a first power FET pair of the plurality of high-side power FETs and a second power FET pair of the plurality of low-side power FETs. Note that for power converters of 4 levels and above, all flying capacitors should be initially discharged to start from 0V. The method includes: during the pre-charging duration, setting the outermost low-side power FET to the conducting state but in a current-limiting reduced gate drive mode (block 1302); setting all high-side power FETs to the off state (block 1304); setting the innermost low-side power FET adjacent to the node Lx to switch (block 1306); setting all other low-side power FETs to the conducting state (block 1308); continuing to switch the innermost low-side power FET until the associated flying capacitor is fully pre-charged to the corresponding target voltage level (block 1310); and if any remaining flying capacitors need to be fully pre-charged, selecting the next low-side power FET further away from the node Lx for switching together with the previously switched one or more low-side power FETs until the flying capacitor associated with the next low-side power FET is fully pre-charged - repeating this step until all flying capacitors are fully pre-charged to the corresponding target voltage levels (block 1312).

[0135] Additional aspects of the above method may include one or more of the following: wherein each of at least one capacitor is pre-charged through the inherent body diode of the corresponding high-side power FET; further including sensing the current through the inductor and, if the current through the inductor exceeds a selected level, setting any switched low-side power FET in the on state to the off state; further including sensing the current through the inductor and preventing any low-side power FET from switching from the off state to the on state until the current flowing through the inductor is close to zero; and / or wherein the outermost low-side power FET is controlled by a driver circuit powered by a reduced gate drive circuit configured to selectively set the outermost low-side power FET to a full gate drive mode or a current-limiting reduced gate drive mode.

[0136] Another aspect of the present invention includes a method for pre-charging other nodes of a multilevel converter unit. For example, Figure 14 FIG. 1400 is a process flow diagram showing a method of pre-charging a voltage node of a multilevel converter unit. In this example, the multilevel converter unit includes a first node of the multilevel converter unit, the multilevel converter unit including a second node, a plurality of high-side power FETs serially coupled between the first node and the second node, a plurality of low-side power FETs serially coupled to the second node, and an inductor coupled to the second node and configured to be coupled to a battery. The method includes: during a pre-charge duration, setting the outermost low-side power FET to a current-limiting reduced gate drive mode (block 1402); setting all high-side power FETs to the off state (block 1404); switching all low-side power FETs to start charging the first node and continuing to switch until the first node is fully pre-charged to a target voltage level (block 1406);

[0137] Additional aspects of the above method may include one or more of the following: wherein the pre-charge of the first node is through the corresponding inherent body diode of each high-side power FET; further including sensing the current through the inductor and, if the current through the inductor exceeds a selected level, setting the innermost low-side power FET from the on state to the off state; further including sensing the current through the inductor and preventing the innermost low-side power FET from switching from the off state to the on state until the current flowing through the inductor is close to zero; and / or wherein the outermost low-side power FET is controlled by a driver circuit powered by a reduced gate drive circuit configured to selectively set the outermost low-side power FET to a full gate drive mode or a current-limiting reduced gate drive mode.

[0138] As used in this disclosure, the term "MOSFET" includes any field effect transistor (FET) having an insulated gate, the voltage of which determines the conductivity of the transistor and includes an insulated gate having a metal or metalloid, insulator, and / or semiconductor structure. The term "metal" or "metalloid" includes at least one conductive material (such as aluminum, copper, or other metals or highly doped polysilicon, graphene, or other electrical conductors), "insulator" includes at least one insulating material (such as silicon oxide or other dielectric materials); and "semiconductor" includes at least one semiconductor material.

[0139] As used in this disclosure, the term "radio frequency" (RF) refers to an oscillation rate in the range of about 3 kHz to about 300 GHz. The term also includes the frequencies used in wireless communication systems. The RF frequency can be the frequency of an electromagnetic wave or the frequency of an alternating voltage or current in a circuit.

[0140] Regarding the figures cited in this disclosure, the dimensions of the various elements are not to scale; for clarity or emphasis, some dimensions may be greatly exaggerated vertically and / or horizontally. Additionally, references to orientation and direction (e.g., "top", "bottom", "above", "below", "lateral", "vertical", "horizontal", etc.) are relative to the exemplary figures and are not necessarily absolute orientation or direction.

[0141] The various embodiments of the present invention can be implemented to meet a wide variety of specifications. Unless otherwise indicated above, the selection of appropriate component values is a matter of design choice. The various embodiments of the present invention can be implemented in any suitable integrated circuit (IC) technology (including but not limited to MOSFET structures) or in the form of hybrid or discrete circuits. Any suitable substrate and process (including but not limited to standard bulk silicon, high resistivity bulk CMOS, silicon-on-insulator (SOI), and silicon-on-sapphire (SOS)) can be used to fabricate the integrated circuit embodiments. Unless otherwise indicated above, the embodiments of the present invention can be implemented in other transistor technologies such as bipolar junction transistors (BJTs), BiCMOS, LDMOS, BCD, GaAs HBTs, GaN HEMTs, GaAs pHEMTs, MESFETs, InP HBTs, InP HEMTs, FinFETs, GAAFETs, and SiC-based device technologies using 2-D, 2.5-D, and 3-D structures. However, the embodiments of the present invention are particularly useful when fabricated using a SOI- or SOS-based process or a process with similar characteristics. Fabrication using a SOI or SOS process in CMOS enables the circuit to have low power consumption, the ability to withstand high power signals during operation due to FET stacking, good linearity, and high frequency operation (i.e., radio frequencies up to and exceeding 300 GHz). Monolithic IC implementations are particularly useful because, through careful design, parasitic capacitances can generally be kept low (or at least consistent across all cells, allowing them to be compensated).

[0142] The voltage levels can be adjusted, and / or the voltage and / or logic signal polarities can be inverted, according to specific specifications and / or implementation technologies (e.g., NMOS, PMOS, or CMOS, and enhancement mode or depletion mode transistor devices). The component voltages, currents, and power handling capabilities can be adjusted as needed, for example, by adjusting the device size, "stacking" components in series (especially FETs) to withstand greater voltages, and / or using multiple components in parallel to handle greater currents. Additional circuit components can be added to enhance the capabilities of the disclosed circuit and / or to provide additional functionality without significantly altering the function of the disclosed circuit.

[0143] Multiple embodiments of the present invention have been described. It should be understood that various modifications can be made without departing from the spirit and scope of the present invention. For example, some of the steps described above can be order-independent and can therefore be performed in an order different from the order described. Additionally, some of the steps described above can be optional. The various activities described with respect to the methods identified above can be performed in repetitive, serial, and / or parallel fashion.

[0144] It should be understood that the foregoing description is intended to be illustrative and not restrictive of the scope of the invention, which is defined by the scope of the appended claims, and that other embodiments are within the scope of the claims. In particular, the scope of the invention includes any and all feasible combinations of one or more of the processes, machines, manufactures, or compositions of matter set forth in the appended claims. (Note that the bracketed designations of claim elements are for convenience in referring to such elements and do not themselves indicate a particular required order or enumeration of the elements; moreover, such designations may be reused in dependent claims as references to additional elements without being regarded as starting a conflicting sequence of designations).

Claims

1. A method of precharging at least one capacitor coupled to a multi-level converter unit, the multi-level converter unit comprising a node, a plurality of high-side power FETs coupled in series to the node, a plurality of low-side power FETs coupled in series to the node, and an inductor coupled to the node and configured to be coupled to a battery, wherein: The multi-level converter unit is configured to be connected to at least one capacitor between a first power FET pair of the plurality of high-side power FETs and a second power FET pair of the plurality of low-side power FETs, the method comprising: (a) Setting the outermost low-side power FET to current limiting reduced gate drive mode; (b) setting all of the plurality of high-side power FETs to an off state; (c) setting all low-side power FETs of the plurality of low-side power FETs except an innermost low-side power FET closest to the node to an on state; (d) switching the innermost low-side power FET to begin charging all of the at least one capacitor, and continuing switching until the capacitors associated with the innermost low-side power FET are fully pre-charged to respective target voltage levels; (e) if any remaining capacitor needs to be fully pre-charged, switching the next low-side power FET farther from the node together with all previously switched low-side power FETs until the capacitor associated with such next low-side power FET is fully pre-charged, and repeating this step until all of the at least one capacitor are fully pre-charged to the corresponding target voltage level.

2. The method according to claim 1, wherein: Pre-charging of each of the at least one capacitor is performed through an inherent body diode of a corresponding high-side power FET.

3. The method of claim 1 further comprising sensing a current through the inductor and setting any switched low-side power FETs that are in an on-state to an off-state if the current through the inductor exceeds a selected level.

4. The method of claim 3 further comprising sensing current through the inductor and preventing any low-side power FET from switching from an off state to an on state until the current through the inductor is close to zero.

5. The method according to claim 1, wherein: The outermost low side power FET is controlled by a driver circuit powered by a reduced gate drive circuit configured to selectively set the outermost low side power FET to a full gate drive mode or a current limited reduced gate drive mode.

6. A circuit arrangement for a multi-level converter unit, the circuit arrangement being for precharging at least one capacitor coupled to the multi-level converter unit, wherein: The multi-level converter unit includes a node, a plurality of high-side power FETs coupled in series to the node, a plurality of low-side power FETs coupled in series to the node, an inductor coupled to the node and configured to be coupled to a battery, wherein the multi-level converter unit is configured to be connected to at least one capacitor between a first power FET pair of the plurality of high-side power FETs and a second power FET pair of the plurality of low-side power FETs, and the circuit configuration includes: (a) Outermost low-side power FET, set to current-limited reduced gate drive mode; (b) all of the plurality of high-side power FETs are set to an off state; (c) all of the plurality of low-side power FETs except for an innermost low-side power FET closest to the node are set to an on state; (d) the innermost low-side power FET being configured to switch to begin charging all of the at least one capacitor and to continue switching until the capacitors associated with the innermost low-side power FET are fully pre-charged to respective target voltage levels; and (e) The next low-side power FET further from the node is arranged to switch together with all previously switched low-side power FETs until the capacitor associated with such next low-side power FET is fully pre-charged to the corresponding target voltage level.

7. The circuit arrangement according to claim 6, wherein: Each of the at least one capacitor is pre-charged through an inherent body diode of a corresponding high-side power FET.

8. The circuit configuration of claim 6, further comprising a first sensor coupled to the multi-level converter unit and configured to switch any switched low-side power FET from an on state to an off state if the current through the inductor exceeds a selected level.

9. The circuit configuration of claim 8, further comprising a second sensor coupled to the multi-level converter unit and configured to prevent any low-side power FET from switching from an off state to an on state until the current flowing through the inductor is close to zero.

10. The circuit arrangement according to claim 6, wherein: The outermost low side power FET is controlled by a driver circuit powered by a reduced gate drive circuit configured to selectively set the outermost low side power FET to a full gate drive mode or a current limited reduced gate drive mode.

11. A circuit arrangement for a multi-level converter unit, the circuit arrangement being for precharging a capacitor coupled to the multi-level converter unit, wherein: The multi-level converter unit includes a node, a plurality of high-side power FETs coupled in series to the node, a plurality of low-side power FETs coupled in series to the node, and an inductor coupled to the node and configured to be coupled to a battery, wherein the multi-level converter unit is configured to be connected to a capacitor between an innermost power FET pair of the plurality of high-side power FETs and an innermost power FET pair of the plurality of low-side power FETs, the circuit configuration comprising: (a) Outermost low-side power FET, set to current-limited reduced gate drive mode; (b) all of the plurality of high-side power FETs are set to an off state; (c) all of the plurality of low-side power FETs, except for an innermost low-side power FET closest to the node, are set to an on state; and (d) the innermost low side power FET being arranged to switch to begin charging the capacitor and to continue switching until the capacitor is fully pre-charged to a corresponding target voltage level.

12. The circuit arrangement according to claim 11, wherein The capacitor is pre-charged through the inherent body diode of the corresponding high-side power FET.

13. The circuit configuration of claim 11, further comprising a first sensor coupled to the multi-level converter unit and configured to switch the innermost low-side power FET from an on-state to an off-state if a current through the inductor exceeds a selected level.

14. The circuit configuration of claim 13, further comprising a second sensor coupled to the multi-level converter unit and configured to prevent the innermost low-side power FET from switching from an off state to an on state until the current flowing through the inductor is close to zero.

15. The circuit arrangement according to claim 11, wherein: The outermost low side power FET is controlled by a driver circuit powered by a reduced gate drive circuit configured to selectively set the outermost low side power FET to a full gate drive mode or a current limited reduced gate drive mode.

16. A method of precharging a first node of a multi-level converter cell, the multi-level converter cell comprising a second node, a plurality of high-side power FETs coupled in series between the first node and the second node, a plurality of low-side power FETs coupled in series to the second node, and an inductor coupled to the second node and configured to be coupled to a battery, the method comprising: (a) Setting the outermost low-side power FET to current limiting reduced gate drive mode; (b) setting all of the plurality of high-side power FETs to an off state; (c) setting all low-side power FETs of the plurality of low-side power FETs except an innermost low-side power FET closest to the second node to an on state; (d) switching the innermost low side power FET to begin charging the first node, and continuing switching until the first node is fully pre-charged to a target voltage level.

17. The method according to claim 16, wherein: Precharging of the first node is performed through the respective intrinsic body diode of each high-side power FET.

18. The method of claim 16, further comprising sensing current through the inductor and setting the innermost low side power FET from an on state to an off state if the current through the inductor exceeds a selected level.

19. The method of claim 18, further comprising sensing current through the inductor and preventing the innermost low-side power FET from switching from an off state to an on state until the current flowing through the inductor is close to zero.

20. The method according to claim 16, wherein: The outermost low side power FET is controlled by a driver circuit powered by a reduced gate drive circuit configured to selectively set the outermost low side power FET to a full gate drive mode or a current limited reduced gate drive mode.

21. A circuit arrangement for a multi-level converter cell, the circuit arrangement being for precharging a first node of the multi-level converter cell, wherein: The multilevel converter unit includes a second node, a plurality of high-side power FETs coupled in series between the first node and the second node, a plurality of low-side power FETs coupled in series to the second node, and an inductor coupled to the second node and configured to be coupled to a battery, the circuit configuration including: (a) Outermost low-side power FET, set to current-limited reduced gate drive mode; (b) all of the plurality of high-side power FETs are set to an off state; (c) all of the plurality of low-side power FETs except for an innermost low-side power FET closest to the second node are set to an on state; (d) said innermost low side power FET being configured to switch to initiate charging of said first node, And the switching continues until the first node is fully precharged to the target voltage level.

22. The circuit arrangement according to claim 21, wherein: Precharging of the first node is performed through the respective intrinsic body diode of each high-side power FET.

23. The circuit configuration of claim 21, further comprising a first sensor coupled to the multi-level converter unit and configured to switch the innermost low-side power FET from an on-state to an off-state if a current through the inductor exceeds a selected level.

24. The circuit configuration of claim 23, further comprising a second sensor coupled to the multi-level converter unit and configured to prevent the innermost low-side power FET from switching from an off state to an on state until the current flowing through the inductor is close to zero.

25. The circuit arrangement according to claim 21, wherein: The outermost low side power FET is controlled by a driver circuit powered by a reduced gate drive circuit configured to selectively set the outermost low side power FET to a full gate drive mode or a current limited reduced gate drive mode.

26. A method of precharging at least one capacitor coupled to a multi-level converter unit, the multi-level converter unit comprising a node, a plurality of high-side power FETs coupled in series to the node, a plurality of low-side power FETs coupled in series to the node, and an inductor coupled to the node and configured to be coupled to a battery, wherein: The multi-level converter unit is configured to be connected to at least one capacitor between a first power FET pair of the plurality of high-side power FETs and a second power FET pair of the plurality of low-side power FETs, and wherein a suitable power supply provides power to gate-side control circuits of the plurality of high-side power FETs, the method comprising: (a) setting the outermost low-side power FET to an on state and setting it to a current limiting reduced gate drive mode; (b) setting all low-side power FETs of the plurality of low-side power FETs except an innermost low-side power FET closest to the node to an on state; (c) switching the innermost low side power FET to charge the inductor; (d) switching the innermost high side power FET in an opposite phase to the switching of the innermost low side power FET to begin charging the at least one capacitor; (e) continuing switching until a capacitor associated with the innermost low-side power FET is fully pre-charged to a corresponding target voltage level; (f) if any remaining capacitor needs to be fully pre-charged, switching the next low-side power FET farther from the node together with all previously switched low-side power FETs to charge the inductor, and switching the next high-side power FET farther from the node together with all previously switched high-side power FETs in phase opposite to the switched low-side power FETs until the capacitor associated with such next low-side power FET is fully pre-charged, and repeating this step until all of the at least one capacitor are fully pre-charged to the corresponding target voltage level.

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