Voltage comparison circuit, chip and electronic equipment

Abstract

The invention provides a voltage comparison circuit, a chip and electronic equipment, relates to the technical field of integrated circuits, and aims to reduce voltage deviation. The voltage comparison circuit comprises a commutation circuit, an input stage comparator and an output stage comparator, the commutation circuit receives a first voltage signal, a second voltage signal and a first clock signal, the first voltage signal is larger than the second voltage signal, and the commutation circuit transmits the first voltage signal to a first input end under the control of a first level of the first clock signal and outputs the first voltage signal to a second input end; and under the control of the first level of the first clock signal, the first voltage signal is transmitted to the first input end and the second voltage signal is transmitted to the second input end, and under the control of the second level of the first clock signal, the first voltage signal is transmitted to the second input end and the second voltage signal is transmitted to the first input end. The third input end of the output-stage comparator is electrically connected with the first output end of the input-stage comparator, and the fourth input end of the output-stage comparator is electrically connected with the second output end of the input-stage comparator. The voltage comparison circuit can be applied to a chip and used as a detection circuit.

Description

Technical Field

[0001] The present application relates to the field of integrated circuit technology, and particularly to a voltage comparison circuit, a chip, and an electronic device. Background Art

[0002] A comparator can be applied in a detection circuit to detect problems such as overvoltage, undervoltage, overcurrent, and overheating in a device.

[0003] During most of each working cycle, one of the inverting input terminal and the non-inverting input terminal of the comparator receives a high level, and the other receives a low level. There is a large voltage difference between the inverting input terminal and the non-inverting input terminal, resulting in a large difference in the aging speed of the electronic components connected to the two input terminals, which easily causes the unilateral aging problem of the comparator and increases the voltage offset (VOS). Summary of the Invention

[0004] Embodiments of the present application provide a voltage comparison circuit, a chip, and an electronic device, aiming to improve the problem of unilateral aging of the circuit and reduce the voltage deviation of the circuit.

[0005] To achieve the above object, the embodiments of the present application adopt the following technical solutions:

[0006] In a first aspect, a voltage comparison circuit is provided. The voltage comparison circuit can be applied to application scenarios such as an overvoltage protection circuit, an undervoltage protection circuit, an overcurrent protection circuit, and an over-temperature protection circuit. The voltage comparison circuit works in a non-equilibrium state of an input signal for a long time in these application scenarios. The input signal of the voltage comparison circuit includes a first voltage signal and a second voltage signal, and the first voltage signal is greater than the second voltage signal for a long time. For example, the first voltage signal is a high level for a long time, and the second voltage signal is a low level for a long time.

[0007] The voltage comparison circuit includes a commutation circuit, an input-stage comparator, and an output-stage comparator. The input-stage comparator includes a first input terminal and a second input terminal, and the commutation circuit is electrically connected to the first input terminal and the second input terminal. The commutation circuit receives the first voltage signal, the second voltage signal, and a first clock signal. The first clock signal switches between a first level and a second level. Under the control of the first level, the commutation circuit transmits the first voltage signal to the first input terminal and transmits the second voltage signal to the second input terminal. And under the control of the second level, the commutation circuit transmits the first voltage signal to the second input terminal and transmits the second voltage signal to the first input terminal.

[0008] The input-stage comparator further includes a first output terminal and a second output terminal. The output-stage comparator includes a third input terminal and a fourth input terminal. The third input terminal is electrically connected to the first output terminal, and the fourth input terminal is electrically connected to the second output terminal.

[0009] The voltage comparison circuit provided by the above embodiments of the present application switches between a first level and a second level through a first clock signal. The first level controls the commutation circuit to transmit a first voltage signal to the first input terminal of the input-stage comparator and transmit a second voltage signal to the second input terminal. The second level controls the commutation circuit to transmit the first voltage signal to the second input terminal and transmit the second voltage signal to the first input terminal. Equivalently, the input signals of the first input terminal and the second input terminal are exchanged, realizing the phase switching of the first input terminal and the second input terminal of the input-stage comparator. It can avoid one of the two input terminals receiving the first voltage signal (high level) for a long time and the other receiving the second voltage signal (low level) for a long time, improve the unbalanced state of the input signals of the two input terminals, and reduce the aging speed difference of the electronic components connected to the two input terminals, thereby improving the unilateral aging problem of circuit devices and reducing the voltage deviation of circuit devices.

[0010] Moreover, taking the output signal of the input-stage comparator as the input signal of the output-stage comparator, when the phase of the input terminal of the input-stage comparator is switched, an electrical signal with a correct level can also be output through the output-stage comparator, and this electrical signal is used as the output signal of the voltage comparison circuit, ensuring the normal logic function of the voltage comparison circuit.

[0011] In some embodiments, the commutation circuit includes a first transistor, a second transistor, a third transistor, a fourth transistor, and a first inverter. The first transistor includes a control electrode, a first electrode, and a second electrode. The control electrode of the first transistor is configured to receive the first clock signal, the first electrode of the first transistor is configured to receive the first voltage signal, and the second electrode of the first transistor is electrically connected to the first input terminal. The second transistor includes a control electrode, a first electrode, and a second electrode. The control electrode of the second transistor is configured to receive the first clock signal, the first electrode of the second transistor is configured to receive the second voltage signal, and the second electrode of the second transistor is electrically connected to the second input terminal. The third transistor includes a control electrode, a first electrode, and a second electrode. The control electrode of the third transistor is electrically connected to the control electrode of the first transistor through the first inverter. The first electrode of the third transistor is configured to receive the first voltage signal, and the second electrode of the third transistor is electrically connected to the second input terminal. The fourth transistor includes a control electrode, a first electrode, and a second electrode. The control electrode of the fourth transistor is electrically connected to the control electrode of the first transistor through the first inverter. The first electrode of the fourth transistor is configured to receive the second voltage signal, and the second electrode of the fourth transistor is electrically connected to the first input terminal.

[0012] The commutation circuit is designed with the above circuit structure. Under the control of the first clock signal, it can achieve that the third transistor and the fourth transistor are cut off while the first transistor and the second transistor are turned on. The first voltage signal is transmitted to the first input terminal of the input-stage comparator through the first transistor, and the second voltage signal is transmitted to the second input terminal of the input-stage comparator through the second transistor. Moreover, while the first transistor and the second transistor are cut off, the third transistor and the fourth transistor are turned on. The first voltage signal is transmitted to the second input terminal of the input-stage comparator through the third transistor, and the second voltage signal is transmitted to the first input terminal of the input-stage comparator through the fourth transistor, thereby realizing the exchange of the input signals at the first input terminal and the second input terminal and the phase switching between the first input terminal and the second input terminal.

[0013] In some embodiments, the voltage comparison circuit includes a plurality of commutation circuits and a plurality of input-stage comparators. One commutation circuit corresponds to and is connected to one input-stage comparator.

[0014] The plurality of commutation circuits all receive the first voltage signal, the second voltage signal, and the first clock signal, and the plurality of input-stage comparators corresponding to the plurality of commutation circuits are arranged in parallel. Each commutation circuit can, under the control of the first clock signal, exchange the input signals at the first input terminal and the second input terminal of the corresponding input-stage comparator, and realize the phase switching between the first input terminal and the second input terminal.

[0015] In some embodiments, the voltage comparison circuit further includes a first gating unit and a second gating unit. The first gating unit is electrically connected to the first output terminals of the plurality of input-stage comparators and the third input terminal of the output-stage comparator, and the second gating unit is electrically connected to the second output terminals of the plurality of input-stage comparators and the fourth input terminal of the output-stage comparator.

[0016] The first gating unit is configured to connect the first output terminal of any one input-stage comparator to the third input terminal under the control of the second clock signal, and the second gating unit is configured to connect the second output terminal of the same input-stage comparator to the fourth input terminal under the control of the second clock signal, thereby realizing using the output signal of any one input-stage comparator as the input signal of the output-stage comparator.

[0017] In some embodiments, the voltage comparison circuit further includes a first clock signal circuit and a second clock signal circuit. Both the first clock signal circuit and the second clock signal circuit include at least one frequency division circuit and at least one delay circuit. The number of frequency division circuits in the second clock signal circuit is different from that in the first clock signal circuit, and the number of delay circuits is also different.

[0018] The first clock signal circuit is used to receive a clock source signal and generate a first clock signal, and the second clock signal circuit is used to receive the clock source signal and generate a second clock signal. By setting different numbers of frequency division circuits and different numbers of delay circuits in the second clock signal circuit and the first clock signal circuit, the frequency of the second clock signal is different from that of the first clock signal, and the moment of level switching is different. In this way, during the process of the phase switching of the input-stage comparator caused by the level switching of the first clock signal, it is avoided that the first gating unit and the second gating unit switch the input-stage comparator gated with the output-stage comparator under the control of the second clock signal, thereby avoiding the influence of the phase switching of the input-stage comparator on the output result of the output-stage comparator and ensuring the normal logical function of the voltage comparison circuit.

[0019] In some embodiments, the first clock signals received by different commutation circuits have a phase difference. Within one control period, the phase difference of the first clock signals received by different commutation circuits is not n = 0, 1, 2, and T is the duration of the control period, that is, the level switching moments of the first clock signals received by different commutation circuits are different, avoiding the influence of the simultaneous phase switching of multiple input-stage comparators on the output result of the output-stage comparator.

[0020] The second clock signal switches between a third level and a fourth level. Among the multiple first clock signals received by multiple commutation circuits, before the level switching of each first clock signal, the second clock signal performs a level switching, avoiding switching the input-stage comparator gated with the output-stage comparator during the phase switching of the input-stage comparator.

[0021] In some embodiments, the multiple input-stage comparators include a first input-stage comparator and a second input-stage comparator. The first gating unit includes a fifth transistor, a sixth transistor, and a second inverter. The fifth transistor includes a control electrode, a first electrode, and a second electrode. The control electrode of the fifth transistor is configured to receive the second clock signal. The first electrode of the fifth transistor is electrically connected to the first output terminal of the first input-stage comparator. The second electrode of the fifth transistor is electrically connected to the third input terminal of the output-stage comparator. The sixth transistor includes a control electrode, a first electrode, and a second electrode. The control electrode of the sixth transistor is electrically connected to the control electrode of the fifth transistor through the second inverter. The first electrode of the sixth transistor is electrically connected to the first output terminal of the second input-stage comparator. The second electrode of the sixth transistor is electrically connected to the third input terminal.

[0022] The second gating unit includes a seventh transistor, an eighth transistor, and a third inverter. The seventh transistor includes a control electrode, a first electrode, and a second electrode. The control electrode of the seventh transistor is configured to receive a second clock signal. The first electrode of the seventh transistor is electrically connected to the second output terminal of the first input stage comparator. The second electrode of the seventh transistor is electrically connected to the fourth input terminal of the output stage comparator. The eighth transistor includes a control electrode, a first electrode, and a second electrode. The control electrode of the eighth transistor is electrically connected to the control electrode of the seventh transistor through the third inverter. The first electrode of the eighth transistor is electrically connected to the second output terminal of the second input stage comparator. The second electrode of the eighth transistor is electrically connected to the fourth input terminal of the output stage comparator.

[0023] With the first gating unit and the second gating unit designed with the above circuit structure, under the control of the second clock signal, it is possible to achieve that the fifth transistor and the seventh transistor are turned on while the sixth transistor and the eighth transistor are turned off, so that the first output terminal of the first input stage comparator is connected to the third input terminal of the output stage comparator through the fifth transistor, and the second output terminal of the first input stage comparator is connected to the fourth input terminal of the output stage comparator through the seventh transistor.

[0024] Moreover, while the fifth transistor and the seventh transistor are turned off, the sixth transistor and the eighth transistor are turned on, so that the first output terminal of the second input stage comparator is connected to the third input terminal of the output stage comparator through the sixth transistor, and the second output terminal of the second input stage comparator is connected to the fourth input terminal of the output stage comparator through the eighth transistor.

[0025] In some embodiments, the output stage comparator further includes a third output terminal and a fourth output terminal, and the voltage comparison circuit further includes a third gating unit. The third gating unit is electrically connected to the third output terminal, the fourth output terminal, and the output terminal of the voltage comparison circuit. The third gating unit is configured to connect the third output terminal to the output terminal of the voltage comparison circuit under the control of a third clock signal, so as to use the electrical signal output from the third output terminal as the output signal of the voltage comparison circuit. Alternatively, connect the fourth output terminal to the output terminal of the voltage comparison circuit, so as to use the electrical signal output from the fourth output terminal as the output signal of the voltage comparison circuit.

[0026] In some embodiments, the third gating unit includes a ninth transistor, a tenth transistor, and a fourth inverter. The ninth transistor includes a control electrode, a first electrode, and a second electrode. The control electrode of the ninth transistor is configured to receive a third clock signal. The first electrode of the ninth transistor is electrically connected to the third output terminal of the output stage comparator. The second electrode of the ninth transistor is electrically connected to the output terminal of the voltage comparison circuit. The tenth transistor includes a control electrode, a first electrode, and a second electrode. The control electrode of the tenth transistor is electrically connected to the control electrode of the ninth transistor through the fourth inverter. The first electrode of the tenth transistor is electrically connected to the fourth output terminal of the output stage comparator. The second electrode of the tenth transistor is electrically connected to the output terminal of the voltage comparison circuit.

[0027] With the above circuit structure design of the third gating unit, under the control of the third clock signal, it can be realized that the tenth transistor is turned off while the ninth transistor is turned on, connecting the third output terminal of the output stage comparator to the output terminal of the voltage comparison circuit. And, the tenth transistor is turned on while the ninth transistor is turned off, connecting the fourth output terminal of the output stage comparator to the output terminal of the voltage comparison circuit.

[0028] In a second aspect, a chip is provided. The chip includes a controller and the voltage comparison circuit in any of the above embodiments, and the controller is electrically connected to the voltage comparison circuit.

[0029] In a third aspect, an electronic device is provided. The electronic device includes a circuit board and the chip in the above embodiment, and the chip is electrically connected to the circuit board.

[0030] It can be understood that for the chip and the electronic device provided in the above embodiments of the present application, the beneficial effects that can be achieved can refer to the beneficial effects of the voltage comparison circuit in the above text, which will not be elaborated here. Description of the Drawings

[0031] Figure 1 is a schematic diagram of an architecture of the voltage comparison circuit provided by an embodiment of the present application;

[0032] Figure 2 is Figure 1 a waveform diagram of the input and output signals of the voltage comparison circuit in

[0033] Figure 3 is a circuit diagram of the input stage comparator provided by an embodiment of the present application;

[0034] Figure 4 is a circuit diagram of the commutation circuit provided by an embodiment of the present application;

[0035] Figure 5 is another schematic diagram of an architecture of the voltage comparison circuit provided by an embodiment of the present application;

[0036] Figure 6Structural block diagram of the first clock signal circuit and the second clock signal circuit provided by the embodiments of the present application;

[0037] Figure 7 Circuit diagram of the first gating unit provided by the embodiments of the present application;

[0038] Figure 8 Circuit diagram of the second gating unit provided by the embodiments of the present application;

[0039] Figure 9 Circuit diagram of the third gating unit provided by the embodiments of the present application;

[0040] Figure 10 Control timing diagram of the voltage comparison circuit provided by the embodiments of the present application;

[0041] Figure 11 Structural block diagram of the switching power supply chip provided by the embodiments of the present application;

[0042] Figure 12 Exploded view of the mobile phone provided by the embodiments of the present application. Detailed implementation manners

[0043] Next, the technical solutions in some embodiments of the present application will be clearly and completely described in conjunction with the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments provided by the present application belong to the scope of protection of the present application.

[0044] The embodiments of the present application provide a voltage comparison circuit. Figure 1 An architecture diagram of the voltage comparison circuit provided by the embodiments of the present application; Figure 2 For Figure 1 The waveforms of the input and output signals of the voltage comparison circuit in

[0045] See Figure 1 And Figure 2 , the voltage comparison circuit 1 includes a commutation (switch) circuit 11, an input stage comparator 12, and an output stage comparator 13.

[0046] The input signals of the voltage comparison circuit 1 include a first voltage signal V INN And a second voltage signal V INP , for example, the first voltage signal V INN Is a constant reference voltage, and the second voltage signal V INP Changes periodically. During most of each control period T, the first voltage signal V INN Is greater than the second voltage signal V INP , for example, the first voltage signal V INNis high level for a long time, the second voltage signal V INP is low level for a long time, the first voltage signal V INN and the second voltage signal V INP have a relatively large voltage difference, causing the voltage comparison circuit 1 to operate in an unbalanced state of the input signal for a long time.

[0047] The commutation circuit 11 is configured to receive the first voltage signal V INN , the second voltage signal V INP and the first clock signal V CLK1 .

[0048] The input stage comparator 12 includes a first input terminal in1 and a second input terminal in2. For example, the first input terminal in1 is the inverting input terminal of the input stage comparator 12, and the second input terminal in2 is the non-inverting input terminal of the input stage comparator 12.

[0049] The input stage comparator 12 further includes a first output terminal out1 and a second output terminal out2. For example, the first output terminal out1 is the non-inverting output terminal of the input stage comparator 12, and the second output terminal out2 is the inverting output terminal of the input stage comparator 12. The first output terminal out1 corresponds to and is connected to the first input terminal in1, and the second output terminal out2 corresponds to and is connected to the second input terminal in2.

[0050] The commutation circuit 11 is electrically connected to the first input terminal in1 and the second input terminal in2 of the input stage comparator 12. The first clock signal V CLK1 received by the commutation circuit 11 switches between a first level and a second level. The commutation circuit 11 can, under the control of the first level of the first clock signal V CLK1 , transmit the first voltage signal V INN to the first input terminal in1 of the input stage comparator 12 and transmit the second voltage signal V INP to the second input terminal in2 of the input stage comparator 12. Moreover, the commutation circuit 11 can, under the control of the second level of the first clock signal V CLK1 , transmit the first voltage signal V INN to the second input terminal in2 of the input stage comparator 12 and transmit the second voltage signal V INP to the first input terminal in1 of the input stage comparator 12.

[0051] By switching the first clock signal V CLK1 between a first level and a second level, the first level controls the commutation circuit 11 to transmit the first voltage signal V INN to the first input terminal in1 of the input stage comparator 12 and transmit the second voltage signal V INP to the second input terminal in2, and the second level controls the commutation circuit 11 to transmit the first voltage signal VINN is transmitted to the second input terminal in2, and the second voltage signal V INP is transmitted to the first input terminal in1. That is to say, the input signals of the first input terminal in1 and the second input terminal in2 are exchanged, realizing the phase switching of the first input terminal in1 and the second input terminal in2 of the input-stage comparator 12. This can prevent one of the two input terminals from receiving a high level for a long time and the other from receiving a low level for a long time, improve the unbalanced state of the input signal of the voltage comparison circuit 1, reduce the aging speed difference of the electronic components connected to the two input terminals, and thus can improve the unilateral aging problem of the circuit device and reduce the voltage offset (VOS) of the circuit device.

[0052] Figure 3 is the circuit diagram of the input-stage comparator 12 provided by the embodiment of the present application.

[0053] Refer to Figure 3 , on the signal transmission path between the first input terminal in1 and the first output terminal out1 of the input-stage comparator 12, there are transistors T1 to T11, and on the signal transmission path between the second input terminal in2 and the second output terminal out2, there are transistors T12 to T22. The circuit structure of the input-stage comparator 12 provided by the present application is not limited to this.

[0054] By performing phase switching through the first input terminal in1 and the second input terminal in2, it can prevent transistors T1 to T11 from working at a high level for a long time, and also prevent transistors T12 to T22 from working at a high level for a long time. It reduces the time difference between the duration of transistors T1 to T11 working at a high level and the duration of transistors T12 to T22 working at a high level, improves the phenomenon of threshold voltage drift generated by transistors T1 to T11 and transistors T12 to T22, and reduces the aging speed difference between transistors T1 to T11 and transistors T12 to T22. Thus, it improves the problem that the transistors on one signal transmission path age faster than those on the other signal transmission path, that is, it improves the unilateral aging problem, which is beneficial to reducing the voltage offset of the circuit device.

[0055] Please continue to refer to Figure 1 , the output-stage comparator 13 includes a third input terminal in3 and a fourth input terminal in4. For example, the third input terminal in3 is the inverting input terminal of the output-stage comparator 13, and the fourth input terminal in4 is the non-inverting input terminal of the output-stage comparator 13.

[0056] The third input terminal in3 of the output-stage comparator 13 is electrically connected to the first output terminal out1 of the input-stage comparator 12, and the fourth input terminal in4 of the output-stage comparator 13 is electrically connected to the second output terminal out2 of the input-stage comparator 12.

[0057] With the above setting method, using the output signal of the input-stage comparator 12 as the input signal of the output-stage comparator 13, even when the phase at the input end of the input-stage comparator 12 is switched, an electrical signal with the correct level can still be output by the output-stage comparator 13, and this electrical signal serves as the output signal V of the voltage comparison circuit 1. out This ensures the normal logical function of the voltage comparison circuit 1.

[0058] For example, in combination with Figure 1 and Figure 2 , in an ideal state, the voltage deviation of the voltage comparison circuit 1 is 0. Based on this, when the second voltage signal V INP is less than the first voltage signal V INN , before and after the phase switch at the input end of the input-stage comparator 12, the output-stage comparator 13 can ensure that the output signal V out is at a low level in both cases. Similarly, when the second voltage signal V INP is greater than the first voltage signal V INN , before and after the phase switch at the input end of the input-stage comparator 12, the output-stage comparator 13 can ensure that the output signal V out is at a high level in both cases, and the logical function of the voltage comparison circuit 1 is not affected by the phase switch of the input-stage comparator 12.

[0059] Figure 4 The circuit diagram of the commutation circuit provided by the embodiment of the present application is shown in

[0060] Refer to Figure 4 . The commutation circuit 11 includes a first transistor M1, a second transistor M2, a third transistor M3, a fourth transistor M4, and a first inverter F1.

[0061] The first transistor M1 includes a control electrode, a first electrode, and a second electrode. The control electrode of the first transistor M1 is configured to receive the first clock signal V CLK1 , the first electrode of the first transistor M1 is configured to receive the first voltage signal V INN , and the second electrode of the first transistor M1 is electrically connected to the first input terminal in1 of the input-stage comparator 12.

[0062] The second transistor M2 includes a control electrode, a first electrode, and a second electrode. The control electrode of the second transistor M2 is configured to receive the first clock signal V CLK1 , the first electrode of the second transistor M2 is configured to receive the second voltage signal V INP , and the second electrode of the second transistor M2 is electrically connected to the second input terminal in2 of the input-stage comparator 12.

[0063] The third transistor M3 includes a control electrode, a first electrode, and a second electrode. The control electrode of the third transistor M3 is electrically connected to the control electrode of the first transistor M1 through a first inverter F1. The first electrode of the third transistor M3 is configured to receive a first voltage signal V INN , and the second electrode of the third transistor M3 is electrically connected to the second input terminal in2 of the input stage comparator 12.

[0064] The fourth transistor M4 includes a control electrode, a first electrode, and a second electrode. The control electrode of the fourth transistor M4 is electrically connected to the control electrode of the first transistor M1 through a first inverter F1. The first electrode of the fourth transistor M4 is configured to receive a second voltage signal V INP , and the second electrode of the fourth transistor M4 is electrically connected to the first input terminal in1 of the input stage comparator 12.

[0065] It can be understood that the first transistor M1 to the fourth transistor M4 can be P-type transistors or N-type transistors, and the embodiments of the present application do not limit this.

[0066] Exemplarily, the first transistor M1 to the fourth transistor M4 are all N-type transistors. The first clock signal V CLK1 switches between a first level and a second level, taking the first level as a high level and the second level as a low level as an example.

[0067] When the first clock signal V CLK1 is at the first level, the control electrode of the first transistor M1 receives a high level, and the first transistor M1 conducts under the control of the high level. The first voltage signal V INN is transmitted to the first input terminal in1 of the input stage comparator 12 through the first transistor M1. The control electrode of the second transistor M2 also receives a high level, and the second transistor M2 conducts under the control of the high level. The second voltage signal V INP is transmitted to the second input terminal in2 of the input stage comparator 12 through the second transistor M2. The first clock signal V CLK1 is converted into a low level through the first inverter F1. The control electrode of the third transistor M3 receives a low level, and the third transistor M3 is cut off under the control of the low level. The control electrode of the fourth transistor M4 also receives a low level, and the fourth transistor M4 is cut off under the control of the low level.

[0068] When the first clock signal V CLK1 is at the second level, the control electrode of the first transistor M1 receives a low level, and the first transistor M1 is cut off under the control of the low level. The control electrode of the second transistor M2 also receives a low level, and the second transistor M2 is cut off under the control of the low level. The first clock signal V CLK1It is converted into a high level by the first inverter F1. The control electrode of the third transistor M3 receives the high level, and the third transistor M3 is turned on under the control of the high level. The first voltage signal V INN is transmitted to the second input terminal in2 of the input stage comparator 12 through the third transistor M3. The control electrode of the fourth transistor M4 also receives the high level, and the fourth transistor M4 is turned on under the control of the high level. The second voltage signal V INP is transmitted to the first input terminal in1 of the input stage comparator 12 through the fourth transistor M4.

[0069] The commutation circuit 11 is designed with the above circuit structure. Under the control of the first clock signal V CLK1 , it can be realized that while the first transistor M1 and the second transistor M2 are turned on, the third transistor M3 and the fourth transistor M4 are turned off. The first voltage signal V INN is transmitted to the first input terminal in1 of the input stage comparator 12 through the first transistor M1, and the second voltage signal V INP is transmitted to the second input terminal in2 of the input stage comparator 12 through the second transistor M2. Moreover, while the first transistor M1 and the second transistor M2 are turned off, the third transistor M3 and the fourth transistor M4 are turned on. The first voltage signal V INN is transmitted to the second input terminal in2 of the input stage comparator 12 through the third transistor M3, and the second voltage signal V INP is transmitted to the first input terminal in1 of the input stage comparator 12 through the fourth transistor M4, thereby realizing the exchange of the input signals of the first input terminal in1 and the second input terminal in2 and realizing the phase switching of the first input terminal in1 and the second input terminal in2.

[0070] Figure 5 It is another architecture diagram of the voltage comparison circuit provided by the embodiment of the present application.

[0071] See Figure 5 , the voltage comparison circuit 1 includes a plurality of commutation circuits 11 and a plurality of input stage comparators 12. One commutation circuit 11 corresponds to and is connected to one input stage comparator 12. The plurality of commutation circuits 11 all receive the first voltage signal V INN , the second voltage signal V INP and the first clock signal V CLK1 , so that the plurality of input stage comparators 12 corresponding to the plurality of commutation circuits 11 are arranged in parallel. Each commutation circuit 11 can, under the control of the first clock signal V CLK1 , exchange the input signals of the first input terminal in1 and the second input terminal in2 of the corresponding input stage comparator 12, and realize the phase switching of the first input terminal in1 and the second input terminal in2.

[0072] Exemplarily, the voltage comparison circuit 1 includes two commutation circuits 11 and two input-stage comparators 12. The two input-stage comparators 12 are the first input-stage comparator 12a and the second input-stage comparator 12b respectively. The first input-stage comparator 12a receives the first voltage signal V INN , the second voltage signal V INP , and the first clock signal V CLK1 ( Figure 5 marked as V CLK1-1 in CLK1-1 for distinction). The commutation circuit 11 corresponding to the first input-stage comparator 12a can, under the control of V CLK1-1 , exchange the input signals of the first input terminal in1 and the second input terminal in2 of the first input-stage comparator 12a, so as to realize the phase switching of the first input-stage comparator 12a.

[0073] The second input-stage comparator 12b receives the first voltage signal V INN , the second voltage signal V INP , and the first clock signal V CLK1 ( Figure 5 marked as V CLK1-2 in CLK1-2 for distinction). The commutation circuit 11 corresponding to the second input-stage comparator 12b can, under the control of V CLK1-2 , exchange the input signals of the first input terminal in1 and the second input terminal in2 of the second input-stage comparator 12b, so as to realize the phase switching of the second input-stage comparator 12b.

[0074] In some embodiments, referring to Figure 5 continuously, the voltage comparison circuit 1 further includes a first gating unit 14 and a second gating unit 15. The first gating unit 14 is electrically connected to the first output terminals out1 of multiple input-stage comparators 12 and the third input terminal in3 of the output-stage comparator 13. The second gating unit 15 is electrically connected to the second output terminals out2 of multiple input-stage comparators 12 and the fourth input terminal in4 of the output-stage comparator 13.

[0075] The first gating unit 14 is configured to connect the first output terminal out1 of any one input-stage comparator 12 to the third input terminal in3 of the output-stage comparator 13 under the control of the second clock signal V CLK2 . The second gating unit 15 is configured to connect the second output terminal out2 of the same input-stage comparator 12 to the fourth input terminal in4 of the output-stage comparator 13 under the control of the second clock signal V CLK2 .

[0076] By setting the first gating unit 14 and the second gating unit 15, both the first gating unit 14 and the second gating unit 15 are controlled by the second clock signal V CLK2For the control, the first gating unit 14 can connect the first output terminal out1 of any one of the input-stage comparators 12 to the third input terminal in3 of the output-stage comparator 13, and the second gating unit 15 can connect the second output terminal out2 of the same input-stage comparator 12 to the fourth input terminal in4 of the output-stage comparator 13, thereby realizing using the output signal of any one of the input-stage comparators 12 as the input signal of the output-stage comparator 13.

[0077] For example, the second clock signal V CLK2 switches between the third level and the fourth level, and the first gating unit 14 and the second gating unit 15 can be controlled by switching the level of the second clock signal V CLK2 to switch the input-stage comparator 12 gated with the output-stage comparator 13.

[0078] In some embodiments, please continue to refer to Figure 5 , within each control period T, the level switching moments of the first clock signal V CLK1 received by different commutation circuits 11 are different (for example, the level switching moments of V CLK1-1 and V CLK1-2 are different), which can avoid simultaneous phase switching of multiple input-stage comparators 12, thereby avoiding affecting the output result of the output-stage comparator 13.

[0079] Taking any one of the multiple commutation circuits 11 as the target commutation circuit, and the input-stage comparator 12 corresponding to the target commutation circuit as the target input-stage comparator. Before the level of the first clock signal V CLK1 received by the target commutation circuit switches, the first gating unit 14 is controlled by the second clock signal V CLK2 to connect the first output terminal out1 of any one of the input-stage comparators 12 other than the target input-stage comparator to the third input terminal in3 of the output-stage comparator 13, and moreover, the second gating unit 15 is controlled by the second clock signal V CLK2 to connect the second output terminal out2 of the same input-stage comparator 12 to the fourth input terminal in4 of the output-stage comparator 13, which can avoid the phase switching of the target input-stage comparator from affecting the output of the output-stage comparator 13, thereby ensuring the normal logical function of the voltage comparison circuit 1.

[0080] In some embodiments, the voltage comparison circuit 1 further includes a first clock signal circuit and a second clock signal circuit, Figure 6 which is the structural block diagram of the first clock signal circuit and the second clock signal circuit provided by the embodiments of the present application.

[0081] Refer to Figure 6, the first clock signal circuit 21 includes at least one frequency division circuit 23 and at least one delay circuit 24. The first clock signal circuit 21 receives the clock source signal V CLK-IN , and the clock source signal V CLK-IN is a pulse signal. The frequency division circuit 23 is used to convert the frequency of the clock source signal V CLK-IN , and the delay circuit 24 is used to delay the clock source signal V CLK-IN to generate the first clock signal V CLK1 .

[0082] The second clock signal circuit 22 also includes at least one frequency division circuit 23 and at least one delay circuit 24. The second clock signal circuit 22 receives the clock source signal V CLK-IN and generates the second clock signal V CLK2 . The difference is that the number of frequency division circuits 23 in the second clock signal circuit 22 and the first clock signal circuit 21 is different, and the number of delay circuits 24 is different. Therefore, the frequency of the second clock signal V CLK2 is different from that of the first clock signal V CLK1 , and the moment of level switching is different.

[0083] According to the foregoing, the first clock signal V CLK1 switches between the first level and the second level, realizing the phase switching of the first input terminal in1 and the second input terminal in2 of the input stage comparator 12. By setting the second clock signal V CLK2 to be different from the first clock signal V CLK1 in frequency and the moment of level switching, during the phase switching process of the input stage comparator 12, it is avoided that the first gating unit 14 and the second gating unit 15 switch the input stage comparator 12 that is gated with the output stage comparator 13 under the control of the second clock signal V CLK2 , thereby avoiding the influence of the phase switching of the input stage comparator 12 on the output result of the output stage comparator 13 and ensuring the normal logical function of the voltage comparison circuit 1.

[0084] Exemplarily, the above frequency division circuit 23 can be a frequency divider by two, and the frequency divider by two can be used to divide the frequency of the clock source signal V CLK-IN into two equal parts. The delay circuit 24 can be an inverter, and the delay can be performed by controlling the conduction time of the transistor in the inverter.

[0085] For example, the number of frequency dividers by two in the second clock signal circuit 22 is one less than the number of frequency dividers by two in the first clock signal circuit 21. Therefore, the frequency of the second clock signal V CLK2 is twice the frequency of the first clock signal V CLK1 .

[0086] In some embodiments, please continue to refer to Figure 5 , when the voltage comparison circuit 1 includes two commutation circuits 11 and two input-stage comparators 12, and the two input-stage comparators 12 are the first input-stage comparator 12a and the second input-stage comparator 12b respectively, the embodiments of the present application provide a circuit structure design of a first gating unit 14 and a second gating unit 15.

[0087] Both the first gating unit 14 and the second gating unit 15 have two input ports and one output port. The two input ports of the first gating unit 14 are respectively connected to the first output terminals out1 of the first input-stage comparator 12a and the second input-stage comparator 12b, and one output port of the first gating unit 14 is connected to the third input terminal in3 of the output-stage comparator 13. The two input ports of the second gating unit 15 are respectively connected to the second output terminals out2 of the first input-stage comparator 12a and the second input-stage comparator 12b, and one output port of the second gating unit 15 is connected to the fourth input terminal in4 of the output-stage comparator 13.

[0088] It can be understood that the commutation circuit 11 corresponding to the first input-stage comparator 12a switches the phase of the first input-stage comparator 12a under the control of the first clock signal V CLK1-1 . Before the first input-stage comparator 12a switches the phase, the first gating unit 14 and the second gating unit 15 are controlled to connect the first output terminal out1 of the second input-stage comparator 12b to the third input terminal in3 of the output-stage comparator 13, and connect the second output terminal out2 of the second input-stage comparator 12b to the fourth input terminal in4 of the output-stage comparator 13, which can avoid the influence of the phase switching of the first input-stage comparator 12a on the output result of the output-stage comparator 13.

[0089] Alternatively, the commutation circuit 11 corresponding to the second input-stage comparator 12b switches the phase of the second input-stage comparator 12b under the control of the first clock signal V CLK1-2 . Before the second input-stage comparator 12b switches the phase, the first gating unit 14 and the second gating unit 15 are controlled to connect the first output terminal out1 of the first input-stage comparator 12a to the third input terminal in3 of the output-stage comparator 13, and connect the second output terminal out2 of the first input-stage comparator 12a to the fourth input terminal in4 of the output-stage comparator 13, which can avoid the influence of the phase switching of the second input-stage comparator 12b on the output result of the output-stage comparator 13.

[0090] The first input-stage comparator 12a and the second input-stage comparator 12b are alternately connected to the output-stage comparator 13, and their output signals are alternately input to the output-stage comparator 13. Therefore, the first input-stage comparator 12a and the second input-stage comparator 12b form an alternately operating "ping-pang" architecture.

[0091] Figure 7 It is the circuit diagram of the first gating unit 14 provided by the embodiment of the present application; Figure 8 It is the circuit diagram of the second gating unit 15 provided by the embodiment of the present application.

[0092] See Figure 7 , the first gating unit 14 includes a fifth transistor M5, a sixth transistor M6 and a second inverter F2.

[0093] The fifth transistor M5 includes a control electrode, a first electrode and a second electrode. The control electrode of the fifth transistor M5 is configured to receive a second clock signal V CLK2 , the first electrode of the fifth transistor M5 is electrically connected to the first output terminal out1 of the first input-stage comparator 12a, and the second electrode of the fifth transistor M5 is electrically connected to the third input terminal in3 of the output-stage comparator 13.

[0094] The sixth transistor M6 includes a control electrode, a first electrode and a second electrode. The control electrode of the sixth transistor M6 is electrically connected to the control electrode of the fifth transistor M5 through the second inverter F2. The first electrode of the sixth transistor M6 is electrically connected to the first output terminal out1 of the second input-stage comparator 12b, and the second electrode of the sixth transistor M6 is electrically connected to the third input terminal in3 of the output-stage comparator 13.

[0095] See Figure 8 , the second gating unit 15 includes a seventh transistor M7, an eighth transistor M8 and a third inverter F3.

[0096] The seventh transistor M7 includes a control electrode, a first electrode and a second electrode. The control electrode of the seventh transistor M7 is configured to receive a second clock signal V CLK2 , the first electrode of the seventh transistor M7 is electrically connected to the second output terminal out2 of the first input-stage comparator 12a, and the second electrode of the seventh transistor M7 is electrically connected to the fourth input terminal in4 of the output-stage comparator 13.

[0097] The eighth transistor M8 includes a control electrode, a first electrode and a second electrode. The control electrode of the eighth transistor M8 is electrically connected to the control electrode of the seventh transistor M7 through the third inverter F3. The first electrode of the eighth transistor M8 is electrically connected to the second output terminal out2 of the second input-stage comparator 12b, and the second electrode of the eighth transistor M8 is electrically connected to the fourth input terminal in4 of the output-stage comparator 13.

[0098] It can be understood that the fifth transistor M5 to the eighth transistor M8 can be P-type transistors or N-type transistors, and the embodiments of the present application do not limit this.

[0099] Exemplarily, the fifth transistor M5 to the eighth transistor M8 are all N-type transistors, and the second clock signal V CLK2 Switches between the third level and the fourth level, taking the third level as the high level and the fourth level as the low level as an example.

[0100] When the second clock signal V CLK2 Is at the third level, the control electrode of the fifth transistor M5 receives a high level, and the fifth transistor M5 conducts under the control of the high level. The first output terminal out1 of the first input stage comparator 12a is connected to the third input terminal in3 of the output stage comparator 13 through the fifth transistor M5. The second clock signal V CLK2 Is converted into a low level by the second inverter F2, and the control electrode of the sixth transistor M6 receives a low level, and the sixth transistor M6 is cut off under the control of the low level.

[0101] Moreover, the control electrode of the seventh transistor M7 receives a high level, and the seventh transistor M7 conducts under the control of the high level. The second output terminal out2 of the first input stage comparator 12a is connected to the fourth input terminal in4 of the output stage comparator 13 through the seventh transistor M7. The second clock signal V CLK2 Is converted into a low level by the third inverter F3, and the control electrode of the eighth transistor M8 receives a low level, and the eighth transistor M8 is cut off under the control of the low level.

[0102] When the second clock signal V CLK2 Is at the fourth level, the control electrode of the fifth transistor M5 receives a low level, and the fifth transistor M5 is cut off under the control of the low level. The second clock signal V CLK2 Is converted into a high level by the second inverter F2, and the control electrode of the sixth transistor M6 receives a high level, and the sixth transistor M6 conducts under the control of the high level. The first output terminal out1 of the second input stage comparator 12b is connected to the third input terminal in3 of the output stage comparator 13 through the sixth transistor M6.

[0103] Moreover, the control electrode of the seventh transistor M7 receives a low level, and the seventh transistor M7 is cut off under the control of the low level. The second clock signal V CLK2 Is converted into a high level by the third inverter F3, and the control electrode of the eighth transistor M8 receives a high level, and the eighth transistor M8 conducts under the control of the high level. The second output terminal out2 of the second input stage comparator 12b is connected to the fourth input terminal in4 of the output stage comparator 13 through the eighth transistor M8.

[0104] The first gating unit 14 and the second gating unit 15 adopt the above circuit structure design. Under the control of the second clock signal V CLK2 , it can be realized that while the fifth transistor M5 and the seventh transistor M7 are conducting, the sixth transistor M6 and the eighth transistor M8 are cut off, so that the first output terminal out1 of the first input stage comparator 12a is connected to the third input terminal in3 of the output stage comparator 13 through the fifth transistor M5, and the second output terminal out2 of the first input stage comparator 12a is connected to the fourth input terminal in4 of the output stage comparator 13 through the seventh transistor M7.

[0105] Moreover, while the fifth transistor M5 and the seventh transistor M7 are cut off, the sixth transistor M6 and the eighth transistor M8 are conducting, so that the first output terminal out1 of the second input stage comparator 12b is connected to the third input terminal in3 of the output stage comparator 13 through the sixth transistor M6, and the second output terminal out2 of the second input stage comparator 12b is connected to the fourth input terminal in4 of the output stage comparator 13 through the eighth transistor M8.

[0106] In some embodiments, please continue to refer to Figure 5 . The output stage comparator 13 further includes a third output terminal out3 and a fourth output terminal out4. For example, the third output terminal out3 is the in-phase output terminal of the output stage comparator 13, and the fourth output terminal out4 is the anti-phase output terminal of the output stage comparator 13.

[0107] The voltage comparison circuit 1 further includes a third gating unit 16. The third gating unit 16 is electrically connected to the third output terminal out3, the fourth output terminal out4 of the output stage comparator 13, and the output terminal OUT of the voltage comparison circuit 1. The third gating unit 16 is configured to connect the third output terminal out3 of the output stage comparator 13 to the output terminal OUT of the voltage comparison circuit 1 under the control of the third clock signal V CLK3 , so as to use the electrical signal output from the third output terminal out3 as the output signal V out of the voltage comparison circuit 1.

[0108] Alternatively, the third gating unit 16 is further configured to connect the fourth output terminal out4 of the output stage comparator 13 to the output terminal OUT of the voltage comparison circuit 1 under the control of the third clock signal V CLK3 , so as to use the electrical signal output from the fourth output terminal out4 as the output signal V out of the voltage comparison circuit 1.

[0109] Exemplarily, the third clock signal V CLK3 can also be generated by a corresponding signal circuit receiving the clock source signal V CLK-IN . For example, through at least one frequency division circuit 23 for the clock source signal VCLK-IN is converted in frequency, and the clock source signal V is delayed by at least one delay circuit 24 CLK-IN to generate a third clock signal V CLK3 .

[0110] Figure 9 is the circuit diagram of the third gating unit 16 provided by the embodiment of the present application.

[0111] Referring to Figure 9 , the third gating unit 16 includes a ninth transistor M9, a tenth transistor M10, and a fourth inverter F4.

[0112] The ninth transistor M9 includes a control electrode, a first electrode, and a second electrode. The control electrode of the ninth transistor M9 is configured to receive the third clock signal V CLK3 . The first electrode of the ninth transistor M9 is electrically connected to the third output terminal out3 of the output stage comparator 13, and the second electrode of the ninth transistor M9 is electrically connected to the output terminal OUT of the voltage comparison circuit 1.

[0113] The tenth transistor M10 includes a control electrode, a first electrode, and a second electrode. The control electrode of the tenth transistor M10 is electrically connected to the control electrode of the ninth transistor M9 through the fourth inverter F4. The first electrode of the tenth transistor M10 is electrically connected to the fourth output terminal out4 of the output stage comparator 13, and the second electrode of the tenth transistor M10 is electrically connected to the output terminal OUT of the voltage comparison circuit 1.

[0114] It can be understood that the ninth transistor M9 and the tenth transistor M10 can be P-type transistors or N-type transistors, and the embodiments of the present application do not limit this.

[0115] Exemplarily, both the ninth transistor M9 and the tenth transistor M10 are N-type transistors. The third clock signal V CLK3 switches between a fifth level and a sixth level, taking the fifth level as the high level and the sixth level as the low level as an example.

[0116] When the third clock signal V CLK3 is at the fifth level, the control electrode of the ninth transistor M9 receives a high level, and the ninth transistor M9 conducts under the control of the high level. The third output terminal out3 of the output stage comparator 13 is connected to the output terminal OUT of the voltage comparison circuit 1 through the ninth transistor M9. The third clock signal V CLK3 is converted into a low level by the fourth inverter F4, the control electrode of the tenth transistor M10 receives a low level, and the tenth transistor M10 is cut off under the control of the low level.

[0117] When the third clock signal V CLK3When it is the sixth level, the control electrode of the ninth transistor M9 receives a low level, and the ninth transistor M9 is cut off under the control of the low level. The third clock signal V CLK3 is converted into a high level through the fourth inverter F4. The control electrode of the tenth transistor M10 receives the high level, and the tenth transistor M10 is turned on under the control of the high level. The fourth output terminal out4 of the output stage comparator 13 is connected to the output terminal OUT of the voltage comparison circuit 1 through the tenth transistor M10.

[0118] The third selection unit 16 is designed with the above circuit structure. Under the control of the third clock signal V CLK3 , it can achieve that the ninth transistor M9 is turned on while the tenth transistor M10 is cut off, so that the third output terminal out3 of the output stage comparator 13 is connected to the output terminal OUT of the voltage comparison circuit 1. Moreover, when the ninth transistor M9 is cut off, the tenth transistor M10 is turned on, so that the fourth output terminal out4 of the output stage comparator 13 is connected to the output terminal OUT of the voltage comparison circuit 1.

[0119] The embodiment of the present application also provides the control method of the above voltage comparison circuit 1, Figure 10 which is the control timing diagram of the voltage comparison circuit 1 provided by the embodiment of the present application.

[0120] Referring to Figure 10 , a control period T of the voltage comparison circuit 1 includes a first stage S1, a second stage S2, a third stage S3, and a fourth stage S4, a total of four stages. The moment when the first stage S1 ends and the second stage S2 starts is t1, the moment when the second stage S2 ends and the third stage S3 starts is t2, and the moment when the third stage S3 ends and the fourth stage S4 starts is t3.

[0121] Among them, the first clock signals V CLK1-1 and V CLK1-2 , the second clock signal V CLK2 , and the third clock signal V CLK3 these four clock signals can all be obtained by frequency division and delay processing of the clock source signal V CLK-IN . The first clock signals V CLK1-1 , V CLK1-2 , and the third clock signal V CLK3 have the same frequency, and the frequency of the second clock signal V CLK2 is twice their frequency.

[0122] Moreover, the first clock signals V CLK1-1 and V CLK1-2 have a phase difference. Within the control period T, the phase difference between the first clock signals V CLK1-1 and V CLK1-2 is not n = 0, 1, 2, so that the level switching moments of the first clock signals V CLK1-1 and V CLK1-2 are different, thereby avoiding simultaneous phase switching of the first input stage comparator 12a and the second input stage comparator 12b, and avoiding affecting the output result of the output stage comparator 13.

[0123] The control method of the voltage comparison circuit 1 includes: in the first stage S1, the first clock signals V CLK1-1 and V CLK1-2 are both at high level, the second clock signal V CLK2 switches from low level to high level, and the third clock signal V CLK3 is at low level.

[0124] Combined with Figure 4 and Figure 5 , the commutation circuit 11 corresponding to the first input stage comparator 12a receives the first voltage signal V INN , the second voltage signal V INP , and the first clock signal V CLK1-1 . The commutation circuit 11 can, under the control of the first clock signal V CLK1-1 , transmit the first voltage signal V INN to the first input terminal in1 of the input stage comparator 12, and transmit the second voltage signal V INP to the second input terminal in2 of the input stage comparator 12.

[0125] When the second voltage signal V INP is greater than the first voltage signal V INN , the first output terminal out1 of the first input stage comparator 12a outputs "1 (high level)", and the second output terminal out2 outputs "0 (low level)".

[0126] Similarly, the commutation circuit 11 corresponding to the second input stage comparator 12b receives the first voltage signal V INN , the second voltage signal V INP , and the first clock signal V CLK1-2 . The commutation circuit 11 can, under the control of the first clock signal V CLK1-2 , transmit the first voltage signal V INN to the first input terminal in1 of the input stage comparator 12, and transmit the second voltage signal V INP to the second input terminal in2 of the input stage comparator 12.

[0127] When the second voltage signal V INP is greater than the first voltage signal V INNIn this case, the first output terminal out1 of the second input stage comparator 12b outputs "1 (high level)", and the second output terminal out2 outputs "0 (low level)".

[0128] Combined with Figure 5 , Figure 7 and Figure 8 , the second clock signal V CLK2 switches from low level to high level. When the second clock signal V CLK2 is at low level, the first gating unit 14, under the control of the second clock signal V CLK2 , connects the first output terminal out1 of the second input stage comparator 12b to the third input terminal in3 of the output stage comparator 13. The second gating unit 15, under the control of the second clock signal V CLK2 , connects the second output terminal out2 of the second input stage comparator 12b to the fourth input terminal in4 of the output stage comparator 13.

[0129] The third input terminal in3 of the output stage comparator 13 receives "1", and the fourth input terminal in4 receives "0". Therefore, the third output terminal out3 of the output stage comparator 13 outputs "0", and the fourth output terminal out4 outputs "1".

[0130] When the second clock signal V CLK2 is at high level, the first gating unit 14, under the control of the second clock signal V CLK2 , connects the first output terminal out1 of the first input stage comparator 12a to the third input terminal in3 of the output stage comparator 13. The second gating unit 15, under the control of the second clock signal V CLK2 , connects the second output terminal out2 of the first input stage comparator 12a to the fourth input terminal in4 of the output stage comparator 13.

[0131] At this time, the third input terminal in3 of the output stage comparator 13 still receives "1", and the fourth input terminal in4 still receives "0". The third output terminal out3 of the output stage comparator 13 outputs "0", and the fourth output terminal out4 outputs "1".

[0132] Combined with Figure 5 and Figure 9 , the third gating unit 16, under the control of the third clock signal V CLK3 , connects the fourth output terminal out4 of the output stage comparator 13 to the output terminal OUT of the voltage comparison circuit 1. The output signal V out of the voltage comparison circuit 1 is "1", and the logic of the voltage comparison circuit 1 is correct.

[0133] At time t1, the first clock signal V CLK1-2Switches from high level to low level. In the second stage S2, the first clock signal V CLK1-2 is at low level, and the first clock signal V CLK1-1 remains at high level. The second clock signal V CLK2 switches from high level to low level, and the third clock signal V CLK3 switches from low level to high level.

[0134] Combined with Figure 4 and Figure 5 , the commutation circuit 11 corresponding to the second input stage comparator 12b, under the control of the first clock signal V CLK1-2 , transmits the first voltage signal V INN to the second input terminal in2 of the second input stage comparator 12b, and transmits the second voltage signal V INP to the first input terminal in1 of the second input stage comparator 12b, and the second input stage comparator 12b completes the phase switching.

[0135] At this time, when the second voltage signal V INP is greater than the first voltage signal V INN , the first output terminal out1 of the second input stage comparator 12b outputs "0", and the second output terminal out2 outputs "1".

[0136] It can be understood that in the first stage S1, by switching the second clock signal V CLK2 from low level to high level, the first output terminal out1 of the first input stage comparator 12a is connected to the third input terminal in3 of the output stage comparator 13, and the second output terminal out2 of the first input stage comparator 12a is connected to the fourth input terminal in4 of the output stage comparator 13. When the first clock signal V CLK1-2 switches from high level to low level, it can avoid the influence of the phase switching of the second input stage comparator 12b on the output of the output stage comparator 13 and reduce the dynamic risk caused by the phase switching.

[0137] Combined with Figure 5 , Figure 7 and Figure 8 , the second clock signal V CLK2 switches from high level to low level. The first gating unit 14, under the control of the low level of the second clock signal V CLK2 , connects the first output terminal out1 of the second input stage comparator 12b to the third input terminal in3 of the output stage comparator 13. The second gating unit 15, under the control of the low level of the second clock signal V CLK2 , connects the second output terminal out2 of the second input stage comparator 12b to the fourth input terminal in4 of the output stage comparator 13.

[0138] At this time, the third input terminal in3 of the output stage comparator 13 receives "0", and the fourth input terminal in4 receives "1". Therefore, the third output terminal out3 of the output stage comparator 13 outputs "1", and the fourth output terminal out4 outputs "0".

[0139] Combined with Figure 5 and Figure 9 , the third clock signal V CLK3 switches from low level to high level. Under the control of the high level of the third clock signal V CLK3 , the third output terminal out3 of the output stage comparator 13 is connected to the output terminal OUT of the voltage comparison circuit 1. The output signal V out of the voltage comparison circuit 1 is "1", and the logic of the voltage comparison circuit 1 is correct.

[0140] At time t2, the first clock signal V CLK1-1 switches from high level to low level. In the third stage S3, the first clock signal V CLK1-1 is at low level, the first clock signal V CLK1-2 remains at low level, the second clock signal V CLK2 switches from low level to high level, and the third clock signal V CLK3 remains at high level.

[0141] Combined with Figure 4 and Figure 5 , the commutation circuit 11 corresponding to the first input stage comparator 12a transmits the first voltage signal V CLK1-2 to the second input terminal in2 of the first input stage comparator 12a under the control of the first clock signal V INN , and transmits the second voltage signal V INP to the first input terminal in1 of the first input stage comparator 12a. The first input stage comparator 12a completes the phase switching.

[0142] At this time, when the second voltage signal V INP is greater than the first voltage signal V INN , the first output terminal out1 of the first input stage comparator 12a outputs "0", and the second output terminal out2 outputs "1".

[0143] It can be understood that in the second stage S2, by switching the second clock signal V CLK2 from high level to low level, the first output terminal out1 of the second input stage comparator 12b is connected to the third input terminal in3 of the output stage comparator 13, and the second output terminal out2 of the second input stage comparator 12b is connected to the fourth input terminal in4 of the output stage comparator 13. In the first clock signal V CLK1-1When switching from high level to low level, the phase switching of the first input stage comparator 12a can be avoided from affecting the output of the output stage comparator 13, reducing the dynamic risk caused by phase switching.

[0144] Combined with Figure 5 、 Figure 7 and Figure 8 , the second clock signal V CLK2 switches from low level to high level. Under the control of the high level of the second clock signal V CLK2 , the first gating unit 14 connects the first output terminal out1 of the first input stage comparator 12a to the third input terminal in3 of the output stage comparator 13. Under the control of the high level of the second clock signal V CLK2 , the second gating unit 15 connects the second output terminal out2 of the first input stage comparator 12a to the fourth input terminal in4 of the output stage comparator 13.

[0145] At this time, the third input terminal in3 of the output stage comparator 13 receives "0", and the fourth input terminal in4 receives "1". Therefore, the third output terminal out3 of the output stage comparator 13 outputs "1", and the fourth output terminal out4 outputs "0".

[0146] Combined with Figure 5 and Figure 9 , the third clock signal V CLK3 remains high. Under the control of the high level of the third clock signal V CLK3 , the third gating unit 16 connects the third output terminal out3 of the output stage comparator 13 to the output terminal OUT of the voltage comparison circuit 1. The output signal V out of the voltage comparison circuit 1 is "1", and the logic of the voltage comparison circuit 1 is correct.

[0147] At time t3, the first clock signal V CLK1-2 switches from low level to high level. In the fourth stage S4, the first clock signal V CLK1-2 is high level, the first clock signal V CLK1-1 remains low level unchanged, the second clock signal V CLK2 switches from high level to low level, and the third clock signal V CLK3 switches from high level to low level.

[0148] Combined with Figure 4 and Figure 5 , the commutation circuit 11 corresponding to the second input stage comparator 12b, under the control of the first clock signal V CLK1-2 , transmits the first voltage signal V INN to the first input terminal in1 of the input stage comparator 12, and transmits the second voltage signal V INPIt is transmitted to the second input terminal in2 of the input - stage comparator 12, and the second input - stage comparator 12b completes the phase - switching again.

[0149] When the second voltage signal V INP is greater than the first voltage signal V INN , the first output terminal out1 of the second input - stage comparator 12b outputs "1", and the second output terminal out2 outputs "0".

[0150] It can be understood that in the third stage S3, with the second clock signal V CLK2 switching from low level to high level, the first output terminal out1 of the first input - stage comparator 12a is connected to the third input terminal in3 of the output - stage comparator 13, and the second output terminal out2 of the first input - stage comparator 12a is connected to the fourth input terminal in4 of the output - stage comparator 13. When the first clock signal V CLK1-2 switches from low level to high level, it can avoid the influence of the phase - switching of the second input - stage comparator 12b on the output of the output - stage comparator 13 and reduce the dynamic risk caused by the phase - switching.

[0151] Combined with Figure 5 、 Figure 7 and Figure 8 , when the second clock signal V CLK2 switches from high level to low level, the first gating unit 14, under the control of the low level of the second clock signal V CLK2 , connects the first output terminal out1 of the second input - stage comparator 12b to the third input terminal in3 of the output - stage comparator 13. The second gating unit 15, under the control of the low level of the second clock signal V CLK2 , connects the second output terminal out2 of the second input - stage comparator 12b to the fourth input terminal in4 of the output - stage comparator 13.

[0152] At this time, the third input terminal in3 of the output - stage comparator 13 receives "1", and the fourth input terminal in4 receives "0". Therefore, the third output terminal out3 of the output - stage comparator 13 outputs "0", and the fourth output terminal out4 outputs "1".

[0153] Combined with Figure 5 and Figure 9 , when the third clock signal V CLK3 switches from high level to low level, the third gating unit 16, under the control of the low level of the third clock signal V CLK3 , connects the fourth output terminal out4 of the output - stage comparator 13 to the output terminal OUT of the voltage - comparison circuit 1. The output signal V out of the voltage - comparison circuit 1 is "1", and the logic of the voltage - comparison circuit 1 is correct.

[0154] It can be seen that for the control method provided by the above embodiments of the present application, when the voltage deviation of the voltage comparison circuit 1 is 0 and the input signal of the voltage comparison circuit 1 satisfies that the second voltage signal V INP is greater than the first voltage signal V INN , the output signal V out of the voltage comparison circuit 1 can always be guaranteed to be "1".

[0155] Similarly, when the second voltage signal V INP is less than the first voltage signal V INN , the output signal V out of the voltage comparison circuit 1 can always be guaranteed to be "0".

[0156] The embodiments of the present application further provide a chip, in which the voltage comparison circuit 1 in the above embodiments is mounted.

[0157] Taking the chip as a switching power supply chip as an example, Figure 11 FIG. is the structural block diagram of the switching power supply chip provided by the embodiments of the present application.

[0158] Referring to Figure 11 , the switching power supply chip 3 includes detection circuits such as a controller 31, an overvoltage protection circuit 32, an undervoltage protection circuit 33, an overcurrent protection circuit 34, and an overtemperature protection circuit 35. The overvoltage protection circuit 32, the undervoltage protection circuit 33, the overcurrent protection circuit 34, and the overtemperature protection circuit 35 are all electrically connected to the controller 31.

[0159] The overvoltage protection circuit 32 can perform overvoltage detection under the control of the controller 31, the undervoltage protection circuit 33 can perform undervoltage detection under the control of the controller 31, the overcurrent protection circuit 34 can perform overcurrent detection under the control of the controller 31, and the overtemperature protection circuit 35 can perform overtemperature detection under the control of the controller 31.

[0160] The overvoltage protection circuit 32, the undervoltage protection circuit 33, the overcurrent protection circuit 34, and the overtemperature protection circuit 35 are all mounted with the voltage comparison circuit 1. The voltage comparison circuit 1 works in the non-equilibrium state of the input signal for a long time in these application scenarios. By switching the phase at the input end of the voltage comparison circuit 1, the unilateral aging problem of circuit devices can be improved, the voltage deviation of circuit devices can be reduced, which is beneficial to improving the detection accuracy of the detection circuit.

[0161] Embodiments of the present application further provide an electronic device, which may be, for example, a mobile phone, a tablet computer, a personal digital assistant (PDA), a television, a smart wearable product (such as a smart watch, a smart bracelet), a virtual reality (VR) terminal device, an augmented reality (AR) terminal device, a charging household small appliance (such as a soymilk machine, a floor sweeping robot), a drone, a radar, an aerospace device, a vehicle-mounted device, and other different types of user equipment or terminal devices; the electronic device may also be a network device such as a base station. Embodiments of the present application do not impose special restrictions on the specific form of the electronic device.

[0162] For the convenience of further explaining the structure of the electronic device, the following takes the electronic device as a mobile phone as an example for exemplary introduction.

[0163] Figure 12 It is an exploded view of the mobile phone provided by the embodiment of the present application.

[0164] See Figure 12 , the electronic device 4 may further include a middle frame 45, a rear shell 46, and a display screen 47. The rear shell 46 and the display screen 47 are respectively located on opposite sides of the middle frame 45, and the middle frame 45 and the display screen 47 are disposed within the rear shell 46. The middle frame 45 includes a carrier plate 450 for carrying the display screen 47, and a frame 451 surrounding the carrier plate 450 for one week.

[0165] Continue to refer to Figure 12 , the electronic device 4 may further include the chip and the circuit board 48 in the above embodiment. The circuit board 48 is disposed on the side of the carrier plate 450 close to the rear shell 46. The chip may be disposed on the circuit board 48 and electrically connected to the circuit board 48.

[0166] The above are only specific embodiments of the present invention, but the protection scope of the present invention is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed by the present invention should be covered by the protection scope of the present invention. Therefore, the protection scope of the present invention should be subject to the protection scope of the claims.

Claims

1. A voltage comparison circuit, characterized in that, the voltage comparison circuit includes a commutation circuit, an input-stage comparator, and an output-stage comparator; the input-stage comparator includes a first input terminal and a second input terminal, and the commutation circuit is electrically connected to the first input terminal and the second input terminal; the commutation circuit is configured to receive a first voltage signal, a second voltage signal, and a first clock signal. When the first voltage signal is greater than the second voltage signal, the first clock signal switches between a first level and a second level; the commutation circuit is further configured to, under the control of the first level, transmit the first voltage signal to the first input terminal and transmit the second voltage signal to the second input terminal, and, under the control of the second level, transmit the first voltage signal to the second input terminal and transmit the second voltage signal to the first input terminal; the input-stage comparator further includes a first output terminal and a second output terminal, the output-stage comparator includes a third input terminal and a fourth input terminal, the third input terminal is electrically connected to the first output terminal, and the fourth input terminal is electrically connected to the second output terminal.

2. The voltage comparison circuit according to claim 1, characterized in that, the commutation circuit includes a first transistor, a second transistor, a third transistor, a fourth transistor, and a first inverter; the first transistor includes a control electrode, a first pole, and a second pole. The control electrode of the first transistor is configured to receive the first clock signal, the first pole of the first transistor is configured to receive the first voltage signal, and the second pole of the first transistor is electrically connected to the first input terminal; the second transistor includes a control electrode, a first pole, and a second pole. The control electrode of the second transistor is configured to receive the first clock signal, the first pole of the second transistor is configured to receive the second voltage signal, and the second pole of the second transistor is electrically connected to the second input terminal; the third transistor includes a control electrode, a first pole, and a second pole. The control electrode of the third transistor is electrically connected to the control electrode of the first transistor through the first inverter. The first pole of the third transistor is configured to receive the first voltage signal, and the second pole of the third transistor is electrically connected to the second input terminal; the fourth transistor includes a control electrode, a first pole, and a second pole. The control electrode of the fourth transistor is electrically connected to the control electrode of the first transistor through the first inverter. The first pole of the fourth transistor is configured to receive the second voltage signal, and the second pole of the fourth transistor is electrically connected to the first input terminal.

3. The voltage comparison circuit according to claim 1 or 2, characterized in that, the voltage comparison circuit includes a plurality of the commutation circuits and a plurality of the input-stage comparators, and one commutation circuit corresponds to and is connected to one input-stage comparator.

4. The voltage comparison circuit according to claim 3, characterized in that, The voltage comparison circuit further includes a first gating unit and a second gating unit. The first gating unit is electrically connected to the first output ends of the plurality of input-stage comparators and the third input end. The second gating unit is electrically connected to the second output ends of the plurality of input-stage comparators and the fourth input end; The first gating unit is configured to connect the first output end of any one input-stage comparator to the third input end under the control of the second clock signal. The second gating unit is configured to connect the second output end of the same input-stage comparator to the fourth input end under the control of the second clock signal.

5. The voltage comparison circuit according to claim 4, wherein, the voltage comparison circuit further includes a first clock signal circuit and a second clock signal circuit. The first clock signal circuit is configured to receive a clock source signal and generate the first clock signal. The second clock signal circuit is configured to receive the clock source signal and generate the second clock signal. Both the first clock signal circuit and the second clock signal circuit include at least one frequency division circuit and at least one delay circuit; the number of the frequency division circuits in the second clock signal circuit and the first clock signal circuit is different, and the number of the delay circuits is different.

6. The voltage comparison circuit according to claim 4 or 5, wherein, The first clock signals received by different commutation circuits have a phase difference, and within one control period, the phase difference of the first clock signals received by different commutation circuits is not 2, where T is the duration of the control period; the second clock signal switches between a third level and a fourth level; among the plurality of first clock signals received by the plurality of commutation circuits, before the level of each first clock signal switches, the second clock signal performs a level switch.

7. The voltage comparison circuit according to any one of claims 4 to 6, wherein, the plurality of input-stage comparators include a first input-stage comparator and a second input-stage comparator; the first gating unit includes a fifth transistor, a sixth transistor, and a second inverter; the fifth transistor includes a control electrode, a first electrode, and a second electrode. The control electrode of the fifth transistor is configured to receive the second clock signal. The first electrode of the fifth transistor is electrically connected to the first output end of the first input-stage comparator. The second electrode of the fifth transistor is electrically connected to the third input end; the sixth transistor includes a control electrode, a first electrode, and a second electrode. The control electrode of the sixth transistor is electrically connected to the control electrode of the fifth transistor through the second inverter. The first electrode of the sixth transistor is electrically connected to the first output end of the second input-stage comparator. The second electrode of the sixth transistor is electrically connected to the third input end; the second gating unit includes a seventh transistor, an eighth transistor, and a third inverter; the seventh transistor includes a control electrode, a first electrode, and a second electrode. The control electrode of the seventh transistor is configured to receive the second clock signal. The first electrode of the seventh transistor is electrically connected to the second output end of the first input-stage comparator. The second electrode of the seventh transistor is electrically connected to the fourth input end; The eighth transistor includes a control electrode, a first electrode, and a second electrode. The control electrode of the eighth transistor is electrically connected to the control electrode of the seventh transistor through the third inverter. The first electrode of the eighth transistor is electrically connected to the second output terminal of the second input stage comparator. The second electrode of the eighth transistor is electrically connected to the fourth input terminal.

8. The voltage comparison circuit according to any one of claims 1 to 7, wherein, the output stage comparator further includes a third output terminal and a fourth output terminal; the voltage comparison circuit further includes a third gating unit, and the third gating unit is electrically connected to the third output terminal, the fourth output terminal, and the output terminal of the voltage comparison circuit; the third gating unit is configured to connect the third output terminal to the output terminal of the voltage comparison circuit or connect the fourth output terminal to the output terminal of the voltage comparison circuit under the control of a third clock signal.

9. The voltage comparison circuit according to claim 8, wherein, the third gating unit includes a ninth transistor, a tenth transistor, and a fourth inverter; the ninth transistor includes a control electrode, a first electrode, and a second electrode. The control electrode of the ninth transistor is configured to receive the third clock signal. The first electrode of the ninth transistor is electrically connected to the third output terminal. The second electrode of the ninth transistor is electrically connected to the output terminal of the voltage comparison circuit; the tenth transistor includes a control electrode, a first electrode, and a second electrode. The control electrode of the tenth transistor is electrically connected to the control electrode of the ninth transistor through the fourth inverter. The first electrode of the tenth transistor is electrically connected to the fourth output terminal. The second electrode of the tenth transistor is electrically connected to the output terminal of the voltage comparison circuit.

10. A chip, wherein, it includes: the voltage comparison circuit according to any one of claims 1 to 9; a controller, electrically connected to the voltage comparison circuit.

11. An electronic device, wherein, it includes: the chip according to claim 10; a circuit board, and the chip is electrically connected to the circuit board.

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