Ultra-low power consumption anti-single event transient level shifter

Abstract

The invention relates to an ultra-low power consumption anti-single event transient level shifter. The level shifter comprises a main body output stage and an auxiliary circuit, the main body output stage adopts a DICE structure and is used for quickly releasing charges after being impacted by SET charges through two pull-down channels arranged on each node in the DICE structure; the auxiliary circuit comprises two improved LEDC structures; the improved LEDC structure is used for controlling the quiescent current in the improved LEDC structure to be completely cut off through an additional control signal by introducing the additional control signal for the DICE structure. The level shifter rapidly releases charges to keep stable output after being impacted by SET charges, and compared with a traditional LEDC structure, the improved LEDC structure can completely solve the problem of quiescent current in a circuit, and ultralow static power consumption of the whole circuit is achieved.

Description

Technical Field

[0001] The present application relates to the technical field of integrated circuit design, and particularly to a level shifter with ultra-low power consumption and single-event transient resistance. Background Art

[0002] With the progress of aerospace technology and MOS transistor technology, the requirements for circuit performance indicators are no longer limited to traditional indicators such as delay and area. Single-event transient effect (SET) and static power consumption have gradually become key indicators that need to be focused on in design. The SET effect is one of the most common circuit soft errors, which originates from the impact of high-energy particles on the semiconductor region of MOS transistors, and then introduces current pulses in the semiconductor, changing the voltage and current of the corresponding nodes, resulting in abnormal working states of MOS transistors. In sequential circuits, this abnormal signal will be transmitted step by step, ultimately affecting multiple modules in the entire system. The level shifter (LS) module, as an important part of sequential circuits, is widely used in the connection between analog and digital circuits and between modules with different operating voltages. However, there is currently a relative lack of research on the resistance of level shifter circuits to the SET effect. Due to the relatively simple and fragile structural design of level shifter circuits, when affected by the SET effect, the output waveform is prone to perturbation, thereby affecting signal transmission between modules. Three traditional level shifter circuits are as Figure 1 shown, where Figure 1 (a) is a cross-type (ccls) level shifter circuit, Figure 1 (b) is a mirror-type (cmls) level shifter circuit, Figure 1 (c) is a Wilson current mirror type level shifter circuit. In terms of static power consumption, since the pull-up and pull-down of the output signal are respectively performed by PMOS transistors and NMOS transistors, the pull-up PMOS transistor cannot be completely turned off when the output is at a low level, which has always been a difficult problem to solve in level shifter circuits. This will cause a large static current to be generated in the circuit, resulting in high static power consumption. Therefore, in many circuits, a LEDC structure as Figure 2 shown is used to reduce the static current of the circuit, but the LEDC structure itself will also generate a certain amount of static current, so this method cannot fundamentally solve the problem. Summary of the Invention

[0003] Based on this, it is necessary to provide a level shifter with ultra-low power consumption and single-event transient resistance for the above technical problems.

[0004] An ultra-low power consumption and single-event transient resistant level shifter, the level shifter includes: a main output stage and an auxiliary circuit.

[0005] The main body output stage adopts a DICE structure, which is used to quickly release charges after being impacted by SET charges through two pull-down paths equipped in each node of the DICE structure.

[0006] The auxiliary circuit includes: two improved LEDC structures; the improved LEDC structure is used to completely cut off the static current in the improved LEDC structure by introducing an additional control signal into the DICE structure and controlling it through the additional control signal.

[0007] In one embodiment, the first improved LEDC structure includes: five PMOS transistors and three NMOS transistors.

[0008] The sources of the first PMOS transistor, the second PMOS transistor, and the third PMOS transistor are all connected to the VDDH terminal. The drain of the first PMOS transistor, the gate of the first PMOS transistor, the gate of the second PMOS transistor, the gate of the fifth PMOS transistor, and the drain of the first NMOS transistor are all connected to the Q point.

[0009] The drain of the second PMOS transistor is connected to the source of the fifth PMOS transistor. The drains of the fifth PMOS transistor, the third NMOS transistor, and the fourth PMOS transistor are all connected to the X point. The source of the fourth PMOS transistor is connected to the drain of the third PMOS transistor. The gates of the third PMOS transistor and the second NMOS transistor are both connected to the B point. The gates of the fourth PMOS transistor and the third NMOS transistor are both connected to the inverting input signal terminal; the source of the first NMOS transistor is connected to the drain of the second NMOS transistor. The gate of the first NMOS transistor is connected to the input signal terminal. The sources of the second NMOS transistor and the third NMOS transistor are both grounded; the X point is the introduction point of the first additional control signal.

[0010] In one embodiment, the second improved LEDC structure includes: the fourteenth PMOS transistor, the fifteenth PMOS transistor, the sixteenth PMOS transistor, the seventeenth PMOS transistor, the eighteenth PMOS transistor, the fourteenth NMOS transistor, the fifteenth NMOS transistor, and the sixteenth NMOS transistor.

[0011] The sources of the fourteenth PMOS transistor, the fifteenth PMOS transistor, and the sixteenth PMOS transistor are all connected to the VDDH terminal. The drain of the fifteenth PMOS transistor, the gate of the fifteenth PMOS transistor, the gate of the fourteenth PMOS transistor, the gate of the eighteenth PMOS transistor, and the drain of the fourteenth NMOS transistor are all connected to the K point.

[0012] The drain of the fourteenth PMOS transistor is connected to the source of the eighteenth PMOS transistor. The drains of the eighteenth PMOS transistor, the fifteenth NMOS transistor, and the seventeenth PMOS transistor are all connected to point Y. The source of the seventeenth PMOS transistor is connected to the drain of the sixteenth PMOS transistor. The gates of the sixteenth PMOS transistor and the sixteenth NMOS transistor are both connected to the OUT terminal. The gates of the seventeenth PMOS transistor and the fifteenth NMOS transistor are both connected to the input signal terminal. The source of the fourteenth NMOS transistor is connected to the drain of the sixteenth NMOS transistor. The gate of the fourteenth NMOS transistor is connected to the inverted input signal terminal. The sources of the fifteenth NMOS transistor and the sixteenth NMOS transistor are both grounded.

[0013] In one embodiment, the main output stage includes: the sixth to thirteenth PMOS transistors and the fourth to thirteenth NMOS transistors.

[0014] The sources of the sixth PMOS transistor, the seventh PMOS transistor, the eighth PMOS transistor, and the ninth PMOS transistor are all connected to the VDDH terminal. The drain of the sixth PMOS transistor is connected to the source of the tenth PMOS transistor. The drains of the tenth PMOS transistor, the gate of the seventh PMOS transistor, the drain of the fifth NMOS transistor, the drain of the tenth NMOS transistor, and the gate of the eighth NMOS transistor are all connected to node A. The gates of the tenth PMOS transistor and the twelfth PMOS transistor are both connected to point X. The gates of the eleventh PMOS transistor, the thirteenth PMOS transistor, the fourth NMOS transistor, and the thirteenth NMOS transistor are all connected to point Y. The drain of the seventh PMOS transistor is connected to the source of the eleventh PMOS transistor. The drain of the eighth PMOS transistor is connected to the source of the twelfth PMOS transistor. The drain of the ninth PMOS transistor is connected to the source of the thirteenth PMOS transistor and the drain of the eighth NMOS transistor. The source of the ninth NMOS transistor is connected to the drain of the thirteenth NMOS transistor.

[0015] The gates of the fifth NMOS transistor, the drain of the sixth NMOS transistor, the drain of the eleventh PMOS transistor, the gate of the eighth PMOS transistor, and the drain of the eleventh NMOS transistor are all connected to node B.

[0016] The gates of the sixth NMOS transistor, the drain of the seventh NMOS transistor, the drain of the twelfth PMOS transistor, the gate of the ninth PMOS transistor, and the drain of the twelfth NMOS transistor are all connected to node C.

[0017] The gates of the sixth PMOS transistor, the drain of the thirteenth PMOS transistor, the drain of the fourth NMOS transistor, and the drain of the ninth NMOS transistor are all connected to the OUT terminal.

[0018] The gate of the seventh NMOS transistor is connected to the source of the fourth NMOS transistor and the drain of the eighth NMOS transistor; the sources of the fifth NMOS transistor, the sixth NMOS transistor, the seventh NMOS transistor, the eighth NMOS transistor, the tenth NMOS transistor, the eleventh NMOS transistor, the twelfth NMOS transistor, and the thirteenth NMOS transistor are all grounded.

[0019] The gates of the tenth NMOS transistor and the twelfth NMOS transistor are connected to the input signal terminal, and the gates of the eleventh NMOS transistor and the ninth NMOS transistor are connected to the inverting signal input terminal.

[0020] The above-mentioned level shifter with ultra-low power consumption and anti-single event transient includes: a main body output stage and an auxiliary circuit; the main body output stage adopts a DICE structure, which is used to quickly release charges through two pull-down paths equipped at each node in the DICE structure after being impacted by SET charges; the auxiliary circuit includes: two improved LEDC structures; the improved LEDC structure is used to introduce an additional control signal into the DICE structure, and the static current in the improved LEDC structure is completely cut off through the additional control signal. The level shifter quickly releases charges and maintains stable output after being impacted by SET charges. Compared with the traditional LEDC structure, the improved LEDC structure can completely solve the static current problem in the circuit and achieve ultra-low static power consumption of the entire circuit. Description of the Drawings

[0021] Figure 1 For three traditional level shifter circuit diagrams, where Figure 1 (a) is the circuit diagram of the cross-type level shifter, Figure 1 (b) is the circuit diagram of the mirror-type level shifter, Figure 1 (c) is the circuit diagram of the Wilson current mirror type level shifter; Figure 2 For the structure diagram of the level shifter using the LEDC structure as the auxiliary circuit in the prior art; Figure 3 For the circuit diagram of the level shifter with ultra-low power consumption and anti-single event transient in an embodiment; Figure 4 For the common LEDC structure diagram and the improved LEDC structure diagram in the level shifter in another embodiment, where Figure 4 (a) is the common LEDC structure diagram in the level shifter, Figure 4 (b) is the improved LEDC structure diagram; Figure 5 For the circuit timing waveform diagram in another embodiment. Detailed Description of the Invention

[0022] In order to make the objectives, technical solutions and advantages of the present application more clear and understandable, the present application will be further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0023] In one embodiment, as Figure 3 shown, a level shifter with ultra-low power consumption and anti-single-event transient is provided. The level shifter includes: a main body output stage and an auxiliary circuit.

[0024] The main body output stage adopts a DICE structure, which is used to quickly release charges through two pull-down paths equipped at each node in the DICE structure after being impacted by SET charges.

[0025] Specifically, the main body output stage is improved on the basis of the traditional DICE structure; a PMOS transistor is added between the drain of the PMOS transistor and the drain of the pull-down NMOS transistor in the first pull-down path of each node, and an NMOS transistor is added between the drain of the PMOS transistor added in the first pull-down path of the fourth node and the drain of the pull-down NMOS transistor, and an NMOS transistor is added in the second pull-down path of the fourth node.

[0026] The gates of the PMOS transistors added in the first pull-down paths of the first and third nodes are connected to point X, the gates of the PMOS transistors added in the first pull-down paths of the second and fourth nodes are connected to point Y, the gate of the NMOS transistor added in the first pull-down path of the fourth node is connected to point Y, the gate of the NMOS transistor added in the second pull-down path of the fourth node is connected to the inverted signal input terminal, and the gate of the pull-down NMOS transistor in the second pull-down path of the fourth node is connected to point Y.

[0027] The auxiliary circuit includes: two improved LEDC structures; the improved LEDC structure is used to introduce an additional control signal for the DICE structure, and the static current in the improved LEDC structure is completely cut off through the additional control signal.

[0028] Specifically, the traditional LEDC structure is improved and added to the circuit as an auxiliary circuit. Compared with the traditional LEDC structure, the improved LEDC structure can completely solve the static current problem in the circuit and achieve ultra-low static power consumption of the entire circuit.

[0029] The main body output stage of the level shifter is used to quickly release charges after being impacted by SET charges. The improved LEDC structures on both sides further improve the resistance of the output to the SET effect by introducing two additional control signals for the middle DICE structure, and keep the delay and power consumption of the circuit at a relatively excellent level.

[0030] When the level shifter operates in a steady state, the static power consumption of the circuit is extremely low, and all PMOS and NMOS can be completely turned off. When the circuit is affected by the external SET effect, it can quickly release charge to maintain the output stability.

[0031] In the above-mentioned level shifter with ultra-low power consumption and anti-single event transient, the level shifter includes: a main body output stage and an auxiliary circuit; the main body output stage adopts a DICE structure, which is used to quickly release charge through two pull-down paths equipped at each node in the DICE structure after being impacted by SET charges; the auxiliary circuit includes: two improved LEDC structures; the improved LEDC structure is used to introduce an additional control signal into the DICE structure, and the static current in the improved LEDC structure is completely cut off through the additional control signal. The level shifter can quickly release charge to maintain the output stability after being impacted by SET charges. Compared with the traditional LEDC structure, the improved LEDC structure can completely solve the static current problem in the circuit and achieve ultra-low static power consumption of the entire circuit.

[0032] In one embodiment, as Figure 3 shown, the first improved LEDC structure includes: 5 PMOS transistors and 3 NMOS transistors.

[0033] The sources of the first PMOS transistor, the second PMOS transistor, and the third PMOS transistor are all connected to the VDDH terminal. The drain of the first PMOS transistor, the gate of the first PMOS transistor, the gate of the second PMOS transistor, the gate of the fifth PMOS transistor, and the drain of the first NMOS transistor are all connected to the Q point.

[0034] The drain of the second PMOS transistor is connected to the source of the fifth PMOS transistor. The drains of the fifth PMOS transistor, the third NMOS transistor, and the fourth PMOS transistor are all connected to the X point. The source of the fourth PMOS transistor is connected to the drain of the third PMOS transistor. The gates of the third PMOS transistor and the second NMOS transistor are both connected to the B point. The gates of the fourth PMOS transistor and the third NMOS transistor are both connected to the inverted input signal terminal; the source of the first NMOS transistor is connected to the drain of the second NMOS transistor. The gate of the first NMOS transistor is connected to the input signal terminal. The sources of the second NMOS transistor and the third NMOS transistor are both grounded; the X point is the introduction point of the first additional control signal.

[0035] Specifically, Figure 4 (a) is the common LEDC structure in the level shifter structure. P5 cannot be completely turned off, and the voltage at the Y point will also be lost. Figure 4(b) The improved LEDC structure uses the K point to control P5 to ensure that the transistor is completely turned off. By using the OUT voltage and IN to control the P3 and P4 paths, the voltage at point Y is maintained at VDDH. This not only solves the voltage loss problem of the LEDC structure but also completely solves the static leakage current problem of the LS structure.

[0036] In one embodiment, as Figure 3 shown, the second improved LEDC structure includes: the fourteenth PMOS transistor, the fifteenth PMOS transistor, the sixteenth PMOS transistor, the seventeenth PMOS transistor, the eighteenth PMOS transistor, the fourteenth NMOS transistor, the fifteenth NMOS transistor, and the sixteenth NMOS transistor.

[0037] The sources of the fourteenth PMOS transistor, the fifteenth PMOS transistor, and the sixteenth PMOS transistor are all connected to the VDDH terminal. The drain of the fifteenth PMOS transistor, the gates of the fifteenth PMOS transistor, the fourteenth PMOS transistor, the eighteenth PMOS transistor, and the drain of the fourteenth NMOS transistor are all connected to the K point.

[0038] The drain of the fourteenth PMOS transistor is connected to the source of the eighteenth PMOS transistor. The drains of the eighteenth PMOS transistor, the fifteenth NMOS transistor, and the seventeenth PMOS transistor are all connected to the Y point. The source of the seventeenth PMOS transistor is connected to the drain of the sixteenth PMOS transistor. The gates of the sixteenth PMOS transistor and the sixteenth NMOS transistor are both connected to the OUT terminal. The gates of the seventeenth PMOS transistor and the fifteenth NMOS transistor are both connected to the input signal terminal; the source of the fourteenth NMOS transistor is connected to the drain of the sixteenth NMOS transistor. The gate of the fourteenth NMOS transistor is connected to the inverted input signal terminal. The sources of the fifteenth NMOS transistor and the sixteenth NMOS transistor are both grounded; point Y is the first additional control signal introduction point.

[0039] In one embodiment, as Figure 3 shown, the main output stage includes: the sixth to thirteenth PMOS transistors and the fourth to thirteenth NMOS transistors.

[0040] The sources of the sixth PMOS transistor, the seventh PMOS transistor, the eighth PMOS transistor, and the ninth PMOS transistor are all connected to the VDDH terminal. The drain of the sixth PMOS transistor is connected to the source of the tenth PMOS transistor. The drains of the tenth PMOS transistor, the gate of the seventh PMOS transistor, the drain of the fifth NMOS transistor, the drain of the tenth NMOS transistor, and the gate of the eighth NMOS transistor are all connected to node A. The gates of the tenth PMOS transistor and the twelfth PMOS transistor are both connected to point X. The gates of the eleventh PMOS transistor, the thirteenth PMOS transistor, the gate of the fourth NMOS transistor, and the gate of the thirteenth NMOS transistor are all connected to point Y. The drain of the seventh PMOS transistor is connected to the source of the eleventh PMOS transistor. The drain of the eighth PMOS transistor is connected to the source of the twelfth PMOS transistor. The drain of the ninth PMOS transistor is connected to the source of the thirteenth PMOS transistor and the drain of the eighth NMOS transistor. The source of the ninth NMOS transistor is connected to the drain of the thirteenth NMOS transistor.

[0041] The gate of the fifth NMOS transistor, the drain of the sixth NMOS transistor, the drain of the eleventh PMOS transistor, the gate of the eighth PMOS transistor, and the drain of the eleventh NMOS transistor are all connected to node B.

[0042] The gate of the sixth NMOS transistor, the drain of the seventh NMOS transistor, the drain of the twelfth PMOS transistor, the gate of the ninth PMOS transistor, and the drain of the twelfth NMOS transistor are all connected to node C.

[0043] The gate of the sixth PMOS transistor, the drain of the thirteenth PMOS transistor, the drain of the fourth NMOS transistor, and the drain of the ninth NMOS transistor are all connected to the OUT terminal.

[0044] The gate of the seventh NMOS transistor is connected to the source of the fourth NMOS transistor and the drain of the eighth NMOS transistor. The sources of the fifth NMOS transistor, the sixth NMOS transistor, the seventh NMOS transistor, the eighth NMOS transistor, the tenth NMOS transistor, the eleventh NMOS transistor, the twelfth NMOS transistor, and the thirteenth NMOS transistor are all grounded.

[0045] The gates of the tenth NMOS transistor and the twelfth NMOS transistor are connected to the input signal terminal. The gates of the eleventh NMOS transistor and the ninth NMOS transistor are connected to the inverted signal input terminal.

[0046] Specifically, for the Figure 3 level shifter shown, since the voltage changes of the LEDC structures on both sides of the circuit change in the opposite direction, only the voltage change of the right LEDC structure is taken as a reference.

[0047] Low level to high level: As Figure 3As shown, when the input signal IN changes from low to high for the improved LEDC structure on the right, the fourteenth NMOS transistor N14 turns on, the fifteenth PMOS transistor P15 and the eighteenth PMOS transistor P18 turn off, the potential at point Y is pulled down to 0. For the DICE structure, the fourth NMOS transistor N4 and the thirteenth NMOS transistor N13 turn off, and the thirteenth PMOS transistor P13 turns on. The twelfth NMOS transistor N12 turns on, the potential at point C becomes 0, and the ninth PMOS transistor P9 turns on. At this time, the output is pulled up to VDDH. At this time, both of the two pull-down paths of the output, the fourth NMOS transistor N4 and the eighth NMOS transistor N8, and the ninth NMOS transistor N9 and the thirteenth NMOS transistor N13 are in the off state. When any one of the MOS transistors is affected by the SET effect and conducts abnormally, the pull-down path is still in the off state, and the OUT terminal is not directly connected to the low potential, so the output does not show large fluctuations. At this time, the fourteenth PMOS transistor P14 and the fifteenth NMOS transistor N15 of the right LEDC structure turn off, and the potential at point K rises to VDDH - Vds (the seventeenth PMOS transistor P17), which can completely turn off the eighteenth PMOS transistor P18. The static current in the improved LEDC is completely cut off.

[0048] High level to low level: As Figure 3When the input changes from high to low as shown, for the right LEDC structure, the inverted input signal INB goes high. Due to the delay, the OUT terminal continues to maintain a high level. The fifteenth NMOS transistor N15 and the sixteenth NMOS transistor N16 are turned on simultaneously. The voltage at point K drops, and at the same time, the sixteenth PMOS transistor P16 and the eighteenth PMOS transistor P18 are turned on, and the voltage at point Y is pulled up to VDDH. For the DICE structure, the thirteenth PMOS transistor P13 is turned off, blocking the connection between the output and the pull-up circuit. At this time, the ninth NMOS transistor N9 and the thirteenth NMOS transistor N13 are turned on simultaneously, and the output is pulled down to zero. At this time, the third NMOS transistor N3 of the left LEDC structure is turned on, and X becomes 0. The sixth PMOS transistor P6 and the tenth PMOS transistor P10 controlled by X in the DICE structure are turned on, and the voltage at point A is pulled up to VDDH. At this time, the second pull-down path of OUT composed of the fourth NMOS transistor N4 and the eighth NMOS transistor N8 is turned on to enhance the output stability. Similarly, the potential at point C rises to VDDH, turning off the ninth PMOS transistor P9. In the pull-up path composed of the ninth PMOS transistor P9 and the thirteenth PMOS transistor P13, one of the MOS transistors is affected by SET, and the other transistor can still ensure the blocking of the output and the pull-up path to ensure the output stability. At the same time, the pull-up path composed of the fourteenth PMOS transistor P14 and the fifteenth PMOS transistor P15 is turned on to maintain the voltage at point Y as VDDH. The static current in the DICE structure is completely turned off. The potential at point K continues to rise to VDDH - Vds (the seventeenth PMOS transistor P17), which can completely turn off the eighteenth PMOS transistor P18. Because the OUT terminal becomes 0 at this time, the sixteenth NMOS transistor N16 is completely turned off, and the static current in the improved LEDC is completely cut off.

[0049] In summary, during the pull-up and pull-down processes, the circuit can achieve strong SET resistance and ultra-low static power consumption. Figure 5 It shows the timing working waveform diagram of the circuit and the waveform changes of different circuits after being impacted.

[0050] The technical features of the above embodiments can be combined arbitrarily. For the sake of brevity of description, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, it should be considered as the scope described in this specification.

[0051] The above-described embodiments only represent several implementation manners of the present application. Their descriptions are relatively specific and detailed, but they should not be construed as limiting the scope of the present application. It should be noted that for those of ordinary skill in the art, without departing from the concept of the present application, several modifications and improvements can still be made, and these all belong to the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the appended claims.

Claims

1. An ultra-low power consumption single event transient resistant level converter, characterized in that: The level converter comprises: a main output stage and an auxiliary circuit; The main output stage adopts a DICE structure, which is used to quickly release the charge after being impacted by the SET charge through two pull-down paths equipped at each node in the DICE structure; The auxiliary circuit includes: two improved LEDC structures; the improved LEDC structure is used to introduce an additional control signal to the DICE structure, and the static current in the improved LEDC structure is completely cut off through the additional control signal.

2. The ultra-low power consumption single event transient resistant level converter according to claim 1, characterized in that: The first improved LEDC structure includes: 5 PMOS tubes and 3 NMOS tubes; The sources of the first PMOS tube, the second PMOS tube and the third PMOS tube are all connected to the VDDH terminal, and the drain of the first PMOS tube, the gate of the first PMOS tube, the gate of the second PMOS tube, the gate of the fifth PMOS tube and the drain of the first NMOS tube are all connected to the Q point; The drain of the second PMOS tube is connected to the source of the fifth PMOS tube, the drain of the fifth PMOS tube, the drain of the third NMOS tube and the drain of the fourth PMOS tube are all connected to point X, the source of the fourth PMOS tube is connected to the drain of the third PMOS tube, the gates of the third PMOS tube and the second NMOS tube are all connected to point B, and the gates of the fourth PMOS tube and the third NMOS tube are all connected to the inverting input signal terminal; the source of the first NMOS tube is connected to the drain of the second NMOS tube, the gate of the first NMOS tube is connected to the input signal terminal, and the sources of the second NMOS tube and the third NMOS tube are all grounded; the point X is the first additional control signal introduction point.

3. The ultra-low power consumption single event transient resistant level converter according to claim 1, characterized in that: The second improved LEDC structure includes: a fourteenth PMOS tube, a fifteenth PMOS tube, a sixteenth PMOS tube, a seventeenth PMOS tube, an eighteenth PMOS tube, a fourteenth NMOS tube, a fifteenth NMOS tube and a sixteenth NMOS tube; The fourteenth PMOS tube, the fifteenth PMOS tube and the source of the sixteenth PMOS tube are all connected to the VDDH terminal, and the drain of the fifteenth PMOS tube, the gate of the fifteenth PMOS tube, the gate of the fourteenth PMOS tube, the gate of the eighteenth PMOS tube and the drain of the fourteenth NMOS tube are all connected to point K; The drain of the fourteenth PMOS tube is connected to the source of the eighteenth PMOS tube, the drain of the eighteenth PMOS tube, the drain of the fifteenth NMOS tube and the drain of the seventeenth PMOS tube are all connected to the Y point, the source of the seventeenth PMOS tube is connected to the drain of the sixteenth PMOS tube, the gates of the sixteenth PMOS tube and the sixteenth NMOS tube are all connected to the OUT terminal, and the gates of the seventeenth PMOS tube and the fifteenth NMOS tube are all connected to the input signal terminal; the source of the fourteenth NMOS tube is connected to the drain of the sixteenth NMOS tube, the gate of the fourteenth NMOS tube is connected to the inverting input signal terminal, and the sources of the fifteenth NMOS tube and the sixteenth NMOS tube are all grounded; the Y point is the second additional control signal introduction point.

4. The ultra-low power consumption single event transient resistant level converter according to claim 1, characterized in that: The main output stage includes: sixth to thirteenth PMOS tubes and fourth to thirteenth NMOS tubes; The sources of the sixth PMOS tube, the seventh PMOS tube, the eighth PMOS tube and the ninth PMOS tube are all connected to the VDDH terminal, the drain of the sixth PMOS tube is connected to the source of the tenth PMOS tube, the drain of the tenth PMOS tube, the gate of the seventh PMOS tube, the drain of the fifth NMOS tube, the drain of the tenth NMOS tube and the gate of the eighth NMOS tube are all connected to the node A, the gates of the tenth PMOS tube and the twelfth PMOS tube are all connected to the point X, the gates of the eleventh PMOS tube, the thirteenth PMOS tube, the gate of the fourth NMOS tube and the gate of the thirteenth NMOS tube are all connected to the point Y, the drain of the seventh PMOS tube is connected to the source of the eleventh PMOS tube, the drain of the eighth PMOS tube is connected to the source of the twelfth PMOS tube, the drain of the ninth PMOS tube is connected to the source of the thirteenth PMOS tube and the drain of the eighth NMOS tube, and the source of the ninth NMOS tube is connected to the drain of the thirteenth NMOS tube; The gate of the fifth NMOS tube, the drain of the sixth NMOS tube, the drain of the eleventh PMOS tube, the gate of the eighth PMOS tube, and the drain of the eleventh NMOS tube are all connected to the node B; The gate of the sixth NMOS tube, the drain of the seventh NMOS tube, the drain of the twelfth PMOS tube, the gate of the ninth PMOS tube and the drain of the twelfth NMOS tube are all connected to the node C; The gate of the sixth PMOS tube, the drain of the thirteenth PMOS tube, the drain of the fourth NMOS tube, and the drain of the ninth NMOS tube are all connected to the OUT terminal; The gate of the seventh NMOS tube is connected to the source of the fourth NMOS tube and the drain of the eighth NMOS tube; the sources of the fifth NMOS tube, the sixth NMOS tube, the seventh NMOS tube, the eighth NMOS tube, the tenth NMOS tube, the eleventh NMOS tube, the twelfth NMOS tube and the thirteenth NMOS tube are all grounded; The gates of the tenth NMOS tube and the twelfth NMOS tube are connected to the input signal terminal, and the gates of the eleventh NMOS tube and the ninth NMOS tube are connected to the inverting signal input terminal.

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