Dual-channel TIADC sampling moment mismatch error estimation and calibration method and device

Abstract

The invention specifically discloses a dual-channel TIADC sampling moment mismatch error estimation and calibration method and device, and relates to the technical field of high-speed analog-to-digital conversion. According to the method, on one hand, data conversion is carried out on an output signal of a sub-analog-to-digital converter serving as a reference, on the other hand, mismatch delay is carried out on an output signal of a calibrated sub-analog-to-digital converter, and then a converted signal imaginary part and a delayed signal are multiplied to solve a mean value; iteration of estimation parameters and adjustment of mismatch parameters are carried out to obtain more appropriate mismatch parameters for next round of calibration; in this way, the sampling moment mismatch error tau is effectively estimated from the output signal of the dual-channel TIADC in a multi-round calibration mode, and then calibration is achieved. According to the method, the sampling time mismatch error tau can be accurately estimated, so that spurious signals caused by sampling time mismatch clock skew are effectively suppressed, the dynamic performance of a system is improved, and signal distortion caused by sampling time mismatch is reduced.

Description

Technical Field

[0001] The present invention relates to the technical field of high-speed analog-to-digital conversion, and specifically relates to: 1. A method for estimating and calibrating the sampling time mismatch error of a dual-channel TIADC; 2. A device for estimating and calibrating the sampling time mismatch error of a dual-channel TIADC using this method. Background Art

[0002] TIADC (Time-Interleaved Analog To Digital Converter) samples an analog input signal by multiple relatively low-speed sub-ADCs in a time-interleaved manner, and theoretically can increase the sampling rate without reducing the conversion accuracy.

[0003] Refer to Figure 1 , which shows a dual-channel TIADC, including: 2 sub-analog-to-digital converters sub_ADC 1 ~sub_ADC 2 , a clock network Clock, and a multiplexer MUX. Among them, sub_ADC 1 , sub_ADC 2 are relatively low-speed and sample the test signal V in in a time-interleaved manner. The number of interleaved channels is 2; the overall sampling rate of the dual-channel TIADC is Fs. Then, the 2 sub-analog-to-digital converters are respectively driven by sampling clocks with an equal phase difference (180°) and a frequency of Fs / 2 to sample V in , and finally the quantization results of the 2 sub-analog-to-digital converters are output in sequence through the MUX (the quantization result of sub_ADC 1 is y 1 [n], and the quantization result of sub_ADC 2 is y 2 [n], n ∈ [0, N]; N represents the total number of sampling points used for each output signal of a single sub-analog-to-digital converter; n represents the nth sampling point in N) to obtain the final digital output y[n]. Ideally, this dual-channel TIADC can double the overall sampling rate without affecting the conversion accuracy, thereby breaking the design limitation between the sampling rate and the conversion accuracy faced by traditional single-channel ADCs.

[0004] However, in the actual chip design and manufacturing process, due to factors such as the uncertainty errors in layout design and chip manufacturing, the above-mentioned dual-channel TIADC has problems of inter-channel parameter mismatch, such as offset, gain, and sampling time mismatch. Among them, the sampling time mismatch will introduce error spur components in the output spectrum, seriously affecting the dynamic performance. Therefore, it is necessary to calibrate the sampling time mismatch existing in the above-mentioned dual-channel TIADC. Summary of the Invention

[0005] Based on this, in view of the problem that the sampling time mismatch in the existing dual-channel TIADC system in the background technology needs to be calibrated, it is necessary to propose a method and device for estimating and calibrating the sampling time mismatch error of the dual-channel TIADC.

[0006] The present invention is implemented by the following technical solutions:

[0007] In a first aspect, the present invention discloses a method for estimating and calibrating the sampling time mismatch error of a dual-channel TIADC, which is used to estimate and calibrate the sampling time mismatch τ of Sub_ADC 1 using Sub_ADC 2 as a reference. Among them, Sub_ADC 1 and Sub_ADC 2 represent two sub-analog-to-digital converters of the dual-channel TIADC.

[0008] The method for estimating and calibrating the sampling time mismatch error of the dual-channel TIADC includes:

[0009] Taking T s as a period, periodically obtaining the output signals of Sub_ADC 1 and Sub_ADC 2 multiple times; where T s represents the sampling period of the dual-channel TIADC;

[0010] Based on the obtained y 1,i [n] and y 2,i [n], perform the i-th round of calibration; where y 1,i [n] and y 2,i [n] respectively represent the output signals of Sub_ADC 1 and Sub_ADC 2 in the i-th time; n ∈ [0, N]; N represents the total number of sampling points used for each output signal of a single sub-analog-to-digital converter; n represents the n-th sampling point in N; i ≥ 1;

[0011] Among them, the method for the i-th round of calibration includes:

[0012] S100, perform data conversion on y 1,i [n] to obtain the imaginary part Im_y 1,i [n] containing the phase information delayed by 90°;

[0013] According to the mismatch parameter C_τ i of the i-th round, perform digital correction on y 2,i [n] to delay the overall signal phase by C_τ i , and obtain the corrected output signal y2_call,i [n];

[0014] S200, multiply Im_y 1,i [n] by y 2_call,i [n] to obtain the multiplication result p i [n];

[0015] S300, calculate the mean value avg of p i [0] to p i [N]; i ;

[0016] S400, use avg i as the iteration parameter and iterate the estimated parameter C_err i-1 in the (i - 1)-th round to obtain the estimated parameter C_err in the i-th round i ;

[0017] S500, add C_err i to T s to obtain the mismatch parameter C_τ in the (i + 1)-th round i+1 ;

[0018] wherein, when i = 1, C_τ 1 takes 0 and C_err i-1 takes 0;

[0019] wherein, if C_τ i has converged, the calibration is completed and C_err i is used as τ to calibrate the output signal of Sub_ADC 2 ; otherwise, the calibration is not completed and the (i + 1)-th round of calibration is performed.

[0020] The implementation of the method for estimating and calibrating the sampling time mismatch error of the dual-channel TIADC follows the method or process of the embodiments of the present disclosure.

[0021] In a second aspect, the present invention discloses a device for estimating and calibrating the sampling time mismatch error of a dual-channel TIADC, which uses the method for estimating and calibrating the sampling time mismatch error of the dual-channel TIADC disclosed in the first aspect.

[0022] The device for estimating and calibrating the sampling time mismatch error of the dual-channel TIADC includes: a signal acquisition module and an error estimation and calibration module.

[0023] The signal acquisition module is configured to periodically acquire the output signals of Sub_ADC s and Sub_ADC 1 multiple times with T 2 as a period. The error estimation and calibration module is configured to, based on the acquired y 1,i [n], y2,i [n] performs the i-th round of calibration.

[0024] Among them, the error estimation and calibration module includes: a data conversion sub-module, a digital correction sub-module, a product calculation sub-module, an averaging calculation sub-module, an estimation sub-module, and an adjustment sub-module.

[0025] The data conversion sub-module is used to perform data conversion on y 1,i [n] to obtain the imaginary part Im_y 1,i [n] containing the phase information delayed by 90°; the digital correction sub-module is used to perform digital correction on y i according to the mismatch parameter C_τ 2,i of the i-th round to delay the overall signal phase by C_τ i , and obtain the corrected output signal y 2_call,i [n]; the product calculation sub-module is used to multiply Im_y 1,i [n] by y 2_call,i [n] to obtain the multiplication result p i [n]; the averaging calculation sub-module is used to calculate the average value avg i of p i [0] to p i [N]; the estimation sub-module is used to use avg i as the iteration parameter and perform iteration on the estimation parameter C_err i-1 of the (i - 1)-th round to obtain the estimation parameter C_err i of the i-th round; the adjustment sub-module is used to add C_err i to T s to obtain the mismatch parameter C_τ i+1 of the (i + 1)-th round.

[0026] The implementation of the TIADC sampling time mismatch calibration device follows the method or process of the embodiments of the present disclosure.

[0027] In a third aspect, the present invention discloses a computer program product, including a computer program. When the computer program is executed by a processor, it implements the steps of the dual-channel TIADC sampling time mismatch error estimation and calibration method disclosed in the first aspect.

[0028] Compared with the prior art, the present invention has the following beneficial effects:

[0029] 1. On the one hand, the present invention performs data transformation on the output signal of the sub - analog - to - digital converter serving as a reference. On the other hand, it performs mismatch delay on the output signal of the calibrated sub - analog - to - digital converter, then multiplies the imaginary part of the transformed signal by the delayed signal and calculates the mean value. After that, it iterates the estimated parameters and adjusts the mismatch parameters to obtain more appropriate mismatch parameters for the next - round calibration. In this way, through multiple - round calibration, the sampling - time mismatch error τ is effectively estimated from the output signal of the dual - channel TIADC, thereby achieving calibration. Through simulation verification, the present invention can accurately estimate the sampling - time mismatch error τ, thus effectively suppressing the spurious signals caused by the sampling - time mismatch clock skew, improving the dynamic performance of the system, and reducing the signal distortion caused by the sampling - time mismatch.

[0030] 2. The present invention utilizes the mathematical characteristics of signals and does not require complex additional hardware circuits to implement. It can be achieved only by using relatively simple digital signal processing methods or steps. While ensuring the accuracy of the estimation of the sampling - time mismatch error τ, it reduces the dependence on additional hardware, and lowers the hardware cost and circuit complexity.

[0031] 3. The method of the present invention can be designed based on digital circuits. Therefore, it has good stability and reliability in the face of process, voltage, and temperature (PVT) variations.

[0032] 4. The method of the present invention can quickly and accurately correct the sampling - time mismatch. Compared with the existing methods, the method of the present invention has a faster convergence speed and requires fewer total sampling points to achieve convergence. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] To more clearly illustrate the technical solutions of the embodiments of the present invention, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the following - described drawings are only some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained based on these drawings.

[0034] Figure 1 It is the structural diagram of the existing dual - channel TIADC mentioned in the background art;

[0035] Figure 2 It is the data - flow diagram of the sampling - time mismatch error estimation and calibration method for the dual - channel TIADC provided in Embodiment 1 of the present invention;

[0036] Figure 3 It is the simulation result provided in Embodiment 2 of the present invention Figure 1 ;

[0037] Figure 4 It is the simulation result provided in Embodiment 2 of the present invention Figure 2 ;

[0038] Figure 5 The simulation results provided for Embodiment 2 of the present invention Figure 3 。 Detailed implementation manners

[0039] Next, the technical solutions in the embodiments of the present invention will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts shall fall within the protection scope of the present invention.

[0040] It should be noted that when a component is referred to as being "installed on" another component, it can be directly on the other component or there may also be an intermediate component. When a component is considered to be "disposed on" another component, it can be directly disposed on the other component or there may be an intermediate component at the same time. When a component is considered to be "fixed to" another component, it can be directly fixed to the other component or there may be an intermediate component at the same time.

[0041] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those of ordinary skill in the technical field to which the present invention belongs. The terms used herein in the specification of the present invention are only for the purpose of describing specific embodiments, and are not intended to limit the present invention. The term "or / and" used herein includes any and all combinations of one or more of the related listed items.

[0042] Embodiment 1

[0043] Please refer to Figure 2 , Figure 2 which is the data flow diagram of the dual-channel TIADC sampling time mismatch error estimation and calibration method proposed for Embodiment 1, and actually also shows the brief process of the dual-channel TIADC sampling time mismatch error estimation and calibration method.

[0044] As recorded in the background art Figure 2 Sub_ADC in 1 、Sub_ADC 2 represent the two sub-analog-to-digital converters of the dual-channel TIADC. Among them, the sampling periods of Sub_ADC 1 、Sub_ADC 2 are the same, both being T s . That is to say, T s is actually the sampling period of the dual-channel TIADC.

[0045] It should be noted that this method is based on Sub_ADC1 As a reference to estimate and calibrate the Sub_ADC 2 for the sampling time mismatch τ. That is, τ is for the Sub_ADC 2 relative to the Sub_ADC 1 in terms of...

[0046] As Figure 2 shown, a method for estimating and calibrating the sampling time mismatch error of a dual-channel TIADC specifically includes:

[0047] Taking T s as a period, obtaining the output signals of the Sub_ADC 1 and Sub_ADC 2 periodically and multiple times;

[0048] It should be noted that, as mentioned in the background art, the Sub_ADC 1 and Sub_ADC 2 sample the test signal V in to obtain the corresponding output signals. Among them, V in can be a single-tone signal or a multi-tone signal.

[0049] Based on the obtained y 1,i [n] and y 2,i [n], perform the i-th round of calibration; i≥1;

[0050] where y 1,i [n] and y 2,i [n] respectively represent the i-th output signals of the Sub_ADC 1 and Sub_ADC 2 ; n∈[0,N]; N represents the total number of sampling points used for each output signal of a single sub-analog-to-digital converter; n represents the n-th sampling point in N.

[0051] Since the principle of each round of calibration is similar, taking the i-th round of calibration as an example for illustration - its method specifically includes:

[0052] S100, perform data conversion on y 1,i [n] to obtain the imaginary part Im_y 1,i [n] containing the phase information delayed by 90°.

[0053] According to the mismatch parameter C_τ i of the i-th round, perform digital correction on y 2,i [n] to delay the overall signal phase by C_τ i , and obtain the corrected output signal y 2_call,i [n].

[0054] S100 aims to obtain Im_y from y 1,i [n] on the one hand, which contains the phase information delayed by 90° for subsequent signal processing, and aims to delay the overall phase of y 1,i [n] by C_τ 2,i for subsequent signal processing on the other hand. i

[0055] In this Embodiment 1:

[0056] 1. It is recommended to use the Hilbert transform to perform data conversion on y 1,i [n], which can convert a real signal into a complex signal and delay the phase of the signal frequency component by 90° (reflected in the imaginary part of the complex signal).

[0057] 2. It is recommended to use an interpolation delay filter to perform digital correction on y 2,i [n], which completes the overall delay of the phase of y 2,i [n] by C_τ i through steps such as interpolation and delay filtering. Among them, C_τ i is used as the configuration parameter of the interpolation delay filter during the i-th round of calibration; that is, y 2,i [n] passes through the interpolation delay filter with the configuration parameter C_τ i and then obtains y i with the overall phase of the signal delayed by C_τ 2_call,i [n].

[0058] In addition, it should be noted that when i = 1, C_τ 1 takes 0, that is, in fact, during the first round of calibration, y 2_call,1 [n] is the same as y 2 [n].

[0059] Of course, other devices or digital circuits can also be used to implement the process of S100, but it should be ensured that the processing effect meets the requirements.

[0060] S200, multiply Im_y 1,i [n] by y 2_call,i [n] to obtain the multiplication result p i [n].

[0061] That is to say, the calculation formula of p i [n] is:

[0062] p i [n] = Im_y 1,i [n] × y 2_call,i [n].

[0063] ​S300, calculate p i [0] to p i [N]'s mean value avg i .

[0064] Since n ranges from 0 to N, there exists p i [0] to p i [N], then calculate its mean value.

[0065] That is to say, the calculation formula of avg i is:

[0066] avg i =(p i [0]+…+p i [N]) / N.

[0067] S400, use avg i as the iteration parameter, and iterate the estimation parameter C_err i-1 in the (i - 1)-th round to obtain the estimation parameter C_err i .

[0068] Among them, the calculation formula of C_err i is:

[0069] C_err i =C_err i-1 -μ * avg i ;

[0070] In the formula, μ represents the iteration coefficient and is a preset value.

[0071] Then, S400 actually updates and calculates C_err i once based on avg i-1 and μ to obtain C_err i .

[0072] In this Embodiment 1:

[0073] It is recommended to use the LMS adaptive engine filter to iterate C_err i-1 , and it implements the above calculation process based on the LMS algorithm. Among them, avg i and μ are used as the configuration parameters used by the LMS adaptive engine filter during the calibration in the i-th round. That is to say, C_err i-1 is processed by the LMS adaptive engine filter with the configuration parameters of avg i and μ to obtain C_err i .

[0074] In addition, it should be noted that when i = 1, C_err i-1Take 0.

[0075] Of course, other devices or digital circuits can also be used to implement the process of S400, but it should be ensured that the processing effect meets the requirements.

[0076] S500, add C_err i to T s to obtain the mismatch parameter C_τ for the (i + 1)-th round i+1 ;

[0077] Since there is T in y 1,i [n], y 2,i [n], if only C_err s is used to update the mismatch parameter, the calibration result will be unsatisfactory; therefore, it is chosen to add C_err i to T i to obtain the mismatch parameter C_τ for the (i + 1)-th round s , that is, C_τ i+1 = C_err i+1 + T i . In this way, during the (i + 1)-th round of calibration, compared with y s , the signal phase of y 2_call,i+1 [n] will be delayed by C_τ 2,i+1 as a whole, i+1 and then subsequent signal processing is carried out.

[0078] For S200, S300, and S500, they are all simple numerical calculation processes and can all be implemented in the form of digital circuits, which will not be elaborated here.

[0079] Since multiple calibrations are carried out - the current calibration will produce a pre-adjustment for the next calibration, after a certain number of calibrations, the estimated parameters and mismatch parameters will gradually converge, the mean value of the multiplication result will tend to 0, and τ will be gradually corrected by the mismatch parameter and tend to the estimated parameter. That is to say, if C_τ i has converged, the calibration is completed and C_err i is used as τ to calibrate the output signal of Sub_ADC 2 ; otherwise, the calibration is not completed and the (i + 1)-th round of calibration is carried out.

[0080] Specifically, if C_τ i has converged, then the estimated τ (i.e., C_err i ) is used to calibrate y 2,i [n] to obtain y 2_call,i [n], and then together with y 1,i [n] is input into MUX, and MUX will sequentially output the quantization results of the two sub-analog-to-digital converters to obtain the final digital output y i [n].

[0081] To facilitate the understanding of the signal changes in the above method, in this Embodiment 1, V in is taken as a cosine signal for illustration:

[0082] First, let V in = cos(2πft in ), where f in represents the signal frequency of V in , and t represents time.

[0083] Assume that there is a sampling time mismatch τ between Sub_ADC 2 and Sub_ADC 1 . Then there is:

[0084] y 1,i [n] = cos[2πf in (2nT s )];

[0085] y 2,i [n] = cos[2πf in [(2n + 1)T s + τ)].

[0086] Next, on the one hand, perform a Hilbert transform on y 1,i [n] to obtain its complex representation, and take the imaginary part of the signal Im_y 1,i [n] = sin[2πf in (2nT s ); on the other hand, use an interpolation delay filter with configuration parameter C_τ i to process y 2,i [n], and obtain: y 2_cal,i [n] = cos[2πf in [(2n + 1)T s + τ - C_τ i )];

[0087] After that, multiply Im_y 1,i [n] by y 2_call,i [n] to obtain:

[0088]

[0089] Then, take the average of p i [0] to p i [N] to obtain:

[0090]

[0091] For avg iFor the sin function, it is a periodic function, and the integral value within one period is zero. Then, when N is large enough (e.g., > 100), the average value of the sin function accumulated over multiple periods tends to zero, that is, avg i approaches 0. Then, in this case, avg i 's first term tends to zero, leaving only the second term related to τ. Therefore, avg i can be approximated as:

[0092]

[0093] Then, as multiple rounds of calibration are carried out, when the estimated parameters and mismatch parameters gradually converge, the mean value of the multiplication result tends to 0, that is, it is considered that the estimated parameters converge to the same value as τ, thus causing the mean value of the multiplication result to tend to 0.

[0094] Although the above example uses a cosine signal belonging to the single-tone signal category, the working mechanism of the method is still common for multi-tone signals.

[0095] Embodiment 2

[0096] This Embodiment 2 conducts simulation verification on the method provided in Embodiment 1 to illustrate its effectiveness and superiority.

[0097] This Embodiment 2 uses MATLAB software to model a dual-channel TIADC, sets parameters such as input signal, sampling frequency, and time mismatch externally, and then compares the situations before and after processing using the method of Embodiment 1; among them, N takes 2 8 = 256.

[0098] 1. Refer to Figure 3 , which shows the comparison of the output signal spectra before and after calibrating a single-tone signal. It can be seen that the spurs caused by the sampling time mismatch are well suppressed, indicating that the calibration is successful; the SNDR (signal-to-noise and distortion ratio) index increases from 38.74 dB to 62.08 dB; the SFDR (spur-free dynamic range) increases from 38.76 dB to 88.53 dB.

[0099] 2. Refer to Figure 4 , which shows the comparison of the output signal spectra before and after calibrating a multi-tone signal. It can be seen that all the spurs caused by the sampling time mismatch are well suppressed, indicating that the calibration is successful.

[0100] 3. Refer to Figure 5 , which shows the convergence curve of the estimated parameters. It can be seen that when the estimated parameters finally converge, it only consumes approximately 3600 sampling points (specifically Figure 5 3584 samples in

[0101] For comparison:

[0102] Ⅰ. In 2017, Han Le Duc proposed a fully digital feed - forward background calibration method for sampling time mismatch of a sub - sampled time - interleaved analog - to - digital converter (TIADC) based on polyphase decomposition, which requires collecting 5000 sampling points to complete the calibration of sampling time mismatch;

[0103] Ⅱ. In 2020, Han Niu proposed an efficient spurious - free aliasing spectrum calibration technique method for a time - interleaved analog - to - digital converter (TIADC), which requires collecting 4000 sampling points to complete the calibration of sampling time mismatch.

[0104] It can be seen that the method of Embodiment 1 requires fewer sampling points and less calibration time, having an advantage in speed.

[0105] Embodiment 3

[0106] This Embodiment 3 discloses a device for estimating and calibrating the sampling time mismatch error of a dual - channel TIADC, which uses the method for estimating and calibrating the sampling time mismatch error of a dual - channel TIADC provided in Embodiment 1.

[0107] This dual - channel TIADC sampling time mismatch error estimation and calibration device includes: a signal acquisition module and an error estimation and calibration module.

[0108] The signal acquisition module is configured to: take T s as a period and periodically acquire the output signals of Sub_ADC 1 and Sub_ADC 2 multiple times. The error estimation and calibration module is configured to: perform the i - th round of calibration based on the acquired y 1,i [n] and y 2,i [n].

[0109] Specifically, the error estimation and calibration module includes: a data conversion sub - module, a digital correction sub - module, a product calculation sub - module, an average calculation sub - module, an estimation sub - module, and an adjustment sub - module.

[0110] The data conversion sub - module is configured to: perform data conversion on y 1,i [n] to obtain the imaginary part Im_y 1,i [n] containing the phase information delayed by 90°; the digital correction sub - module is configured to: perform digital correction on y i [n] according to the mismatch parameter C_τ 2,i of the i - th round to delay the overall signal phase by C_τ i , and obtain the corrected output signal y 2_call,i [n]; the product calculation sub - module is configured to: multiply Im_y 1,i[n] multiplied by y 2_call,i [n] to obtain the multiplication result p i [n]; the averaging calculation sub-module is configured to calculate p i [0] to p i [N] to obtain the mean value avg i ; the estimation sub-module is configured to use avg i as the iteration parameter and perform iteration on the estimation parameter C_err i-1 in the (i - 1)-th round to obtain the estimation parameter C_err i in the i-th round; the adjustment sub-module is configured to add C_err i to T s to obtain the mismatch parameter C_τ i+1 .

[0111] Of course, a judgment module can also be added to the error estimation and calibration module, which is configured to judge whether C_τ i has converged to timely feedback the calibration progress.

[0112] Embodiment 4

[0113] This Embodiment 4 discloses a computer device, including a memory and a processor. A computer program is stored in the memory. When the processor executes the computer program, the steps of the dual-channel TIADC sampling time mismatch error estimation and calibration method disclosed in Embodiment 1 are implemented.

[0114] This Embodiment 4 also discloses a readable storage medium in which computer program instructions are stored. When the computer program instructions are read and run by a processor, the steps of the dual-channel TIADC sampling time mismatch error estimation and calibration method disclosed in Embodiment 1 are executed.

[0115] This Embodiment 4 also discloses a computer program product, including a computer program. When the computer program is executed by a processor, the steps of the dual-channel TIADC sampling time mismatch error estimation and calibration method disclosed in Embodiment 1 are implemented.

[0116] The technical features of the above embodiments can be combined arbitrarily. For the sake of brevity of description, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, it should be considered as the scope recorded in this specification.

[0117] The above-described embodiments merely represent several implementation manners of the present invention. The description thereof is relatively specific and detailed, but it should not be construed as a limitation on the scope of the invention patent. It should be noted that for those of ordinary skill in the art, without departing from the concept of the present invention, several modifications and improvements can still be made, and these all fall within the protection scope of the present invention. Therefore, the protection scope of the present invention patent shall be subject to the appended claims.

Claims

1. A dual-channel TIADC sampling time mismatch error estimation and calibration method, which is used to estimate and calibrate the sampling time mismatch τ of Sub_ADC2 using Sub_ADC1 as a reference; Sub_ADC1 and Sub_ADC2 represent two sub-analog-to-digital converters of the dual-channel TIADC; characterized in that, It includes: T s is a cycle, and the output signals of Sub_ADC1 and Sub_ADC2 are obtained multiple times periodically; wherein, T s Indicates the sampling period of dual-channel TIADC; Based on the obtained y 1,i [n], y 2,i [n] performs the i-th round of calibration; where y 1,i [n], y 2,i [n] represents the i-th output signal of Sub_ADC1 and Sub_ADC2 respectively; n∈[0,N]; N represents the total number of sampling points used by a single sub-ADC to output the signal each time; n represents the n-th sampling point in N; i≥1; Among them, the method of the i-th round of calibration includes: S100, for 1,i [n] Perform data conversion to obtain the imaginary part Im_y containing the phase information delayed by 90° 1,i [n]; According to the mismatch parameter C_τ of the i-th round i For 2,i [n] Perform digital correction to delay the signal phase by C_τ i , and obtain the corrected output signal y 2_call,i [n]; S200, Im_y 1,i [n] multiplied by y 2_call,i [n] to get the multiplication result p i [n]; S300, calculate p i [0]~p i The mean value of [N] i ; S400, avg i As the iteration parameter, and the estimated parameter C_err for the i-1th round i-1 Iterate to get the estimated parameter C_err of the i-th round i ; S500, C_err i Add T s To obtain the mismatch parameter C_τ of the i+1th round i+1 ; Among them, if C_τ i If convergence has occurred, the calibration is complete and C_err i as τ to calibrate the output signal of Sub_ADC2; otherwise, the calibration is not completed and the (i+1)th round of calibration is performed.

2. The dual-channel TIADC sampling time mismatch error estimation and calibration method according to claim 1, characterized in that: In S100, Hilbert transform is used to transform y 1,i [n] Perform data conversion.

3. The dual-channel TIADC sampling time mismatch error estimation and calibration method according to claim 1, characterized in that: In S100, an interpolation delay filter is used to 2,i [n] Perform digital correction; Among them, C_τ i As the configuration parameters used by the interpolation delay filter during the i-th round of calibration.

4. The dual-channel TIADC sampling time mismatch error estimation and calibration method according to claim 1, characterized in that: In S200, p i The calculation formula for [n] is: p i [n]=Im_y 1,i [n]×y 2_call,i [n]; In S300, avg i The calculation formula is: avg i =(p i [0]+…+p i [N]) / N。 5. The dual-channel TIADC sampling time mismatch error estimation and calibration method according to claim 1, characterized in that: In S400, C_err i The calculation formula is: C_err i =C_err i-1 -μ*avg i ; Where μ represents the iteration coefficient.

6. The dual-channel TIADC sampling time mismatch error estimation and calibration method according to claim 5, characterized in that: In S400, LMS adaptive engine filter is used to filter C_err i-1 Iterate Among them, avg i , μ are the configuration parameters used by the LMS adaptive engine filter during the i-th round of calibration.

7. The dual-channel TIADC sampling time mismatch error estimation and calibration method according to claim 1, characterized in that: Sub_ADC1 and Sub_ADC2 test signal V in Perform sampling to obtain a corresponding output signal; V in It can be a single tone signal or a multi-tone signal.

8. A dual-channel TIADC sampling time mismatch error estimation and calibration device, characterized in that: The dual-channel TIADC sampling time mismatch error estimation and calibration method described in any one of claims 1 to 7 is used, The dual-channel TIADC sampling time mismatch error estimation and calibration device comprises: The signal acquisition module is used to s For one cycle, the output signals of Sub_ADC1 and Sub_ADC2 are obtained multiple times periodically; as well as Error estimation and calibration module, which is used to obtain y 1,i [n], y 2,i [n] Perform the i-th round of calibration; The error estimation and calibration module includes: a data conversion submodule, a digital correction submodule, a product calculation submodule, an average calculation submodule, an estimation submodule, and an adjustment submodule; The data conversion submodule is used to convert y 1,i [n] Perform data conversion to obtain the imaginary part Im_y containing the phase information delayed by 90° 1,i [n]; The digital correction submodule is used to calculate the mismatch parameter C_τ according to the i-th round i For 2,i [n] Perform digital correction to delay the signal phase by C_τ i , and obtain the corrected output signal y 2_call,i [n]; The product calculation submodule is used to convert Im_y 1,i [n] multiplied by y 2_call,i [n] to get the multiplication result p i [n]; The average calculation submodule is used to calculate p i [0]~p i The mean value of [N] i ; The estimation submodule is used to convert avg i As the iteration parameter, and the estimated parameter C_err for the i-1th round i-1 Iterate to get the estimated parameter C_err of the i-th round i ; Adjust the submodule to use C_err i Add T s To obtain the mismatch parameter C_τ of the i+1th round i+1 .

9. The dual-channel TIADC sampling time mismatch error estimation and calibration device according to claim 8, characterized in that: The error estimation and calibration module also includes: The judgment module is used to judge C_τ i Whether it has converged.

10. A computer program product, characterized in that It includes a computer program; when the computer program is executed by a processor, it implements the steps of the dual-channel TIADC sampling time mismatch error estimation and calibration method as described in any one of claims 1 to 7.

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