Data transmission method, device and system and computer readable storage medium

Abstract

The invention discloses a data transmission method, device and system and a computer readable storage medium, and relates to the technical field of communication. The method comprises the following steps: a first module carries out convolution interleaving on symbols included in a plurality of obtained first code words to obtain an interleaving result, and the first code words are code words obtained by coding first data by adopting a first FEC (Forward Error Correction) code; and obtaining second data including the identification information according to the interleaving result, and transmitting the second data to the second module. Convolutional interleaving is carried out on the symbols included in the plurality of first code words, and when burst error codes occur in subsequent second data, the burst error codes are dispersed into the plurality of symbols, so that the BER of the second data after error correction is reduced. Under the condition that the second data comprises the second code word, the identification information comprises the code word boundary information of the second code word, additional data does not need to be additionally inserted as the identification information, and therefore the data transmission cost is low.

Description

[0001] This application is a divisional application. The application number of the original application is 202310037983.5, the original application date is January 10, 2023, and the entire content of the original application is incorporated herein by reference. Technical Field

[0002] This application relates to the field of communication technologies, and in particular, to a data transmission method, apparatus, system, and computer-readable storage medium. Background Art

[0003] With the development of communication technologies, encoding data according to forward error correction (FEC) codes at the data sending end and decoding the received data using the same FEC codes at the data receiving end has become a relatively widespread data transmission method. During the decoding process, the data receiving end corrects errors in the received data to correct bit errors in the data. Due to the different distributions of bit errors in the data, even when the bit error rate (BER) before error correction is the same, the BER after error correction may be different.

[0004] For example, according to the distribution, bit errors include random errors and non-random errors, and non-random errors are manifested as multiple bit errors concentrated in a relatively short data sequence. Generally, based on the same BER before error correction, non-random errors will result in a higher BER after error correction than random errors. Therefore, a data transmission method is needed that, on the basis of combining FEC, swaps the data positions in an interleaved manner at the data sending end and restores the data positions in a de-interleaved manner at the data receiving end, so that the distribution of non-random errors approaches random errors after de-interleaving, thereby reducing the BER after error correction. Summary of the Invention

[0005] This application proposes a data transmission method, apparatus, system, and computer-readable storage medium for realizing data transmission by combining convolutional interleaving on the basis of FEC.

[0006] In a first aspect, a data transmission method is provided. The method includes: a first module performing convolutional interleaving on symbols included in a plurality of first codewords obtained, where the first codewords are codewords obtained by encoding first data using a first FEC code; then, the first module obtaining second data including identification information according to the interleaving result and transmitting the second data to a second module, and when the second data includes a second codeword, the identification information includes codeword boundary information of the second codeword.

[0007] In this method, by performing convolutional interleaving on the symbols included in multiple first codewords, when burst errors occur in the subsequent second data, the burst errors will be dispersed into multiple symbols, thereby reducing the BER of the second data after error correction. Furthermore, when the second data includes a second codeword, the identification information is the codeword boundary information of the second codeword, and there is no need to additionally insert identification information indicating the starting interleaving position for performing convolutional interleaving on the symbols included in multiple first codewords. Therefore, the data transmission cost is relatively low, the applicability to data transmission scenarios with limited bandwidth or PLL frequency points is relatively high, and the implementation complexity of the data transmission system for executing this method is relatively low.

[0008] In a possible implementation manner, performing convolutional interleaving on the symbols included in the obtained multiple first codewords to obtain an interleaving result includes: inputting the symbols included in the multiple first codewords into multiple first delay units of a convolutional interleaver, performing convolutional interleaving on the symbols included in the multiple first codewords polled by the multiple first delay units, obtaining multiple first bit groups output by polling of the multiple first delay units, and using the multiple first bit groups output by polling of the multiple first delay units as the interleaving result, where one first bit group includes the symbols output by polling of the multiple first delay units once. In the process of obtaining the interleaving result through convolutional interleaving in this method, convolutional interleaving is performed on the symbols included in the multiple first codewords without introducing additional data. Therefore, the amount of data for performing convolutional interleaving is relatively small, and the efficiency of convolutional interleaving is relatively high.

[0009] In a possible implementation manner, the interleaving result includes n first bit groups output by polling of the multiple first delay units n times. Obtaining second data including identification information according to the interleaving result includes: encoding the n first bit groups output by polling of the multiple first delay units n times according to a second FEC code to obtain m second codewords, and obtaining the second data according to the m second codewords; where the number of bits corresponding to the n first bit groups is equal to the number of bits included in the information bits of the codewords of the m second FEC codes, and both m and n are positive integers, and m is less than or equal to n.

[0010] In this implementation manner, by encoding the n first bit groups according to the second FEC code to obtain m second codewords, the receiving end can obtain the starting interleaving position for performing convolutional interleaving on the symbols included in the multiple first codewords by obtaining the codeword boundary information of the second codewords, and then perform convolutional deinterleaving according to the starting interleaving position. Since there is no need to additionally insert identification information, the data transmission cost of this implementation manner is relatively low, and the applicability to data transmission scenarios with limited bandwidth or PLL frequency points is relatively high.

[0011] In a possible implementation, the second data does not include a second codeword. The interleaving result includes n first bit groups output by polling multiple first delay units n times. Obtaining the second data including identification information based on the interleaving result includes: obtaining k target data frames based on the n first bit groups output by polling multiple first delay units n times in accordance with the format of a reference data frame, and obtaining the second data from the k target data frames; wherein, the target data frame includes frame synchronization information, and the frame synchronization information is used as identification information. The number of bits corresponding to the n first bit groups is less than or equal to the number of bits included in the k target data frames. Both k and n are positive integers, and k is less than or equal to n. When the second data does not include a second codeword, it means that this method can be applied to non-cascaded coding scenarios, and the applicable scenarios of this method are relatively flexible.

[0012] In a possible implementation, the second data does not include a second codeword. Convolutionally interleaving the symbols included in the obtained multiple first codewords to obtain an interleaving result includes: inputting at least one identification information and the symbols included in the multiple first codewords into multiple first delay units of a convolutional interleaver, and performing convolutional interleaving on the at least one identification information and the symbols included in the multiple first codewords polled by the multiple first delay units to obtain multiple second bit groups output by polling the multiple first delay units, and using the multiple second bit groups output by polling the multiple first delay units as the interleaving result; wherein, at least one second bit group includes symbols output by polling the multiple first delay units once, or at least one second bit group includes identification information and symbols output by polling the multiple first delay units once. The identification information is used to indicate the starting interleaving position for convolutional interleaving of the symbols included in the multiple first codewords. When the interleaving result is obtained through this implementation, the specific form of the identification information can be set according to experience or actual requirements, as long as the identification information can indicate the starting interleaving position for convolutional interleaving of the symbols included in the multiple first codewords, and the type of the identification information is relatively flexible.

[0013] In a possible implementation, the starting interleaving position for convolutional interleaving of the symbols included in the multiple first codewords is located in any one of the multiple first delay units, and the position where the starting interleaving position is located is relatively flexible.

[0014] In a possible implementation, the symbols included in the multiple first codewords are input into the multiple first delay units of the convolutional interleaver in the form of a first data stream, and the transmission rate of the first data stream is greater than or equal to 100 gigabits per second (Gbps), and the rate at which the symbols included in the multiple first codewords are input into the multiple first delay units of the convolutional interleaver is relatively high.

[0015] In a possible implementation, the first data stream is transmitted to a plurality of first delay units of the convolutional interleaver through at least one channel of an attachment unit interface (AUI), and the way of transmitting the first data stream is relatively flexible.

[0016] In a second aspect, a data transmission method is provided. The method includes: a second module receives second data including identification information transmitted by a first module, where the second data is obtained according to an interleaving result obtained by performing convolutional interleaving on symbols included in a plurality of first codewords, and the first codewords are codewords obtained by encoding first data using a first FEC code. When the second data includes a second codeword, the identification information includes codeword boundary information of the second codeword; obtaining a starting interleaving position for performing convolutional interleaving on symbols included in the plurality of first codewords and data to be de-interleaved in the second data according to the identification information; and performing convolutional de-interleaving on the data to be de-interleaved based on the starting interleaving position to obtain a plurality of first codewords.

[0017] In this method, since the second data is obtained according to an interleaving result obtained by performing convolutional interleaving on symbols included in a plurality of first codewords, when burst errors occur in the second data, the burst errors will be dispersed into a plurality of symbols, thereby reducing the BER of the second data after error correction. Further, when the second data includes a second codeword, the identification information is the codeword boundary information of the second codeword, and there is no need to additionally insert identification information for indicating the starting interleaving position for performing convolutional interleaving on symbols included in the plurality of first codewords in the second data, so the data transmission cost is relatively low, the applicability to data transmission scenarios with limited bandwidth or PLL frequency points is relatively high, and the implementation complexity of the data transmission system for executing this method is relatively low.

[0018] In a possible implementation, obtaining a starting interleaving position for performing convolutional interleaving on symbols included in a plurality of first codewords and data to be de-interleaved in the second data according to the identification information includes: obtaining at least one second codeword included in the second data according to the codeword boundary information of the second codeword; obtaining the starting position of at least one second codeword, and using the starting position as the starting interleaving position for performing convolutional interleaving on symbols included in the plurality of first codewords; and decoding at least one second codeword to obtain the data to be de-interleaved. This implementation can be applied to the scenario of concatenated coding.

[0019] In a possible implementation, when the second data does not include a second codeword, the identification information is frame synchronization information. Obtaining the starting interleaving position for convolutional interleaving of the symbols included in multiple first codewords and the data to be deinterleaved in the second data according to the identification information includes: obtaining at least one target data frame included in the second data according to the frame synchronization information; obtaining the starting position of the frame data of at least one target data frame, and using the starting position as the starting interleaving position for convolutional interleaving of the symbols included in multiple first codewords; and using the frame data included in at least one target data frame as the data to be deinterleaved. This implementation can be applied to the scenario of non-cascaded coding and the case where the second data includes target data frames.

[0020] In a possible implementation, the data to be deinterleaved includes multiple third bit groups, and one third bit group includes the symbols of the first codeword output by polling multiple first delay units of a convolutional interleaver once; performing convolutional deinterleaving on the data to be deinterleaved based on the starting interleaving position to obtain multiple first codewords, including: obtaining the starting deinterleaving position corresponding to the starting interleaving position in multiple second delay units of a convolutional deinterleaver; inputting multiple third bit groups from the starting deinterleaving position into multiple second delay units, and performing convolutional deinterleaving on the symbols included in the polled multiple third bit groups by the multiple second delay units; obtaining the symbols included in the multiple first codewords output by polling multiple second delay units, and obtaining multiple first codewords according to the symbols included in the multiple first codewords. In this implementation, the third bit group does not include identification information, and the efficiency of performing convolutional deinterleaving is relatively high.

[0021] In a possible implementation, when the second data does not include a second codeword, the identification information is used to indicate the starting interleaving position for convolutional interleaving of the symbols included in multiple first codewords; obtaining the starting interleaving position for convolutional interleaving of the symbols included in multiple first codewords and the data to be deinterleaved in the second data according to the identification information includes: obtaining the starting interleaving position for convolutional interleaving of the symbols included in multiple first codewords indicated by the identification information; and using the data in the second data located at the starting interleaving position and the data after the starting interleaving position as the data to be deinterleaved. This implementation can be applied to the scenario of non-cascaded coding and the case where the second data does not include target data frames.

[0022] In a possible implementation, the data to be deinterleaved includes a plurality of fourth bit groups. At least one fourth bit group includes symbols of a first codeword output by polling a plurality of first delay units of a convolutional interleaver once, or at least one fourth bit group includes identification information and symbols output by polling a plurality of first delay units once; performing convolutional deinterleaving on the data to be deinterleaved based on the starting interleaving position to obtain a plurality of first codewords, including: obtaining a starting deinterleaving position corresponding to the starting interleaving position in a plurality of second delay units of the convolutional deinterleaver; inputting the plurality of fourth bit groups from the starting deinterleaving position into the plurality of second delay units, and performing convolutional deinterleaving on the symbols included in the plurality of fourth bit groups polled, or the identification information and symbols included in the plurality of fourth bit groups, by the plurality of second delay units; obtaining the symbols and identification information included in the plurality of first codewords output by polling the plurality of second delay units, and obtaining a plurality of first codewords according to the symbols included in the plurality of first codewords. This implementation can be applied to convolutional deinterleaving of fourth bit groups including identification information.

[0023] In a possible implementation, the starting deinterleaving position is located in any one of the plurality of second delay units, and the position where the starting deinterleaving position is located is relatively flexible.

[0024] In a possible implementation, the plurality of second delay units of the convolutional deinterleaver output the symbols included in the plurality of first codewords in the form of a second data stream, and the transmission rate of the second data stream is greater than or equal to 100 Gbps. The rate at which the plurality of second delay units output the symbols included in the plurality of first codewords is relatively high.

[0025] In a possible implementation, the plurality of second delay units of the convolutional deinterleaver output the second data stream through at least one channel of the AUI, and the manner of transmitting the second data stream is relatively flexible.

[0026] In a third aspect, a data transmission device is provided. The device is applied to a first module, and the device includes:

[0027] An interleaving unit, configured to perform convolutional interleaving on the symbols included in the obtained plurality of first codewords to obtain an interleaving result, where the first codeword is a codeword obtained by encoding first data using a first FEC code;

[0028] An obtaining unit, configured to obtain second data including identification information according to the interleaving result, where when the second data includes a second codeword, the identification information includes the codeword boundary information of the second codeword;

[0029] A transmission unit, configured to transmit the second data to a second module.

[0030] In a possible implementation, an interleaving unit is configured to input symbols included in a plurality of first codewords into a plurality of first delay units of a convolutional interleaver, perform convolutional interleaving on the symbols included in the plurality of first codewords polled by the plurality of first delay units, and obtain a plurality of first bit groups output by polling the plurality of first delay units. One first bit group includes symbols output by polling the plurality of first delay units once; and use the plurality of first bit groups output by polling the plurality of first delay units as an interleaving result.

[0031] In a possible implementation, the interleaving result includes n first bit groups output by polling the plurality of first delay units n times. An obtaining unit is configured to encode the n first bit groups output by polling the plurality of first delay units n times according to a second FEC code to obtain m second codewords. The number of bits corresponding to the n first bit groups is equal to the number of bits included in the information bits of the codewords of the m second FEC codes. Both m and n are positive integers, and m is less than or equal to n; and obtain second data according to the m second codewords.

[0032] In a possible implementation, the second data does not include the second codewords. The interleaving result includes n first bit groups output by polling the plurality of first delay units n times. An obtaining unit is configured to obtain k target data frames based on the n first bit groups output by polling the plurality of first delay units n times according to the format of a reference data frame. The target data frames include frame synchronization information, and the frame synchronization information is used as identification information. The number of bits corresponding to the n first bit groups is less than or equal to the number of bits included in the k target data frames. Both k and n are positive integers, and k is less than or equal to n; and obtain second data according to the k target data frames.

[0033] In a possible implementation, the second data does not include the second codewords. The interleaving unit is configured to input at least one identification information and symbols included in a plurality of first codewords into a plurality of first delay units of a convolutional interleaver, perform convolutional interleaving on the at least one identification information and the symbols included in the plurality of first codewords polled by the plurality of first delay units, and obtain a plurality of second bit groups output by polling the plurality of first delay units. At least one second bit group includes symbols output by polling the plurality of first delay units once, or at least one second bit group includes the identification information and symbols output by polling the plurality of first delay units once. The identification information is used to indicate a starting interleaving position for performing convolutional interleaving on the symbols included in the plurality of first codewords; and use the plurality of second bit groups output by polling the plurality of first delay units as an interleaving result.

[0034] In a possible implementation, the starting interleaving position for performing convolutional interleaving on the symbols included in the plurality of first codewords is located in any one of the plurality of first delay units.

[0035] In a possible implementation, the symbols included in multiple first codewords are input into multiple first delay units of a convolutional interleaver in the manner of a first data stream, and the transmission rate of the first data stream is greater than or equal to 100 Gbps.

[0036] In a possible implementation, the first data stream is transmitted to multiple first delay units of the convolutional interleaver through at least one channel of the AUI.

[0037] In a fourth aspect, a data transmission device is provided. The device is applied to a second module and includes:

[0038] An obtaining unit, configured to receive second data including identification information transmitted by a first module. The second data is obtained according to an interleaving result obtained by performing convolutional interleaving on the symbols included in multiple first codewords. The first codewords are codewords obtained by encoding first data using a first FEC code. When the second data includes a second codeword, the identification information includes codeword boundary information of the second codeword;

[0039] The obtaining unit is further configured to obtain a starting interleaving position for performing convolutional interleaving on the symbols included in multiple first codewords and the data to be de-interleaved in the second data according to the identification information;

[0040] A de-interleaving unit, configured to perform convolutional de-interleaving on the data to be de-interleaved based on the starting interleaving position to obtain multiple first codewords.

[0041] In a possible implementation, the obtaining unit is configured to obtain at least one second codeword included in the second data according to the codeword boundary information of the second codeword; obtain the starting position of at least one second codeword, and use the starting position as the starting interleaving position for performing convolutional interleaving on the symbols included in multiple first codewords; decode at least one second codeword to obtain the data to be de-interleaved.

[0042] In a possible implementation, when the second data does not include a second codeword, the identification information is frame synchronization information. The obtaining unit is configured to obtain at least one target data frame included in the second data according to the frame synchronization information; obtain the starting position of the frame data of at least one target data frame, and use the starting position as the starting interleaving position; use the frame data included in at least one target data frame as the data to be de-interleaved.

[0043] In a possible implementation, the data to be deinterleaved includes a plurality of third bit groups, and one third bit group includes symbols of a first codeword output by polling a plurality of first delay units of a convolutional interleaver once; a deinterleaving unit, configured to obtain a starting deinterleaving position corresponding to a starting interleaving position in a plurality of second delay units of a convolutional deinterleaver; input the plurality of third bit groups into the plurality of second delay units from the starting deinterleaving position, and perform convolutional deinterleaving on the symbols included in the plurality of polled third bit groups through the plurality of second delay units; obtain the symbols included in a plurality of first codewords output by polling the plurality of second delay units, and obtain a plurality of first codewords according to the symbols included in the plurality of first codewords.

[0044] In a possible implementation, when the second data does not include a second codeword, the identification information is used to indicate a starting interleaving position for performing convolutional interleaving on the symbols included in a plurality of first codewords; an obtaining unit, configured to obtain the starting interleaving position for performing convolutional interleaving on the symbols included in a plurality of first codewords indicated by the identification information; and use the data in the second data located at the starting interleaving position and the data after the starting interleaving position as the data to be deinterleaved.

[0045] In a possible implementation, the data to be deinterleaved includes a plurality of fourth bit groups, at least one fourth bit group includes symbols of a first codeword output by polling a plurality of first delay units of a convolutional interleaver once, or at least one fourth bit group includes identification information and symbols output by polling a plurality of first delay units once; a deinterleaving unit, configured to obtain a starting deinterleaving position corresponding to a starting interleaving position in a plurality of second delay units of a convolutional deinterleaver; input the plurality of fourth bit groups into the plurality of second delay units from the starting deinterleaving position, and perform convolutional deinterleaving on the symbols included in the plurality of polled fourth bit groups, or the identification information and symbols included in the plurality of fourth bit groups through the plurality of second delay units; obtain the symbols and identification information included in a plurality of first codewords output by polling the plurality of second delay units, and obtain a plurality of first codewords according to the symbols included in the plurality of first codewords.

[0046] In a possible implementation, the starting deinterleaving position is located in any one of the plurality of second delay units.

[0047] In a possible implementation, a plurality of second delay units of a convolutional deinterleaver output symbols included in a plurality of first codewords in a second data stream, and the transmission rate of the second data stream is greater than or equal to 100 Gbps.

[0048] In a possible implementation, a plurality of second delay units of a convolutional deinterleaver output the second data stream through at least one channel of an AUI.

[0049] Fifth aspect, a data transmission system is provided. The system includes a first module and a second module. The first module is configured to execute any of the data transmission methods in the first aspect above, and the second module is configured to execute any of the data transmission methods in the second aspect above.

[0050] Sixth aspect, a computer system is provided. The computer system includes a processor. The processor includes a first module or a second module. When the processor includes the first module, when the processor executes program instructions or code, the computer system implements any of the data transmission methods in the first aspect. When the processor includes the second module, when the processor executes program instructions or code, the computer system implements any of the data transmission methods in the second aspect. Exemplarily, the computer system further includes a memory, and the memory is configured to store the above program instructions or code.

[0051] Seventh aspect, a computer-readable storage medium is provided. At least one program instruction or code is stored in the computer-readable storage medium. The program instruction or code is executed by a computer, and the computer includes a first module or a second module. When the computer includes the first module, when the program instruction or code is executed by the computer, the computer is caused to implement any of the data transmission methods in the first aspect. When the computer includes the second module, when the program instruction or code is executed by the computer, the computer is caused to implement any of the data transmission methods in the second aspect.

[0052] Eighth aspect, a communication device is provided. The device includes: a transceiver, a memory, and a processor. Among them, the transceiver, the memory, and the processor communicate with each other through an internal connection path. The memory is configured to store instructions, and the processor is configured to execute the instructions stored in the memory to control the transceiver to transmit and receive signals. The processor includes a first module or a second module. When the processor includes the first module, when the processor executes the instructions stored in the memory, the processor is caused to execute any of the data transmission methods in the first aspect. When the processor includes the second module, when the processor executes the instructions stored in the memory, the processor is caused to execute any of the data transmission methods in the second aspect.

[0053] Exemplarily, the processor is one or more, and the memory is one or more.

[0054] Exemplarily, the memory may be integrated with the processor, or the memory is separately provided from the processor.

[0055] In the specific implementation process, the memory can be a non-transitory memory, such as a read only memory (ROM), which can be integrated with the processor on the same chip or can be separately arranged on different chips. This application does not limit the type of the memory and the setting manner of the memory and the processor.

[0056] In a ninth aspect, a computer program product is provided. The computer program product includes computer program instructions or codes, and the computer program instructions or codes are run by a computer. The computer includes a first module or a second module. In the case where the computer includes the first module, when the computer program instructions or codes are run by the computer, the computer is caused to execute any one of the data transmission methods in the first aspect. In the case where the computer includes the second module, when the computer program instructions or codes are run by the computer, the computer is caused to execute any one of the data transmission methods in the second aspect.

[0057] In a tenth aspect, a chip is provided. The chip includes a processor, and the processor includes a first module or a second module. The processor is used to run program instructions or codes. In the case where the processor includes the first module, a device including the chip executes any one of the data transmission methods in the first aspect. In the case where the processor includes the second module, a device including the chip executes any one of the data transmission methods in the second aspect.

[0058] Exemplarily, the chip further includes: an input interface, an output interface, and the above-mentioned memory. The input interface, the output interface, the processor, and the memory are connected through an internal connection path, and the memory is used to store the above-mentioned program instructions or codes.

[0059] It should be understood that for the beneficial effects obtained by the technical solutions of the third aspect to the tenth aspect of this application and their corresponding possible implementation manners, reference can be made to the technical effects of the first aspect and the second aspect and their corresponding possible implementation manners above, which will not be elaborated here. Description of the Drawings

[0060] Figure 1 is a schematic diagram of random error codes and burst error codes provided by an embodiment of this application;

[0061] Figure 2 is a schematic diagram of the usage process of an interleaver and a deinterleaver provided by an embodiment of this application;

[0062] Figure 3 is a schematic diagram of an interleaving process provided by an embodiment of this application;

[0063] Figure 4 is a schematic diagram of a starting interleaving position provided by an embodiment of this application;

[0064] Figure 5 It is a schematic diagram of an implementation scenario provided by an embodiment of the present application;

[0065] Figure 6 It is a schematic diagram of another implementation scenario provided by an embodiment of the present application;

[0066] Figure 7 It is a schematic diagram of yet another implementation scenario provided by an embodiment of the present application;

[0067] Figure 8 It is a flowchart of a data transmission method provided by an embodiment of the present application;

[0068] Figure 9 It is a schematic diagram of a process for obtaining second data provided by an embodiment of the present application;

[0069] Figure 10 It is a schematic diagram of another process for obtaining second data provided by an embodiment of the present application;

[0070] Figure 11 It is a schematic diagram of yet another process for obtaining second data provided by an embodiment of the present application;

[0071] Figure 12 It is a schematic diagram of still another process for obtaining second data provided by an embodiment of the present application;

[0072] Figure 13 It is a schematic diagram of the structure of a data transmission device provided by an embodiment of the present application;

[0073] Figure 14 It is a schematic diagram of the structure of another data transmission device provided by an embodiment of the present application;

[0074] Figure 15 It is a schematic diagram of the structure of a computer system provided by an embodiment of the present application;

[0075] Figure 16 It is a schematic diagram of the structure of another computer system provided by an embodiment of the present application. Detailed implementation manners

[0076] The terms used in the implementation part of the present application are only for explaining the embodiments of the present application, and are not intended to limit the present application. The embodiments of the present application will be described below with reference to the accompanying drawings.

[0077] During the data transmission process, due to environmental interference and system errors, bit errors have always been an inevitable problem. A bit error refers to the inconsistent bits between the data received at the receiving end and the data sent by the sending end. Bit errors in the data may cause the data transmission system to crash and data loss. Moreover, the occurrence of bit errors may also affect the communication delay and the user experience of video, games, calls, etc. Therefore, the number of bit errors in the received data, that is, the bit error rate (BER) of the data, has always been a measure of the performance of the communication system.

[0078] Since the smaller the BER of the data, the higher the reliability of the data transmission. Therefore, by limiting the BER of the received data, the reliability of the data transmission system can be guaranteed. For example, the Institute of Electrical and Electronics Engineers (IEEE) 802.3 400 Gigabit Ethernet (GE) standard requires that the BER of the data at the receiving end when entering the media access control (MAC) layer is lower than 1e-13, and 1e-13 has the same meaning as 1×10-13. Since the BER of the data when transmitted via the link and entering the receiving end is about 2e-4, where 2e-4 has the same meaning as 2×10-4, therefore, encoding the data with FEC codes at the sending end of the data and decoding the received data with the same FEC codes at the receiving end of the data, so as to correct the bit errors in the received data, becomes a way to eliminate the bit errors that occur during the data transmission process. After correcting the bit errors in the data based on the FEC codes, the BER of the received data is relatively low.

[0079] Among them, according to the distribution, bit errors include random bit errors and non-random bit errors. Non-random bit errors can also be called burst errors. Figure 1 FIG. is a schematic diagram of a scenario of random bit errors and burst errors provided by an embodiment of the present application. In Figure 1 b represents correct data and y represents bit errors. Figure 1 (1) in FIG. represents the distribution of random bit errors. Figure 1 (2) in FIG. represents the distribution of burst bit errors. Figure 1 (1) and (2) in FIG. show that the BER of the data is the same.

[0080] Due to the different distributions of error codes in the data, the BER after error correction may be different when the BER before error correction is the same. Under most data transmission conditions, based on the same BER before error correction, burst errors will result in a higher BER after error correction than random errors. Therefore, by interleaving the data through an interleaver, the BER after error correction can be further reduced for burst errors.

[0081] Figure 2 FIG. is a schematic diagram of the usage process of an interleaver and a deinterleaver provided by an embodiment of the present application. At the data sending end, the data positions are swapped through interleaving, and at the data receiving end, the data positions are restored through deinterleaving, so that the burst errors that occur when the data is transmitted through the transmission channel are dispersed, so that the distribution of burst errors after deinterleaving approaches random errors, thereby reducing the BER after error correction. As Figure 2 shown, the data sending end can perform FEC encoding on the data through an FEC encoder before interleaving, and perform interleaving on the data after FEC encoding through an interleaver. The interleaved data is transmitted to the receiving end through the channel. The receiving end can perform deinterleaving on the received data through a deinterleaver, and perform FEC decoding on the data through an FEC decoder after deinterleaving. The FEC encoder at the sending end and the FEC decoder at the receiving end use the same FEC code. For example, the FEC code is a Reed-Solomon (RS) code, a Bose-Chaudhuri-Hocquenghem (BCH) code, an extended BCH code, a Hamming code, an extended Hamming code, a staircase code, a low-density parity-check (LDPC) code, a turbo code, or a turbo product code (TPC). The FEC codes mentioned in other parts of the present application can also be a Reed-Solomon (RS) code, a Bose-Chaudhuri-Hocquenghem (BCH) code, an extended BCH code, a Hamming code, an extended Hamming code, a staircase code, a low-density parity-check (LDPC) code, a turbo code, or a turbo product code (TPC).

[0082] In some embodiments, the interleaver may include a block interleaver and a convolution interleaver. Figure 3 FIG. is a schematic diagram of an interleaving process provided by an embodiment of the present application, wherein, Figure 3In (1) is a schematic diagram of the data interleaving by the block interleaver. Figure 3 In (2) is a schematic diagram of the data interleaving by the convolutional interleaver. Taking Figure 3 (1) in as an example, at the transmitter side (Tx) of the data, the codewords (cw) A to D encoded according to the first FEC code are arranged in four rows, and then the symbols of the FEC codewords are output column by column to form the interleaved data. In Figure 3 (1), a represents the symbol included in cwA, b represents the symbol included in cwB, c represents the symbol included in cwC, and d represents the symbol included in cwD.

[0083] Taking Figure 3 (2) in as an example, the convolutional interleaver includes a plurality of delay units, and the delay units can correspond to Figure 3 (2) shown in the delay line, and the delay length corresponding to each delay line is determined according to the delay block length and the number of delay blocks of each delay line. As Figure 3 (2) shown, the number of delay lines is 4. In the order from top to bottom, the four delay lines can be delay line 0, delay line 1, delay line 2, and delay line 3. The delay block can be implemented by a linear-feedback shift register (LFSR), and the delay block can store data. Exemplarily, when the sizes of the delay blocks in each delay line are the same, the number of delay blocks in each delay line is different; when the sizes of the delay blocks in each delay line are different, the number of delay blocks in each delay line is the same. There is a switchable connection switch on each of the input side and the output side of the convolutional interleaver, and these two connection switches are used to connect a certain delay line simultaneously. As Figure 3 (2) shown, the symbols of the FEC codewords can enter the convolutional interleaver column by column. Every time a symbol enters from the input side, a symbol will be output from the output side, and then the connection switches on both sides will switch to the next delay line. The multiple delay lines can be polled in the order of 0, 1, 2, 3, 0, 1, 2, 3, 0, 1, …. In Figure 3 (2), the delay block is represented by D, and the data before cwA to cwD stored in the delay block is represented by x.

[0084] Since the convolutional interleaver includes multiple delay units with different delay lengths, when deinterleaving at the data receiving end, it is necessary to determine the starting interleaving position for symbol interleaving to obtain the correct data. In the embodiments of this application, the starting interleaving position can also be referred to as the synchronization position. Since the multiple delay units input and output symbols in a polling manner, the starting interleaving position appears periodically in the data stream after convolutional interleaving. Figure 4 It is a schematic diagram of a starting interleaving position provided by the embodiments of this application. Figure 4 The data stream shown can be Figure 3 the data stream after convolutional interleaving shown in (2) of Figure 4 In this data stream, the starting interleaving position is Figure 4 also shown in the process of convolutional deinterleaving of the interleaved data stream. Refer to Figure 4 . Poll the multiple symbols received through the channel into the multiple delay units of the convolutional deinterleaver, perform convolutional deinterleaving on the multiple symbols through the multiple delay units of the convolutional deinterleaver, and obtain cwA to cwD according to the symbols polled and output by the multiple delay units of the convolutional deinterleaver.

[0085] The embodiments of this application provide a data transmission method for realizing data transmission by combining convolutional interleaving on the basis of FEC. This method can be applied to Figure 5 the implementation scenario shown. Refer to Figure 5 . This implementation scenario includes a first module 101 and a second module 102, which are communicatively connected. Exemplarily, the first module 101 is included in the first device, the second module 102 is included in the second device, and the first module 101 and the second module 102 can also be included in the same device. Among them, the devices where the first module 101 and the second module 102 are located can be network devices or other devices based on Ethernet interfaces.

[0086] Figure 5 The implementation scenario shown can be combined with the scenario of concatenated coding. That is to say, the implementation environment of this method can be as Figure 6 shown. Refer to Figure 6, the first module 101 can perform encoding according to the first FEC code, convolutional interleaving, and encoding according to the second FEC code, and transmit the data obtained by encoding according to the second FEC code to the second module 102 through a channel. The second module 102 can perform decoding according to the second FEC code, convolutional deinterleaving, and decoding according to the first FEC code. In a possible implementation, after the first module 101 encodes the data according to the second FEC code, it can also interleave the data and transmit the interleaved data encoded according to the second FEC code to the second module 102 through a channel. Accordingly, the second module 102 can also deinterleave the interleaved data encoded according to the second FEC code to obtain the data encoded according to the second FEC code, and then perform subsequent operations such as decoding according to the second FEC code. Among them, the methods of interleaving the data obtained by encoding according to the second FEC code include but are not limited to block interleaving and convolutional interleaving. When the interleaving method is block interleaving, the method for the second module 102 to deinterleave the interleaved data encoded according to the second FEC code is block deinterleaving. When the interleaving method is convolutional interleaving, the method for the second module 102 to deinterleave the interleaved data encoded according to the second FEC code is convolutional deinterleaving.

[0087] In addition, the above takes Figure 6 the first module 101 in which uses two interleavings, and the first interleaving is convolutional interleaving, and the second interleaving is convolutional interleaving or block interleaving as an example for illustration. In a possible implementation, the method provided by the embodiments of the present application can also support the first module 101 to use block interleaving for the first interleaving and convolutional interleaving for the second interleaving. Accordingly, the second module 102 performs two deinterleavings, the first deinterleaving method is block deinterleaving, and the second deinterleaving method is convolutional deinterleaving. Among them, regardless of which order the convolutional interleaving or convolutional deinterleaving is performed according to the above, the methods of convolutional interleaving and convolutional deinterleaving provided by the embodiments of the present application can be referred to.

[0088] Figure 5 The implementation scenario shown can also be combined with the scenario of non-cascaded coding, that is, the implementation environment of this method can be as Figure 7 shown. Refer to Figure 7 , the first module 101 can perform encoding according to the first FEC code, convolutional interleaving, and obtaining a data frame, and transmit the obtained data frame to the second module 102 through a channel. The second module 102 can perform receiving the data frame, convolutional deinterleaving, and decoding according to the first FEC code. Figures 5 to 7 Other modules may also be included in the implementation scenario shown, and the embodiments of the present application do not limit this.

[0089] The data transmission method provided by the embodiments of the present application can be as Figure 8 shown. Next, in combination with Figure 5The following shows an implementation scenario to illustrate the data transmission method provided by the embodiments of this application. As Figure 8 shown, this method includes S801 to S803.

[0090] S801, the first module performs convolutional interleaving on the symbols included in multiple first codewords obtained, to obtain an interleaving result. The first codewords are the codewords obtained by encoding first data using a first FEC code.

[0091] The embodiments of this application do not limit the manner in which the first module obtains the first codewords. For example, the first module may receive multiple first codewords transmitted by other modules, or the first module encodes the first data according to the first FEC code to obtain multiple first codewords. The first data may be data received by the first module from other modules or data generated by the first module.

[0092] Exemplarily, the symbols of the multiple first codewords used to perform convolutional interleaving may undergo distribution processing. For example, the first module performs distribution processing on the symbols included in each first codeword to obtain multiple paths of data. Any path of data includes symbols from multiple first codewords, and then the symbols included in each path of data are respectively used as the symbols for performing convolutional interleaving. Of course, the first module may also not perform distribution processing on the symbols included in the multiple first codewords, and directly use the symbols included in the multiple first codewords as the symbols for performing convolutional interleaving.

[0093] In the embodiments of this application, the number of bits included in the symbols used to perform convolutional interleaving may be related or unrelated to the first FEC code. For example, the number of bits included in the symbols used to perform convolutional interleaving is equal to the number of bits included in the symbols of the codewords of the first FEC code, or the number of bits included in the symbols used to perform convolutional interleaving may be determined according to experience or actual requirements. The embodiments of this application do not limit the number of bits included in the symbols used to perform convolutional interleaving.

[0094] In a possible implementation manner, performing convolutional interleaving on the symbols included in the multiple first codewords obtained to obtain an interleaving result includes the following Method 1 and Method 2.

[0095] Method 1, input the symbols included in the multiple first codewords into multiple first delay units of a convolutional interleaver, and perform convolutional interleaving on the symbols included in the multiple first codewords polled by the multiple first delay units to obtain multiple first bit groups output by polling of the multiple first delay units. A first bit group includes the symbols output by polling the multiple first delay units once; use the multiple first bit groups output by polling of the multiple first delay units as the interleaving result.

[0096] In the case of performing convolutional interleaving through multiple first delay units of a convolutional interleaver, the starting interleaving position for convolutional interleaving of the symbols included in multiple first codewords may refer to the starting polling position when polling the symbols of the first codewords in a round-robin manner. For example, the convolutional interleaver includes four first delay units, which are numbered as the first delay unit 0 to the first delay unit 3 respectively. When the symbols of the first codeword are polled and input starting from the first delay unit 0, the starting interleaving position is located at the first delay unit 0. When the symbols of the first codeword are polled and input starting from the first delay unit 1, the starting interleaving position is located at the first delay unit 1. When the symbols of the first codeword are polled and input starting from the first delay unit 2 or the first delay unit 3, the principle of the position where the starting interleaving position is located is the same, and will not be elaborated here. Combining the above content, it can be seen that in the embodiments of the present application, the starting interleaving position for convolutional interleaving of the symbols included in multiple first codewords may be located in any one of the multiple first delay units.

[0097] Exemplarily, the symbols output after polling the multiple first delay units once are used as a first bit group, then the symbols output after polling the multiple first delay units n times are used as n first bit groups, and the n first bit groups are used as the interleaving result, where n is a positive integer. In the case where the delay unit is a delay row, the multiple delay rows may output symbols column by column. Thus, if the starting interleaving position is located in the first delay row among the multiple delay rows, the symbols output after polling the multiple delay rows once are in the same column; if the starting interleaving position is located in a delay row other than the first delay row among the multiple delay rows, the symbols output after polling the multiple delay rows once are in different columns.

[0098] In the process of obtaining the interleaving result by convolutional interleaving in the above method 1, only the symbols included in multiple first codewords are subjected to convolutional interleaving, and no additional data is introduced. Thus, the amount of data for performing convolutional interleaving is small, and the efficiency of convolutional interleaving is high. In the embodiments of the present application, for a non-cascaded coding scenario, the first module may further obtain identification information, where the identification information is used to indicate the starting interleaving position for convolutional interleaving of the symbols included in multiple first codewords, and perform convolutional interleaving on the identification information and the symbols included in multiple first codewords together. In this case, the obtained interleaving result includes the identification information indicating the starting interleaving position. The process of performing convolutional interleaving on the identification information and the symbols included in multiple first codewords together can be seen in Method 2 below.

[0099] Method 2: Input the symbols included in at least one identification information and multiple first codewords into multiple first delay units of a convolutional interleaver. Perform convolutional interleaving on the symbols included in the polled at least one identification information and multiple first codewords through the multiple first delay units to obtain multiple second bit groups polled and output by the multiple first delay units. At least one second bit group includes the symbols output by polling the multiple first delay units once, or at least one second bit group includes the identification information and symbols output by polling the multiple first delay units once; Use the multiple second bit groups polled and output by the multiple first delay units as the interleaving result.

[0100] The number of bits included in the identification information may be equal to the number of bits included in the symbol. In the case of obtaining the interleaving result through Method 2, the specific form of the identification information can be set according to experience or actual requirements, as long as the identification information can indicate the starting interleaving position, and the embodiments of the present application do not limit this.

[0101] In Method 2, the starting interleaving position may also be located in any one of the multiple first delay units, and the embodiments of the present application do not limit this. Since the identification information and the symbols of the first codeword are jointly subjected to convolutional interleaving in Method 2, a second bit group output by polling the multiple first delay units once may only include symbols, or may include both symbols and identification information. Exemplarily, a second bit group is output by polling the multiple first delay units once. In the case where the multiple first delay units poll and output t times, the multiple first delay units output t second bit groups, and the t second bit groups are used as the interleaving result, where t is a positive integer.

[0102] Exemplarily, the symbols included in the multiple first codewords are input into the multiple first delay units of the convolutional interleaver in the form of a first data stream, and the transmission rate of the first data stream is greater than or equal to 100 Gbps. Of course, the transmission rate of the first data stream may also be a higher rate, for example, the transmission rate of the first data stream is greater than or equal to 200 Gbps. In a possible implementation manner, the first data stream may be transmitted to the multiple first delay units of the convolutional interleaver through at least one channel of the AUI. Since the embodiments of the present application can jointly perform convolutional interleaving on at least one identification information and the symbols included in the multiple first codewords, in this case, at least one identification information and the symbols included in the multiple first codewords may also be input into the multiple first delay units of the convolutional interleaver in the form of a data stream, that is, the first data stream may include at least one identification information and the symbols included in the multiple first codewords. In the embodiments of the present application, the symbols or identification information in the first data stream are input into the multiple first delay units in a polling manner.

[0103] S802. The first module obtains second data including identification information according to the interleaving result.

[0104] Combined with the content of S801 above, the identification information can be used to indicate the starting interleaving position for convolutional interleaving of the symbols included in multiple first codewords. Since the interleaving result obtained through the above-mentioned first method does not include the identification information, the first module can introduce the identification information when obtaining the second data according to the interleaving result. For example, when the second data includes a second codeword, the identification information includes the codeword boundary information of the second codeword, that is, the codeword boundary information of the second codeword can be used to indicate the starting interleaving position for convolutional interleaving of the symbols included in multiple first codewords. Since the interleaving result obtained through the above-mentioned second method includes the identification information, the first module can directly use the obtained interleaving result as the second data, thereby improving the efficiency of obtaining the second data. When directly using the interleaving result as the second data, the second data does not include the second codeword. In the embodiments of the present application, the second codeword can be a codeword obtained by performing FEC encoding on the interleaving result according to the second FEC code. For the content of obtaining the second codeword, please refer to the content in the following method A1, which will not be elaborated here for the time being. When the second data does not include the second codeword, it means that this method can be applied to non-cascaded coding scenarios.

[0105] Exemplarily, when obtaining the interleaving result through the above-mentioned first method, the interleaving result includes n first bit groups output by polling multiple first delay units n times. When this method is applied to a cascaded coding scenario, the second data can be obtained through the following method A1.

[0106] Method A1: Encode the n first bit groups output by polling multiple first delay units n times according to the second FEC code to obtain m second codewords. The number of bits corresponding to the n first bit groups is equal to the number of bits included in the information bits of the m second FEC codewords. Both m and n are positive integers, and m is less than or equal to n; obtain the second data according to the m second codewords.

[0107] When the second data includes the second codeword, the identification information includes the codeword boundary information of the second codeword. The second codeword includes information bits and parity bits. The codeword boundary information of the second codeword can include the demarcation position between the parity bits of the previous second codeword and the information bits of the next second codeword among two adjacent second codewords.

[0108] The embodiments of the present application do not limit the second FEC code, and the second FEC code can be determined according to experience or actual requirements. For example, when a certain FEC code is used as the second FEC code, the number of bits corresponding to one first bit group is equal to the number of bits included in the information bits of a codeword of the second FEC code, that is, n first bit groups are encoded to obtain n second codewords, and m is equal to n. Another example is that when a certain FEC code is used as the second FEC codeword, the number of bits corresponding to multiple first bit groups is equal to the number of bits included in the information bits of a codeword of the second FEC code, that is, n first bit groups are encoded to obtain m second codewords, and m is less than n.

[0109] The number of bits included in n first bit groups depends on the number of delay units included in the convolutional interleaver and the number of bits included in the symbol. The number of bits included in the symbol can be determined according to the delay length corresponding to the delay block of the delay unit. That is to say, the number of bits included in n first bit groups can be determined according to the structure of the convolutional interleaver. When the number of bits corresponding to n first bit groups is equal to the number of bits included in the information bits of m second FEC codewords, since the size relationship between m and n is relatively flexible, it means that the adaptation relationship between the convolutional interleaver and the second FEC code is relatively flexible. When both m and n are greater than 2 and m and n are not equal, at least two of the codeword boundary information in the codeword boundary information of multiple second codewords are different. When the method provided by the embodiments of the present application obtains the second data including the identification information according to the interleaving result, additional data can be inserted on the basis of the interleaving result for use as the identification information, and the starting interleaving position is indicated by this identification information.

[0110] Still taking Figure 4 the schematic diagram as an example, if n = 3 and m = 2, that is, 3 first bit groups are encoded to obtain 2 second codewords. In this case, there are two types of codeword boundary information for the second codewords. Then, additional data can be inserted on the basis of the obtained interleaving result for use as the identification information to indicate the starting interleaving position, so that the starting interleaving position can be determined based on the inserted identification information during deinterleaving, avoiding the problem that correct deinterleaving cannot be performed due to different codeword boundary information, thereby ensuring the accuracy of deinterleaving.

[0111] Figure 9 It is a schematic diagram of a process for obtaining the second data provided by the embodiments of the present application. In Figure 9 the process of obtaining the second data shown, m is equal to n, that is, n bit groups are encoded according to the second FEC code to obtain n second codewords, and the number of bits corresponding to one first bit group is equal to the number of bits included in the information bits of a codeword of the second FEC code. Figure 9 The process of convolutional interleaving of cwA to cwD shown in Figure 3The convolutional interleaving process shown in (2) therein has the same principle and will not be elaborated here.

[0112] Figure 10 is a schematic diagram of another process for obtaining the second data provided by an embodiment of the present application. In Figure 10 In the process of obtaining the second data shown, m is less than n, and the number of bits corresponding to the two first bit groups is equal to the number of bits included in the information bits of a codeword of a second FEC code. Figure 10 The process of convolutional interleaving cwA to cwD shown is the same as the Figure 3 The convolutional interleaving process shown in (2) therein has the same principle and will not be elaborated here.

[0113] Figure 9 and Figure 10 Both take the symbols included in cwA to cwD appearing continuously in one delay unit as an example for illustration. This method can also be applicable to the scenario where multiple symbols from one codeword appear continuously in one delay unit. Figure 11 is a schematic diagram of yet another process for obtaining the second data provided by an embodiment of the present application. Refer to Figure 11 , the first codeword includes 320 bits, that is, cwA to cwD all include 320 bits, and the information bits of the codeword of the second FEC code include 160 bits. Figure 11 In , convolutional interleaving is performed on the symbols included in cwA to cwD. The number of delay rows of the convolutional interleaver is equal to the number of first codewords, that is, the convolutional interleaver includes four delay rows. In Figure 11 , a represents the symbol included in cwA, b represents the symbol included in cwB, c represents the symbol included in cwC, and d represents the symbol included in cwD. When the symbols output by each column of the convolutional interleaver are used to obtain a second codeword encoded according to the second FEC code, each symbol included in cwA to cwD includes 40 bits, and the number of bits corresponding to the delay blocks included in each delay row is also 40 bits. Since one first codeword includes 320 bits, the difference quantity of the delay blocks included in each delay row is equal to (320 / 40) / 4 = 2. Thus, as Figure 11 shown, D represents a delay block. Delay row 0 can include 6 delay blocks, delay row 1 can include 4 delay blocks, delay row 2 can include 2 delay blocks, and delay row 3 can include 0 delay blocks.

[0114] Please continue to refer to Figure 11 , after convolutional interleaving the symbols included in multiple first codewords through the delay rows, the adjacent four output symbols all come from different first codewords. Thus, if a burst error of 160 bits appears in the second data, the bits included in the burst error will be dispersed into four symbols, and the four symbols come from different first codewords, thereby realizing the dispersion of the burst error. Furthermore, as Figure 11As shown, four symbols of a column output are used to obtain a codeword encoded by a second FEC codeword. That is, in Figure 11 four symbols output by polling four delayed rows once are encoded according to the second FEC code to obtain a second codeword.

[0115] By encoding n first bit groups according to the second FEC code, m second codewords are obtained. The receiving end can obtain the starting interleaving position by acquiring the codeword boundary information of the second codeword, and then perform convolutional deinterleaving according to the starting interleaving position, without inserting identification information for indicating the starting interleaving position. The method of additionally inserting identification information will increase the link transmission rate and the transmission bandwidth required for data transmission, resulting in higher data transmission costs. Moreover, since the method of additionally inserting identification information will increase the link transmission rate, for data transmission scenarios with limited bandwidth or PLL frequency points, the applicability of the method of additionally inserting identification information is poor. In method A1, since no additional identification information needs to be inserted, the codeword boundary information of the second codeword can be directly used as identification information. This method has a lower data transmission cost and higher applicability for data transmission scenarios with limited bandwidth or PLL frequency points.

[0116] When the method provided in the embodiment of the present application is applied to a non-cascaded coding scenario, the second data can be obtained through the following method A2.

[0117] Method A2: According to the format of the reference data frame, k target data frames are obtained based on n first bit groups output by polling multiple first delay units n times. The target data frame includes frame synchronization information, and the frame synchronization information is used as identification information. The number of bits corresponding to the n first bit groups is less than or equal to the number of bits included in the k target data frames. Both k and n are positive integers, and k is less than or equal to n; the second data is obtained according to the k target data frames.

[0118] That is, in a non-cascaded coding scenario, the second data can be obtained by obtaining k target data frames according to n first bit groups. In this case, the second data does not include the second codeword. Exemplarily, the frame synchronization information includes, but is not limited to, a frame alignment word in coherent transmission or other data for frame synchronization. The format of the reference data frame can be determined according to the frame format required for data transmission, and the embodiment of the present application does not limit this. Exemplarily, the k target data frames are used as the second data.

[0119] Figure 12 is a schematic diagram of another process of obtaining the second data provided by the embodiment of the present application. In Figure 12 the process of obtaining the second data shown, k is less than n, and four first bit groups are used to obtain one target data frame. Figure 12The process of convolutional interleaving for cwA to cwD shown is the same as the principle of the convolutional interleaving process shown in Figure 3 , and will not be elaborated here.

[0120] S803. The first module transmits the second data to the second module.

[0121] Embodiments of the present application do not limit the manner in which the first module transmits the second data to the second module. For example, the first module transmits the second data to the second module through a channel.

[0122] In the method provided by the embodiments of the present application, by performing convolutional interleaving on the symbols included in multiple first codewords, when burst errors occur in the subsequent second data, the burst errors will be dispersed into multiple symbols, thereby reducing the BER of the second data after error correction. Furthermore, when the second data includes a second codeword, the identification information is the codeword boundary information of the second codeword, and there is no need to additionally insert identification information for indicating the starting interleaving position, so the data transmission cost is relatively low, the applicability to data transmission scenarios with limited bandwidth or PLL frequency points is relatively high, and the implementation complexity of the data transmission system for executing this method is relatively low.

[0123] The above takes the first module side as an example to illustrate the data transmission method provided by the embodiments of the present application. Next, the data transmission method will be described taking the second module side as an example. As Figure 8 shown, the data transmission method includes S804 to S806.

[0124] S804. The second module receives the second data including identification information transmitted by the first module.

[0125] Embodiments of the present application do not limit the manner in which the second module receives the second data, and it is only necessary to be adapted to the manner in which the first module transmits the second data to the second module. Combining the content in S802 above, it can be known that the second data is obtained according to the interleaving result obtained by performing convolutional interleaving on the symbols included in multiple first codewords, and the first codeword is the codeword obtained by encoding the first data using the first FEC code. When the second data includes a second codeword, the identification information includes the codeword boundary information of the second codeword.

[0126] S805. The second module obtains the starting interleaving position of the convolutional interleaving of the symbols included in multiple first codewords and the data to be de-interleaved in the second data according to the identification information.

[0127] According to different situations of the second data, the second module can perform the operation of obtaining the starting interleaving position of the convolutional interleaving of the symbols included in multiple first codewords and the data to be de-interleaved in the second data according to the identification information in different ways.

[0128] Case B1, the second data includes a second codeword.

[0129] When the second data includes a second codeword, the second module obtains at least one second codeword included in the second data according to the codeword boundary information of the second codeword; obtains the starting position of at least one second codeword, and uses the starting position as the starting interleaving position for convolutional interleaving of the symbols included in the multiple first codewords; decodes at least one second codeword to obtain the data to be de-interleaved.

[0130] Exemplarily, the codeword boundary information of the second codeword can be obtained by means of codeword self-synchronization, so that the second module can obtain at least one second codeword included in the second data according to the boundary information of the second codeword. For example, the process by which the second module obtains the codeword boundary information of the second codeword by means of codeword self-synchronization includes: obtaining the codewords of the second FEC code locally, and identifying the codeword boundary information of the second codeword according to the codewords of the second FEC code locally. When the second data includes an alignment marker (AM), the position of the AM is associated with the position of the second codeword, so that the second module can obtain the codeword boundary information of the second codeword by determining the position of the AM in the second data.

[0131] Since the second codeword is obtained by encoding n first bit groups according to the second FEC code, and the n first bit groups are obtained from the starting interleaving position for convolutional interleaving of the symbols included in the multiple first codewords, the starting position of the second codeword can be used as the starting interleaving position for convolutional interleaving of the symbols included in the multiple first codewords. The second module can decode the second codeword in a manner corresponding to the manner of encoding the second codeword, that is, the second module can decode at least one second codeword according to the second FEC code to obtain the data to be de-interleaved.

[0132] Case B2, the second data does not include a second codeword.

[0133] When the second data does not include a second codeword, if the second data includes at least one target data frame and the identification information is frame synchronization information, the second module can perform the operation of obtaining the starting interleaving position for convolutional interleaving of the symbols included in the multiple first codewords and the data to be de-interleaved in the second data by the following method C1.

[0134] Method C1: Obtain at least one target data frame included in the second data according to the frame synchronization information; obtain the starting position of the frame data of at least one target data frame, and use the starting position as the starting interleaving position for convolutional interleaving of the symbols included in the multiple first codewords; use the frame data included in at least one target data frame as the data to be de-interleaved.

[0135] For example, the second module divides the second data according to the frame synchronization information to obtain at least one target data frame included in the second data, and the number of target data frames may be k. Further, after obtaining at least one target data frame, the starting position of the frame data of each target data frame can be obtained. Since the k target data frames are obtained based on n first bit groups, and the n first bit groups are obtained from the starting interleaving position of the symbols included in multiple first codewords after convolutional interleaving, the starting position of the frame data of the target data frame can be used as the starting interleaving position of the symbols included in multiple first codewords for convolutional interleaving.

[0136] If the second data does not include a second codeword nor a target data frame, the identification information is used to indicate the starting interleaving position of the symbols included in multiple first codewords; the second module can perform the operation of obtaining the starting interleaving position of the symbols included in multiple first codewords and the data to be deinterleaved in the second data according to the following method C2.

[0137] Method C2: Obtain the starting interleaving position of the symbols included in multiple first codewords indicated by the identification information; use the data in the second data located at the starting interleaving position and the data after the starting interleaving position as the data to be deinterleaved.

[0138] That is to say, the identification information can directly indicate the starting interleaving position of the symbols included in multiple first codewords, and then the second module uses the data in the second data located at the starting interleaving position and the data after the starting interleaving position as the data to be deinterleaved.

[0139] S806, the second module performs convolutional deinterleaving on the data to be deinterleaved based on the starting interleaving position to obtain multiple first codewords.

[0140] Exemplarily, in the case of obtaining the data to be deinterleaved by using the method in the above case B1 or method C1 in case B2, the data to be deinterleaved includes multiple third bit groups, and one third bit group includes the symbols of the first codeword output by polling multiple first delay units of the convolutional interleaver once. Since there may be bit errors during data transmission, there may be bit errors in the third bit group.

[0141] In the case where the data to be de-interleaved includes a plurality of third bit groups, performing convolutional de-interleaving on the data to be de-interleaved starting from the starting interleaving position to obtain a plurality of first codewords may include: obtaining the starting de-interleaving position corresponding to the starting interleaving position in the plurality of second delay units of the convolutional de-interleaver; inputting the plurality of third bit groups into the plurality of second delay units from the starting de-interleaving position, and performing convolutional de-interleaving on the symbols included in the plurality of third bit groups polled by the plurality of second delay units; obtaining the symbols included in the plurality of first codewords polled and output by the plurality of second delay units, and obtaining the plurality of first codewords according to the symbols included in the plurality of first codewords.

[0142] The starting interleaving position may be the same as the starting de-interleaving position. After the second module obtains the starting interleaving position, it may use the starting interleaving position as the starting de-interleaving position. Similar to the starting de-interleaving position that may be located in any one of the plurality of first delay units, the starting de-interleaving position may be located in any one of the plurality of second delay units. After obtaining the symbols included in the plurality of first codewords, each first codeword may be obtained based on the symbols included in each first codeword.

[0143] Exemplarily, in the case of obtaining the data to be de-interleaved by using the method C2 in the above case B2, the data to be de-interleaved includes a plurality of fourth bit groups. At least one fourth bit group includes the symbols of the first codeword output by polling the plurality of first delay units of the convolutional interleaver once, or at least one fourth bit group includes the identification information and symbols output by polling the plurality of first delay units once. Since errors may occur during data transmission, there may be errors in the fourth bit groups.

[0144] In the case where the data to be de-interleaved includes a plurality of fourth bit groups, performing convolutional de-interleaving on the data to be de-interleaved starting from the starting interleaving position to obtain a plurality of first codewords may include: obtaining the starting de-interleaving position corresponding to the starting interleaving position in the plurality of second delay units of the convolutional de-interleaver, inputting the plurality of fourth bit groups into the plurality of second delay units from the starting de-interleaving position, and performing convolutional de-interleaving on the symbols included in the plurality of fourth bit groups polled, or the identification information and symbols included in the plurality of fourth bit groups; obtaining the symbols and identification information included in the plurality of first codewords polled and output by the plurality of second delay units, and obtaining the plurality of first codewords according to the symbols included in the plurality of first codewords.

[0145] In this case, the method by which the second module obtains the content of the starting de-interleaving position, performs convolutional de-interleaving, and obtains the plurality of first codewords is the same as the relevant content principle in the above case where the data to be de-interleaved includes a plurality of third bit groups, and will not be elaborated here.

[0146] Exemplarily, multiple second delay units of the convolutional deinterleaver output symbols included in multiple first codewords in the form of a second data stream, and the transmission rate of the second data stream is greater than or equal to 100 Gbps. Of course, the transmission rate of the second data stream can also be a higher rate, for example, the transmission rate of the second data stream is greater than or equal to 200 Gbps. In the case where the second data is convolutionally interleaved based on the identification information and the symbols of the multiple first codewords, the second data stream may further include identification information. In this case, multiple second delay units of the convolutional deinterleaver output the identification information and the symbols included in the multiple first codewords in the form of a second data stream. Exemplarily, multiple second delay units of the convolutional deinterleaver output the second data stream through at least one channel of the AUI. The multiple second delay units can input the second data stream into at least one channel of the AUI in a polling manner, so as to output the second data stream through at least one channel of the AUI.

[0147] In the method provided in the embodiments of the present application, since the second data is obtained by convolutionally interleaving the symbols included in the multiple first codewords, when a burst error occurs in the second data, the burst error will be dispersed into multiple symbols, thereby reducing the BER of the second data after error correction. Furthermore, in the case where the second data includes a second codeword, the identification information is the codeword boundary information of the second codeword, and there is no need to additionally insert identification information for indicating the starting interleaving position in the second data, so that the data transmission cost is low, the applicability to data transmission scenarios with limited bandwidth or PLL frequency points is high, and the implementation complexity of the data transmission system for executing this method is low.

[0148] The embodiments of the present application further provide a data transmission device. Figure 13 It is a schematic structural diagram of a data transmission device provided by the embodiments of the present application. Based on Figure 13 the multiple units shown, Figure 13 the data transmission device shown can perform all or part of the operations executed by the first module. It should be understood that the device may include more additional units than the units shown or omit some of the units shown, and the embodiments of the present application do not limit this. As Figure 13 shown, the device includes:

[0149] An interleaving unit 1301, configured to perform convolutional interleaving on symbols included in multiple obtained first codewords to obtain an interleaving result, where the first codeword is a codeword obtained by encoding first data using a first FEC code;

[0150] An obtaining unit 1302, configured to obtain second data including identification information according to the interleaving result, where in the case where the second data includes a second codeword, the identification information includes the codeword boundary information of the second codeword;

[0151] A transmission unit 1303, configured to transmit second data to a second module.

[0152] In a possible implementation, an interleaving unit 1301 is configured to input symbols included in a plurality of first codewords into a plurality of first delay units of a convolutional interleaver, perform convolutional interleaving on the symbols included in the polled plurality of first codewords through the plurality of first delay units, to obtain a plurality of first bit groups polled and output by the plurality of first delay units, where one first bit group includes symbols output by the plurality of first delay units in one poll; and use the plurality of first bit groups polled and output by the plurality of first delay units as an interleaving result.

[0153] In a possible implementation, the interleaving result includes n first bit groups polled and output by the plurality of first delay units in n polls. An obtaining unit 1302 is configured to encode the n first bit groups polled and output by the plurality of first delay units in n polls according to a second FEC code, to obtain m second codewords, where the number of bits corresponding to the n first bit groups is equal to the number of bits included in the information bits of the codewords of the m second FEC codes, and both m and n are positive integers, and m is less than or equal to n; and obtain second data according to the m second codewords.

[0154] In a possible implementation, the second data does not include the second codewords. The interleaving result includes n first bit groups polled and output by the plurality of first delay units in n polls. An obtaining unit 1302 is configured to obtain k target data frames based on the n first bit groups polled and output by the plurality of first delay units in n polls according to the format of a reference data frame, where the target data frames include frame synchronization information, and the frame synchronization information is used as identification information, and the number of bits corresponding to the n first bit groups is less than or equal to the number of bits included in the k target data frames, and both k and n are positive integers, and k is less than or equal to n; and obtain second data according to the k target data frames.

[0155] In a possible implementation, the second data does not include the second codewords. An interleaving unit 1301 is configured to input at least one identification information and symbols included in a plurality of first codewords into a plurality of first delay units of a convolutional interleaver, perform convolutional interleaving on the polled at least one identification information and symbols included in the plurality of first codewords through the plurality of first delay units, to obtain a plurality of second bit groups polled and output by the plurality of first delay units, where at least one second bit group includes symbols output by the plurality of first delay units in one poll, or at least one second bit group includes the identification information and symbols output by the plurality of first delay units in one poll, and the identification information is used to indicate a starting interleaving position for performing convolutional interleaving on the symbols included in the plurality of first codewords; and use the plurality of second bit groups polled and output by the plurality of first delay units as an interleaving result.

[0156] In a possible implementation, the starting interleaving position for the convolutional interleaving of the symbols included in multiple first codewords is located in any one of the multiple first delay units.

[0157] In a possible implementation, the symbols included in multiple first codewords are input into the multiple first delay units of the convolutional interleaver in the form of a first data stream, and the transmission rate of the first data stream is greater than or equal to 100 Gbps.

[0158] In a possible implementation, the first data stream is transmitted to the multiple first delay units of the convolutional interleaver through at least one channel of the AUI.

[0159] In the apparatus provided by the embodiments of the present application, by performing convolutional interleaving on the symbols included in multiple first codewords, when burst errors occur in the subsequent second data, the burst errors will be dispersed into multiple symbols, thereby reducing the BER of the second data after error correction. Furthermore, when the second data includes a second codeword, the identification information is the codeword boundary information of the second codeword, and there is no need to additionally insert identification information for indicating the starting interleaving position, so the data transmission cost is relatively low, the applicability to data transmission scenarios with limited bandwidth or PLL frequency points is relatively high, and the implementation complexity of the data transmission system including this apparatus is relatively low.

[0160] Figure 14 It is a schematic structural diagram of another data transmission apparatus provided by the embodiments of the present application. Based on Figure 14 the multiple units shown, the Figure 14 data transmission apparatus shown can perform all or part of the operations performed by the second module. It should be understood that the apparatus may include more additional units than those shown or omit some of the units shown, and the embodiments of the present application do not limit this. As Figure 14 shown, the apparatus includes:

[0161] An acquisition unit 1401, configured to receive second data including identification information transmitted by the first module, where the second data is obtained according to an interleaving result obtained by performing convolutional interleaving on the symbols included in multiple first codewords, and the first codewords are codewords obtained by encoding first data using a first FEC code; wherein, when the second data includes a second codeword, the identification information includes the codeword boundary information of the second codeword;

[0162] The acquisition unit 1401 is further configured to obtain the starting interleaving position for the convolutional interleaving of the symbols included in multiple first codewords and the data to be deinterleaved in the second data according to the identification information;

[0163] A deinterleaving unit 1402, configured to perform convolutional deinterleaving on the data to be deinterleaved based on the starting interleaving position to obtain multiple first codewords.

[0164] In a possible implementation, an obtaining unit 1401 is configured to obtain at least one second codeword included in second data according to the codeword boundary information of the second codeword; obtain the starting position of at least one second codeword, and use the starting position as the starting interleaving position for convolution interleaving of symbols included in a plurality of first codewords; decode at least one second codeword to obtain data to be deinterleaved.

[0165] In a possible implementation, when the second data does not include a second codeword, the identification information is frame synchronization information, and an obtaining unit 1401 is configured to obtain at least one target data frame included in the second data according to the frame synchronization information; obtain the starting position of the frame data of at least one target data frame, and use the starting position as the starting interleaving position for convolution interleaving of symbols included in a plurality of first codewords; use the frame data included in at least one target data frame as the data to be deinterleaved.

[0166] In a possible implementation, the data to be deinterleaved includes a plurality of third bit groups, and one third bit group includes symbols of a first codeword output by polling a plurality of first delay units of a convolutional interleaver once; a deinterleaving unit 1402 is configured to obtain the starting deinterleaving position corresponding to the starting interleaving position among a plurality of second delay units of a convolutional deinterleaver; input the plurality of third bit groups into the plurality of second delay units from the starting deinterleaving position, and perform convolutional deinterleaving on the symbols included in the plurality of third bit groups polled by the plurality of second delay units; obtain the symbols included in a plurality of first codewords output by polling the plurality of second delay units, and obtain a plurality of first codewords according to the symbols included in the plurality of first codewords.

[0167] In a possible implementation, when the second data does not include a second codeword, the identification information is used to indicate the starting interleaving position for convolution interleaving of symbols included in a plurality of first codewords; an obtaining unit 1401 is configured to obtain the starting interleaving position for convolution interleaving of symbols included in a plurality of first codewords indicated by the identification information; use the data in the second data located at the starting interleaving position and the data after the starting interleaving position as the data to be deinterleaved.

[0168] In a possible implementation, the data to be deinterleaved includes a plurality of fourth bit groups, and at least one fourth bit group includes symbols of a first codeword output by polling a plurality of first delay units of a convolutional interleaver once, or at least one fourth bit group includes identification information and symbols output by polling a plurality of first delay units once; the deinterleaving unit 1402 is configured to obtain a starting deinterleaving position corresponding to a starting interleaving position among a plurality of second delay units of a convolutional deinterleaver; input the plurality of fourth bit groups into the plurality of second delay units from the starting deinterleaving position, and perform convolutional deinterleaving on the symbols included in the plurality of fourth bit groups polled, or the identification information and symbols included in the plurality of fourth bit groups, by the plurality of second delay units; obtain the symbols and identification information included in a plurality of first codewords output by polling the plurality of second delay units, and obtain a plurality of first codewords according to the symbols included in the plurality of first codewords.

[0169] In a possible implementation, the starting deinterleaving position is located in any one of the plurality of second delay units.

[0170] In a possible implementation, the plurality of second delay units of the convolutional deinterleaver output the symbols included in a plurality of first codewords in the form of a second data stream, and the transmission rate of the second data stream is greater than or equal to 100 Gbps.

[0171] In a possible implementation, the plurality of second delay units of the convolutional deinterleaver output the second data stream through at least one channel of an AUI.

[0172] In the device provided in the embodiments of the present application, since the second data is obtained by performing convolutional interleaving on the symbols included in a plurality of first codewords, when a burst error occurs in the second data, the burst error will be dispersed into a plurality of symbols, thereby reducing the BER of the second data after error correction. Furthermore, when the second data includes a second codeword, the identification information is the codeword boundary information of the second codeword, and there is no need to additionally insert identification information for indicating the starting interleaving position in the second data, so the data transmission cost is relatively low, the applicability to data transmission scenarios with limited bandwidth or PLL frequency points is relatively high, and the implementation complexity of the data transmission system including the device is relatively low.

[0173] It should be understood that when the above Figures 13 - 14 provided device implements its functions, only the above division of each functional unit is used for illustration. In actual applications, the above functions can be allocated to different functional units according to needs, that is, the internal structure of the device is divided into different functional units to complete all or part of the functions described above. In addition, the device provided in the above embodiments and the method embodiments belong to the same concept, and the specific implementation process is detailed in the method embodiments, which will not be repeated here.

[0174] See Figure 15, Figure 15 It is a schematic structural diagram of a computer system provided by an embodiment of the present application. Exemplarily, as Figure 15 shown, the computer system is the computer system 2000. The computer system 2000 may be a network device, a routing device, or a switching device. Figure 15 The computer system 2000 shown is used to perform the operations involved in the first module or the operations involved in the second module in the data transmission method shown above. Figure 8 The computer system 2000 is, for example, a server, etc. The computer system 2000 may be implemented by a general bus architecture.

[0175] As Figure 15 shown, the computer system 2000 includes at least one processor 2001, a memory 2003, and at least one communication interface 2004.

[0176] The processor 2001 is, for example, a central processing unit (CPU), a digital signal processor (DSP), a network processor (NP), a graphics processing unit (GPU), a neural-network processing unit (NPU), a data processing unit (DPU), a microprocessor, or one or more integrated circuits for implementing the solution of the present application. For example, the processor 2001 includes an application-specific integrated circuit (ASIC), a programmable logic device (PLD), or other programmable logic devices, transistor logic devices, hardware components, or any combination thereof. The PLD is, for example, a complex programmable logic device (CPLD), a field-programmable gate array (FPGA), a generic array logic (GAL), or any combination thereof. It can implement or execute various logic blocks, modules, and circuits described in connection with the disclosed content of the embodiments of the present application. The processor may also be a combination for implementing computing functions, such as a combination of one or more microprocessors, a combination of a DSP and a microprocessor, and so on.

[0177] Optionally, computer system 2000 further includes a bus. The bus is used to transfer information between the components of computer system 2000. The bus can be a Peripheral Component Interconnect (PCI) bus or an Extended Industry Standard Architecture (EISA) bus, etc. The bus can be divided into an address bus, a data bus, a control bus, etc. For ease of representation, Figure 15 it is only represented by a thick line in Figure 15 , but it does not mean that there is only one bus or one type of bus.

[0178] Memory 2003 is, for example, a read-only memory (ROM) or other type of static storage device that can store static information and instructions, or a random access memory (RAM) or other type of dynamic storage device that can store information and instructions, or an electrically erasable programmable read-only memory (EEPROM), a compact disc read-only memory (CD-ROM) or other optical disc storage, optical disc storage (including compact discs, laser discs, optical discs, digital versatile discs, Blu-ray discs, etc.), magnetic disk storage media or other magnetic storage devices, or any other medium that can be used to carry or store the desired program code in the form of instructions or data structures and can be accessed by a computer, but is not limited thereto. Memory 2003 exists independently, for example, and is connected to processor 2001 through a bus. Memory 2003 can also be integrated with processor 2001.

[0179] The communication interface 2004 uses any transceiver-like device for communicating with other devices or communication networks, which can be an Ethernet, a radio access network (RAN), a wireless local area network (WLAN), etc. The communication interface 2004 can include a wired communication interface and can also include a wireless communication interface. Specifically, the communication interface 2004 can be an Ethernet interface, a fast Ethernet (FE) interface, a gigabit Ethernet (GE) interface, an asynchronous transfer mode (ATM) interface, a WLAN interface, a cellular network communication interface, or a combination thereof. The Ethernet interface can be an optical interface, an electrical interface, or a combination thereof. In the embodiment of the present application, the communication interface 2004 can be used for the computer system 2000 to communicate with other devices.

[0180] In a specific implementation, as an embodiment, the processor 2001 can include one or more CPUs, such as Figure 15 CPU0 and CPU1 shown in []. Each of these processors can be a single-CPU processor or a multi-CPU processor. Here, the processor can refer to one or more devices, circuits, and / or processing cores for processing data (such as computer program instructions).

[0181] In a specific implementation, as an embodiment, the computer system 2000 can include multiple processors, such as Figure 15 the processor 2001 and the processor 2005 shown in []. Each of these processors can be a single-CPU processor or a multi-CPU processor. Here, the processor can refer to one or more devices, circuits, and / or processing cores for processing data (such as computer program instructions).

[0182] In a specific implementation, as an embodiment, the computer system 2000 may further include an output device and an input device. The output device communicates with the processor 2001 and can display information in various ways. For example, the output device may be a liquid crystal display (LCD), a light emitting diode (LED) display device, a cathode ray tube (CRT) display device, or a projector, etc. The input device communicates with the processor 2001 and can receive user input in various ways. For example, the input device may be a mouse, a keyboard, a touch screen device, or a sensing device, etc.

[0183] In some embodiments, the memory 2003 is used to store the program code 2010 for executing the solution of this application, and the processor 2001 can execute the program code 2010 stored in the memory 2003. The program code 2010 may include one or more software modules. Optionally, the processor 2001 itself can also store the program code or instructions for executing the solution of this application.

[0184] In a specific embodiment, the computer system 2000 of the embodiment of this application may include the first module in each of the above method embodiments. The processor 2001 in the computer system 2000 reads the program code 2010 in the memory 2003 or the program code or instructions stored by the processor 2001 itself, so that Figure 15 the computer system 2000 shown can perform all or part of the operations performed by the first module.

[0185] In a specific embodiment, the computer system 2000 of the embodiment of this application may include the second module in each of the above method embodiments. The processor 2001 in the computer system 2000 reads the program code 2010 in the memory 2003 or the program code or instructions stored by the processor 2001 itself, so that Figure 15 the computer system 2000 shown can perform all or part of the operations performed by the second module.

[0186] The computer system 2000 may also correspond to the above Figure 13 、 14 shown devices, Figure 13 、 14 Each functional unit in the shown devices is implemented by the software of the computer system 2000. In other words, Figure 13 、 14 The functional units included in the shown devices are generated after the processor 2001 of the computer system 2000 reads the program code 2010 stored in the memory 2003.

[0187] Among them,Figure 8 Each step of the data transmission method shown is completed by the integrated logic circuit of the hardware in the processor of the computer system 2000 or the instructions in the form of software. The steps of the method disclosed in combination with the embodiments of the present application can be directly embodied as being executed by the hardware processor, or executed by the combination of the hardware and software modules in the processor. The software module can be located in a mature storage medium in the art such as random access memory, flash memory, read-only memory, programmable read-only memory, or electrically erasable programmable memory, register, etc. This storage medium is located in the memory, and the processor reads the information in the memory and combines its hardware to complete the steps of the above method. To avoid repetition, it will not be described in detail here.

[0188] Figure 16 is a schematic structural diagram of another computer system provided by the embodiments of the present application. This computer system is used to execute the above Figure 8 operations involved in the first module or the operations involved in the second module in the shown data transmission method. Exemplarily, this computer system is a server, and the server may vary greatly due to different configurations or performances. This computer system may include one or more processors 1601 and one or more memories 1602. Among them, at least one computer program is stored in the one or more memories 1602, and the at least one computer program is loaded and executed by the one or more processors 1601. Exemplarily, the processor 1601 is a CPU. Of course, this computer system may also have components such as a wired or wireless network interface, a keyboard, and an input / output interface for input / output. This computer system may also include other components for implementing the functions of the device, which will not be elaborated here.

[0189] The embodiments of the present application also provide a computer system. This computer system includes a processor, and the processor includes a first module or a second module. The processor is used to call and run the instructions stored in the memory from the memory; when the processor includes the first module, this computer system implements the data transmission method executed by the first module above. When the processor includes the second module, this computer system implements the data transmission method executed by the second module above.

[0190] In a possible implementation manner, this computer system further includes: an input interface, an output interface, and the above-mentioned memory. The input interface, the output interface, the processor, and the memory are connected through an internal connection path.

[0191] The embodiments of the present application also provide a data transmission system. This data transmission system includes a first module and a second module. The first module is used to execute Figure 8 the method executed by the first module shown, and the second module is used to execute Figure 8The method performed by the second module shown. The functions of the first module and the second data module of the data transmission system can be referred to the relevant descriptions shown above Figure 8 and will not be elaborated here one by one.

[0192] The embodiment of the present application further provides a communication device, which includes: a transceiver, a memory, and a processor. Among them, the transceiver, the memory, and the processor communicate with each other through an internal connection path. The memory is used to store instructions, and the processor is used to execute the instructions stored in the memory to control the transceiver to send and receive signals. The processor includes a first module or a second module. When the processor includes the first module, when the processor executes the instructions stored in the memory, the processor is caused to execute the data transmission method performed by the first module. When the processor includes the second module, when the processor executes the instructions stored in the memory, the processor is caused to execute the data transmission method performed by the second module.

[0193] It should be understood that the above-mentioned processor can be a CPU, or other general-purpose processors, DSPs, ASICs, FPGAs, or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. The general-purpose processor can be a microprocessor or any conventional processor, etc. It is worth noting that the processor can be a processor that supports the advanced RISC machines (ARM) architecture.

[0194] Furthermore, in an optional embodiment, the above-mentioned memory may include a read-only memory and a random access memory, and provide instructions and data to the processor. The memory may also include a non-volatile random access memory. For example, the memory may also store information about the device type.

[0195] The memory may be a volatile memory or a non-volatile memory, or may include both volatile and non-volatile memories. Among them, the non-volatile memory may be a ROM, a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), or a flash memory. The volatile memory may be a RAM, which is used as an external cache. By way of example but not limitation, many forms of RAM are available. For example, static random access memory (SRAM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), double data rate synchronous dynamic random access memory (DDR SDRAM), enhanced synchronous dynamic random access memory (ESDRAM), synchlink dynamic random access memory (SLDRAM), and direct rambus random access memory (DR RAM).

[0196] An embodiment of the present application further provides a computer-readable storage medium, in which at least one program instruction or code is stored. The program instruction or code is executed by a computer, and the computer includes a first module or a second module. When the computer includes the first module, when the program instruction or code is executed by the computer, the computer is caused to implement the data transmission method executed by the first module. When the computer includes the second module, when the program instruction or code is executed by the computer, the computer is caused to implement the data transmission method executed by the second module.

[0197] An embodiment of the present application further provides a computer program product, which includes: computer program instructions or code. The computer program instructions or code are run by a computer, and the computer includes a first module or a second module. When the computer includes the first module, when the computer program instructions or code are run by the computer, the computer is caused to execute the data transmission method executed by the first module. When the computer includes the second module, when the computer program instructions or code are run by the computer, the computer is caused to execute the data transmission method executed by the second module.

[0198] An embodiment of the present application further provides a chip, which includes a processor. The processor includes a first module or a second module, and the processor is configured to run program instructions or code. When the processor includes the first module, a device including the chip executes a data transmission method performed by the first module. When the processor includes the second module, a device including the chip executes a data transmission method performed by the second module.

[0199] Exemplarily, the chip further includes: an input interface, an output interface, and a memory. The input interface, the output interface, the processor, and the memory are connected through an internal connection path, and the memory stores the above-mentioned program instructions or code.

[0200] In the above embodiments, it can be implemented in whole or in part by software, hardware, firmware, or any combination thereof. When implemented using software, it can be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, the processes or functions according to the present application are generated in whole or in part. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable devices. The computer instructions can be stored in a computer-readable storage medium, or transmitted from one computer-readable storage medium to another computer-readable storage medium. For example, the computer instructions can be transmitted from one website, computer, server, or data center to another website, computer, server, or data center in a wired manner (such as coaxial cable, optical fiber, digital subscriber line) or a wireless manner (such as infrared, wireless, microwave, etc.). The computer-readable storage medium can be any available medium that can be accessed by a computer, or a data storage device such as a server or a data center that includes one or more integrated available media. The available medium can be a magnetic medium (such as a floppy disk, a hard disk, a magnetic tape), an optical medium (such as a digital video disc (DVD)), or a semiconductor medium (such as a solid state disk (SSD)), etc.

[0201] In the above embodiments, the unit of the transmission rate is Gb / s, which can also be abbreviated as G. For example, a rate of 400 Gb / s can also be abbreviated as 400G.

[0202] To clearly illustrate the interchangeability of hardware and software, the steps and components of each embodiment have been generally described according to functions in the above description. Whether these functions are executed in a hardware or software manner depends on the specific application and design constraints of the technical solution. Those of ordinary skill in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered to exceed the scope of the present application.

[0203] The computer program code for implementing the method of the embodiments of the present application can be written in one or more programming languages. These computer program codes can be provided to the processor of a general-purpose computer, a special-purpose computer, or other programmable data transmission devices, such that when the program codes are executed by the computer or other programmable data transmission devices, the functions / operations defined in the flowchart and / or block diagram are implemented. The program codes can be executed entirely on the computer, partially on the computer, as an independent software package, partially on the computer and partially on a remote computer, or entirely on a remote computer or server.

[0204] In the context of the embodiments of the present application, the computer program code or related data can be carried by any suitable carrier, so that the device, apparatus, or processor can execute the various processes and operations described above. Examples of the carrier include signals, computer-readable media, and the like. Examples of signals can include electrical, optical, radio, acoustic, or other forms of propagated signals, such as carrier waves, infrared signals, etc.

[0205] Those skilled in the art can clearly understand that for the convenience and brevity of description, the specific working processes of the systems, devices, and modules described above can refer to the corresponding processes in the foregoing method embodiments, and will not be elaborated herein.

[0206] In several embodiments provided by the present application, it should be understood that the disclosed systems, devices, and methods can be implemented in other ways. For example, the device embodiments described above are merely illustrative. For example, the division of the module is only a logical function division, and there can be other division methods in actual implementation. For example, multiple modules or components can be combined or integrated into another system, or some features can be ignored or not executed. In addition, the displayed or discussed mutual coupling or direct coupling or communication connection can be an indirect coupling or communication connection through some interfaces, devices, or modules, and can also be in the form of electrical, mechanical, or other connections.

[0207] The module described as a separate component may or may not be physically separated, and the component displayed as a module may or may not be a physical module, that is, it can be located in one place, or can be distributed to multiple network modules. Some or all of the modules can be selected according to actual needs to achieve the purpose of the solution of the embodiments of the present application.

[0208] In addition, the functional modules in the various embodiments of the present application can be integrated into one processing module, or each module can exist physically alone, or two or more modules can be integrated into one module. The above integrated modules can be implemented in the form of hardware or in the form of software functional modules.

[0209] In this application, terms such as "first" and "second" are used to distinguish identical or similar items with basically the same functions and effects. It should be understood that there is no logical or chronological dependence between "first", "second", and "nth", nor are the quantity and execution order limited. It should also be understood that although the following description uses terms such as first and second to describe various elements, these elements should not be limited by the terms. These terms are only used to distinguish one element from another. For example, without departing from the scope of various examples, the first module can be called the second module, and similarly, the second module can be called the first module.

[0210] It should also be understood that in various embodiments of this application, the magnitude of the serial numbers of each process does not mean the sequence of execution order. The execution order of each process should be determined by its function and internal logic, and should not impose any limitation on the implementation process of the embodiments of this application.

[0211] In this application, the meaning of the term "at least one" refers to one or more, and the meaning of the term "multiple" refers to two or more. For example, multiple code blocks refer to two or more code blocks. In this article, the terms "system" and "network" are often used interchangeably.

[0212] It should be understood that the terms used in the description of various examples in this article are only for describing specific examples and are not intended to be limiting. As used in the description of various examples and the appended claims, the singular forms "a", "an", and "the" are also intended to include the plural forms unless the context clearly indicates otherwise.

[0213] It should also be understood that the term "including" (also known as "includes", "including", "comprises", and / or "comprising") when used in this specification specifies the presence of the stated features, integers, steps, operations, elements, and / or components, but does not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or their groups.

[0214] It should also be understood that depending on the context, the phrase "if it is determined..." or "if [the stated condition or event] is detected" can be interpreted to mean "when it is determined..." or "in response to determining..." or "when [the stated condition or event] is detected" or "in response to detecting [the stated condition or event]".

[0215] It should be understood that determining B based on A does not mean determining B only based on A, and B can also be determined based on A and / or other information.

[0216] It should also be understood that the "one embodiment", "an embodiment", and "a possible implementation" mentioned throughout the specification mean that the specific features, structures, or characteristics related to the embodiment or implementation are included in at least one embodiment of the present application. Therefore, the "in one embodiment" or "in an embodiment", "a possible implementation" that appear throughout the specification do not necessarily refer to the same embodiment. In addition, these specific features, structures, or characteristics may be combined in one or more embodiments in any suitable manner.

Claims

1. A data transmission method, characterized in that, the method includes: Inputting the symbols included in multiple first codewords into multiple delay lines of a convolutional interleaver for convolutional interleaving, where the first codewords are encoded using a first forward error correction (FEC) code; Encoding the n first bit groups output by polling the multiple delay lines n times according to a second FEC code to obtain n second codewords, where the symbols output by polling the multiple delay lines once serve as one first bit group, and the number of bits corresponding to one first bit group is equal to the number of bits included in the information bits of a codeword of a second FEC code, and n is a positive integer.

2. The method according to claim 1, characterized in that, The multiple symbols output by each column of the convolutional interleaver are used to obtain one second codeword encoded according to the second FEC code.

3. The method according to claim 2, characterized in that, The symbol includes 40 bits.

4. The method according to claim 2, characterized in that, The adjacent symbols output by each column of the convolutional interleaver come from different first codewords.

5. The method according to any one of claims 1-4, characterized in that, The multiple delay lines of the convolutional interleaver include delay line 0, delay line 1, and delay line 2.

6. The method according to any one of claims 1-5, characterized in that, The number of bits corresponding to the delay blocks included in each delay line is 40 bits.

7. The method according to any one of claims 1-5, characterized in that, The starting position of the convolutional interleaving is the first delay line numbered in sequence among the multiple delay lines.

8. The method according to claim 6, characterized in that, The starting position of the convolutional interleaving is the first delay line numbered in sequence among the multiple delay lines.

9. The method according to any one of claims 1-8, characterized in that, The symbols included in the multiple first codewords are input into the multiple delay lines in the form of a first data stream, and the transmission rate of the first data stream is greater than or equal to 100 gigabits per second.

10. The method according to claim 9, characterized in that, The transmission rate of the first data stream is greater than or equal to 200 gigabits per second.

11. The method according to claim 9 or 10, characterized in that, The first data stream is transmitted to the multiple delay lines of the convolutional interleaver through at least one channel of a connection unit interface AUI.

12. The method according to any one of claims 1-11, characterized in that, The second FEC code is: Reed-Solomon (RS) code, Bose-Chaudhuri-Hocquenghem (BCH) code, extended BCH code, Hamming code, extended Hamming code, staircase code, low-density parity-check (LDPC) code, turbo code, or turbo product code (TPC).

13. The method according to any one of claims 1-12, characterized in that, The first FEC code is: Reed - Solomon (RS) code, Bose - Chaudhuri - Hocquenghem (BCH) code, extended BCH code, Hamming code, extended Hamming code, staircase code, Low - Density Parity - Check (LDPC) code, turbo code, or Turbo Product Code (TPC).

14. A data transmission device, characterized in that, it includes: a convolutional interleaver, which includes a plurality of delay lines, and is used for performing convolutional interleaving on symbols included in a plurality of first codewords input to the plurality of delay lines, where the first codewords are encoded using a first Forward Error Correction (FEC) code; a Forward Error Correction (FEC) encoder, which is used for encoding n first bit groups output by polling the plurality of delay lines n times according to a second FEC code to obtain n second codewords, where symbols output by polling the plurality of delay lines once serve as one first bit group, and the number of bits corresponding to one first bit group is equal to the number of bits included in the information bits of a codeword of the second FEC code, and n is a positive integer.

15. The data transmission device according to claim 14, characterized in that, a plurality of symbols output by each column of the convolutional interleaver are used to obtain a second codeword encoded according to the second FEC code.

16. The data transmission device according to claim 15, characterized in that, the symbol includes 40 bits.

17. The data transmission device according to claim 15, characterized in that, adjacent symbols output by each column of the convolutional interleaver come from different first codewords.

18. The data transmission device according to any one of claims 14 - 17, characterized in that, the plurality of delay lines of the convolutional interleaver include delay line 0, delay line 1, and delay line 2.

19. The data transmission device according to any one of claims 14 - 18, characterized in that, the number of bits corresponding to the delay blocks included in each delay line is 40 bits.

20. The data transmission device according to any one of claims 14 - 18, characterized in that, the starting position of the convolutional interleaving is the first delay line numbered in sequence among the plurality of delay lines.

21. The data transmission device according to claim 19, characterized in that, the starting position of the convolutional interleaving is the first delay line numbered in sequence among the plurality of delay lines.

22. The data transmission device according to any one of claims 14 - 18, characterized in that, symbols included in the plurality of first codewords are input to the plurality of delay lines in the form of a first data stream, and the transmission rate of the first data stream is greater than or equal to 100 gigabits per second.

23. The data transmission device according to claim 19, characterized in that, symbols included in the plurality of first codewords are input to the plurality of delay lines in the form of a first data stream, and the transmission rate of the first data stream is greater than or equal to 100 gigabits per second.

24. The data transmission device according to claim 20, characterized in that, symbols included in the plurality of first codewords are input to the plurality of delay lines in the form of a first data stream, and the transmission rate of the first data stream is greater than or equal to 100 gigabits per second.

25. The data transmission device according to claim 22, wherein, the transmission rate of the first data stream is greater than or equal to 200 gigabits per second.

26. The data transmission device according to any one of claims 23-25, wherein, the first data stream is transmitted to multiple delay lines of the convolutional interleaver through at least one channel of the connection unit interface AUI.

27. The data transmission device according to any one of claims 14-26, wherein, the second FEC code is: Reed-Solomon RS code, Bose-Chaudhuri-Hocquenghem BCH code, extended BCH code, Hamming code, extended Hamming code, staircase code, low density parity check LDPC code, turbo code or turbo product code TPC.

28. The data transmission device according to any one of claims 14-27, wherein, the first FEC code is: Reed-Solomon RS code, Bose-Chaudhuri-Hocquenghem BCH code, extended BCH code, Hamming code, extended Hamming code, staircase code, low density parity check LDPC code, turbo code or turbo product code TPC.

29. A communication system, wherein, the communication system includes a transmitting end device and a receiving end device, wherein, the transmitting end device includes a convolutional interleaver and an FEC encoder for performing the method according to any one of claims 1-13; the receiving end device includes a deinterleaver and an FEC decoder for deinterleaving and FEC decoding the data transmitted by the transmitting end device; wherein, the FEC encoder and the FEC decoder use the same FEC code.

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