Semiconductor structure and preparation method thereof

Abstract

The invention relates to a semiconductor structure and a preparation method thereof. The semiconductor structure comprises a substrate; the first conductive wires are located on the substrate and extend in the first direction, the multiple first conductive wires are arranged in the second direction, and the second direction intersects with the first direction; the storage array is positioned on the first conductive wire and is connected with the first conductive wire; the second conductive wire is connected with the storage array and extends in the third direction, and the third direction intersects with the first direction; a first interconnection structure on the first conductive line and electrically connected with the first conductive line; and a second interconnection structure on the second conductive line and connected with the second conductive line. The plurality of first conductive wires are arranged on the substrate, and the storage array is arranged on the first conductive wires, so that the first conductive wires are positioned below the storage array, the space above the storage array is not occupied, a larger preparation space is further reserved for the second conductive wires, and the difficulty of preparing the first conductive wires and the second conductive wires is reduced.

Description

Technical Field

[0001] The present disclosure relates to the field of integrated circuit technologies, and particularly to a semiconductor structure and a method for manufacturing the same. Background Art

[0002] In the prior art, a memory often includes structures such as word lines, bit lines, and transistors. The transistors are connected to logic circuits and the like through structures such as word lines and bit lines. As the size of the memory is scaled down, the interconnection space between the word lines and the bit lines and the logic circuits is limited.

[0003] Nowadays, how to improve the integration degree of the memory has become an urgent problem to be solved. Summary of the Invention

[0004] Based on this, it is necessary to provide a semiconductor structure and a method for manufacturing the same for the problem of how to improve the integration degree of the memory.

[0005] To achieve the above object, on the one hand, the present disclosure provides a semiconductor structure, including:

[0006] A substrate;

[0007] A first conductive line, located on the substrate, extending along a first direction, and a plurality of the first conductive lines are arranged along a second direction, the second direction intersecting the first direction;

[0008] A memory array, located on the first conductive line and connected to the first conductive line;

[0009] A second conductive line, connecting the memory array and extending along a third direction, the third direction intersecting the first direction;

[0010] A first interconnecting structure, extending along a vertical direction and located on the first conductive line, and electrically connected to the first conductive line;

[0011] A second interconnecting structure, extending along the vertical direction and located on the second conductive line, and connected to the second conductive line.

[0012] In some embodiments, the substrate includes a substrate and an isolation layer, the isolation layer being located between the substrate and the first conductive line; the first conductive line is located on the upper surface of the isolation layer, or the first conductive line is located in a trench of the isolation layer.

[0013] In some embodiments, the first interconnecting structure is located at an end of the first conductive line, and the semiconductor structure further includes:

[0014] The pad layer is located above the first interconnect structure and the second interconnect structure. The pad layer includes a first pad and a second pad. The first pad is electrically connected to the first interconnect structure, and the second pad is electrically connected to the second interconnect structure.

[0015] In some embodiments, the second conductive lines are arranged along the first direction and the vertical direction. The memory array includes memory cells located on opposite sides of each of the second conductive lines along the first direction. The memory cells located on opposite sides of the same second conductive line are arranged in a staggered manner in the third direction, and the memory cells located on opposite sides of the same second conductive line are connected to the first conductive line. The dimension of the first conductive line along the first direction is greater than the dimension of the memory array along the first direction. The first interconnect structures connected to adjacent first conductive lines are respectively located on opposite sides of the memory array along the first direction.

[0016] In some embodiments, the semiconductor structure further includes:

[0017] A first connection line that contacts the top end of the first interconnect structure and extends in a direction from the periphery of the memory array towards the inside of the memory array;

[0018] A third interconnect structure that extends along the vertical direction and is located between the first connection line and the first pad;

[0019] A second connection line that contacts the top end of the second interconnect structure and extends in a direction from the periphery of the memory array towards the inside of the memory array;

[0020] A fourth interconnect structure that extends along the vertical direction and is located between the second connection line and the second pad.

[0021] In some embodiments, the third interconnect structures located on different first connection lines are arranged in a staggered manner;

[0022] The first connection line extends along the first direction, and multiple first connection lines are arranged along the second direction. The lengths of the multiple first connection lines arranged along the second direction increase or decrease in sequence.

[0023] The present disclosure also provides a method for manufacturing a semiconductor structure, including the following steps:

[0024] Provide a substrate;

[0025] Form multiple first conductive lines that extend along the first direction and are arranged along the second direction on the substrate. The second direction intersects the first direction.

[0026] A memory array is formed on the plurality of first conductive lines, and a plurality of second conductive lines extending in a third direction and arranged in a first direction are formed. The second conductive lines and the first conductive lines are both connected to the memory array, and the third direction intersects the first direction.

[0027] A first interconnect structure is formed on the first conductive line, and a second interconnect structure is formed on the second conductive line. Both the first interconnect structure and the second interconnect structure extend in the vertical direction.

[0028] In some embodiments, the substrate includes a substrate and an isolation layer;

[0029] The forming of the plurality of first conductive lines extending in a first direction and arranged in a second direction on the substrate includes:

[0030] Forming trenches in the isolation layer;

[0031] Forming the first conductive lines to fill the trenches;

[0032] Or,

[0033] The forming of the plurality of first conductive lines extending in a first direction and arranged in a second direction on the substrate includes:

[0034] Forming a first conductive line material layer on the isolation layer;

[0035] Performing a patterning process on the first conductive line material layer to form the first conductive lines.

[0036] In some embodiments, the forming of the first interconnect structure on the first conductive line and the forming of the second interconnect structure on the second conductive line include:

[0037] Forming the first interconnect structure at an end of the first conductive line along the first direction;

[0038] After the forming of the first interconnect structure on the first conductive line and the forming of the second interconnect structure on the second conductive line, it includes:

[0039] Forming a pad layer above the first interconnect structure and the second interconnect structure. The pad layer includes a first pad and a second pad. The first pad is electrically connected to the first interconnect structure, and the second pad is electrically connected to the second interconnect structure.

[0040] In some embodiments, before forming the pad layer above the first interconnect structure and the second interconnect structure, it further includes:

[0041] Form a first connection line extending along the first direction on the first interconnect structure, and the first connection line extends from the top of the first interconnect structure in a direction away from the edge of the memory array;

[0042] Form a second connection line extending along the first direction on the second interconnect structure, and the second connection line extends from the top of the second interconnect structure in a direction away from the edge of the memory array;

[0043] Form a third interconnect structure on the first connection line, and the third interconnect structure is located between the first connection line and the first pad;

[0044] Form a fourth interconnect structure on the second connection line, and the fourth interconnect structure is located between the second connection line and the second pad.

[0045] In the semiconductor structure and its manufacturing method of the present disclosure, by arranging a plurality of first conductive lines on a substrate and arranging a memory array on the first conductive lines, the first conductive lines are located below the memory array, without occupying the space above the memory array, thereby leaving a larger manufacturing space for the second conductive lines, reducing the difficulty of manufacturing the first conductive lines and the second conductive lines, and improving the integration degree of the semiconductor structure. Description of the Drawings

[0046] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure or the prior art, the following will briefly introduce the drawings required for the description of the embodiments or the prior art. Obviously, the drawings in the following description are only some embodiments of the present disclosure. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0047] Figure 1 Schematic diagram of a memory structure in the related art;

[0048] Figure 2 Flowchart of the manufacturing method of the semiconductor structure provided in an embodiment;

[0049] Figures 3 to 7 Schematic diagram of an intermediate structure obtained in the manufacturing process of the semiconductor structure provided in an embodiment;

[0050] Figure 8 Schematic diagram of the semiconductor structure provided in an embodiment;

[0051] Figure 9 Schematic diagram of a pad layer provided in an embodiment.

[0052] Explanation of the reference numerals: semiconductor structure-100; base-110; substrate-111; isolation layer-112; first conductive line-120; storage array-130; transistor-131; gate structure-1311; channel region-1312; source-1313; drain-1314; capacitor-132; second conductive line-140; first interconnect structure-150; second interconnect structure-160; pad layer-170; first pad-171; second pad-172; first connection line-181; second connection line-182; third interconnect structure-191; fourth interconnect structure-192. DETAILED DESCRIPTION

[0053] In order to facilitate understanding of the present disclosure, the present disclosure will be described more fully below with reference to the relevant drawings. The preferred embodiments of the present disclosure are shown in the drawings. However, the present disclosure can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present disclosure more thorough and comprehensive.

[0054] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which the present disclosure belongs. The terms used herein in the specification of the present disclosure are only for the purpose of describing specific embodiments and are not intended to limit the present disclosure.

[0055] It should be understood that when an element or layer is referred to as being "on, adjacent to, or connected to" another element or layer, it may be directly on, adjacent to, or connected to the other element or layer, or there may be intervening elements or layers. In contrast, when an element is referred to as being "directly on, directly adjacent to, or directly connected to" another element or layer, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, and / or parts, these elements, components, regions, layers, and / or parts should not be limited by these terms. These terms are merely used to distinguish one element, component, region, layer, or part from another element, component, region, layer, or part. Therefore, without departing from the teachings of the present disclosure, the first element, component, region, layer, or part discussed below may be represented as a second element, component, region, layer, or part.

[0056] Spatial relationship terms such as "under", "below", "lower", "beneath", "above", "upper", etc. can be used herein to describe the relationship of one element or feature shown in the figures to other elements or features. It should be understood that, in addition to the orientations shown in the figures, spatial relationship terms also include different orientations of the device in use and operation. For example, if the device in the figures is flipped, an element or feature described as "under other elements" or "beneath them" or "underneath them" will be oriented "above" the other elements or features. Thus, the exemplary terms "under" and "beneath" can include both upward and downward orientations. Additionally, the device may also include additional orientations (such as, rotated 90 degrees or other orientations), and the spatial descriptors used herein are to be interpreted accordingly.

[0057] As used herein, the singular forms "a", "an", and "the" may also include the plural forms unless the context clearly dictates otherwise. It should also be understood that when the terms "comprising" and / or "including" are used in this specification, the presence of the stated features, integers, steps, operations, elements, and / or components can be determined, but one or more other features, integers, steps, operations, elements, components, and / or groups thereof are not precluded from existence or addition. Also, as used herein, the term "and / or" includes any and all combinations of the associated listed items.

[0058] Embodiments of the invention are described herein with reference to cross-sectional views that are schematic illustrations of ideal embodiments (and intermediate structures) of the present disclosure, and variations in the illustrated shapes can be expected due to, for example, manufacturing techniques and / or tolerances. Accordingly, embodiments of the present disclosure should not be limited to the specific shapes of the regions shown herein, but include shape deviations due to, for example, manufacturing techniques. The regions shown in the figures are substantially schematic, and their shapes do not represent the actual shapes of the regions of the device and do not limit the scope of the present disclosure.

[0059] As shown in the background art, in the related art, as the memory size is scaled down, the interconnect space between the word lines and the bit lines and the logic circuit is limited.

[0060] As an example, in the WOW (wafer on wafer) technology, a memory array and a logic circuit can be formed on two wafers respectively, and the two wafers are interconnected by means such as hybrid bonding to form a memory. Please refer to Figure 1, after forming the memory array 10, a word line lead-out structure 21 for leading out the word lines 11 in the memory array 10 and a bit line lead-out structure 22 for leading out the bit lines 12 in the memory array 10 can be formed. The memory array 10 needs to be interconnected with a logic circuit on another wafer through the bit line lead-out structure 22 and the word line lead-out structure 21. Since at least one of the bit line 12 and the word line 11 is a horizontally extending structure, at least one of the bit line lead-out structure 22 and the word line lead-out structure 21 needs to connect the horizontally extending structures of different layers of the memory array 10 through a stepped structure. Figure 1 As shown in Figure 1 , the word line 11 is a horizontally extending structure, and the word line lead-out structure 21 is connected to the word line 11 through a word line stepped structure 13. However, as the number of layers of the memory array 10 increases, the stepped structure 13 needs to occupy a large area, which is not conducive to improving the integration degree.

[0061] Based on this, in some embodiments, please refer to Figure 2 , the present disclosure provides a method for manufacturing a semiconductor structure 100, including the following steps:

[0062] Step S100: Provide a substrate 110.

[0063] Step S200: Form a plurality of first conductive lines 120 extending along a first direction and arranged along a second direction on the substrate 110, and the second direction intersects the first direction.

[0064] Step S300: Form a memory array 130 on the plurality of first conductive lines 120, and form a plurality of second conductive lines 140 extending along a third direction and arranged along the first direction. The second conductive lines 140 and the first conductive lines 120 are both connected to the memory array 130, and the third direction intersects the first direction.

[0065] Step S400: Form a first interconnect structure 150 on the first conductive lines 120, and form a second interconnect structure 160 on the second conductive lines 140. The first interconnect structure 150 and the second interconnect structure 160 both extend in the vertical direction.

[0066] In step S100, please refer to Figure 3 , the substrate 110 can be composed of a semiconductor material, an insulating material, a conductive material, or any combination thereof.

[0067] In step 200, please refer to Figure 3 , form a plurality of first conductive lines 120 on the substrate 110, and the plurality of first conductive lines 120 can be arranged in parallel.

[0068] Any one of the first conductive lines 120 extends along the first direction. And the plurality of first conductive lines 120 are arranged along the second direction, and the second direction intersects the first direction. As an example, the first direction and the second direction can be perpendicular. As an example, please refer toFigure 3 The X direction can be the first direction, and the Y direction can be the second direction.

[0069] The material of the first conductive wire 120 is a conductive material. For example, the material of the first conductive wire 120 is a conductive material, such as one or more of the following: metals (such as tungsten (W), titanium (Ti), molybdenum (Mo), copper (Cu), aluminum (Al)); alloys (such as Co-based alloys, Mo-based alloys, Ti-based alloys); conductive metal-containing materials (such as conductive metal nitrides, conductive metal silicides, conductive metal oxides); and conductive doped semiconductor materials (such as conductive doped polysilicon, conductive doped silicon germanium (SiGe)).

[0070] In step S300, please refer to Figure 4 The storage array 130 is located above the first conductive wire 120 and is connected to the first conductive wire 120.

[0071] After or during the formation of the storage array 130, the second conductive wire 140 can be formed. The second conductive wire 140 is connected to the storage array 130.

[0072] The second conductive wire 140 extends along a third direction and is arranged along the first direction. The third direction intersects the first direction. The first direction, the second direction, and the third direction are all directions parallel to the plane of the substrate. As an example, the third direction can be perpendicular to the first direction. At this time, the third direction is the same as the second direction. Of course, the third direction can form other angles with the first direction. For example, the third direction forms an angle of 30 degrees, 45 degrees, or 60 degrees, etc. with the first direction.

[0073] There can be multiple second conductive wires 140, and the multiple second conductive wires 140 can be arranged in parallel along the vertical direction. The vertical direction is the direction perpendicular to the plane of the substrate.

[0074] Similarly, the material of the second conductive wire 140 can be a conductive material such as metal or metal oxide. For example, the material of the second conductive wire 140 is copper, aluminum, or silver. The material of the second conductive wire 140 can be the same as the material of the first conductive wire 120. Of course, the material of the second conductive wire 140 can also be different from the material of the first conductive wire 120.

[0075] As an example, when the storage array includes word lines extending along the vertical direction, the first conductive wire 120 can be set to be connected to the word lines, and the second conductive wire 140 is a bit line. As another example, when the storage array includes bit lines extending along the vertical direction, at this time, the first conductive wire 120 is set to be connected to the bit lines, and the second conductive wire 140 is a word line. Please refer to Figure 8 The Z direction can be the vertical direction.

[0076] The following is an exemplary description of a memory structure in which the first conductive line 120 is connected to a word line extending in the vertical direction, and the second conductive line 140 is a bit line.

[0077] Please refer to Figure 4 、 Figure 7 and Figure 8 , the first conductive line 120 extends in a first direction and is arranged in a second direction, and the memory array 130 is located above the first conductive line 120. The second conductive line 140 extends in a third direction and is arranged in the first direction and the vertical direction. At this time, the third direction is the same as the second direction, and moreover, the third direction (or the second direction) is perpendicular to the first direction.

[0078] The memory array 130 includes a plurality of memory cells. The plurality of memory cells are connected to both sides of the second conductive line 140.

[0079] The memory cell includes a transistor 131 and a capacitor 132. The transistor 131 includes a gate structure 1311, a channel region 1312, a source 1313, and a drain 1314. The gate structure 1311 extends in the vertical direction and is connected to the first conductive line 120. The gate structure 1311 includes a gate and a gate dielectric layer, and the gates of the plurality of transistors 131 arranged in the vertical direction are connected to each other as a word line extending in the vertical direction. In some embodiments, referring to Figure 8 , the transistor 131 is a vertical annular channel structure (CAA), the gate dielectric layer surrounds the gate, and a channel region 1312 is provided between the source 1313 and the drain 1314, and the channel region 1312 surrounds the gate dielectric layer between the source 1313 and the drain 1314. In other embodiments, the transistor 131 may also be a gate-all-around structure (GAA), and the gate structure covers at least one side of the channel region. The present disclosure does not limit the type of the transistor 131.

[0080] The capacitor 132 may include a lower plate, a capacitive dielectric layer, and an upper plate. Either the source 1313 or the drain 1314 of the transistor 131 is connected to the second conductive line 140, and the other is connected to the lower plate of the capacitor 132. As Figure 8 shown, the source 1313 of the transistor 131 is connected to the second conductive line 140, and the drain 1314 is connected to the lower plate of the capacitor 132.

[0081] The memory cells located on opposite sides of the same second conductive line 140 are arranged in a staggered manner in the third direction (or the second direction), and the adjacent memory cells located on opposite sides of the same second conductive line 140 are connected to adjacent first conductive lines 120.

[0082] It can be understood that in the vertical direction (for example, Figure 8The memory cell groups are formed by memory cells stacked in the Z direction (the middle Z direction). The adjacent first conductive lines 120 are respectively connected to the memory cell groups on the opposite sides of the second conductive line 140. Exemplarily, at this time, the first conductive line 120 is electrically connected to the word line, the second conductive line 140 is the bit line, the bit lines can be shared, and the word lines need to be separately connected to control the memory cell groups, so as to selectively select a memory cell.

[0083] The word lines of multiple memory cell groups arranged along the first direction can be connected through the same first conductive line 120.

[0084] The dimension of the first conductive line 120 along the first direction is greater than the dimension of the memory array 130 along the first direction. The first interconnecting structures 150 connected to the adjacent first conductive lines 120 are located on the opposite sides of the memory array 130 along the first direction. At this time, it is convenient to set the first interconnecting structures 150 at both ends of the first conductive line 120.

[0085] In step S400, please refer to Figure 6 , the material of the first interconnecting structure 150 is a conductive material and is connected to the first conductive line 120. The first conductive line 120 is connected to other structures through the first interconnecting structure 150, making the setting of the first conductive line 120 more flexible.

[0086] At the same time, the material of the second interconnecting structure 160 is also a conductive material and is connected to the second conductive line 140. The second conductive line 140 is connected to other structures through the second interconnecting structure 160, making the setting of the second conductive line 140 more flexible. In the third direction in which the second conductive line 140 extends, multiple second interconnecting structures 160 can be set. The projections of the multiple second interconnecting structures 160 on the substrate 111 and the projection of the second conductive line 140 on the substrate 111 all at least partially overlap. The projection of the second interconnecting structure 160 on the substrate 111 can be located between the projections of the first conductive line 120 on the substrate 111, and the projections of the second interconnecting structures 160 on the substrate 111 are arranged at intervals from the projections of the first conductive line 120 on the substrate 111. The lengths of the respective second interconnecting structures 160 in the vertical direction can be different, and the different second interconnecting structures 160 are respectively electrically connected to the second conductive lines 140 located in different layers. Exemplarily, an electrical isolation layer can also be formed between the second interconnecting structure 160 and the second conductive line 140 that is not electrically connected.

[0087] As an example, the first interconnecting structure 150 and the second interconnecting structure 160 can both extend along the thickness direction of the memory array 130, that is, extend in the vertical direction. It can be understood that the first interconnecting structure 150 and the second interconnecting structure 160 can extend in the same direction. Of course, the first interconnecting structure 150 and the second interconnecting structure 160 can also extend in different directions.

[0088] In this embodiment, by disposing the first conductive line 120 below the memory array 130 and without the need to provide a stepped structure, the arrangement density of the conductive lines is increased, thereby increasing the memory density.

[0089] In some embodiments, the substrate 110 includes a substrate 111 and an isolation layer 112 located above the substrate 111. At this time, step S200 includes:

[0090] Step S210: Form trenches in the isolation layer 112.

[0091] Step S220: Form the first conductive line 120 filling the trenches.

[0092] In step S210, the material of the isolation layer 112 is an insulating material. As an example, the material of the isolation layer 112 is silicon oxide, silicon nitride or silicon oxynitride. The isolation layer 112 can better isolate the subsequently formed first conductive line 120 from the substrate 111.

[0093] When forming trenches in the isolation layer 112, a dry etching or wet etching method can be used to form a plurality of trenches extending in the first direction and arranged in the second direction in the isolation layer 112. As an example, dry etching can include at least any one of reactive ion etching, inductively coupled plasma etching or high density plasma etching.

[0094] In step S220, the trenches are filled with a conductive material to form the first conductive line 120. As an example, a conductive material can be deposited over the entire surface first to form a first conductive material layer. Then, the first conductive material layer located outside the trenches is removed, and the first conductive material layer located in the trenches is retained to form the first conductive line 120. For example, the deposition process can include one or more of, but is not limited to, chemical vapor deposition process, atomic layer deposition process, high density plasma deposition process, plasma enhanced deposition process and spin-on dielectric layer process.

[0095] In this embodiment, by forming trenches and filling the trenches to form the first conductive line 120, a flat upper surface can be obtained. This flat upper surface enables the memory array 130 to be formed on a flat surface, thereby facilitating improving the performance of the memory array 130.

[0096] In another embodiment, the substrate 110 includes a substrate 111 and an isolation layer 112 located above the substrate 111. Step S200 may further include:

[0097] Step S2100: Form a first conductive line material layer on the isolation layer 112.

[0098] Step S2200: Pattern the first conductive line material layer to form the first conductive line 120.

[0099] In step S2100, a first conductive wire material layer can be deposited over the entire surface of the isolation layer 112.

[0100] In step S2200, a mask plate can be formed on the first conductive wire material layer, and the first conductive wire material layer can be etched based on the mask plate to form the first conductive wire 120.

[0101] In some embodiments, step S400 includes:

[0102] Step S410: forming a first interconnect structure 150 at an end of the first conductive wire 120 along a first direction.

[0103] After step S400, it includes:

[0104] Step S600: forming a pad layer 170 above the first interconnect structure 150 and the second interconnect structure 160, the pad layer 170 includes a first pad 171 and a second pad 172, the first pad 171 is electrically connected to the first interconnect structure 150, and the second pad 172 is electrically connected to the second interconnect structure 160.

[0105] In step S410, referring to Figure 6 , the dimension of the first conductive wire 120 along the first direction is greater than the dimension of the storage array 130 along the first direction, which facilitates disposing the first interconnect structure 150 at an end of the first conductive wire 120 along the first direction, and the first interconnect structure 150 extends in the vertical direction.

[0106] At this time, multiple first interconnect structures 150 can be arranged in a staggered manner. As an example, adjacent first interconnect structures 150 corresponding to adjacent first conductive wires 120 can be respectively located at different ends of the adjacent first conductive wires 120. The first conductive wire 120 has opposite first and second ends. The first interconnect structure 150 and the first conductive wire 120 are electrically connected in a one-to-one correspondence, and multiple first interconnect structures 150 are alternately located at one of the two ends of the first conductive wire 120. For example, the first interconnect structures 150 of the odd-numbered first conductive wires 150 are located at the first ends of the corresponding odd-numbered first conductive wires 120, and the first interconnect structures 150 of the even-numbered first conductive wires 150 are located at the second ends of the corresponding odd-numbered first conductive wires 120, thereby reducing the parasitic capacitance between adjacent first interconnect structures 150. At the same time, the multiple first interconnect structures 150 arranged in a staggered manner can enable each first interconnect structure 150 to have a larger preparation space, save the occupied area, and reduce the preparation difficulty. The first conductive wire 120 is connected in series with multiple storage units arranged along the first direction, thereby being able to reduce the number of the first interconnect structures 150 and the manufacturing difficulty of the first interconnect structures 150.

[0107] In other embodiments, multiple first interconnect structures 150 can also be located at the same end of multiple first conductive wires 120.

[0108] Meanwhile, the ends of multiple first conductive lines 120 can all be aligned along the second direction, that is, the projections of the ends of the multiple first conductive lines 120 along the second direction coincide. Alternatively, the ends of the multiple first conductive lines 120 can be at least partially aligned along the second direction. Exemplarily, for example, the ends of the odd-numbered first conductive lines 120 are aligned with each other, and the ends of the even-numbered first conductive lines 120 are aligned with each other. The ends of the odd-numbered first conductive lines 120 and the ends of the even-numbered first conductive lines 120 can be arranged in a staggered manner in the second direction to increase the space for the ends of the first conductive lines 120 to contact the first interconnecting structure 150.

[0109] The height of the first interconnecting structure 150 in the vertical direction is greater than the thickness of the memory array 130, so as to facilitate forming a first connection line 181 connected to the first interconnecting structure 150 above the memory array 130 in subsequent steps.

[0110] In step S600, please refer to Figure 7 , as an example, both the first interconnecting structure 150 and the second interconnecting structure 160 extend along the vertical direction, and the tops of the first interconnecting structure 150 and the second interconnecting structure 160 can be flush.

[0111] At this time, a first pad 171 can be formed at the end of the first interconnecting structure 150 or at the end of the first connection line 181 connected to the first interconnecting structure 150, and a second pad 172 can be formed at the end of the second interconnecting structure 160. The first pad 171 and the second pad 172 can be at different levels or flush. The first pad 171 and the second pad 172 constitute a pad layer 170.

[0112] In this embodiment, the pad layer 170 can be used to connect the logic circuit on the driving substrate. The first pad 171 and the second pad 172 can be used for soldering or bonding with the driving substrate.

[0113] In some embodiments, before step S600, it includes:

[0114] Step S500: Form a first connection line 181 extending along the first direction on the first interconnecting structure 150, and the first connection line 181 extends from the outer periphery of the memory array 130 towards the inside of the memory array 130.

[0115] Step S510: Form a second connection line 182 extending along the first direction on the second interconnecting structure 160, and the second connection line 182 extends from the outer periphery of the memory array 130 towards the inside of the memory array 130.

[0116] Step S520: Form a third interconnect structure 191 on the first connection line 181, where the third interconnect structure 191 is located between the first connection line 181 and the first pad 171.

[0117] Step S530: Form a fourth interconnect structure 192 on the second connection line 182, where the fourth interconnect structure 192 is located between the second connection line 182 and the second pad 172.

[0118] In step S500, refer to Figure 6 and Figure 7 , a first dielectric layer covering the second conductive line 140 and the memory array 130 can be formed first, and then the first dielectric layer is etched to form a plurality of first trenches extending from the outer periphery of the memory array 130 towards the inside of the memory array 130. The first trenches are filled with a conductive material to form the first connection line 181.

[0119] When the plurality of first interconnect structures 150 are arranged in a staggered manner, the plurality of corresponding first connection lines 181 extend from the outer periphery of the opposite memory arrays 130 towards the inside of the memory arrays 130.

[0120] Of course, when the plurality of first interconnect structures 150 are located on the same side of the first conductive line 120, the plurality of corresponding first connection lines 181 extend from the outer periphery of the same side of the memory array 130 towards the inside of the memory array 130.

[0121] In step S510, similarly, a second connection line 182 extending in the first direction is formed at the end of the second interconnect structure 160. The second connection line 182 extends in the direction from the outer periphery of the memory array 130 towards the inside of the memory array 130.

[0122] The process of forming the second connection line 182 is similar to the process of forming the first connection line 181, and will not be elaborated here.

[0123] In step S520, the third interconnect structure 191 is connected to the end of the first connection line 181, and the third interconnect structure 191 can be distributed in the vertical direction.

[0124] As an example, after forming the first connection line 181 and the second connection line 182, a second dielectric layer covering the first connection line 181 and the second connection line 182 can be formed. The second dielectric layer is etched to form a plurality of through holes, and the plurality of through holes expose the first connection line 181. The plurality of through holes are filled to form the third interconnect structure 191.

[0125] After forming the third interconnect structure 191, a first pad 171 is formed on the top of the third interconnect structure 191.

[0126] In step S530, similarly, the fourth interconnect structure 192 is connected to the end of the second connection line 182, and the fourth interconnect structure 192 can also extend in the vertical direction.

[0127] The formation process of the fourth interconnect structure 192 is similar to that of the third interconnect structure 191, and will not be elaborated here.

[0128] After the fourth interconnect structure 192 is formed, a second pad 172 is formed at the top of the fourth interconnect structure 192.

[0129] In this embodiment, by forming the first connection line 181 and the second connection line 182, not only can the positions of the pads in the pad layer 170 be set more flexibly, enabling the first interconnect structure 150 and the second interconnect structure 160 to avoid other structures, but also it is convenient to disperse the arrangement of the pad layer 170.

[0130] Of course, the first connection line 181 and the second connection line 182 can be formed simultaneously. The third interconnect structure 191 and the fourth interconnect structure 192 can also be formed simultaneously.

[0131] In some embodiments, the third interconnect structures 191 located on different first connection lines 181 are arranged staggeredly.

[0132] The first connection line 181 extends in the first direction and multiple first connection lines 181 are arranged in the second direction. At this time, as an example, the lengths of the multiple first connection lines 181 arranged in the second direction increase in sequence. Or, the lengths of the multiple first connection lines 181 arranged in the second direction decrease in sequence. Or, the lengths of the multiple first connection lines 181 arranged in the second direction can also be set at intervals of long and short.

[0133] At this time, the first pads 171 connected to the third interconnect structures 191 are also distributed staggeredly, so that the multiple first pads 171 can be distributed more evenly.

[0134] In another embodiment, the fourth interconnect structures 192 located on different second connection lines 182 can also be arranged staggeredly. Similarly, the second pads 172 connected to the fourth interconnect structures 192 are also distributed staggeredly.

[0135] In another embodiment, please refer to Figure 9 , the first pads 171 and the second pads 172 can also be arranged neatly.

[0136] It should be understood that although Figure 2 the steps in the flowchart ofFigure 2 At least some of the steps in Figure 2 may include multiple steps or multiple stages. These steps or stages are not necessarily executed and completed at the same time, but can be executed at different times. The execution order of these steps or stages is not necessarily sequential, but can be executed alternately or in turn with at least some of the steps or stages in other steps or other steps.

[0137] Please continue to refer to Figure 8 The present disclosure also provides a semiconductor structure 100, including: a substrate 110, a first conductive line 120, a memory array 130, a second conductive line 140, a first interconnect structure 150, and a second interconnect structure 160.

[0138] The substrate 110 can be made of semiconductor material, insulating material, conductive material, or any combination thereof.

[0139] The first conductive line 120 is located on the substrate 110. The first conductive line 120 extends in a first direction, and a plurality of first conductive lines 120 are arranged in a second direction.

[0140] The first direction intersects the second direction. As an example, the first direction and the second direction can be perpendicular.

[0141] The material of the first conductive line 120 can be a conductive material, for example, one or more of the following: metal (e.g., tungsten (W), titanium (Ti), molybdenum (Mo), copper (Cu), aluminum (Al)); alloy (e.g., Co-based alloy, Mo-based alloy, Ti-based alloy); conductive metal-containing material (e.g., conductive metal nitride, conductive metal silicide, conductive metal oxide); and conductive doped semiconductor material (e.g., conductive doped polysilicon, conductive doped silicon germanium (SiGe)).

[0142] The memory array 130 is located on the first conductive line 120, and the memory array 130 is connected to the first conductive line 120.

[0143] The second conductive line 140 is connected to the memory array 130 and extends in a third direction. The first direction intersects the third direction. As an example, the first direction and the third direction can be perpendicular. It can be understood that the third direction and the second direction can be the same. Of course, the third direction can form other angles with the first direction. For example, the third direction forms an angle of 30 degrees, 45 degrees, or 60 degrees with the first direction.

[0144] Similarly, the material of the second conductive line 140 can be a conductive material such as metal or metal oxide. For example, the material of the second conductive line 140 is copper, aluminum, or silver. The material of the second conductive line 140 can be the same as the material of the first conductive line 120. Of course, the material of the second conductive line 140 can also be different from the material of the first conductive line 120.

[0145] When the semiconductor structure 100 is a memory, the first conductive line 120 can be electrically connected to the word line or the bit line. When the first conductive line 120 is electrically connected to the word line, the second conductive line 140 is the bit line; conversely, when the first conductive line 120 is electrically connected to the bit line, the second conductive line 140 is the word line.

[0146] The following exemplarily describes the memory structure when the first conductive line 120 is electrically connected to the word line and the second conductive line 140 is the bit line.

[0147] The first conductive line 120 extends along a first direction and is arranged along a second direction, and the memory array 130 is located above the first conductive line 120. The second conductive line 140 extends along a third direction and is arranged in the first direction and the vertical direction. At this time, the third direction is the same as the second direction, and moreover, the third direction (or the second direction) is perpendicular to the first direction.

[0148] The memory array 130 includes a plurality of memory cells. The memory array 130 includes a plurality of memory cells arranged in an array along the first direction, the second direction, and the vertical direction. Each first conductive line 120 is electrically connected to at least two memory cells arranged along the first direction, and two adjacent memory cells electrically connected to the first conductive line 120 can be connected to the same second conductive line 140. The plurality of memory cells arranged in the first direction and the vertical direction can be led out and connected to other structures through one second conductive line 140, improving the interconnection efficiency.

[0149] The memory cell includes a transistor 131 and a capacitor 132. The gate structure 1311 of the transistor 131 extends along the vertical direction and is connected to the first conductive line 120. The gate structure 1311 includes a gate and a gate dielectric layer. The gate dielectric layer 1312 surrounds the gate. A channel region 1312 is provided between the source 1313 and the drain 1314, and the channel region 1312 surrounds the gate dielectric layer between the source 1313 and the drain 1314.

[0150] The capacitor 132 can include a lower plate, a capacitive dielectric layer, and an upper plate. Either the source 1313 or the drain 1314 of the transistor 131 is connected to the second conductive line 140, and the other is connected to the lower plate of the capacitor. As Figure 8 shown, the source 1313 of the transistor 131 is connected to the second conductive line 140, and the drain 1314 is connected to the lower plate of the capacitor 132.

[0151] The memory cells located on opposite sides of the same second conductive line 140 are arranged in a staggered manner in the third direction (or the second direction), and the adjacent memory cells located on opposite sides of the same second conductive line 140 are connected to adjacent first conductive lines 120.

[0152] It can be understood that in the vertical direction (for example,Figure 8 Memory cell groups are formed by memory cells stacked in the Z direction (the middle Z direction). Adjacent first conductive lines 120 are respectively connected to memory cell groups on opposite sides of the second conductive line 140. Exemplarily, at this time, the first conductive line 120 is electrically connected to the word line, the second conductive line 140 is the bit line, the bit lines can be shared, and the word lines need to be separately connected to control the memory cell groups, so as to selectively select a memory cell.

[0153] The word lines of multiple memory cell groups arranged in the first direction can be connected through the same first conductive line 120.

[0154] The dimension of the first conductive line 120 in the first direction is greater than the dimension of the memory array 130 in the first direction. The first interconnect structures 150 connected to adjacent first conductive lines 120 are located on opposite sides of the memory array 130 in the first direction.

[0155] The first interconnect structure 150 is located on the first conductive line 120 and is electrically connected to the first conductive line 120. The second interconnect structure 160 is located on the second conductive line 140 and is connected to the second conductive line 140. The first conductive line 120 is connected to other structures through the first interconnect structure 150, making the setting of the first conductive line 120 more flexible.

[0156] At the same time, the material of the second interconnect structure 160 is also a conductive material and is connected to the second conductive line 140. The second conductive line 140 is connected to other structures through the second interconnect structure 160, making the setting of the second conductive line 140 more flexible.

[0157] As an example, the first interconnect structure 150 and the second interconnect structure 160 can both extend in the vertical direction. At this time, the first interconnect structure 150 and the second interconnect structure 160 can both extend in the vertical direction. Please refer to Figure 8 , the Z direction can be the vertical direction. It can be understood that the first interconnect structure 150 and the second interconnect structure 160 can extend in the same direction. Of course, the first interconnect structure 150 and the second interconnect structure 160 can also extend in different directions.

[0158] In this embodiment, by arranging the first conductive line 120 below the memory array 130 and arranging the second conductive line 140 above the memory array 130. Not only does it simultaneously reduce the difficulty of fabricating the first conductive line 120 and the second conductive line 140, but also there is no need to set a step structure, improving the arrangement density of the conductive lines and enhancing the integration degree of the semiconductor structure.

[0159] In some embodiments, the substrate 110 includes a substrate 111 and an isolation layer 112 located above the substrate 111. The isolation layer 112 is located between the substrate 111 and the first conductive line 120. At this time, the first conductive line 120 is located on the upper surface of the isolation layer 112.

[0160] The material of the isolation layer 112 is an insulating material. As an example, the material of the isolation layer 112 is silicon oxide, silicon nitride, or silicon oxynitride. The isolation layer 112 can better isolate the subsequently formed first conductive line 120 from the substrate 111.

[0161] In another embodiment, trenches are provided in the isolation layer 112, and the first conductive line 120 is located in the trenches of the isolation layer 112.

[0162] In this embodiment, by forming trenches and filling the trenches to form the first conductive line 120, a flat upper surface can be obtained. This flat upper surface enables the storage array 130 to be formed on a flat surface, thereby facilitating the improvement of the performance of the storage array 130.

[0163] In some embodiments, the first interconnect structure 150 is located at the end of the first conductive line 120. The semiconductor structure 100 further includes a pad layer 170.

[0164] The dimension of the first conductive line 120 in the first direction is greater than the dimension of the storage array 130 in the first direction, facilitating the arrangement of the first interconnect structure 150 at the end of the first conductive line 120 in the first direction, and the first interconnect structure 150 extends in the vertical direction.

[0165] At this time, multiple first interconnect structures 150 or multiple second interconnect structures 160 can be arranged in a staggered manner. As an example, the adjacent first interconnect structures 150 corresponding to adjacent first conductive lines 120 can be respectively located at different ends of the adjacent first conductive lines 120. The first conductive line 120 has opposite first and second ends. Multiple first interconnect structures 150 are alternately located at one of the two ends of the first conductive line 120. The odd-numbered first interconnect structures 150 are located at the first end of the first conductive line 120, and the even-numbered first interconnect structures 150 are located at the second end of the first conductive line 120, thereby reducing the parasitic capacitance between adjacent first interconnect structures 150. At the same time, the staggered arrangement of multiple first interconnect structures 150 can enable each first interconnect structure 150 to have a larger preparation space, save the occupied area, and reduce the preparation difficulty.

[0166] Of course, multiple first interconnect structures 150 can also be located at the same end of multiple first conductive lines 120.

[0167] Meanwhile, the ends of multiple first conductive wires 120 can all be aligned along the second direction. Alternatively, the ends of multiple first conductive wires 120 can be at least partially aligned along the second direction. Exemplarily, for example, the ends of the odd-numbered first conductive wires 120 are aligned with each other, the ends of the even-numbered first conductive wires 120 are aligned with each other, and the ends of the odd-numbered first conductive wires 120 and the ends of the even-numbered first conductive wires 120 can be arranged in a staggered manner in the second direction to increase the space for the ends of the first conductive wires 120 to contact the first interconnecting structure 150.

[0168] Both the first interconnecting structure 150 and the second interconnecting structure 160 extend along the vertical direction, and the tops of the first interconnecting structure 150 and the second interconnecting structure 160 are flush. The height of the first interconnecting structure 150 in the vertical direction is greater than the thickness of the memory array 130, facilitating the formation of a first connecting wire 181 connected to the first interconnecting structure 150 above the memory array 130 in subsequent steps.

[0169] The pad layer 170 is located above the first interconnecting structure 150 and the second interconnecting structure 160. The pad layer 170 includes a first pad 171 and a second pad 172. The first pad 171 is electrically connected to the first interconnecting structure 150, and the second pad 172 is electrically connected to the second interconnecting structure 160.

[0170] At this time, a first pad 171 is formed at the end of the first interconnecting structure 150, and a second pad 172 is formed at the end of the second interconnecting structure 160. The first pad 171 and the second pad 172 can be staggered or flush.

[0171] In this embodiment, the pad layer 170 is used to connect devices such as logic circuits. The flush first pad 171 and second pad 172 can be used for soldering or bonding with a driving substrate.

[0172] In some embodiments, the semiconductor structure 100 further includes: a first connecting wire 181, a second connecting wire 182, a third interconnecting structure 191, and a fourth interconnecting structure 192.

[0173] The first connecting wire 181 contacts the top of the first interconnecting structure 150 and extends along the direction from the outer periphery of the memory array 130 to the inside of the memory array 130.

[0174] The third interconnecting structure 191 is located between the first connecting wire 181 and the first pad 171.

[0175] The second connecting wire 182 contacts the top of the second interconnecting structure 160 and extends along the direction from the outer periphery of the memory array 130 to the inside of the memory array 130.

[0176] The fourth interconnecting structure 192 is located between the second connecting wire 182 and the second pad 172.

[0177] In this embodiment, by forming the first connection line 181 and the second connection line 182, not only can the positions of the pads in the pad layer 170 be set more flexibly, enabling the first interconnect structure 150 and the second interconnect structure 160 to avoid other structures, but also it is convenient to disperse the arrangement of the pad layer 170.

[0178] In some embodiments, the third interconnect structures 191 located on different first connection lines 181 are arranged staggeredly;

[0179] The first connection line 181 extends in the first direction and multiple first connection lines 181 are arranged in the second direction. At this time, as an example, the lengths of the multiple first connection lines 181 arranged in the second direction increase in sequence. Or, the lengths of the multiple first connection lines 181 arranged in the second direction decrease in sequence. Or, the lengths of the multiple first connection lines 181 arranged in the second direction can also be arranged at intervals of long and short.

[0180] At this time, the first pads 171 connected to the third interconnect structures 191 are also distributed staggeredly, so that the multiple first pads 171 can be distributed more evenly.

[0181] In another embodiment, the fourth interconnect structures 192 located on different second connection lines 182 can also be arranged staggeredly. Similarly, the second pads 172 connected to the fourth interconnect structures 192 are also distributed staggeredly.

[0182] In another embodiment, please refer to Figure 9 , the first pads 171 and the second pads 172 can also be arranged neatly.

[0183] The technical features of the above-described embodiments can be combined arbitrarily. For the sake of brevity of description, not all possible combinations of the technical features of the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, it should be considered as the scope described in this specification.

[0184] The above-described embodiments only represent several implementation manners of the present disclosure, and their descriptions are relatively specific and detailed, but they should not be construed as limiting the scope of the patent application. It should be noted that for those of ordinary skill in the art, without departing from the concept of the present disclosure, several deformations and improvements can still be made, and these all belong to the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure patent shall be subject to the appended claims.

Claims

1. A semiconductor structure, characterized in that, comprising: a substrate; a first conductive line located on the substrate, extending in a first direction, and a plurality of the first conductive lines arranged in a second direction, the second direction intersecting the first direction; a memory array located on the first conductive line and connected to the first conductive line; a second conductive line connecting the memory array and extending in a third direction, the third direction intersecting the first direction; a first interconnect structure extending in a vertical direction and located on the first conductive line and electrically connected to the first conductive line; a second interconnect structure extending in the vertical direction and located on the second conductive line and connected to the second conductive line.

2. The semiconductor structure according to claim 1, characterized in that, the substrate includes a substrate and an isolation layer, the isolation layer being located between the substrate and the first conductive line; the first conductive line is located on the upper surface of the isolation layer, or the first conductive line is located in a trench of the isolation layer.

3. The semiconductor structure according to claim 1, characterized in that, the first interconnect structure is located at an end of the first conductive line, and the semiconductor structure further includes: a pad layer located above the first interconnect structure and the second interconnect structure, the pad layer including a first pad and a second pad, the first pad being electrically connected to the first interconnect structure, and the second pad being electrically connected to the second interconnect structure.

4. The semiconductor structure according to claim 1, characterized in that, the second conductive line is arranged in the first direction and the vertical direction, the memory array includes memory cells located on opposite sides of each of the second conductive lines in the first direction, the memory cells located on opposite sides of the same second conductive line are arranged in a staggered manner in the third direction, and the memory cells located on opposite sides of the same second conductive line are connected to the first conductive line; the dimension of the first conductive line in the first direction is greater than the dimension of the memory array in the first direction, and the first interconnect structures connected to adjacent first conductive lines are respectively located on opposite sides of the memory array in the first direction.

5. The semiconductor structure according to claim 3, characterized in that, the semiconductor structure further includes: a first connection line in contact with the top end of the first interconnect structure and extending in a direction from the periphery of the memory array towards the inside of the memory array; a third interconnect structure extending in the vertical direction and located between the first connection line and the first pad; a second connection line in contact with the top end of the second interconnect structure and extending in a direction from the periphery of the memory array towards the inside of the memory array; a fourth interconnect structure extending in the vertical direction and located between the second connection line and the second pad.

6. The semiconductor structure according to claim 5, characterized in that, the third interconnect structures located on different first connection lines are arranged in a staggered manner; The first connection lines extend along the first direction, and a plurality of the first connection lines are arranged along the second direction. The lengths of the plurality of the first connection lines arranged along the second direction increase or decrease in sequence.

7. A method for manufacturing a semiconductor structure, characterized in that, it includes the following steps: Provide a substrate; Form a plurality of first conductive lines on the substrate that extend along the first direction and are arranged along the second direction, where the second direction intersects the first direction; Form a memory array on the plurality of first conductive lines, and form a plurality of second conductive lines that extend along the third direction and are arranged along the first direction. The second conductive lines and the first conductive lines are both connected to the memory array, and the third direction intersects the first direction; Form a first interconnect structure on the first conductive lines, and form a second interconnect structure on the second conductive lines. The first interconnect structure and the second interconnect structure both extend in the vertical direction.

8. The method for manufacturing a semiconductor structure according to claim 7, characterized in that, the substrate includes a substrate and an isolation layer; The forming a plurality of first conductive lines on the substrate that extend along the first direction and are arranged along the second direction includes: Form trenches in the isolation layer; Form the first conductive lines that fill the trenches; Or, The forming a plurality of first conductive lines on the substrate that extend along the first direction and are arranged along the second direction includes: Form a first conductive line material layer on the isolation layer; Perform patterning on the first conductive line material layer to form the first conductive lines.

9. The method for manufacturing a semiconductor structure according to claim 7, characterized in that, The forming a first interconnect structure on the first conductive lines and forming a second interconnect structure on the second conductive lines includes: Form the first interconnect structure at an end of the first conductive line along the first direction; After the forming a first interconnect structure on the first conductive lines and forming a second interconnect structure on the second conductive lines, it includes: Form a pad layer above the first interconnect structure and the second interconnect structure. The pad layer includes a first pad and a second pad. The first pad is electrically connected to the first interconnect structure, and the second pad is electrically connected to the second interconnect structure.

10. The method for manufacturing a semiconductor structure according to claim 9, characterized in that, Before the forming a pad layer above the first interconnect structure and the second interconnect structure, it further includes: Form a first connection line that extends along the first direction on the first interconnect structure, and the first connection line extends along a direction from the periphery of the memory array to the inside of the memory array; Form a second connection line that extends along the first direction on the second interconnect structure, and the second connection line extends along a direction from the periphery of the memory array to the inside of the memory array; Form a third interconnect structure on the first connection line, and the third interconnect structure is located between the first connection line and the first pad; Form a fourth interconnect structure on the second connection line, and the fourth interconnect structure is located between the second connection line and the second pad.

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