Semiconductor structure, preparation method thereof and electronic equipment

Abstract

The invention relates to a semiconductor structure, a preparation method thereof and electronic equipment. The method comprises the following steps: alternately forming a plurality of first dielectric layers and a plurality of second dielectric layers on a substrate along a direction vertical to the substrate; etching the plurality of first dielectric layers and the plurality of second dielectric layers along the direction vertical to the substrate to form a laminated structure; filling the etching areas of the plurality of first dielectric layers and the plurality of second dielectric layers with isolation structures; etching the laminated structure to form a first etching hole; etching the side wall of the second dielectric layer based on the first etching hole to form a first accommodating groove; forming a first electrode in the first accommodating groove; forming a sacrificial layer covering the first electrode and filling the first etching hole; etching the isolation structure to form a second etching hole; sequentially forming a first dielectric layer and a second electrode in the second etching hole; and removing the sacrificial layer, and sequentially forming a second dielectric layer and a third electrode in the first etching hole.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and particularly to a semiconductor structure, a method for manufacturing the same, and an electronic device. Background Art

[0002] With the continuous development of semiconductor technology, people have been continuously pursuing products with lower power consumption, lighter weight, and better performance. Three-dimensional memories are prone to having higher integration densities and larger storage capacities, and have gradually become one of the important research directions in the current storage field. However, the process complexity of three-dimensional memories is relatively high, and there is room for improvement in multiple aspects such as the control accuracy of the process, the capabilities of the machines (such as etching, film filling, etc.), and the selection of device materials. Summary of the Invention

[0003] Based on this, embodiments of the present disclosure provide a semiconductor structure, a method for manufacturing the same, and an electronic device, which are beneficial to simplifying the manufacturing process of capacitors and effectively improving the electrical performance of capacitors and electronic devices.

[0004] According to some embodiments, one aspect of the present disclosure provides a method for manufacturing a semiconductor structure, including the following steps.

[0005] Provide a substrate, and alternately form a plurality of first dielectric layers and a plurality of second dielectric layers on the substrate along a direction perpendicular to the substrate.

[0006] Etch the plurality of first dielectric layers and the plurality of second dielectric layers along a direction perpendicular to the substrate to form a stacked structure; the stacked structure includes a first part extending in a first direction and a plurality of second parts spaced apart in the first direction and extending from the first part in a second direction; the first direction and the second direction are parallel to the substrate and intersect.

[0007] Fill an isolation structure in the etched area of the plurality of first dielectric layers and the plurality of second dielectric layers.

[0008] Etch the stacked structure to form a first etching hole penetrating through the second part along a direction perpendicular to the substrate.

[0009] Based on the first etching hole, etch the sidewalls of the second dielectric layer to expose at least the isolation structure in the first direction, and form a first accommodation groove.

[0010] Form a first electrode in the first accommodation groove.

[0011] Form a sacrificial layer covering the first electrode and filling the first etching hole.

[0012] Etch the isolation structure to form a second etching hole penetrating through the isolation structure along a direction perpendicular to the substrate and located between adjacent first electrodes in the first direction.

[0013] A first dielectric layer covering the first electrode and a second electrode covering the first dielectric layer and filling the second etching hole are sequentially formed in the second etching hole.

[0014] Remove the sacrificial layer.

[0015] A second dielectric layer covering the first electrode and a third electrode covering the second dielectric layer and filling the first etching hole are sequentially formed in the first etching hole.

[0016] Thus, the capacitor includes: a first electrode, a second electrode located outside the first electrode, and a third electrode located inside the first electrode.

[0017] According to some embodiments, forming the first electrode in the first accommodation groove includes: forming the first electrode that fills the first accommodation groove; or, forming the first electrode that conformally covers the inner wall of the first accommodation groove.

[0018] According to some embodiments, forming the first electrode in the first accommodation groove includes: depositing a first electrode material layer in the first etching hole and the first accommodation groove; removing the first electrode material layer on the inner wall of the first etching hole so that the first electrode material layer remaining in the first accommodation groove constitutes the first electrode.

[0019] According to some embodiments, the first accommodation groove is formed by wet etching the second dielectric layer.

[0020] According to some embodiments, the method for manufacturing the semiconductor structure further includes: after forming the sacrificial layer and before forming the second etching hole, removing each remaining second dielectric layer in the stacked structure and forming a conductive layer in the removal area of the second dielectric layer.

[0021] According to some embodiments, the method for manufacturing the semiconductor structure further includes: after forming the second etching hole and before forming the first dielectric layer, wet-etching the first dielectric layer in the target areas on the upper and lower sides of the first electrode to expose the sacrificial layer at least in a first direction and connect adjacent second etching holes, thereby forming a second accommodation groove.

[0022] Correspondingly, the first dielectric layer is further formed on the inner wall of the second accommodation groove, and the second electrode further fills the second accommodation groove.

[0023] According to some embodiments, forming a second dielectric layer covering the first electrode and a third electrode covering the second dielectric layer and filling the first etching hole in the first etching hole includes the following steps.

[0024] Form a second dielectric material layer on the exposed surface of the first electrode facing away from the first dielectric layer, the exposed surface of the first dielectric layer facing away from the second electrode, and the top surface of the second electrode.

[0025] Form a third electrode material layer covering the exposed surface of the second dielectric material layer and filling the first etching hole.

[0026] The third electrode material layer and the second dielectric material layer are polished until the top surface of the second electrode is exposed, such that the second dielectric material layer retained in the first etching hole forms the second dielectric layer, and the third electrode material layer retained in the first etching hole forms the third electrode.

[0027] Correspondingly, the method for manufacturing the semiconductor structure further includes: forming a contact layer on the top surfaces of the second electrodes and the third electrodes, and the contact layer interconnects the second electrodes and the third electrodes.

[0028] According to some embodiments, the first dielectric layer includes an oxide layer, the second dielectric layer includes a nitride layer, and the sacrificial layer includes a low-k dielectric layer.

[0029] According to some embodiments, on the other hand, the present disclosure further provides a semiconductor structure, which can be manufactured by using the manufacturing method in the above-mentioned some embodiments. The semiconductor structure includes: a substrate, a plurality of first electrodes, a plurality of first dielectric layers, a plurality of second electrodes, a plurality of second dielectric layers, and a plurality of third electrodes.

[0030] The plurality of first electrodes are spaced apart along a first direction parallel to the substrate. The first electrode has an annular structure and the axial direction of the annular structure is perpendicular to the substrate. The first dielectric layer covers the inner sidewall of the first electrode and extends along a direction perpendicular to the substrate to the surface of the substrate to form a cup-shaped structure. The second electrode covers the surface of the corresponding first dielectric layer facing away from the first electrode and fills the cup-shaped region inside the first dielectric layer. The second dielectric layer is located between two adjacent first electrodes along the first direction, covers the outer sidewall of the corresponding first electrode, and extends along a direction perpendicular to the substrate to cover the surface of the first dielectric layer facing away from the second electrode, and extends to the surface of the substrate to form a cup-shaped structure. The third electrode covers the surface of the corresponding second dielectric layer facing away from the first electrode and fills the cup-shaped region inside the second dielectric layer.

[0031] According to some embodiments, the semiconductor structure further includes: a contact layer. The contact layer is located on the top surfaces of the second electrodes and the third electrodes, and interconnects the second electrode and the third electrode.

[0032] According to some embodiments, both the first dielectric layer and the second dielectric layer include a high-k dielectric layer; the first electrode includes a titanium nitride layer; the second electrode and the third electrode both include a titanium nitride layer and a polysilicon layer stacked along a direction away from the corresponding dielectric layer.

[0033] According to some embodiments, on yet another aspect, the present disclosure further provides an electronic device, including: the semiconductor structure as described in the above-mentioned some embodiments.

[0034] The embodiments of the present disclosure can / at least have the following advantages:

[0035] In the embodiments of the present disclosure, based on the alternately stacked multiple first dielectric layers and multiple second dielectric layers, a stacked structure can be patterned and an isolation structure can be filled. Then, by forming a first etching hole and etching the second dielectric layer to form a first accommodation groove, a first electrode can be directly formed in the first accommodation groove. In this way, compared with the deep high-aspect-ratio etching process of a metal thin film, the process difficulty and production cost can be effectively reduced.

[0036] On this basis, in the embodiments of the present disclosure, after a sacrificial layer is formed in the first etching hole, a second etching hole can be formed by etching the isolation structure between adjacent first electrodes, so as to sequentially form a first dielectric layer and a second electrode in the second etching hole; and, after removing the sacrificial layer, a second dielectric layer and a third electrode can be sequentially formed in the first etching hole. In this way, the capacitor includes a first electrode, a second electrode located outside the first electrode, and a third electrode located inside the first electrode, which not only helps to simplify the preparation process of the capacitor, but also helps to increase the effective electrode area in the capacitor to increase the capacitance value of the capacitor, thereby improving the electrical performance of the capacitor and the electronic device. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings required for the description of the embodiments will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the present disclosure. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained based on these drawings.

[0038] Figure 1 is a flowchart of a method for preparing a semiconductor structure provided in some embodiments of the present disclosure;

[0039] Figure 2 is a flowchart of another method for preparing a semiconductor structure provided in some embodiments of the present disclosure;

[0040] Figure 3 is a schematic structural diagram of a structure obtained after alternately stacking multiple first dielectric layers and multiple second dielectric layers; wherein, Figure 3 FIG. (a) is a top view schematic diagram of the shown structure, Figure 3 FIG. (b) is a cross-sectional schematic diagram of the shown structure along the A-A direction;

[0041] Figure 4 is a schematic structural diagram of a structure obtained after forming a stacked structure and an isolation structure; wherein, Figure 4 FIG. (a) is a top view schematic diagram of the shown structure, Figure 4 FIG. (b) is a cross-sectional schematic diagram of the shown structure along the A-A direction;

[0042] Figure 5 A schematic diagram of a structure obtained after forming a first etching hole in some embodiments of the present disclosure; wherein, Figure 5 Figure (a) in is a top view schematic diagram of the shown structure, Figure 5 Figure (b) in is a cross-sectional schematic diagram of the shown structure along the A-A direction;

[0043] Figure 6 A schematic diagram of a structure obtained after forming a first accommodation groove in some embodiments of the present disclosure; wherein, Figure 6 Figure (a) in is a top view schematic diagram of the shown structure, Figure 6 Figure (b) in is a cross-sectional schematic diagram of the shown structure along the A-A direction, Figure 6 Figure (c) in is a cross-sectional schematic diagram of the shown structure along the B-B direction;

[0044] Figure 7 A schematic diagram of a structure obtained after forming a first electrode material layer in some embodiments of the present disclosure; wherein, Figure 7 Figure (a) in is a cross-sectional schematic diagram of the shown structure along the A-A direction, Figure 7 Figure (b) in is a cross-sectional schematic diagram of the shown structure along the B-B direction;

[0045] Figure 8 A schematic diagram of a structure obtained after forming a first electrode in some embodiments of the present disclosure; wherein, Figure 8 Figure (a) in is a cross-sectional schematic diagram of the shown structure along the A-A direction, Figure 8 Figure (b) in is a cross-sectional schematic diagram of the shown structure along the B-B direction;

[0046] Figure 9 A schematic diagram of a structure obtained after forming a sacrificial layer in some embodiments of the present disclosure; wherein, Figure 9 Figure (a) in is a cross-sectional schematic diagram of the shown structure along the A-A direction, Figure 9 Figure (b) in is a cross-sectional schematic diagram of the shown structure along the B-B direction;

[0047] Figure 10 A schematic diagram of a structure obtained after forming a second etching hole and a second accommodation groove in some embodiments of the present disclosure; wherein, Figure 10 Figure (a) in is a top view schematic diagram of the shown structure, Figure 10 Figure (b) in is a cross-sectional schematic diagram of the shown structure along the B-B direction;

[0048] Figure 11Schematic diagram of a structure obtained after forming a first dielectric layer and a second electrode in some embodiments of the present disclosure; wherein, Figure 11 Figure (a) in Figure 11 is a top view schematic diagram of the structure shown, and

[0049] Figure 12 Schematic diagram of a structure obtained after removing a sacrificial layer in some embodiments of the present disclosure; wherein, Figure 12 Figure (a) in Figure 12 is a top view schematic diagram of the structure shown, and

[0050] Figure 13 Cross-sectional schematic diagram along B-B direction of a structure obtained after forming a second dielectric material layer and a third electrode material layer in some embodiments of the present disclosure;

[0051] Figure 14 Schematic diagram of a structure obtained after forming a second dielectric layer and a third electrode in some embodiments of the present disclosure; wherein, Figure 14 Figure (a) in Figure 14 is a top view schematic diagram of the structure shown, and

[0052] Figure 15 Cross-sectional schematic diagram along B-B direction of a structure obtained after forming a contact layer in some embodiments of the present disclosure;

[0053] Figure 16 Schematic diagram of a structure obtained after forming a first electrode material layer in some embodiments of the present disclosure; wherein, Figure 16 Figure (a) in Figure 16 is a cross-sectional schematic diagram along A-A direction of the structure shown, and

[0054] Figure 17 Schematic diagram of a structure obtained after forming a first electrode in some embodiments of the present disclosure; wherein, Figure 17 Figure (a) in Figure 17 is a cross-sectional schematic diagram along A-A direction of the structure shown, and

[0055] Figure 18 Schematic diagram of a structure obtained after forming a sacrificial layer and a conductive layer in some embodiments of the present disclosure; wherein, Figure 18 Figure (a) inFigure 18 Figure (b) in [reference] is a schematic cross-sectional view of the shown structure along the B-B direction;

[0056] Figure 19 Figure [reference] is a schematic structural view of a structure obtained after forming a first dielectric layer and a second electrode in some embodiments of the present disclosure; wherein, Figure 19 Figure (a) in [reference] is a schematic cross-sectional view of the shown structure along the A-A direction, Figure 19 Figure (b) in [reference] is a schematic cross-sectional view of the shown structure along the B-B direction;

[0057] Figure 20 Figure [reference] is a schematic structural view of a structure obtained after forming a second dielectric layer and a third electrode in some embodiments of the present disclosure; wherein, Figure 20 Figure (a) in [reference] is a schematic cross-sectional view of the shown structure along the A-A direction, Figure 20 Figure (b) in [reference] is a schematic cross-sectional view of the shown structure along the B-B direction.

[0058] Reference numerals:

[0059] 1 - Substrate, N - Stacked structure, N1 - First part, N2 - Second part, L1 - First dielectric layer, L2 - Second dielectric layer, L3 - Conductive layer, H1 - First etching hole, H2 - Second etching hole, G1 - First accommodating groove, G2 - Second accommodating groove, 2 - Isolation structure, 3 - Capacitor, 31 - First electrode, 310 - First electrode material layer, 32 - First dielectric layer, 33 - Second electrode, 34 - Second dielectric layer, 340 - Second dielectric material layer, 35 - Third electrode, 36 - Contact layer, 331 and 351 - Titanium nitride layer, 3510 - Titanium nitride material layer, 332 and 352 - Polysilicon layer, 3520 - Polysilicon material layer, 4 - Sacrificial layer. Detailed implementation manners

[0060] To facilitate the understanding of the present disclosure, the present disclosure will be described more comprehensively below with reference to the relevant drawings. Embodiments of the present disclosure are shown in the drawings. However, the present disclosure can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, these embodiments are provided to make the disclosure of the present disclosure more thorough and comprehensive.

[0061] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those of ordinary skill in the technical field to which the present disclosure belongs. The terms used in the specification of the present disclosure herein are only for the purpose of describing specific embodiments and are not intended to limit the present disclosure.

[0062] As used herein, "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment can be included in at least one embodiment of the present disclosure. The phrase appears in various places in the specification and does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment mutually exclusive with other embodiments. Those skilled in the art will explicitly and implicitly understand that the embodiments described herein can be combined with other embodiments.

[0063] It will be understood that the terms "first", "second", "third", "fourth", etc. used in this application may be used herein to describe various elements, but these elements are not limited by these terms. These terms are only used to distinguish one element from another. For example, without departing from the scope of this application, the first transistor may be referred to as the second transistor, and similarly, the second transistor may be referred to as the first transistor. Both the first transistor and the second transistor are transistors, but they are not the same transistor.

[0064] It will be understood that in the following embodiments, "connection", if there is a transfer of electrical signals or data between the connected circuits, modules, units, etc., should be understood as "electrical connection", "communication connection", etc.

[0065] As used herein, the singular forms "a", "an", and "the" may also include the plural forms unless the context clearly dictates otherwise. It should also be understood that the terms "comprise / include" or "have" etc. specify the presence of the stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not preclude the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. At the same time, the term "and / or" used in this specification includes any and all combinations of the related listed items.

[0066] Please refer to Figure 1 , some embodiments of the present disclosure provide a method for preparing a semiconductor structure, including steps S100 to S1100.

[0067] S100, provide a substrate, and alternately form a plurality of first dielectric layers and a plurality of second dielectric layers on the substrate along a direction perpendicular to the substrate.

[0068] Exemplarily, the first dielectric layer includes but is not limited to an oxide layer, for example, it may be a silicon oxide layer. The second dielectric layer includes but is not limited to a nitride layer, for example, it may be a silicon nitride layer.

[0069] S200, etch the multiple layers of the first dielectric layer and the multiple layers of the second dielectric layer in a direction perpendicular to the substrate to form a stacked structure; the stacked structure includes a first part extending in a first direction and a plurality of second parts spaced apart in the first direction and extending from the first part in a second direction; the first direction and the second direction are parallel to the substrate and intersect.

[0070] S300, fill an isolation structure in the etched area of the multiple layers of the first dielectric layer and the multiple layers of the second dielectric layer.

[0071] Exemplarily, the material of the isolation structure can be the same as that of the first dielectric layer to facilitate subsequent synchronous etching.

[0072] S400, etch the stacked structure to form a first etching hole penetrating the second part in a direction perpendicular to the substrate.

[0073] S500, etch the sidewalls of the second dielectric layer based on the first etching hole to expose the isolation structure at least in the first direction, forming a first accommodation groove.

[0074] S600, form a first electrode in the first accommodation groove.

[0075] Exemplarily, the first electrode includes, but is not limited to, a titanium nitride layer.

[0076] S700, form a sacrificial layer covering the first electrode and filling the first etching hole.

[0077] Exemplarily, the sacrificial layer includes, but is not limited to, a low-K (low-dielectric constant) dielectric layer.

[0078] Here, K is the dielectric constant, which is used to measure the ability of a material to store charge. Generally, materials can be classified into low-dielectric (low-K) materials and high-dielectric (high-K) materials according to the value of K; generally, the K value of low-dielectric (low-K) materials is less than 3.0.

[0079] S800, etch the isolation structure to form a second etching hole penetrating the isolation structure in a direction perpendicular to the substrate and located between adjacent first electrodes in the first direction.

[0080] S900, sequentially form a first dielectric layer covering the first electrode and a second electrode covering the first dielectric layer and filling the second etching hole in the second etching hole.

[0081] Exemplarily, the first dielectric layer includes, but is not limited to, a high-K (high-dielectric constant) dielectric layer, where the K value of the high-dielectric (high-K) material is greater than 3.9.

[0082] Exemplarily, the second electrode includes, but is not limited to, a titanium nitride layer and a polysilicon layer stacked in a direction away from the first dielectric layer.

[0083] S1000, remove the sacrificial layer.

[0084] S1100, a second dielectric layer covering the first electrode and a third electrode covering the second dielectric layer and filling the first etching hole are sequentially formed in the first etching hole.

[0085] Exemplarily, the second dielectric layer includes, but is not limited to, a high-K dielectric layer, wherein the K value of the high-K material is greater than 3.9.

[0086] Exemplarily, the third electrode includes, but is not limited to, a titanium nitride layer and a polysilicon layer stacked in a direction away from the second dielectric layer.

[0087] As described above, by using the above preparation method provided by the embodiments of the present disclosure, a capacitor conducive to realizing three-dimensional stacking can be prepared. The capacitor includes: a first electrode, a second electrode located outside the first electrode, and a third electrode located inside the first electrode.

[0088] In the embodiments of the present disclosure, based on the alternately stacked multiple first dielectric layers and multiple second dielectric layers, a stacked structure can be patterned and an isolation structure can be filled. Then, by forming a first etching hole and etching the second dielectric layer to form a first accommodation groove, the first electrode can be directly formed in the first accommodation groove. In this way, compared with the deep high-aspect-ratio etching process of a metal thin film, the process difficulty and production cost can be effectively reduced.

[0089] On this basis, after forming a sacrificial layer in the first etching hole in the embodiments of the present disclosure, a second etching hole can be formed by etching the isolation structure between adjacent first electrodes, so that a first dielectric layer and a second electrode are sequentially formed in the second etching hole; and, after removing the sacrificial layer, a second dielectric layer and a third electrode can be sequentially formed in the first etching hole. In this way, the capacitor includes a first electrode, a second electrode located outside the first electrode, and a third electrode located inside the first electrode, which not only helps to simplify the preparation process of the capacitor, but also helps to increase the effective electrode area in the capacitor to increase the capacitance value of the capacitor, thereby improving the electrical performance of the capacitor and the electronic device.

[0090] In addition, in the embodiments of the present disclosure, the first electrode is made of a titanium nitride layer, which can avoid problems such as metal diffusion and metal oxidation caused by direct contact between the first electrode made of a metal element (such as tungsten) and the high-K dielectric layer (such as the first dielectric layer and the second dielectric layer), and is beneficial to ensuring the reliability of the capacitor.

[0091] In some embodiments of the present disclosure, forming the first electrode in the first accommodation groove in step S600 may include: forming a first electrode that fills the first accommodation groove; or, forming a first electrode that conformally covers the inner wall of the first accommodation groove.

[0092] It can be understood that the first accommodation groove is obtained by widening based on the first etching hole, which can ensure that the first electrode formed in the first accommodation groove is in an annular structure. Correspondingly, filling the first electrode into the first accommodation groove means that the inner ring wall of the first electrode is flush with the inner wall of the first etching hole, that is, they can form the same surface, and this surface can be a plane or a curved surface. The conformal coverage of the inner wall of the first accommodation groove by the first electrode means that the first electrode is a thin-layer structure, and the surface of the first electrode conforms to the inner wall of the first accommodation groove, so that the surface shape of the first electrode is similar to the surface shape of the inner wall of the first accommodation groove.

[0093] In some embodiments of the present disclosure, forming the first electrode in the first accommodation groove in step S600 may include steps S610 to S620.

[0094] S610, deposit a first electrode material layer in the first etching hole and the first accommodation groove.

[0095] S620, remove the first electrode material layer on the inner wall of the first etching hole, so that the first electrode material layer remaining in the first accommodation groove forms the first electrode.

[0096] It should be added that the first accommodation groove is formed by wet etching the second dielectric layer.

[0097] In some embodiments of the present disclosure, please refer to Figure 2 , after forming the sacrificial layer and before forming the second etching hole, the manufacturing method of the semiconductor structure may further include S750.

[0098] S750, remove the remaining second dielectric layers in the stacked structure, and form a conductive layer in the removal area of the second dielectric layer.

[0099] Exemplarily, the conductive layer includes but is not limited to a metal conductive layer, for example, it can be a single layer or a stacked layer of titanium nitride or tungsten.

[0100] In the embodiments of the present disclosure, the second dielectric layer in contact connection with the first electrode is replaced with a conductive layer, and this conductive layer includes, for example, a metal conductive layer or a semiconductor conductive layer with a doping type. In this way, it is beneficial to prepare other electrical components connected to the first electrode based on this conductive layer, and it is beneficial to reduce the contact resistance by selecting the materials of the first electrode and the conductive layer, thereby improving the electrical performance of the capacitor.

[0101] It should be added that in some embodiments of the present disclosure, the manufacturing method of the semiconductor structure further includes: after forming the second etching hole and before forming the first dielectric layer, wet-etch the first dielectric layer in the target areas above and below the first electrode to expose the sacrificial layer at least in the first direction and connect adjacent second etching holes to form a second accommodation groove.

[0102] Accordingly, a first dielectric layer is further formed on the inner wall of the second receiving groove, and the second electrode further fills the second receiving groove.

[0103] In some embodiments of the present disclosure, step S1100 of sequentially forming a second dielectric layer covering the first electrode and a third electrode covering the second dielectric layer and filling the first etching hole in the first etching hole may include steps S1101 to S1103.

[0104] S1101, form a second dielectric material layer on the exposed surface of the first electrode facing away from the first dielectric layer, the exposed surface of the first dielectric layer facing away from the second electrode, and the top surface of the second electrode.

[0105] S1102, form a third electrode material layer covering the exposed surface of the second dielectric material layer and filling the first etching hole.

[0106] S1103, polish the third electrode material layer and the second dielectric material layer until the top surface of the second electrode is exposed, so that the second dielectric material layer remaining in the first etching hole constitutes the second dielectric layer, and the third electrode material layer remaining in the first etching hole constitutes the third electrode.

[0107] Accordingly, please continue to refer to Figure 2 , the method for manufacturing the semiconductor structure further includes: S1200.

[0108] S1200, form a contact layer on the top surfaces of the second electrodes and the third electrodes, and the contact layer interconnects the second electrodes and the third electrodes.

[0109] Exemplarily, the contact layer includes, but is not limited to, a polysilicon layer.

[0110] In the above embodiments of the present disclosure, unless otherwise clearly stated in this article, the execution of each step in the method does not have a strict order limitation, and these steps may not necessarily be executed in the described order, and there may be other execution manners. Moreover, at least a part of each step may include multiple sub-steps or multiple stages. These sub-steps or stages do not necessarily need to be executed at the same time, but may be executed at different times. The execution order of these sub-steps or stages is not necessarily sequential, but may be executed alternately or alternately with at least a part of other steps or sub-steps or stages of other steps.

[0111] To more clearly illustrate the method for manufacturing the semiconductor structure described in the above some embodiments, the following some embodiments are described in detail by taking the Figure 2 shown method as an example, and please refer to Figures 3 to 20 for understanding.

[0112] In step S100, please refer to Figure 3In FIGS. (a) and (b), a substrate 1 is provided, and a plurality of first dielectric layers L1 and a plurality of second dielectric layers L2 are alternately formed on the substrate 1 along a direction perpendicular to the substrate (e.g., the Z direction).

[0113] Exemplarily, the first dielectric layer L1 is a silicon oxide layer. The second dielectric layer L2 is a silicon nitride layer.

[0114] Exemplarily, the substrate 1 can be composed of a semiconductor material, an insulating material, a conductive material, or any combination thereof. The substrate 1 can be a single-layer structure or a multi-layer structure. For example, the substrate 1 can be a substrate such as a silicon (Si) substrate, a silicon germanium (SiGe) substrate, a silicon germanium carbon (SiGeC) substrate, a silicon carbide (SiC) substrate, a gallium arsenide (GaAs) substrate, an indium arsenide (InAs) substrate, an indium phosphide (InP) substrate, or other III / V semiconductor substrates or II / VI semiconductor substrates. Or, for another example, the substrate 1 can be a layered substrate including, for example, Si / SiGe, Si / SiC, silicon on insulator (SOI), or silicon germanium on insulator.

[0115] Exemplarily, the number of stacked layers of the first dielectric layer L1 and the second dielectric layer L2 can be selected and set according to requirements. Moreover, the alternating stacking of the first dielectric layer L1 and the second dielectric layer L2 can start with the first dielectric layer L1 and end with the first dielectric layer L1. The following embodiments of the present disclosure are described in detail by taking this as an example, but it is not limited thereto. For example, starting with the second dielectric layer L2 and ending with the first dielectric layer L1 is also allowed.

[0116] Exemplarily, the formation process of the first dielectric layer L1 and the second dielectric layer L2 includes, but is not limited to, a chemical vapor deposition process.

[0117] In step S200, please refer to Figure 4 FIGS. (a) and (b), etch a plurality of first dielectric layers L1 and a plurality of second dielectric layers L2 along a direction perpendicular to the substrate (e.g., the Z direction) to form a stacked structure N; the stacked structure N includes a first part N1 extending along a first direction (e.g., the Y direction) and a plurality of second parts N2 spaced apart in the first direction (e.g., the Y direction) and extending from the first part N1 along a second direction (e.g., the X direction); the first direction (e.g., the Y direction) and the second direction (e.g., the X direction) are parallel to the substrate 1 and intersect, for example, orthogonally.

[0118] Exemplarily, the stacked structure N is patterned by a dry etching process.

[0119] Exemplarily, before etching the plurality of first dielectric layers L1 and the plurality of second dielectric layers L2 to form the stacked structure N, a hard mask layer can be formed on the top surface of the top first dielectric layer L1 to form the stacked structure N based on the mask pattern in the hard mask layer.

[0120] Exemplarily, the first part N1 in the stacked structure N can be used to define the orthographic projection shape of the bit line forming region on the substrate 1, and the second part N2 can be used to define the orthographic projection shape of the forming regions of the transistors and capacitors on the substrate 1. In addition, it can be understood that the first part N1 and the second part N2 are only the divisions of the orthographic projection shape of the stacked structure N on the substrate 1, and both include the foregoing first dielectric layers L1 and second dielectric layers L2 in the direction perpendicular to the substrate (for example, the Z direction).

[0121] In step S300, please continue to refer to Figure 4 Figures (a) and (b) in, and fill the etching regions of the multiple first dielectric layers L1 and the multiple second dielectric layers L2 with the isolation structure 2.

[0122] Exemplarily, the material of the isolation structure 2 can be the same as that of the first dielectric layer L1, such as silicon oxide, for the convenience of subsequent synchronous etching.

[0123] Exemplarily, after filling and forming the isolation structure 2, the surface of the obtained structure can be polished by a chemical mechanical polishing process to expose the flat top first dielectric layer L1.

[0124] In step S400, please refer to Figure 5 Figures (a) and (b) in, and etch the stacked structure N to form a first etching hole H1 that penetrates the second part N2 in the direction perpendicular to the substrate (for example, the Z direction).

[0125] Exemplarily, the first etching hole H1 is formed by a dry etching process.

[0126] Exemplarily, the dimension of the first etching hole H1 in the first direction (for example, the Y direction) is slightly smaller than the dimension of the second part N2 in the first direction (for example, the Y direction).

[0127] In step S500, please refer to Figure 6 Figures (a), (b) in, and Figures (a), (b) in, and etch the side walls of the second dielectric layer L2 based on the first etching hole H1 to expose the isolation structure 2 at least in the first direction (for example, the Y direction) to form a first accommodation groove G1.

[0128] Exemplarily, the first accommodation groove G1 is formed by wet etching the second dielectric layer L2. The first accommodation groove G1 is an annular groove surrounding the periphery of the first etching hole H1.

[0129] In step S600, please refer to Figure 7 Figures (a), (b) in, and Figure 8 Figures (a), (b) in, and form a first electrode 31 in the first accommodation groove G1.

[0130] Exemplarily, the first electrode 31 includes but is not limited to a titanium nitride layer.

[0131] Exemplarily, forming the first electrode 31 in the first receiving groove G1 in step S600 may include: forming the first electrode 31 to fill the first receiving groove G1, as shown in FIGS. (a) and (b) of Figure 8 ; or, forming the first electrode 31 to conformally cover the inner wall of the first receiving groove G1, as shown in FIGS. (a) and (b) of Figures 16 to 20 .

[0132] Exemplarily, step S600 may include steps S610 to S620.

[0133] In step S610, referring to FIGS. (a) and (b) of Figure 7 , deposit the first electrode material layer 310 in the first etching hole H1 and the first receiving groove G1.

[0134] In step S620, referring to FIGS. (a) and (b) of Figure 8 , remove the first electrode material layer 310 on the inner wall of the first etching hole H1, so that the first electrode material layer 310 remaining in the first receiving groove G1 constitutes the first electrode 31.

[0135] In step S700, referring to FIGS. (a) and (b) of Figure 9 , form the sacrificial layer 4 that covers the first electrode 31 and fills the first etching hole H1.

[0136] Exemplarily, the sacrificial layer 4 includes but is not limited to a low-K dielectric layer. Here, K is the dielectric constant, which is used to measure the ability of the material to store charges. Generally, materials can be classified into low-K materials and high-K materials according to the level of the K value; generally, the K value of low-K materials is less than 3.0.

[0137] In step S750, continue to refer to FIGS. (a) and (b) of Figure 9 , remove each remaining second dielectric layer L2 in the stacked structure N, and form the conductive layer L3 in the removal area of the second dielectric layer L2.

[0138] Exemplarily, the conductive layer L3 includes but is not limited to a metal conductive layer, for example, it can be a single layer or a stack of titanium nitride or tungsten.

[0139] In some examples, the conductive layer L3 is a tungsten metal layer.

[0140] In step S800, referring to FIGS. (a) and (b) of Figure 10 , etch the isolation structure 2 to form the second etching hole H2 that penetrates the isolation structure 2 along the vertical direction of the substrate (e.g., the Z direction) and is located between adjacent first electrodes 31 along the first direction (e.g., the Y direction).

[0141] Exemplarily, the second etching hole H2 is formed by a dry etching process.

[0142] Exemplarily, after the second etching hole H2 is formed, the first dielectric layer L1 in the target areas on the upper and lower sides of the first electrode 31 is removed by wet etching to expose the sacrificial layer 4 at least in a first direction (e.g., the Y direction) and connect adjacent second etching holes H2, thereby forming a second accommodation groove G2.

[0143] Here, it can be understood that only a small amount of the first dielectric layer L1 in the target areas on the upper and lower sides of the first electrode 31 is removed, that is, a wet etching process is used to expose the side wall of the sacrificial layer 4 in the first direction (e.g., the Y direction) and connect adjacent second etching holes H2.

[0144] In step S900, please refer to Figure 11 Figures (a) and (b) in, a first dielectric layer 32 covering the first electrode 31 and a second electrode 33 covering the first dielectric layer 32 and filling the second etching hole H2 are sequentially formed in the second etching hole H2.

[0145] It can be understood that in the example where the second accommodation groove G2 is formed, the entire first dielectric layer 32 is deposited in the second etching hole H2 and the second accommodation groove G2, that is, the first dielectric layer 32 also covers the inner wall of the second accommodation groove G2. Correspondingly, the second electrode 33 also fills the second accommodation groove G2.

[0146] Exemplarily, the first dielectric layer 32 includes but is not limited to a high-K (high-K) dielectric layer, where the K value of the high dielectric (high-K) material is greater than 3.9.

[0147] Exemplarily, the second electrode 33 includes but is not limited to a titanium nitride layer 331 and a polysilicon layer 332 stacked in a direction away from the first dielectric layer 32.

[0148] In step S1000, please refer to Figure 12 Figures (a) and (b) in, the sacrificial layer 4 is removed.

[0149] Exemplarily, the sacrificial layer 4 can be removed by dry etching or wet etching.

[0150] In step S1100, please refer to Figure 13 and Figure 14 Figures (a) and (b) in, a second dielectric layer 34 covering the first electrode 31 and a third electrode 35 covering the second dielectric layer 34 and filling the first etching hole H1 are sequentially formed in the first etching hole H1.

[0151] Exemplarily, the second dielectric layer 34 includes, but is not limited to, a high-K dielectric layer, wherein the K value of the high-K material is greater than 3.9.

[0152] Exemplarily, the third electrode 35 includes, but is not limited to, a titanium nitride layer 351 and a polysilicon layer 352 stacked in a direction away from the second dielectric layer 34.

[0153] In some embodiments of the present disclosure, step S1100 may include steps S1101 to S1103.

[0154] In step S1101, refer to Figure 13 to form a second dielectric material layer 340 on the exposed surface of the first electrode 31 facing away from the first dielectric layer 32, the exposed surface of the first dielectric layer 32 facing away from the second electrode 33, and the top surface of the second electrode 33.

[0155] In step S1102, continue to refer to Figure 13 to form a third electrode material layer covering the exposed surface of the second dielectric material layer 340 and filling the first etching hole H1, such as a stacked titanium nitride material layer 3510 and a polysilicon material layer 3520.

[0156] In step S1103, refer to Figure 14 figures (a) and (b) in

[0157] to grind the third electrode material layer (including the polysilicon material layer 3520 and the titanium nitride material layer 3510) and the second dielectric material layer 340 until the top surface of the second electrode 33 is exposed, so that the second dielectric material layer 340 remaining in the first etching hole H1 constitutes the second dielectric layer 34, and the third electrode material layer remaining in the first etching hole H1 constitutes the third electrode 35; for example, the titanium nitride material layer 3510 remaining in the first etching hole H1 constitutes the titanium nitride layer 351, the polysilicon material layer 3520 remaining in the first etching hole H1 constitutes the polysilicon layer 352, and the third electrode 35 includes the titanium nitride layer 351 and the polysilicon layer 352. Figure 15 to form a contact layer 36 on the top surfaces of the second electrodes 33 and the third electrodes 35, and the contact layer 36 interconnects the second electrodes 33 and the third electrodes 35.

[0158] Exemplarily, the contact layer 36 includes, but is not limited to, a polysilicon layer.

[0159] As described above, by using the above preparation method provided by the embodiments of the present disclosure, a capacitor 3 that is conducive to realizing three-dimensional stacking can be prepared. The capacitor 3 includes: a first electrode 31, a second electrode 33 located outside the first electrode 31, and a third electrode 35 located inside the first electrode 31.

[0160] It should be noted that Figures 16 to 20 Taking the example that the first electrode 31 conformally covers the inner wall of the first accommodating groove G1, the subsequent steps of the manufacturing method of the semiconductor structure provided by the embodiments of the present disclosure are schematically shown. It can be understood adaptively in combination with the descriptions of the foregoing related steps, and will not be elaborated here.

[0161] Some embodiments of the present disclosure also provide a semiconductor structure, which can be manufactured by using the manufacturing methods in some of the above embodiments. The semiconductor structure also has all the technical advantages of the foregoing manufacturing methods.

[0162] In some embodiments, please refer to Figure 14 the (a) figure and (b) figure in Figure 20 and the (a) figure and (b) figure in

[0163] to understand that the semiconductor structure includes: a substrate 1, a plurality of first electrodes 31, a plurality of first dielectric layers 32, a plurality of second electrodes 33, a plurality of second dielectric layers 34, and a plurality of third electrodes 35.

[0163] In some examples, the plurality of first electrodes 31 are spaced apart along a first direction (e.g., the Y direction) parallel to the substrate 1. The first electrode 31 has an annular structure and the axial direction of the annular structure is perpendicular to the substrate 1 (e.g., extending along the Z direction).

[0164] Exemplarily, the plurality of first electrodes 31 are three-dimensionally stacked along a direction perpendicular to the substrate (e.g., the Z direction).

[0165] Exemplarily, the shape of the orthographic projection of the first electrode 31 on the substrate 1 is a rectangle, a circle, an ellipse, or the like.

[0166] Exemplarily, the first electrode 31 includes, but is not limited to, a titanium nitride layer.

[0167] In some examples, the first dielectric layer 32 covers the inner sidewall of the first electrode 31 and extends along a direction perpendicular to the substrate (e.g., the Z direction) to the surface of the substrate 1 to form a cup-shaped structure. The second electrode 33 covers the surface of the corresponding first dielectric layer 32 facing away from the first electrode 31 and fills the cup-shaped inner region of the first dielectric layer 32.

[0168] Here, matching the sidewall shape of the first electrode 31, the inner and / or outer sides of the cup wall of the first dielectric layer 32 can be a flat surface or a non-flat surface having protrusions and depressions for fitting with the first electrode 31 (e.g., Figure 14 and Figure 20 as shown in

[0169] In some examples, the second dielectric layer 34 is located between two first electrodes 31 adjacent along the first direction (e.g., the Y direction), covers the outer sidewalls of the corresponding first electrodes 31, and extends in the direction perpendicular to the substrate (e.g., the Z direction) to cover the surface of the first dielectric layer 32 facing away from the second electrode 33, and extends to the surface of the substrate 1 to form a cup-shaped structure. The third electrode 35 covers the surface of the corresponding second dielectric layer 34 facing away from the first electrode 31 and fills the cup-shaped region inside the second dielectric layer 34.

[0170] Here, matching the sidewall shape of the first electrode 31, the inner and / or outer sides of the cup wall of the second dielectric layer 34 can be a flat surface (e.g., as shown in Figure 14 ), or a non-flat surface with protrusions and depressions for fitting with the first electrode 31 (e.g., as shown in Figure 20 ).

[0171] Exemplarily, both the first dielectric layer 32 and the second dielectric layer 34 include but are not limited to high-K dielectric layers. The material of the high-K dielectric layer can be selected and set according to requirements, and the embodiments of the present disclosure do not limit this.

[0172] Exemplarily, the second electrode 33 includes but is not limited to a titanium nitride layer 331 and a polysilicon layer 332 stacked in the direction away from the first dielectric layer 32.

[0173] Exemplarily, the third electrode 35 includes but is not limited to a titanium nitride layer 351 and a polysilicon layer 352 stacked in the direction away from the second dielectric layer 35.

[0174] In some embodiments, please refer to Figure 15 for understanding. The semiconductor structure further includes: a contact layer 36. The contact layer 36 is located on the top surfaces of the second electrodes 33 and the third electrodes 35, and interconnects the second electrode 32 and the third electrode 35. In this way, it is convenient to prepare and use the contact layer 36 to realize the interconnection between the second electrodes 33 and the third electrodes 35.

[0175] Exemplarily, the contact layer 36 includes but is not limited to a polysilicon layer.

[0176] In summary, in the embodiments of the present disclosure, the structure of the capacitor 3 and the material of the first electrode 31 in the capacitor 3 are optimized. Based on the thin film stack structure of the first dielectric layer L1 and the second dielectric layer L2, the second dielectric layer L2 can be selectively replaced with the first electrode 31 and the corresponding conductive layer L3, thereby avoiding the complexity of the process caused by the etching of the high aspect ratio of the metal film layer structure, which is beneficial to simplifying the process and reducing costs. Moreover, the capacitor 3 provided by the embodiments of the present disclosure reduces the implementation of the lateral etching process of the first dielectric layer L1, and is also beneficial to providing stable process mechanical properties and support properties during the preparation process of the capacitor 3, so as to improve the process yield.

[0177] In addition, in the embodiments of the present disclosure, the first electrode 31 of the capacitor 3 is made of a titanium nitride layer, which can avoid using a simple metal such as tungsten as the first electrode 31 in contact with the high-K dielectric layer, thereby avoiding the risks of metal diffusion and metal oxidation, and being beneficial to ensuring the reliability of the capacitor 3. In the embodiments of the present disclosure, the first electrode 31 of the capacitor 3 adopts an annular structure, and the first dielectric layer 32 and the second dielectric layer 34 adopt a cup-shaped structure, which is also beneficial to providing surrounding outer electrodes (i.e., the second electrode 33 and the third electrode 35) on both the inner and outer sides of the first electrode 31, so as to be beneficial to increasing the capacitance value of the capacitor 3, for example, effectively improving the storage performance of the capacitor 3.

[0178] Some embodiments of the present disclosure also provide an electronic device, such as a data storage device, a photocopier, a network device, a household appliance, an instrument, a mobile phone, a computer, and other devices with data storage functions. The electronic device may include a housing, a circuit board disposed in the housing, and a memory integrated on the circuit board. The memory includes a plurality of storage units, and the storage units include capacitors. The structure and manufacturing method of the capacitors can refer to the relevant descriptions in the above-mentioned embodiments. Other necessary elements or components may also be included in the electronic device, which are not limited in the embodiments of the present disclosure.

[0179] In some embodiments, the memory may be coupled to an external control device such as a processor or an actuator. The processor is coupled to the memory, and the processor can control the read and write operations of the memory.

[0180] The technical features of the above-described embodiments can be combined arbitrarily. For the sake of brevity of description, not all possible combinations of the technical features of the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, it should be considered as the scope described in this specification.

[0181] The above-described embodiments merely represent several implementation manners of the present disclosure, and their descriptions are relatively specific and detailed, but should not be construed as a limitation on the scope of the patent application. It should be noted that for those of ordinary skill in the art, without departing from the concept of the present disclosure, several modifications and improvements can be made, and these all belong to the protection scope of the present disclosure. Therefore, the protection scope of the patent of the present disclosure should be subject to the appended claims.

Claims

1. A method for fabricating a semiconductor structure, characterized in that, comprising: providing a substrate, and alternately forming a plurality of first dielectric layers and a plurality of second dielectric layers on the substrate along a direction perpendicular to the substrate; etching the plurality of first dielectric layers and the plurality of second dielectric layers along a direction perpendicular to the substrate to form a stacked structure; the stacked structure includes a first portion extending along a first direction and a plurality of second portions spaced apart from each other in the first direction and extending from the first portion along a second direction; the first direction and the second direction are parallel to the substrate and intersect; filling an isolation structure in the etching regions of the plurality of first dielectric layers and the plurality of second dielectric layers; etching the stacked structure to form a first etching hole penetrating through the second portion along a direction perpendicular to the substrate; etching the sidewalls of the second dielectric layer based on the first etching hole to expose at least the isolation structure in the first direction, thereby forming a first accommodation groove; forming a first electrode in the first accommodation groove; forming a sacrificial layer covering the first electrode and filling the first etching hole; etching the isolation structure to form a second etching hole penetrating through the isolation structure along a direction perpendicular to the substrate and located between adjacent first electrodes in the first direction; sequentially forming a first dielectric layer covering the first electrode and a second electrode covering the first dielectric layer and filling the second etching hole in the second etching hole; removing the sacrificial layer; sequentially forming a second dielectric layer covering the first electrode and a third electrode covering the second dielectric layer and filling the first etching hole in the first etching hole; wherein, the capacitor includes: the first electrode, the second electrode located outside the first electrode, and the third electrode located inside the first electrode.

2. The method for fabricating a semiconductor structure according to claim 1, characterized in that, the forming a first electrode in the first accommodation groove includes: forming the first electrode to fill the first accommodation groove; or, forming the first electrode to conformally cover the inner wall of the first accommodation groove.

3. The method for fabricating a semiconductor structure according to claim 1, characterized in that, the forming a first electrode in the first accommodation groove includes: depositing a first electrode material layer in the first etching hole and the first accommodation groove; removing the first electrode material layer on the inner wall of the first etching hole, such that the first electrode material layer remaining in the first accommodation groove constitutes the first electrode.

4. The method for fabricating a semiconductor structure according to claim 1, characterized in that, the first accommodation groove is formed by wet etching the second dielectric layer.

5. The method for fabricating a semiconductor structure according to claim 1, characterized in that, further comprising: after forming the sacrificial layer and before forming the second etching hole, removing each of the second dielectric layers remaining in the stacked structure, and forming a conductive layer in the removal region of the second dielectric layer.

6. The method for fabricating a semiconductor structure according to claim 1, characterized in that, further comprising: After forming the second etching hole and before forming the first dielectric layer, the first dielectric layer in the target regions on the upper and lower sides of the first electrode is removed by wet etching to expose the sacrificial layer at least in the first direction and connect adjacent second etching holes, thereby forming a second accommodation groove. Wherein, the first dielectric layer is further formed on the inner wall of the second accommodation groove, and the second electrode further fills the second accommodation groove.

7. The method for manufacturing a semiconductor structure according to claim 6, characterized in that successively forming a second dielectric layer covering the first electrode and a third electrode covering the second dielectric layer and filling the first etching hole in the first etching hole includes: forming a second dielectric material layer on the exposed surface of the first electrode facing away from the first dielectric layer, the exposed surface of the first dielectric layer facing away from the second electrode, and the top surface of the second electrode; forming a third electrode material layer covering the exposed surface of the second dielectric material layer and filling the first etching hole; grinding the third electrode material layer and the second dielectric material layer until the top surface of the second electrode is exposed, so that the second dielectric material layer remaining in the first etching hole constitutes the second dielectric layer, and the third electrode material layer remaining in the first etching hole constitutes the third electrode; wherein, the manufacturing method further includes: forming a contact layer on the top surfaces of the second electrodes and the third electrodes, and the contact layer interconnects the second electrodes and the third electrodes.

8. The method for manufacturing a semiconductor structure according to any one of claims 1 to 7, characterized in that the first dielectric layer includes an oxide layer, the second dielectric layer includes a nitride layer, and the sacrificial layer includes a low-K dielectric layer.

9. A semiconductor structure, characterized in that including a substrate; a plurality of first electrodes, spaced apart along a first direction parallel to the substrate; the first electrode has an annular structure and the axial direction of the annular structure is perpendicular to the substrate; a plurality of first dielectric layers; the first dielectric layer covers the inner sidewall of the first electrode and extends in a direction perpendicular to the substrate to the substrate surface to form a cup-shaped structure; a plurality of second electrodes; the second electrode covers the surface of the corresponding first dielectric layer facing away from the first electrode and fills the cup-shaped region inside the first dielectric layer; a plurality of second dielectric layers; the second dielectric layer is located between two adjacent first electrodes along the first direction, covers the outer sidewall of the corresponding first electrode, and extends in a direction perpendicular to the substrate to cover the surface of the first dielectric layer facing away from the second electrode, and extends to the substrate surface to form a cup-shaped structure; a plurality of third electrodes; the third electrode covers the surface of the corresponding second dielectric layer facing away from the first electrode and fills the cup-shaped region inside the second dielectric layer.

10. The semiconductor structure according to claim 9, characterized in that further including: a contact layer, located on the top surfaces of the second electrodes and the third electrodes, and interconnecting the second electrodes and the third electrodes.

11. The semiconductor structure according to claim 10, characterized in that Both the first dielectric layer and the second dielectric layer include high-K dielectric layers; The first electrode includes a titanium nitride layer; Both the second electrode and the third electrode include a titanium nitride layer and a polysilicon layer stacked in a direction away from the corresponding dielectric layer.

12. An electronic device, comprising the semiconductor structure according to any one of claims 9 to 11.

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