Semiconductor structure and manufacturing method thereof

Abstract

The embodiment of the invention relates to the technical field of semiconductors, and provides a semiconductor structure and a manufacturing method thereof, and the semiconductor structure comprises a first doping structure which is provided with a first part, a second part and a third part which are sequentially arranged in a first direction; the second doped structure and the third doped structure are arranged at an interval, the second doped structure is in contact connection with the first part, and the third doped structure is in contact connection with the third part; wherein one of N-type doped ions and P-type doped ions is doped in the first doped structures, the other one of N-type doped ions and P-type doped ions is doped in the second doped structures and the third doped structures, and the two adjacent first doped structures in the second direction are in contact connection with the same third doped structure; the gate structure is provided with a first surface and a second surface which are opposite in a second direction, at least the first surface is in contact connection with the second part, and the second direction and the first direction intersect. The embodiment of the invention is at least beneficial to improving the electrical performance of the semiconductor structure.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to the field of semiconductor technologies, and in particular, to a semiconductor structure and a manufacturing method thereof. Background Art

[0002] Dynamic Random Access Memory (DRAM) is a memory component for storing programs and various data information. A DRAM generally includes a capacitor and a transistor connected to the capacitor. The capacitor is used to store charges representing the stored programs and various data information, and the transistor is a switch that controls the inflow and outflow of charges in the capacitor. When writing data, the word line gives a high level, the transistor conducts, and the bit line charges the capacitor. When reading data, the word line also gives a high level, the transistor conducts, and the capacitor discharges, causing the bit line to obtain a read signal.

[0003] However, with the continuous development of the manufacturing process of semiconductor structures, the process nodes of semiconductor structures are continuously reduced, making the sizes of various functional structures in the semiconductor structure gradually reduced, and the spacing between various functional structures gradually reduced. For example, the spacing between the capacitor and the bit line on the same side of the transistor is reduced, which easily increases the coupling effect between the capacitor and the bit line, resulting in a reduction in the electrical performance of the semiconductor structure. Summary of the Invention

[0004] Embodiments of the present disclosure provide a semiconductor structure and a manufacturing method thereof, which are at least beneficial to improving the electrical performance of the semiconductor structure.

[0005] According to some embodiments of the present disclosure, on the one hand, an embodiment of the present disclosure provides a semiconductor structure, including: a first doping structure having a first portion, a second portion, and a third portion arranged in sequence along a first direction; a second doping structure and a third doping structure arranged at intervals, the second doping structure being in contact connection with the first portion, and the third doping structure being in contact connection with the third portion; wherein, one of N-type doping ions and P-type doping ions is doped in the first doping structure, and the other of N-type doping ions and P-type doping ions is doped in the second doping structure and the third doping structure, and two adjacent first doping structures along a second direction are in contact connection with the same third doping structure, the second direction intersecting the first direction; a gate structure having a first surface and a second surface opposite to each other along the second direction, and at least the first surface or the second surface being in contact connection with the second portion.

[0006] In some embodiments, only the first surface or only the second surface of the gate structure is in contact connection with the second portion.

[0007] In some embodiments, the gate structure has a third surface and a fourth surface that are opposite to each other along the first direction, at least a portion of the third surface is also in contact connection with the second portion, and at least a portion of the fourth surface is also in contact connection with the second portion.

[0008] In some embodiments, the gate structure has a third surface and a fourth surface that are opposite to each other along the first direction, and the second surface and the fourth surface are also in contact connection with the second portion.

[0009] In some embodiments, the semiconductor structure further includes: an isolation layer that is in contact connection with the third surface, and both the isolation layer and the gate structure are embedded in the first doped structure.

[0010] In some embodiments, the semiconductor structure further includes: an active region, the active region includes two of the first doped structures that are adjacent to each other along the second direction, and two gate structures that are in contact connection with the two first doped structures are spaced apart from each other and are both located in the active region.

[0011] In some embodiments, at least a portion of the second doped structure is embedded in the first portion, and / or at least a portion of the third doped structure is embedded in the third portion.

[0012] In some embodiments, a plurality of the first doped structures and a plurality of the second doped structures are arranged at intervals along the third direction, and the first doped structures, the second doped structures, and the gate structures arranged at intervals along the third direction all correspond one by one; the third doped structure extends along the third direction, and one third doped structure is in contact connection with a plurality of the first doped structures arranged at intervals along the third direction, and the first direction, the second direction, and the third direction intersect pairwise.

[0013] In some embodiments, a plurality of the first doped structures, a plurality of the second doped structures, and a plurality of the third doped structures are arranged at intervals along the third direction, and the first doped structures, the second doped structures, the third doped structures, and the gate structures arranged at intervals along the third direction all correspond one by one; the semiconductor structure further includes: a conductive layer that extends along the third direction, and the same conductive layer is in contact connection with a plurality of the third doped structures arranged at intervals along the third direction.

[0014] In some embodiments, the gate structure is in contact connection with the third doped structure.

[0015] In some embodiments, the semiconductor structure further includes: a substrate, and the first doped structure, the second doped structure, the third doped structure, and the gate structure are all located in the substrate.

[0016] According to some embodiments of the present disclosure, on the other hand, an embodiment of the present disclosure further provides a method for manufacturing a semiconductor structure, including: providing an initial substrate; performing doping processes on different parts of the initial substrate to form a first doping structure, a second doping structure, and a third doping structure; wherein, the first doping structure has a first part, a second part, and a third part arranged in sequence along a first direction; the second doping structure and the third doping structure are arranged at intervals, the second doping structure is in contact connection with the first part, and the third doping structure is in contact connection with the third part; the first doping structure is doped with one of N-type doping ions and P-type doping ions, and the second doping structure and the third doping structure are doped with the other of N-type doping ions and P-type doping ions; two adjacent first doping structures along a second direction are in contact connection with the same third doping structure, and the second direction intersects with the first direction; forming a gate structure, the gate structure has a first surface and a second surface opposite to each other along the second direction, at least the first surface is in contact connection with the second part, and the gate structure is in contact connection with the third doping structure.

[0017] In some embodiments, the initial substrate has a front surface and a back surface opposite to each other along the first direction; the steps of forming the second doping structure and the third doping structure include: performing a first doping process on a partial region of the initial substrate to form a plurality of initial first doping structures arranged at intervals, the initial first doping structures extend from the front surface into the initial substrate, the initial first doping structures further extend along a fourth direction, and the initial first doping structures have a fourth part, a fifth part, and a sixth part arranged in sequence along the fourth direction; performing a second doping process on both the fourth part and the sixth part, along the first direction, such that a partial thickness of the fourth part is transformed into one of the second doping structures, and a partial thickness of the sixth part is transformed into the other second doping structure, and the second doping structures extend from the front surface into the initial substrate; performing patterning processing on the initial substrate from the back surface to expose at least a part of the fifth part; performing a third doping process on the exposed fifth part to form the third doping structure.

[0018] In some embodiments, a plurality of the fifth portions are arranged at intervals along a third direction, and the first direction, the second direction, and the third direction intersect pairwise; the patterning the initial substrate from the back surface includes: patterning the initial substrate from the back surface to form grooves extending along the third direction, and the grooves expose a plurality of the fifth portions arranged at intervals along the third direction; the performing a third doping process on the exposed fifth portions includes: performing the third doping process on the fifth portions exposed by the grooves to form the third doping structure extending along the third direction; the manufacturing method further includes: forming a first electrical connection layer, and the first electrical connection layer fills the grooves.

[0019] In some embodiments, a plurality of the fifth portions are arranged at intervals along a third direction, and the first direction, the second direction, and the third direction intersect pairwise; the patterning the initial substrate from the back surface includes: patterning the initial substrate from the back surface to form a plurality of through holes arranged at intervals along the third direction, and one through hole exposes one of the fifth portions; the performing a third doping process on the exposed fifth portions includes: performing the third doping process on the fifth portions exposed by the through holes to form a plurality of the third doping structures arranged at intervals along the third direction; the manufacturing method further includes: forming conductive posts, and the conductive posts fill the through holes, and the conductive posts and the through holes correspond to each other one by one; forming a second electrical connection layer extending along the third direction, and the same second electrical connection layer is in contact connection with a plurality of the conductive posts arranged at intervals along the third direction.

[0020] The technical solutions provided by the embodiments of the present disclosure have at least the following advantages:

[0021] The first part and the third part are arranged at intervals in the first direction. The second doping structure and the third doping structure are arranged at intervals. The second doping structure is in contact connection with the first part, and the third doping structure is in contact connection with the third part. Moreover, the second part is located between the first part and the third part, and the gate structure is in contact connection with the second part. In this way, the second doping structure and the third doping structure can be regarded as being on opposite sides of the gate structure along the first direction. That is, taking a plane parallel to the first direction as a reference plane, the second doping structure and the third doping structure are not directly opposite, that is, the orthographic projections of the second doping structure and the third doping structure on the reference plane do not overlap, so as to increase the distance between the second doping structure and the third doping structure, which is beneficial to reducing the coupling effect between the second doping structure and the third doping structure on each other. Further, after making a first conductive structure on one side of the second doping structure and the third doping structure away from the gate structure, and making a second conductive structure on the other side away from the gate structure, it is beneficial to avoid the first conductive structure and the second conductive structure being directly opposite, so as to reduce the coupling effect between the first conductive structure and the second conductive structure on each other, thereby improving the electrical performance of the semiconductor structure.

[0022] Moreover, it can be understood that the first doping structure, the second doping structure, the third doping structure and the gate structure together constitute a transistor structure. Among them, the second doping structure and the third doping structure do not directly contact, but the second doping structure and the third doping structure are respectively in contact connection with the first doping structure. That is, one of the second doping structure and the third doping structure can be used as the source electrode of the transistor structure, and the other can be used as the drain electrode of the transistor structure. A part of the first doping structure can be used as the channel region of the transistor structure, and the gate structure controls the conduction or cut-off of the channel region. Two adjacent first doping structures in the second direction are in contact connection with the same third doping structure, that is, two adjacent transistor structures in the second direction share a third doping structure, which is beneficial to improving the integration density of the transistor structures in the semiconductor structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] One or more embodiments are exemplarily illustrated by pictures in the corresponding drawings. These exemplary illustrations do not limit the embodiments. Elements with the same reference numerals in the drawings are represented as similar elements. Unless otherwise stated, the drawings in the figures do not constitute a proportional limitation. In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure or the prior art, the following will briefly introduce the drawings required to be used in the embodiments. Obviously, the following-described drawings are only some embodiments of the present disclosure. For those of ordinary skill in the art, other drawings can be obtained according to these drawings without creative efforts.

[0024] Figures 1 to 4 FIGS. 12A-12D are schematic diagrams of four partial cross-sectional structures of a semiconductor structure provided by an embodiment of the present disclosure;

[0025] Figure 5 A top view structural diagram of a semiconductor structure provided by an embodiment of the present disclosure;

[0026] Figure 6 and Figure 7 Two other partial cross-sectional structural diagrams of the semiconductor structure provided by an embodiment of the present disclosure;

[0027] Figure 8 and Figure 9 Two other top view structural diagrams of the semiconductor structure provided by an embodiment of the present disclosure;

[0028] Figure 10 Another partial cross-sectional structural diagram of the semiconductor structure provided by an embodiment of the present disclosure;

[0029] Figures 11 to 19 Cross-sectional structural diagrams corresponding to each step in the manufacturing method of the semiconductor structure provided by another embodiment of the present disclosure. Detailed implementation manners

[0030] As can be seen from the background art, the electrical performance of the semiconductor structure needs to be improved.

[0031] The present disclosure provides a semiconductor structure and a manufacturing method thereof. In the semiconductor structure, the second doping structure and the third doping structure can be regarded as being located on opposite sides of the gate structure along the first direction X. That is, with a plane parallel to the first direction X as a reference plane, the second doping structure and the third doping structure are not directly opposite, that is, the orthographic projections of the second doping structure and the third doping structure on the reference plane do not overlap, so as to increase the distance between the second doping structure and the third doping structure, thereby facilitating reducing the coupling effect of the second doping structure and the third doping structure on each other. Further, when conductive structures are respectively made on one side of the second doping structure and the third doping structure and the gate structure, it is beneficial to avoid the two conductive structures being directly opposite, thereby facilitating reducing the coupling effect of the two conductive structures on each other to improve the electrical performance of the semiconductor structure. Moreover, the first doping structure, the second doping structure, the third doping structure and the gate structure together constitute a transistor structure. Two adjacent first doping structures along the second direction are in contact connection with the same third doping structure, that is, two adjacent transistor structures along the second direction share one third doping structure, which is beneficial to improving the integration density of the transistor structures in the semiconductor structure.

[0032] The following will elaborate on each embodiment of the present disclosure with reference to the accompanying drawings. However, those of ordinary skill in the art can understand that in each embodiment of the present disclosure, many technical details are proposed for the reader to better understand the embodiments of the present disclosure. However, even without these technical details and various changes and modifications based on the following embodiments, the technical solutions required to be protected by the embodiments of the present disclosure can still be achieved.

[0033] One embodiment of the present disclosure provides a semiconductor structure, and the semiconductor structure provided by one embodiment of the present disclosure will be described in detail below with reference to the accompanying drawings. Figures 1 to 4 are schematic diagrams of four partial cross-sectional structures of the semiconductor structure provided by one embodiment of the present disclosure; Figure 5 is a schematic top view structure of the semiconductor structure provided by one embodiment of the present disclosure; Figure 6 and Figure 7 are schematic diagrams of two other partial cross-sectional structures of the semiconductor structure provided by one embodiment of the present disclosure; Figure 8 and Figure 9 are schematic diagrams of two other top view structures of the semiconductor structure provided by one embodiment of the present disclosure; Figure 10 is a schematic diagram of yet another partial cross-sectional structure of the semiconductor structure provided by one embodiment of the present disclosure. It should be noted that, for the convenience of description and to clearly illustrate the semiconductor structure, the Figures 1 to 10 in one embodiment of the present disclosure are all schematic diagrams of partial structures of the semiconductor structure.

[0034] Referring to Figures 1 to 4 , the semiconductor structure may include: a first doping structure 101 having a first portion 111, a second portion 121, and a third portion 131 arranged in sequence along a first direction X; a second doping structure 102 and a third doping structure 103 arranged at intervals, the second doping structure 102 being in contact connection with the first portion 111, and the third doping structure 103 being in contact connection with the third portion 131; wherein, the first doping structure 101 is doped with one of N-type doping ions and P-type doping ions, the second doping structure 102 and the third doping structure 103 are doped with the other of N-type doping ions and P-type doping ions, and two adjacent first doping structures 101 along a second direction Y are in contact connection with the same third doping structure 103, and the second direction Y intersects the first direction X; a gate structure 104 having a first surface 114 and a second surface 124 opposite to each other along the second direction Y, and at least the first surface 114 or the second surface 124 is in contact connection with the second portion 121.

[0035] In some embodiments, the first doping structure 101 may be doped with P-type doping ions, and the second doping structure 102 and the third doping structure 103 may be doped with N-type doping ions; in other embodiments, the first doping structure 101 may be doped with N-type doping ions, and the second doping structure 102 and the third doping structure 103 may be doped with P-type doping ions.

[0036] It should be noted that, for the convenience of description, hereinafter, an example will be given in which the first doping structure 101 may be doped with P-type doping ions, and the second doping structure 102 and the third doping structure 103 may be doped with N-type doping ions.

[0037] In some embodiments, the N-type doping ions may include at least one of arsenic ions, phosphorus ions, or antimony ions; the P-type doping ions may include at least one of boron ions, indium ions, or gallium ions.

[0038] It can be understood that the first doping structure 101, the second doping structure 102, the third doping structure 103, and the gate structure 104 together form a transistor structure. Among them, the second doping structure 102 and the third doping structure 103 do not directly contact each other, but the second doping structure 102 and the third doping structure 103 are respectively in contact with the first doping structure 101. That is, one of the second doping structure 102 and the third doping structure 103 can be used as the source of the transistor structure, and the other can be used as the drain of the transistor structure. A part of the first doping structure 101 can be used as the channel region of the transistor structure, and the gate structure 104 controls the conduction or cutoff of the channel region. It should be noted that for the convenience of description, hereinafter, the second doping structure 102 is used as the drain of the transistor structure, and the third doping structure 103 is used as the source of the transistor structure as an example for illustration.

[0039] In this way, two adjacent first doping structures 101 along the second direction Y are in contact with the same third doping structure 103, that is, two adjacent transistor structures along the second direction Y share a third doping structure 103, which is beneficial to improving the integration density of the transistor structures in the semiconductor structure.

[0040] It should be noted that in the gate structure 104, at least the first surface 114 is in contact with the second part 121, and the relative positional relationship between the gate structure 104 and the second part 121 will be described in detail later.

[0041] It can be understood that the first part 111 and the third part 131 are arranged at intervals along the first direction X, the second doping structure 102 and the third doping structure 103 are arranged at intervals, the second doping structure 102 is in contact connection with the first part 111, the third doping structure 103 is in contact connection with the third part 131, and the second part 121 is located between the first part 111 and the third part 131. The gate structure 104 is in contact connection with the second part 121. In this way, the second doping structure 102 and the third doping structure 103 can be regarded as being on opposite sides of the gate structure 104 along the first direction X. That is, taking the plane parallel to the first direction X as the reference plane, the second doping structure 102 and the third doping structure 103 are not directly opposite, that is, the orthographic projections of the second doping structure 102 and the third doping structure 103 on the reference plane do not overlap, so as to increase the distance between the second doping structure 102 and the third doping structure 103, which is conducive to reducing the coupling effect of the second doping structure 102 and the third doping structure 103 on each other. Further, after a first conductive structure is formed on the side of one of the second doping structure 102 and the third doping structure 103 away from the gate structure 104, and a second conductive structure is formed on the side of the other away from the gate structure 104, it is beneficial to avoid the direct opposition of the first conductive structure and the second conductive structure, which is conducive to reducing the coupling effect of the first conductive structure and the second conductive structure on each other, so as to improve the electrical performance of the semiconductor structure.

[0042] In some embodiments, the first conductive structure may be a capacitor structure, and the second conductive structure may be a bit line structure. The bit line structure and the capacitor structure will be described in detail later.

[0043] The following will describe an embodiment of the present disclosure in more detail with reference to the accompanying drawings.

[0044] In some embodiments, referring to Figures 1 to 4 , the gate structure 104 may include: a gate dielectric layer 154 and a gate 164. The gate dielectric layer 154 is located between the gate 164 and the second part 121. It can be understood that regardless of the positional relationship between the gate 164 and the second part 121, there is a gate dielectric layer 154 spaced between the gate 164 and the second part 121.

[0045] In some embodiments, the material of the gate dielectric layer 154 may be a material with a relatively high relative dielectric constant such as silicon oxide, hafnium oxide, or zirconium oxide.

[0046] In some embodiments, the material of the gate 164 may be a metal material, such as titanium, tungsten, or copper, or the material of the gate 164 may be a compound material such as titanium nitride.

[0047] The positional relationship between the gate structure 104 and the second part 121 includes at least the following embodiments.

[0048] In some embodiments, referring to Figure 1 , only the first surface 114 of the gate structure 104 is in contact connection with the second portion 121. In other embodiments, continuing to refer to Figure 1 , only the second surface 124 of the gate structure 104 is in contact connection with the second portion 121. It can be understood that along the second direction Y, only one surface of the gate structure 104 is in contact connection with the second portion 121, that is, the gate dielectric layer 154 is located on the surface of the second portion 121 and is not embedded in the second portion 121. The gate 164 is located on the side of the gate dielectric layer 154 away from the second portion 121, and the gate dielectric layer 154 is at least also located between the third doping structure 103 and the gate 164.

[0049] It should be noted that Figure 1 , Fig. 1a is a schematic diagram of a partial cross-sectional structure of a semiconductor structure provided by an embodiment of the present disclosure, Figure 1 , and Fig. 1b in it is a cross-sectional structure diagram of two gate structures 104 shown in Fig. 1a. It can be understood that according to the change in the relative position relationship between the gate structure 104 and the second portion 121, the gate dielectric layer 154 in the gate structure 104 can form the first surface 114 or the second surface 124.

[0050] In some embodiments, continuing to refer to Figure 1 , on the basis that two adjacent first doping structures 101 in the second direction Y are in contact connection with the same third doping structure 103, the two gate structures 104 corresponding to the two second portions 121 adjacent to the second direction Y can both be located between the two second portions 121, and the two gate structures 104 are spaced apart from each other. For example, the two adjacent first doping structures 101 in the second direction Y are divided into A and B, the gate structure 104 in contact connection with A is regarded as C, and the gate structure 104 in contact connection with B is regarded as D. Along the second direction Y, C is located on the side of A close to B, and D is located on the side of B close to A, that is, the first surface 114 of C is in contact connection with the second portion 121, and the second surface 124 of D is in contact connection with the second portion 121.

[0051] In practical applications, along the second direction Y, on the basis that C is located on the side of A close to B, D can also be located on the side of B away from A, and there is only one C between A and B. In other words, in both C and D, the first surface 114 is in contact connection with the second portion 121.

[0052] In other embodiments, referring to Figure 2, based on the contact connection between the first surface 114 or the second surface 124 and the second part 121 in the gate structure 104, the gate structure 104 has opposite third surface 134 and fourth surface 144 in the first direction X. At least part of the third surface 134 is also in contact connection with the second part 121, and at least part of the fourth surface 144 is also in contact connection with the second part 121. It can be understood that the gate dielectric layer 154 encloses a first groove with an opening facing the second direction Y. The outer wall of the first groove is in contact connection with the second part 121, the inner wall of the first groove is in contact connection with the gate 164, and the gate 164 fills the first groove.

[0053] It should be noted that Figure 2 in 2a, the entire third surface 134 and the entire fourth surface 144 are in contact connection with the second part 121, that is, the gate structure 104 is integrally embedded in the second part 121, and the second part 121 exposes the first surface 114 or the second surface 124 as an example. In practical applications, it can be that part of the third surface 134 is in contact connection with the second part 121, and part of the fourth surface 144 is in contact connection with the second part 121, that is, part of the gate structure 104 is embedded in the second part 121. In addition, Figure 2 Figure 2a is another partial cross-sectional structure schematic diagram of the semiconductor structure provided by an embodiment of the present disclosure, Figure 2 Figure 2b is a cross-sectional structure schematic diagram of two gate structures 104 shown in Figure 2a.

[0054] In some embodiments, continue to refer to Figure 2 , based on the contact connection between two adjacent first doping structures 101 in the second direction Y and the same third doping structure 103, the two gate structures 104 corresponding to the two second parts 121 adjacent in the second direction Y can both be located between the two second parts 121, and the two gate structures 104 are spaced apart from each other. For example, distinguish the two adjacent first doping structures 101 in the second direction Y as A and B, regard the gate structure 104 in contact connection with A as C, and regard the gate structure 104 in contact connection with B as D. In the second direction Y, C is located on the side of A close to B, and D is located on the side of B close to A, that is, the first surface 114, at least part of the third surface 134 and at least part of the fourth surface 144 of C are all in contact connection with the second part 121, and the second surface 124, at least part of the third surface 134 and at least part of the fourth surface 144 of D are all in contact connection with the second part 121.

[0055] In practical applications, in the second direction Y, based on C being located on the side of A close to B, D can also be located on the side of B away from A, and there is only one C between A and B. In other words, in both C and D, the first surface 114, at least part of the third surface 134 and at least part of the fourth surface 144 are in contact connection with the second part 121.

[0056] In still other embodiments, referring to Figure 3 and Figure 4 , based on the first surface 114 or the second surface 124 in the gate structure 104 being in contact connection with the second portion 121, the gate structure 104 has opposite third and fourth surfaces 134 and 144 in the first direction X, and the second surface 124 and the fourth surface 144 are also in contact connection with the second portion 121, that is, the entire gate structure 104 is embedded in the second portion 121. It can be understood that the gate dielectric layer 154 encloses a second groove with an opening facing the first direction X, the outer wall of the second groove is in contact connection with the second portion 121, the inner wall of the second groove is in contact connection with the gate 164, and the gate 164 fills the second groove.

[0057] It should be noted that Figure 3 in 3a is another partial cross-sectional structure schematic diagram of the semiconductor structure provided by an embodiment of the present disclosure, Figure 3 and in 3b is a cross-sectional structure schematic diagram of any one of the gate structures 104 shown in 3a.

[0058] In some embodiments, continuing to refer to Figure 3 and Figure 4 , the semiconductor structure may further include: an isolation layer 105, which is in contact connection with the third surface 134, and both the isolation layer 105 and the gate structure 104 are embedded in the first doping structure 101.

[0059] In some embodiments, the material of the isolation layer 105 may be a dielectric material such as silicon nitride, silicon oxynitride, or silicon carbonitride.

[0060] In some embodiments, referring to Figure 4 , the semiconductor structure may further include: an active region 106, the active region 106 includes two first doping structures 101 adjacent to each other along the second direction Y, and the two gate structures 104 in contact connection with the two first doping structures 101 are spaced apart from each other and are both located in the active region 106.

[0061] It should be noted that Figure 4 in the areas of the two first doping structures 101 in the active region 106 are respectively framed by box I and box II. In practical applications, the active region 106 is an integral structure. For the convenience of describing the positional relationship between different second doping structures 102, different gate structures 104, and the third doping structure 103 in the active region 106, the active region 106 is divided to divide out two first doping structures 101.

[0062] It can be understood that the active region 106 including two first doping structures 101 adjacent to each other along the second direction Y means that the two first doping structures 101 adjacent to each other along the second direction Y are both part of the active region 106. In combination with referring to Figure 4 andFigure 5 , an active region 106 corresponds to two second doping structures 102, two gate structures 104, and a third doping structure 103. Among them, one second doping structure 102, one gate structure 104, and the third doping structure 103 form a transistor structure, and the other second doping structure 102, the other gate structure 104, and the third doping structure 103 form another transistor structure, that is, one active region 106 corresponds to two transistor structures.

[0063] It should be noted that Figure 5 in 5a is a top view structural schematic diagram of the relative position relationship between the active region 106, the bit line structure BL, and the word line structure WL in the semiconductor structure; Figure 5 in 5b is a top view structural schematic diagram of any one active region 106 and the two second doping structures 102 corresponding thereto; Figure 4 is a partial cross-sectional structural schematic diagram of the semiconductor structure shown in 5a along the first cross-sectional direction AA1. The first cross-sectional direction AA1 is the second direction Y, that is, the extending direction U of the active region 106. It can be understood that Figure 5 the bit line structure BL and the word line structure WL drawn in 5a are only for indicating the relative position relationship among the bit line structure BL, the word line structure WL, and the active region 106 in the top view. Figure 5 There is no limitation on the internal structure of the bit line structure BL and the word line structure WL themselves, nor on the three-dimensional position relationship among the bit line structure BL, the word line structure WL, and the active region 106. In addition, in order to clearly show the relative position relationship among the active region 106, the bit line structure BL, and the word line structure WL in the top view, a perspective drawing method is adopted for both the word line structure WL and the active region 106. Moreover, for the convenience of illustration, Figure 5 the third doping structure 103 and the gate structure 104 embedded in the active region 106 are not shown in 5a. Figure 5

[0064] In some embodiments, there is a shallow trench isolation structure (not shown) between adjacent active regions 106.

[0065] Figure 5 In some embodiments, the extending direction of the bit line structure BL is the third direction Z, and the extending direction of the word line structure WL is the fifth direction V. Refer to Figure 5In 5a, multiple active regions 106 are not only arranged at intervals along the third direction Z and the fifth direction V, but also the adjacent two groups of active region groups arranged at intervals along the fifth direction V are staggeredly arranged in the third direction Z. The extending direction U of the active region 106 itself, the first direction X, and the second direction Y intersect pairwise, and the extending direction U of the active region 106 itself, the third direction Z, and the fifth direction V are in a plane. It can be understood that taking the multiple active regions 106 arranged at intervals along the third direction Z as a column, along the fifth direction V, the adjacent two columns are staggeredly arranged, and the arrangement modes of the two columns with one column in between are the same.

[0066] It should be noted that in practical applications, multiple active regions may also be arranged in an array along the third direction Z and the fifth direction V or in other arrangement modes, and the arrangement mode of the multiple active regions can be adjusted according to actual needs, which is not limited herein. For the sake of convenience of description, hereinafter, taking the arrangement mode shown in Figure 5 5a as an example will be described in detail.

[0067] In some embodiments, with reference to Figure 4 and Figure 5 , the word line structure WL includes multiple gate structures 104 arranged at intervals along the third direction Z and an isolation layer 105 located on the gate structure 104. In other embodiments, the multiple gate structures 104 arranged at intervals along the third direction Z may be an integral structure extending along the third direction Z, that is, the multiple active regions 106 arranged at intervals along the third direction Z share one gate structure 104. On this basis, the isolation layer 105 is also an integral structure extending along the third direction Z.

[0068] In some embodiments, with reference to Figures 1 to 4 , at least part of the second doping structure 102 is embedded in the first part 111. It should be noted that Figures 1 to 4 in the examples, the second doping structure 102 with the entire thickness along the first direction X is embedded in the first part 111. In practical applications, it may also be that the second doping structure 102 with a partial thickness along the first direction X is embedded in the first part 111.

[0069] In some embodiments, with reference to Figures 1 to 4 , at least part of the third doping structure 103 is embedded in the third part 131. It should be noted that Figures 1 to 4 in the examples, the third doping structure 103 with the entire thickness along the first direction X is embedded in the third part 131. In practical applications, it may also be that the third doping structure 103 with a partial thickness along the first direction X is embedded in the third part 131.

[0070] It should be noted that the division of the first part 111, the second part 121, and the third part 131 in the first doping structure 101 is related to the relative positions of the second doping structure 102, the gate structure 104, and the third doping structure 103 with respect to the first doping structure 101. At least the part of the first doping structure 101 that is in contact with and connected to the second doping structure 102 is regarded as the first part 111, at least the part of the first doping structure 101 that is in contact with and connected to the third doping structure 103 is regarded as the third part 131, and the remaining first doping structure 101 is regarded as the second part 121.

[0071] In some embodiments, referring to Figures 2 to 4 , the gate structure 104 can be in contact with and connected to the third doping structure 103.

[0072] In some embodiments, the gate structure 104 may include: a gate dielectric layer 154 and a gate 164. The third doping structure 103 is only in contact with and connected to the gate dielectric layer 154, that is, there is at least a gate dielectric layer 154 between the gate 164 and the third doping structure 103.

[0073] In some embodiments, continuing to refer to Figures 2 to 4 , on the basis that the gate 164 and the second doping structure 102 are mutually insulated and the gate 164 and the third doping structure 103 are mutually insulated, the third doping structure 103 can not only be in contact with and connected to the third part 131, but also be in contact with and connected to a part of the second part 121 along the first direction X in terms of thickness.

[0074] In some other embodiments, referring to Figure 6 , the second doping structure 102 and the gate structure 104 are in one-to-one correspondence. The second doping structure 102 is located on the same side of the corresponding gate structure 104 along the second direction Y. For example, Figure 6 in the second doping structure 102 is located on the first side of the corresponding gate structure 104, and two adjacent and spaced-apart gate structures 104 are located in the same active region 106, and the two second doping structures 102 are located.

[0075] It should be noted that, referring to Figures 2 to 4 and Figure 6 , the gate structure 104 can not only be in contact with and connected to the second part 121. On the basis that the gate 164 and the second doping structure 102 are mutually insulated and the gate 164 and the third doping structure 103 are mutually insulated, the gate structure 104 can also be in contact with and connected to a part of the first part 111 along the first direction X in terms of thickness. In practical applications, the gate structure 104 can only be in contact with and connected to the second part 121. In addition, Figure 6 in the general areas of two first doping structures 101 in the active region 106 are respectively framed by box I and box II.

[0076] In some embodiments, referring to Figure 7 , the semiconductor structure may further include: a substrate 100, a first doping structure 101, a second doping structure 102, a third doping structure 103, and a gate structure 104 are all located in the substrate 100. It can be understood that there are multiple active regions 106 arranged at intervals in the substrate 100, and at least part of the regions of the first doping structure 101, the second doping structure 102, the third doping structure 103, and the gate structure 104 are embedded in the active regions 106.

[0077] It can be understood that, continuing to refer to Figure 7 , in the same active region 106, along the second direction Y, the third doping structure 103 is located between two adjacent gate structures 104, and two adjacent gate structures 104 are located between two adjacent second doping structures 102, so as to realize that two transistor structures share a third doping structure 103.

[0078] The third doping structure 103 will be described in detail through two embodiments below.

[0079] In some embodiments, with reference to Figure 5 and Figure 7 , a plurality of first doping structures 101 and a plurality of second doping structures 102 are arranged at intervals along the third direction Z, and the first doping structures 101, the second doping structures 102, and the gate structures 104 arranged at intervals along the third direction Z correspond one by one; the third doping structure 103 extends along the third direction Z, and a third doping structure 103 is in contact connection with a plurality of first doping structures 101 arranged at intervals along the third direction Z, and the first direction X, the second direction Y, and the third direction Z intersect pairwise.

[0080] It can be understood that the first doping structure 101 is a part of the active region 106, and a second doping structure 102 is embedded at each end of an active region 106 along its extending direction U. The region in the active region 106 between the two second doping structures in contact connection with it corresponds to a bit line structure BL and two word line structures WL; for any active region 106, the region corresponding to the word line structure WL is embedded with a gate structure 104, and the region corresponding to the bit line structure BL is embedded with a third doping structure 103. The relationship between the word line structure WL and the gate structure 104, and the relationship between the bit line structure BL and the third doping structure 103 will be described in detail later.

[0081] In some embodiments, referring to Figure 5In 5a, a plurality of bit line structures BL are arranged at intervals along a fifth direction V, and a plurality of word line structures WL are arranged at intervals along a third direction Z. It can be understood that the plurality of bit line structures BL and the plurality of word line structures WL form a plurality of rectangular windows in a top view. A capacitor contact hole is formed in each rectangular window, and each capacitor contact hole exposes a second doping structure 102. A capacitor structure in contact connection with the second doping structure 102 is formed based on the capacitor contact hole.

[0082] In some embodiments, referring to Figure 5 In 5a, a gate structure 104 and an isolation layer 105 are embedded in the active region 106 opposite to the word line structure WL. It can be understood that the word line structure WL includes the gate structure 104 and the isolation layer 105. A plurality of active regions 106 arranged at intervals along the fifth direction V are all opposite to a partial region of the word line structure WL, that is, the orthographic projection of a partial gate structure 104 on the active region 106 coincides with the active region 106. A plurality of active regions 106 arranged at intervals along the fifth direction V share a gate structure 104.

[0083] Combined with reference to Figure 7 and Figure 8 , the third doping structure 103 extends along the third direction Z. It can be understood that a plurality of active regions 106 arranged at intervals along the third direction Z are all opposite to a partial region of the third doping structure 103, that is, the orthographic projection of a partial third doping structure 103 on the active region 106 coincides with the active region 106. A plurality of active regions 106 arranged at intervals along the third direction Z share a third doping structure 103. It should be noted that the bit line structure BL includes the third doping structure 103. In addition, the first doping structure 101 is a part of the active region 106. Two second doping structures 102 are respectively embedded at both ends of an active region 106 along its extending direction U. An active region 106 can be regarded as a basic component constituting two transistor structures, and these two transistor structures share a third doping structure 103.

[0084] In some embodiments, referring to Figure 7 , the semiconductor structure may further include: a first electrical connection layer 117, which is located on a side of the third doping structure 103 away from the gate structure 104, and the first electrical connection layer 117 extends along the third direction Z. It can be understood that the bit line structure BL (referring to Figure 5 ) may include the first electrical connection layer 117 and the third doping structure 103 in contact connection with the first electrical connection layer 117. One bit line structure BL corresponds to one first electrical connection layer 117 and one third doping structure 103.

[0085] It should be noted that, for clearly showing the relative positional relationship between the active region 106 and the third doping structure 103 in a top view, Figure 8In [the figure], a perspective drawing method is adopted for the active region 106.

[0086] In some other embodiments, with reference to Figure 9 and Figure 10 , a plurality of first doping structures 101, a plurality of second doping structures 102, and a plurality of third doping structures 103 are arranged at intervals along the third direction Z. The first doping structures 101, second doping structures 102, third doping structures 103, and gate structures 104 arranged at intervals along the third direction Z all correspond one by one.

[0087] It can be understood that the first doping structure 101 is a part of the active region 106. At both ends of an active region 106 along its extending direction U, a second doping structure 102 is respectively embedded. Figure 9 In the top view shown, between the second doping structure 102 and the third doping structure 103 corresponding to the same active region 106 (refer to Figure 7 ), there is a gate structure 104 (refer to Figure 7 ). It can be understood that the third doping structure 103 can serve as the bit line contact layer in the bit line structure BL. It should be noted that the same or corresponding parts as those in the above embodiments will not be elaborated here.

[0088] Continuing to refer to Figure 9 and Figure 10 , the semiconductor structure may further include: a conductive layer 107 extending along the third direction Z, and the same conductive layer 107 is in contact connection with a plurality of third doping structures 103 arranged at intervals along the third direction Z. It can be understood that a bit line structure BL includes a plurality of third doping structures 103 arranged at intervals along the third direction Z and a conductive layer 107 in contact connection therewith. In addition, an active region 106 can be regarded as a basic component constituting two transistor structures. The two transistor structures have their respective second doping structures 102 and their respective gate structures 104, and the two transistor structures share a third doping structure 103.

[0089] In some embodiments, with reference to Figure 10 , the conductive layer 107 may include: a second electrical connection layer 137 and a plurality of conductive posts 127 in contact connection with the second electrical connection layer 137 and arranged at intervals along the third direction Z. Among them, the conductive posts 127 and the third doping structures 103 correspond one by one. A conductive post 127 is in contact connection with a third doping structure 103. The second electrical connection layer 137 extends along the third direction Z, and the same second electrical connection layer 137 is in contact connection with a plurality of conductive posts 127 arranged at intervals along the third direction Z.

[0090] In some embodiments, the orthographic projections of the conductive posts 127 and the third doping structures 103 on the substrate 100 may coincide.

[0091] It should be noted that, in order to clearly show the relative positional relationship between the active region 106 and the third doping structure 103 in the top view, Figure 9 in [the figure], a perspective drawing method is adopted for the active region 106.

[0092] In the above embodiments, referring to Figure 7 or Figure 10 , the semiconductor structure may further include: a capacitor structure 109, located on a side of the second doping structure 102 away from the gate structure 104, and the bit line structure BL includes the third doping structure 103 and is located on a side of the gate structure 104 away from the capacitor structure 109. In this way, it is beneficial to avoid the capacitor structure 109 and the bit line structure BL facing each other, thereby being beneficial to reducing the coupling influence of the capacitor structure 109 and the bit line structure BL on each other, so as to improve the electrical performance of the semiconductor structure.

[0093] In some cases, at least a part of the second doping structure 102 is in contact connection with the gate dielectric layer 154 in the corresponding gate structure 104.

[0094] In summary, the second doping structure 102 and the third doping structure 103 can be regarded as being located on opposite sides of the gate structure 104 along the first direction X. That is, taking a plane parallel to the first direction X as a reference plane, the second doping structure 102 and the third doping structure 103 do not face each other, that is, the orthographic projections of the second doping structure 102 and the third doping structure 103 on the reference plane do not overlap, so as to increase the distance between the second doping structure 102 and the third doping structure 103, thereby being beneficial to reducing the coupling influence of the second doping structure 102 and the third doping structure 103 on each other. Further, the capacitor structure 109 is located on a side of the second doping structure 102 away from the gate structure 104, and the bit line structure BL is located on a side of the gate structure 104 away from the capacitor structure 109, which is beneficial to avoiding the capacitor structure 109 and the bit line structure BL facing each other, thereby being beneficial to reducing the coupling influence of the capacitor structure 109 and the bit line structure BL on each other, so as to improve the electrical performance of the semiconductor structure. In addition, two adjacent transistor structures along the second direction Y share a third doping structure 103, which is beneficial to improving the integration density of the transistor structures in the semiconductor structure.

[0095] Another embodiment of the present disclosure further provides a manufacturing method of a semiconductor structure for forming the semiconductor structure provided in the foregoing embodiments. Figures 11 to 19 It is a schematic cross-sectional structure diagram corresponding to each step in the manufacturing method of the semiconductor structure provided in another embodiment of the present disclosure. It should be noted that, for the convenience of description and to clearly show the steps of the semiconductor structure manufacturing method, in this embodiment, Figures 11 to 19 are all schematic diagrams of partial structures of the semiconductor structure. In addition, the same or corresponding parts as those in the foregoing embodiments will not be elaborated here.

[0096] Reference Figures 1 to 19 , a method for manufacturing a semiconductor structure includes: providing an initial substrate 110; doping different parts of the initial substrate 110 using different doping processes to form a first doped structure 101, a second doped structure 102, and a third doped structure 103; wherein, the first doped structure 101 has a first part 111, a second part 121, and a third part 131 arranged in sequence along a first direction X; the second doped structure 102 and the third doped structure 103 are arranged at intervals, the second doped structure 102 is in contact connection with the first part 111, and the third doped structure 103 is in contact connection with the third part 131; the first doped structure 101 is doped with one of N-type doping ions and P-type doping ions, and the second doped structure 102 and the third doped structure 103 are doped with the other of N-type doping ions and P-type doping ions; two adjacent first doped structures 101 along a second direction Y are in contact connection with the same third doped structure 103, and the second direction Y intersects with the first direction X; forming a gate structure 104, the gate structure 104 has a first surface 114 and a second surface 124 opposite to each other along the second direction Y, at least the first surface 114 is in contact connection with the second part 121, and the gate structure 104 is in contact connection with the third doped structure 103.

[0097] It should be noted that the order of the steps of forming the second doped structure 102, the third doped structure 103, and the gate structure 104 can be adjusted, and the following will be described in detail. In addition, for the sake of understanding, hereinafter, an exemplary description of the manufacturing method will be given using the semiconductor structure shown Figure 4 . In practical applications, various semiconductor structures in the foregoing embodiments can be manufactured by the manufacturing method provided in another embodiment of the present disclosure.

[0098] In some embodiments, the initial substrate 110 has a front surface 120 and a back surface 130 opposite to each other along the first direction X; Reference Figures 11 to 19 , forming the second doped structure 102 and the third doped structure 103 may include the following steps:

[0099] Reference Figure 11 and Figure 12 , performing a first doping process on a partial region of the initial substrate 110 to form a plurality of initial first doped structures 141 arranged at intervals, the initial first doped structures 141 extend from the front surface 120 into the initial substrate 110, the initial first doped structures 141 also extend along a fourth direction U, and the initial first doped structures 141 have a fourth part 151, a fifth part 161, and a sixth part 171 arranged in sequence along the fourth direction U.

[0100] It should be noted that the first doped structure 101 is subsequently formed based on the initial first doped structure 141, thusFigures 11 to 19 The initial first doping structure 141 is drawn using the same filling method as the first doping structure 101.

[0101] In some embodiments, performing a first doping process on a partial region of the initial substrate 110 includes: doping P-type doping ions into a partial region of the initial substrate 110, such that the initial first doping structure 141 is doped with P-type doping ions. In other embodiments, performing a first doping process on a partial region of the initial substrate 110 includes: doping N-type doping ions into a partial region of the initial substrate 110, such that the initial first doping structure 141 is doped with N-type doping ions.

[0102] It can be understood that the initial first doping structure 141 can be regarded as the active region 106 before the second doping structure 102, the third doping structure 103, and the gate structure 104 are embedded. The orthographic projection of the initial first doping structure 141 on the top view plane coincides with the orthographic projection of the active region 106 on the top view plane, and the top view plane is the plane formed by the third direction Z and the fifth direction V.

[0103] In some embodiments, with reference to Figure 11 and Figure 12 , Figure 11 is Figure 12 a schematic partial cross-sectional structure diagram of the semiconductor structure shown along the second cross-sectional direction BB1. Multiple initial first doping structures 141 are not only arranged at intervals along both the third direction Z and the fifth direction V, but also the adjacent two groups of initial first doping structure groups arranged at intervals along the fifth direction V are staggeredly arranged in the third direction Z. The extending direction U of the initial first doping structure 141 itself, the third direction Z, and the fifth direction V intersect pairwise, and the extending direction U of the initial first doping structure 141 itself, the third direction Z, and the fifth direction V are located in a plane. It can be understood that taking multiple initial first doping structures 141 arranged at intervals along the third direction Z as a column, along the fifth direction V, the adjacent two columns are staggeredly arranged, and the arrangement manners of the two columns with one column in between are the same.

[0104] It should be noted that in practical applications, multiple initial first doping structures can also be arranged in an array along the third direction Z and the fifth direction V or in other arrangement manners, and the arrangement manner of multiple active regions can be adjusted according to actual requirements, which is not limited herein. For the sake of convenience of description, hereinafter, multiple initial first doping structures 141 arranged in the Figure 12 shown arrangement manner are taken as an example for detailed description.

[0105] With reference to Figures 11 to 14 , Figure 13 is Figure 14Schematic diagram of a partial cross-sectional structure of the semiconductor structure shown along the second cross-sectional direction BB1. A second doping process is performed on both the fourth part 151 and the sixth part 171. Along the first direction X, a part of the thickness of the fourth part 151 is transformed into a second doped structure 102, and a part of the thickness of the sixth part 171 is transformed into another second doped structure 102. The second doped structure 102 extends from the front surface 120 into the interior of the initial substrate 110.

[0106] It can be understood that the two second doped structures 102 are prepared from two different regions of an initial first doped structure 141, that is, the two second doped structures 102 correspond to an initial first doped structure 141. Subsequently, a third doped structure 103 and a gate structure 104 can be formed in the fifth part 161. In addition, the types of doping ions doped in the first doping process and the second doping process are different.

[0107] In some embodiments, on the basis that the initial first doped structure 141 is doped with P-type doping ions, the second doping process for the fourth part 151 and the sixth part 171 includes: doping N-type doping ions into the fourth part 151 and the sixth part 171, so that the second doped structure 102 is doped with N-type doping ions. In other embodiments, on the basis that the initial first doped structure 141 is doped with N-type doping ions, the second doping process for the fourth part 151 and the sixth part 171 includes: doping P-type doping ions into the fourth part 151 and the sixth part 171, so that the second doped structure 102 is doped with P-type doping ions.

[0108] Reference Figure 15 and Figure 16 or reference Figure 18 and Figure 19 , perform patterning on the initial substrate 110 from the back surface 130 to expose at least part of the fifth part 161; reference Figure 17 or reference Figure 10 , perform a third doping process on the exposed fifth part 161 to form a third doped structure 103.

[0109] The steps of forming the third doped structure 103 are described in detail below through two embodiments.

[0110] In some embodiments, in combination with reference Figure 13 and Figure 14 , a plurality of fifth parts 161 are arranged at intervals along the third direction Z, and the first direction X, the second direction Y, and the third direction Z intersect pairwise. Among them, the second direction Y is the extension direction U of the initial first doped structure 141.

[0111] In some embodiments, the second direction Y, the third direction Z, and the fifth direction V intersect pairwise and the three form a plane, and the first direction X is perpendicular to this plane.

[0112] Patterning the initial substrate 110 from the back surface 130 may include the following steps:

[0113] Referring to Figure 15 and Figure 16 , Figure 15 as Figure 16 a schematic partial cross-sectional structure diagram of the semiconductor structure shown along the second cross-sectional direction BB1, patterning the initial substrate 110 from the back surface 130 to form trenches 108 extending along the third direction Z, and the trenches 108 expose a plurality of fifth portions 161 arranged at intervals along the third direction Z.

[0114] It should be noted that, to clearly show the relative positional relationship between the trenches 108 and the initial substrate 110 in the top view, Figure 16 the initial substrate 110 is drawn in a perspective manner in

[0115] Combining with reference to Figures 15 to 17 and Figure 8 , the steps of performing the third doping process on the exposed fifth portions 161 may include: performing the third doping process on the fifth portions 161 exposed by the trenches 108 to form a third doping structure 103 extending along the third direction Z. It can be understood that a third doping structure 103 is in contact connection with a plurality of fifth portions 161 arranged at intervals along the third direction Z. In addition, the types of ions doped in the third doping process and the second doping process are the same.

[0116] In some embodiments, on the basis that the initial first doping structure 141 is doped with P-type doping ions, performing the third doping process on the exposed fifth portions 161 includes: doping N-type doping ions into the exposed fifth portions 161, so that the third doping structure 103 is doped with N-type doping ions. In other embodiments, on the basis that the initial first doping structure 141 is doped with N-type doping ions, performing the third doping process on the exposed fifth portions 161 includes: doping P-type doping ions into the exposed fifth portions 161, so that the third doping structure 103 is doped with P-type doping ions.

[0117] Combining with reference to Figure 17 and Figure 7, the manufacturing method may further include: forming a first electrical connection layer 117 that fills the trench 108. It can be understood that the bit line structure BL may include the first electrical connection layer 117 and the third doped structure 103 in contact connection with the first electrical connection layer 117, and one bit line structure BL corresponds to one first electrical connection layer 117 and one third doped structure 103.

[0118] In some other embodiments, with reference to Figure 13 and Figure 14 , a plurality of fifth portions 161 are arranged at intervals along the third direction Z, and the first direction X, the second direction Y, and the third direction Z intersect pairwise. It should be noted that the same or corresponding parts as those in the above embodiments will not be elaborated here.

[0119] Patterning the initial substrate 110 from the back surface 130 may include the following steps:

[0120] With reference to Figure 18 and Figure 19 , Figure 18 as Figure 19 is a schematic partial cross-sectional structure diagram of the semiconductor structure along the second cross-sectional direction BB1. Patterning the initial substrate 110 from the back surface 130 to form a plurality of through holes 118 arranged at intervals along the third direction Z, and one through hole 118 exposes one fifth portion 161.

[0121] It should be noted that, for clearly showing the relative positional relationship between the through hole 118 and the initial substrate 110 in the top view, Figure 19 the initial substrate 110 is drawn in a perspective manner in

[0122] With reference to Figures 18 to 19 , Figure 9 and Figure 10 , the step of performing the third doping process on the exposed fifth portion 161 may include: performing the third doping process on the fifth portion 161 exposed by the through hole 118 to form a plurality of third doped structures 103 arranged at intervals along the third direction Z. It can be understood that one third doped structure 103 is only in contact connection with one fifth portion 161, that is, one third doped structure 103 corresponds to one fifth portion 161.

[0123] With reference to Figure 18 and Figure 10 , the manufacturing method may further include: forming conductive pillars 127 that fill the through holes 118, and the conductive pillars 127 and the through holes 118 correspond one by one. In this way, the conductive pillars 127 and the third doped structures 103 correspond one by one, that is, one conductive pillar 127 is in contact connection with one third doped structure 103.

[0124] Continuing to refer to Figure 10, a second electrical connection layer 137 extending along the third direction Z is formed, and the same second electrical connection layer 137 is in contact connection with a plurality of conductive posts 127 arranged at intervals along the third direction Z.

[0125] It can be understood that the second electrical connection layer 137 and a plurality of conductive posts 127 that are in contact connection with the second electrical connection layer 137 and arranged at intervals along the third direction Z together constitute a conductive layer 107. The bit line structure BL includes the conductive layer 107 and a plurality of third doping structures 103 that are in contact connection with the conductive layer 107.

[0126] In practical applications, after patterning the initial substrate from the back side to form a plurality of through holes arranged at intervals along the third direction, and performing third doping treatment on the fifth part exposed by the through holes to form a third doping structure, then patterning the substrate on the back side to form a groove extending along the third direction. One groove exposes a plurality of third doping structures arranged at intervals along the third direction, and a third electrical connection layer is formed in the groove. In this way, the bit line structure can include a third electrical connection layer and a plurality of third doping structures that are in contact connection with the third electrical connection layer. It can be understood that after forming the third doping structure by means of the through hole, the through hole is expanded into a groove, and a third electrical connection layer is formed in the groove, so that a third electrical connection layer can supply power to a plurality of third doping structures.

[0127] In some embodiments, with reference to Figure 5 and Figure 10 , the steps of forming the gate structure 104 include: patterning the fifth part 161 (refer to Figure 11 ) from the front side 120 to form a second groove (not shown) extending along the fifth direction V; wherein, one fifth part 161 corresponds to two second grooves adjacent along the third direction Z; the gate structure 104 and the isolation layer 105 are sequentially formed in the second groove. It should be noted that in the manufacturing method provided by another embodiment of the present disclosure, the specific processes of forming the gate structure 104 and the isolation layer 105 are not limited and can be adjusted according to actual needs.

[0128] It should be noted that the steps of forming the gate structure 104 can be before forming the second doping structure 102 and the third doping structure 103, or after forming the second doping structure 102 and the third doping structure 103. In addition, after forming the second doping structure 102, the third doping structure 103, and the gate structure 104 in the initial first doping structure 141, the remaining initial first doping structure 141 serves as the first doping structure 101.

[0129] It can be understood that after the second doping structure 102, the third doping structure 103, and the gate structure 104 are formed, the remaining initial first doping structure 141 serves as the first doping structure 101, and the remaining initial substrate 110 serves as the substrate 100.

[0130] In some embodiments, with continued reference to Figure 10 , after the second doping structure 102 is formed, the manufacturing method may further include forming a capacitor structure 109 in contact with the second doping structure 102 on the front surface 120, with one second doping structure 102 corresponding to one capacitor structure 109.

[0131] In summary, in the formed semiconductor structure, the second doping structure 102 and the third doping structure 103 can be regarded as being located on opposite sides of the gate structure 104 along the first direction X. That is, with a plane parallel to the first direction X as the reference plane, the second doping structure 102 and the third doping structure 103 are not directly opposite, that is, the orthographic projections of the second doping structure 102 and the third doping structure 103 on the reference plane do not overlap, so as to increase the distance between the second doping structure 102 and the third doping structure 103, thereby facilitating the reduction of the coupling effect of the second doping structure 102 and the third doping structure 103 on each other. Further, the capacitor structure 109 is located on the side of the second doping structure 102 away from the gate structure 104, and the bit line structure BL is located on the side of the gate structure 104 away from the capacitor structure 109, which is conducive to avoiding the direct opposition of the capacitor structure 109 and the bit line structure BL, thereby facilitating the reduction of the coupling effect of the capacitor structure 109 and the bit line structure BL on each other to improve the electrical performance of the semiconductor structure. In addition, two adjacent transistor structures along the second direction Y share one third doping structure 103, which is conducive to improving the integration density of the transistor structures in the semiconductor structure.

[0132] Those of ordinary skill in the art can understand that the above embodiments are specific embodiments for implementing the present disclosure, and in actual applications, various changes can be made in form and details without departing from the spirit and scope of the embodiments of the present disclosure. Any person skilled in the art can make various modifications and changes without departing from the spirit and scope of the embodiments of the present disclosure. Therefore, the protection scope of the embodiments of the present disclosure should be subject to the scope defined by the claims.

Claims

1. A semiconductor structure, characterized in that, comprising: A first doping structure having a first part, a second part, and a third part arranged in sequence along a first direction; A second doping structure and a third doping structure arranged at intervals, the second doping structure being in contact connection with the first part, and the third doping structure being in contact connection with the third part; Wherein, one of N-type doping ions and P-type doping ions is doped in the first doping structure, and the other of N-type doping ions and P-type doping ions is doped in the second doping structure and the third doping structure, and two adjacent first doping structures along a second direction are in contact connection with the same third doping structure, and the second direction intersects with the first direction; A gate structure having a first surface and a second surface opposite to each other along the second direction, and at least the first surface or the second surface is in contact connection with the second part.

2. The semiconductor structure according to claim 1, characterized in that, Only the first surface or only the second surface of the gate structure is in contact connection with the second part.

3. The semiconductor structure according to claim 2, characterized in that, The gate structure has a third surface and a fourth surface opposite to each other along the first direction, at least part of the third surface is also in contact connection with the second part, and at least part of the fourth surface is also in contact connection with the second part.

4. The semiconductor structure according to claim 2, characterized in that, The gate structure has a third surface and a fourth surface opposite to each other along the first direction, and the second surface and the fourth surface are also in contact connection with the second part.

5. The semiconductor structure according to claim 4, characterized in that, further comprising: An isolation layer in contact connection with the third surface, and both the isolation layer and the gate structure are embedded in the first doping structure.

6. The semiconductor structure according to claim 4, characterized in that, further comprising: An active region, the active region includes two first doping structures adjacent to each other along the second direction, and two gate structures in contact connection with the two first doping structures are spaced apart from each other and are both located in the active region.

7. The semiconductor structure according to any one of claims 1 to 6, characterized in that, At least part of the second doping structure is embedded in the first part, and / or at least part of the third doping structure is embedded in the third part.

8. The semiconductor structure according to any one of claims 1 to 6, characterized in that, A plurality of the first doping structures and a plurality of the second doping structures are arranged at intervals along a third direction, and the first doping structures, the second doping structures, and the gate structures arranged at intervals along the third direction correspond to each other one by one; the third doping structure extends along the third direction, and one third doping structure is in contact connection with a plurality of the first doping structures arranged at intervals along the third direction, and the first direction, the second direction, and the third direction intersect pairwise.

9. The semiconductor structure according to any one of claims 1 to 6, characterized in that, A plurality of the first doping structures, a plurality of the second doping structures, and a plurality of the third doping structures are arranged at intervals in a third direction, and the first doping structures, the second doping structures, the third doping structures, and the gate structures arranged at intervals in the third direction correspond to each other one by one; The semiconductor structure further includes: a conductive layer extending in the third direction, and the same conductive layer is in contact connection with a plurality of the third doping structures arranged at intervals in the third direction.

10. The semiconductor structure according to any one of claims 1 to 6, wherein, the gate structure is in contact connection with the third doping structure.

11. The semiconductor structure according to claim 1, wherein, it further includes: a substrate, and the first doping structure, the second doping structure, the third doping structure, and the gate structure are all located in the substrate.

12. A manufacturing method of a semiconductor structure, wherein, it includes: providing an initial substrate; performing doping treatments on different parts of the initial substrate by using different doping processes to form a first doping structure, a second doping structure, and a third doping structure; wherein, the first doping structure has a first part, a second part, and a third part arranged in sequence in a first direction; the second doping structure and the third doping structure are arranged at intervals, the second doping structure is in contact connection with the first part, and the third doping structure is in contact connection with the third part; one of an N-type doping ion and a P-type doping ion is doped in the first doping structure, and the other of the N-type doping ion and the P-type doping ion is doped in the second doping structure and the third doping structure; two adjacent first doping structures in a second direction are in contact connection with the same third doping structure, and the second direction intersects with the first direction; forming a gate structure, the gate structure has a first surface and a second surface opposite to each other in the second direction, at least the first surface is in contact connection with the second part, and the gate structure is in contact connection with the third doping structure.

13. The manufacturing method according to claim 12, wherein, the initial substrate has a front surface and a back surface opposite to each other in the first direction; the step of forming the second doping structure and the third doping structure includes: performing a first doping treatment on a partial region of the initial substrate to form a plurality of initial first doping structures arranged at intervals, the initial first doping structures extend from the front surface into the initial substrate, the initial first doping structures further extend in a fourth direction, and the initial first doping structures have a fourth part, a fifth part, and a sixth part arranged in sequence in the fourth direction; performing a second doping treatment on both the fourth part and the sixth part, along the first direction, such that a partial thickness of the fourth part is transformed into one second doping structure, and a partial thickness of the sixth part is transformed into another second doping structure, and the second doping structures extend from the front surface into the initial substrate; Pattern the initial substrate from the back side to expose at least a portion of the fifth portion; Perform a third doping process on the exposed fifth portion to form the third doping structure.

14. The manufacturing method according to claim 13, wherein, a plurality of the fifth portions are arranged at intervals along a third direction, and the first direction, the second direction, and the third direction intersect pairwise; the patterning the initial substrate from the back side includes: pattern the initial substrate from the back side to form trenches extending along the third direction, and the trenches expose a plurality of the fifth portions arranged at intervals along the third direction; the performing a third doping process on the exposed fifth portion includes: perform the third doping process on the fifth portion exposed by the trenches to form the third doping structure extending along the third direction; the manufacturing method further includes: forming a first electrical connection layer that fills the trenches.

15. The manufacturing method according to claim 13, wherein, a plurality of the fifth portions are arranged at intervals along a third direction, and the first direction, the second direction, and the third direction intersect pairwise; the patterning the initial substrate from the back side includes: pattern the initial substrate from the back side to form a plurality of through holes arranged at intervals along the third direction, and one through hole exposes one fifth portion; the performing a third doping process on the exposed fifth portion includes: perform the third doping process on the fifth portion exposed by the through holes to form a plurality of the third doping structures arranged at intervals along the third direction; the manufacturing method further includes: forming conductive pillars that fill the through holes, and the conductive pillars and the through holes are in one-to-one correspondence; forming a second electrical connection layer extending along the third direction, and the same second electrical connection layer is in contact connection with a plurality of the conductive pillars arranged at intervals along the third direction.

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