Semiconductor structure and manufacturing method thereof, memory and electronic equipment

Abstract

The invention relates to a semiconductor structure and a manufacturing method thereof, a memory and electronic equipment. The manufacturing method of the semiconductor structure comprises the following steps: providing a substrate, and forming a laminated structure on one side of the substrate; etching the laminated structure along the direction vertical to the substrate to form an etching groove extending along the first direction; forming a sacrificial material layer in the etching groove; etching the sacrificial material layer by adopting an isotropic etching process, and synchronously and sequentially etching the side wall, exposed in the etching groove, of each target material layer along the direction parallel to the substrate from top to bottom; and respectively etching the adjacent transfer material layers by taking each first step as a mask, so that the reserved part of each transfer material layer correspondingly forms a second step, and the step structure is obtained. According to the invention, efficient manufacturing of the step structure is realized.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductors, and particularly to a semiconductor structure, a manufacturing method thereof, a memory, and an electronic device. Background Art

[0002] With the development of semiconductor technology, in order to further pursue the miniaturization of device structures, the process has been transformed from planarization to three-dimensionalization, that is, the three-dimensional arrangement of memory cells has become the main development direction of current memory structure research.

[0003] Currently, in three-dimensional memories, when leading out bit lines at different height positions, it is necessary to lead out each layer of bit lines separately. However, as the number of stacked layers of memory cells increases to hundreds or thousands of layers, the number of separate lead-out processes also needs to increase by hundreds or thousands, which seriously increases the complexity of the process. Therefore, the manufacturing of the staircase structure is particularly important. Summary of the Invention

[0004] Based on this, some embodiments of the present disclosure provide a semiconductor structure, a manufacturing method thereof, a memory, and an electronic device to achieve the efficient manufacturing of the staircase structure.

[0005] To achieve the above object, in a first aspect, some embodiments of the present disclosure provide a manufacturing method of a semiconductor structure, including:

[0006] Providing a substrate, and forming a stacked structure on one side of the substrate; the stacked structure includes: a plurality of target material layers stacked along a direction perpendicular to the substrate, and transfer material layers located between any two adjacent target material layers.

[0007] Etching the stacked structure along a direction perpendicular to the substrate to form an etching trench extending along a first direction.

[0008] Forming a sacrificial material layer in the etching trench;

[0009] Etching the sacrificial material layer using an isotropic etching process, and synchronously etching the side walls of the target material layers exposed in the etching trench in sequence from top to bottom along a direction parallel to the substrate, so that the remaining portions of the target material layers respectively form first steps, and the plurality of first steps are arranged in a second direction to form an initial staircase structure; wherein the second direction intersects the first direction.

[0010] Using each first step as a mask to etch the adjacent transfer material layers respectively, so that the remaining portions of the transfer material layers respectively form second steps, and a staircase structure is obtained.

[0011] In some embodiments, the etching selectivity between different layers of target material layers and the sacrificial material layer is different.

[0012] In some embodiments, the thickness of the transfer material layer is positively correlated with the width of the second step formed by the adjacent transfer material layer below it.

[0013] In some embodiments, the dimension of the etching trench in the second direction is negatively correlated with the step width difference between any two adjacent first steps.

[0014] In some embodiments, the sacrificial material layer is etched using an isotropic etching process, and simultaneously, the sidewalls of each target material layer exposed in the etching trench are etched in sequence from top to bottom along the direction parallel to the substrate, including: symmetrically etching the sidewalls of each target material layer exposed in the etching trench on the two opposite sides of the etching trench in the second direction to form an initial stepped structure symmetrically arranged with the etching trench as the center.

[0015] In some embodiments, the sacrificial material layer includes a plurality of sub-selection regions distributed at intervals along the direction perpendicular to the substrate and corresponding to the target material layers one by one; wherein, the etching selectivity between the target material layer and the sacrificial material layer of different sub-selection regions is different.

[0016] In some embodiments, before forming the stacked structure on one side of the substrate, the manufacturing method further includes: forming an isolation barrier on one side of the substrate; wherein, the stacked structure is formed on one side of the isolation barrier, and the etching trench exposes the sidewall of the isolation barrier facing the stacked structure.

[0017] In some embodiments, the stacking number of the target material layers is greater than a first threshold; the sacrificial material layer is etched using an isotropic etching process, and simultaneously, the sidewalls of each target material layer exposed in the etching trench are etched in sequence from top to bottom along the direction parallel to the substrate, and further includes:

[0018] Using the target material layer of the target number and the corresponding transfer material layer as an etching unit; the target number is less than or equal to a second threshold, and the second threshold is less than or equal to one-half of the first threshold.

[0019] Etching the sacrificial material layer corresponding to the etching unit one by one from top to bottom, and after forming an initial first step on the target material layer in the etching unit and an initial second step on the transfer material layer in the etching unit, etching the sacrificial material layer corresponding to the next etching unit.

[0020] In some embodiments, the target material layer is an insulating material layer and the transfer material layer is a conductive material layer; or, the target material layer is a conductive material layer and the transfer material layer is an insulating material layer.

[0021] In some embodiments, the target material layer is an insulating material layer and the transfer material layer is a conductive material layer; before etching the adjacent transfer material layers using each first step as a mask to make the remaining parts of the transfer material layers respectively form second steps to obtain a stepped structure, the manufacturing method further includes:

[0022] A first filling layer is formed in the etched grooves and the removal regions of the target material layers, and the material of the first filling layer is the same as that of the transfer material layer; wherein, when etching the adjacent transfer material layers using the respective first steps as masks, etching of the first filling layer is further included.

[0023] In some embodiments, the method for manufacturing the semiconductor structure further includes: after obtaining the stepped structure, forming a second filling layer covering the stepped structure and filling the etched grooves.

[0024] In a second aspect, the present disclosure also provides a semiconductor structure according to some embodiments, including:

[0025] A substrate.

[0026] A stacked structure located on one side of the substrate, including: a plurality of target material layers stacked along a direction perpendicular to the substrate, and a transfer material layer located between any two adjacent target material layers; the stacked structure has etched grooves.

[0027] A sacrificial material layer is filled in the etched grooves.

[0028] Wherein, the target material layer is configured to: after etching, form a plurality of first steps arranged in a second direction; the transfer material layer is configured to: using the adjacent first steps as masks, after etching, form second steps, so that the first steps and the second steps constitute a stepped structure.

[0029] In some embodiments, the semiconductor structure further includes: an isolation barrier located on one side of the stacked structure along a direction parallel to the substrate; wherein, the sacrificial material layer is located between the isolation barrier and the stacked structure.

[0030] In a third aspect, the present disclosure also provides a memory according to some embodiments, including: at least one stepped structure; wherein, the stepped structure is obtained by etching the semiconductor structure as described in the second aspect of the embodiments of the present application; the stepped structure includes: a plurality of first steps stacked along a direction perpendicular to the substrate, and second steps located between any two adjacent first steps.

[0031] In a fourth aspect, the present disclosure also provides an electronic device according to some embodiments, including: the memory as described in the third aspect of the embodiments of the present application.

[0032] The embodiments of the present disclosure may / at least have the following advantages:

[0033] In the embodiments of the present disclosure, by using an isotropic etching process to etch the sacrificial material layer, and synchronously etching the sidewalls of each target material layer exposed in the etching trench in sequence from top to bottom along the direction parallel to the substrate, a stepped structure of multiple target material layers is formed in one step by taking advantage of the different etching times of different target material layers in the spatial dimension; then, using the target material layer as a mask to etch the adjacent transfer material layer, the stepped structure is transferred between the target material layer and the corresponding transfer material layer to form a stepped structure of the transfer material layer, thereby obtaining a stepped structure. In this way, compared with the related art in which step partitions are manufactured by adjusting-etching multiple cycles and stepped structures are formed through multiple replication etching processes, this solution only requires one photomask pattern definition to achieve the manufacture of multi-layer stepped structures, thereby reducing the complexity of the process and achieving the efficient manufacture of stepped structures.

[0034] Details of one or more embodiments of the present disclosure are set forth in the following drawings and description. Other features, objects, and advantages of the present disclosure will become apparent from the specification, drawings, and claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure or in the prior art, the following will briefly introduce the drawings required for use in the description of the embodiments or the prior art. Obviously, the following drawings are only some embodiments of the present disclosure. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0036] Figure 1 is a flowchart of a manufacturing method of a semiconductor structure provided in some embodiments;

[0037] Figure 2 is a three-dimensional schematic diagram of a structure obtained after forming an etching trench in some embodiments;

[0038] Figure 3 is a three-dimensional schematic diagram of a structure obtained after forming a sacrificial material layer in some embodiments;

[0039] Figure 4 is a three-dimensional schematic diagram of a structure obtained after forming a first step in some embodiments;

[0040] Figure 5 is a three-dimensional schematic diagram of a structure obtained after forming a first filling layer in some embodiments;

[0041] Figure 6 is a three-dimensional schematic diagram of a stepped structure provided in some embodiments;

[0042] Figure 7A three-dimensional schematic diagram of a structure obtained after forming a second filling layer in some embodiments;

[0043] Figure 8 A three-dimensional schematic diagram of a structure obtained after forming a sacrificial material layer in some other embodiments;

[0044] Figure 9 A flowchart of a manufacturing method of a semiconductor structure provided in some other embodiments;

[0045] Figure 10 A three-dimensional schematic diagram of a structure obtained after forming an etching trench in some other embodiments;

[0046] Figure 11 A three-dimensional schematic diagram of a structure obtained after forming a sacrificial material layer in some other embodiments;

[0047] Figure 12 A three-dimensional schematic diagram of a structure obtained after forming a first step in some other embodiments;

[0048] Figure 13 A three-dimensional schematic diagram of a structure obtained after forming a first filling layer in some other embodiments;

[0049] Figure 14 A three-dimensional schematic diagram of a stepped structure provided in some other embodiments;

[0050] Figure 15 A three-dimensional schematic diagram of a structure obtained after forming a second filling layer in some other embodiments;

[0051] Figure 16 A three-dimensional schematic diagram of a structure obtained after forming a sacrificial material layer in some other embodiments;

[0052] Figure 17 A three-dimensional schematic diagram of a structure obtained after forming an initial first step in some embodiments;

[0053] Figure 18 A three-dimensional schematic diagram of a structure obtained after forming an initial second step in some embodiments;

[0054] Figure 19 A three-dimensional schematic diagram of a structure obtained after etching to expose a transfer material layer in some embodiments;

[0055] Figure 20 A three-dimensional schematic diagram of a structure obtained after forming a first step in some other embodiments;

[0056] Figure 21A three-dimensional schematic diagram of a stepped structure provided in yet other embodiments;

[0057] Figure 22 A three-dimensional schematic diagram of a structure obtained after forming a sacrificial material layer provided in yet other embodiments;

[0058] Figure 23 A three-dimensional schematic diagram of a structure obtained after forming an initial first step provided in other embodiments;

[0059] Figure 24 A three-dimensional schematic diagram of a structure obtained after forming an initial second step provided in other embodiments;

[0060] Figure 25 A three-dimensional schematic diagram of a structure obtained after etching to expose a transfer material layer provided in other embodiments;

[0061] Figure 26 A three-dimensional schematic diagram of a structure obtained after forming a first step provided in yet other embodiments;

[0062] Figure 27 A three-dimensional schematic diagram of a stepped structure provided in yet other embodiments;

[0063] Figure 28 A three-dimensional schematic diagram of a structure obtained after forming a sacrificial material layer provided in yet other embodiments;

[0064] Figure 29 A three-dimensional schematic diagram of a structure obtained after forming an initial first step provided in yet other embodiments;

[0065] Figure 30 A three-dimensional schematic diagram of a structure obtained after forming an initial second step provided in yet other embodiments;

[0066] Figure 31 A three-dimensional schematic diagram of a structure obtained after etching to expose a transfer material layer provided in yet other embodiments;

[0067] Figure 32 A three-dimensional schematic diagram of a structure obtained after forming a first step provided in yet other embodiments;

[0068] Figure 33 A three-dimensional schematic diagram of a stepped structure provided in yet other embodiments;

[0069] Figure 34 A three-dimensional schematic diagram of a structure obtained after forming a second filling layer provided in yet other embodiments;

[0070] Figure 35A three-dimensional schematic diagram of a structure obtained after forming a sacrificial material layer in some other embodiments;

[0071] Figure 36 A three-dimensional schematic diagram of a structure obtained after forming an initial first step in some other embodiments;

[0072] Figure 37 A three-dimensional schematic diagram of a structure obtained after forming an initial second step in some other embodiments;

[0073] Figure 38 A three-dimensional schematic diagram of a structure obtained after etching to expose a transfer material layer in some other embodiments;

[0074] Figure 39 A three-dimensional schematic diagram of a structure obtained after forming a first step in some other embodiments;

[0075] Figure 40 A three-dimensional schematic diagram of a stepped structure provided in some other embodiments;

[0076] Figure 41 A three-dimensional schematic diagram of a structure obtained after forming a second filling layer in some other embodiments;

[0077] Figure 42 A top view schematic diagram of a memory provided in some embodiments;

[0078] Figure 43 A three-dimensional schematic diagram of a structure obtained after forming an initial target material layer and an initial transfer material layer in some embodiments;

[0079] Figure 44 A three-dimensional schematic diagram of a structure obtained after forming a target material layer and a transfer material layer in some embodiments.

[0080] Explanation of reference numerals:

[0081] 1 - Substrate, 2 - Stacked structure, 21 - Target material layer, 22 - Transfer material layer, 210 - Initial target material layer, 220 - Initial transfer material layer, U - Etching unit, G - Etching trench, 3 - Sacrificial material layer, 31 - Sub - selection area, 4 - Stepped structure, 41 - First step, 42 - Second step, 41A - Initial first step, 42A - Initial second step, 5 - Isolation barrier, 6 - Isolation layer, 71 - First filling layer, 72 - Second filling layer, 81 - Gate, 82 - Gate dielectric layer, 83 - Semiconductor layer, 9 - Photoresist pattern, 91 - Etching protection layer, WL - Word line, BL - Bit line, CBL - Common bit line, C - Capacitor, CT - Lead. Detailed implementation manners

[0082] For the convenience of understanding the present disclosure, the present disclosure will be described more comprehensively below with reference to the relevant accompanying drawings. Preferred embodiments of the present disclosure are shown in the drawings. However, the present disclosure may be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, these embodiments are provided so that the disclosure of the present disclosure is more thorough and comprehensive.

[0083] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the technical field to which this disclosure belongs. The terms used herein in the specification of the present disclosure are only for the purpose of describing specific embodiments and are not intended to limit the present disclosure.

[0084] It should be understood that when an element or layer is referred to as "on", "adjacent to", or "connected to" another element or layer, it can be directly on, adjacent to, connected, or coupled to the other element or layer, or there may be intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, doping types, and / or parts, these elements, components, regions, layers, doping types, and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, doping type, or part from another element, component, region, layer, doping type, or part. Thus, without departing from the teachings of the present disclosure, the first element, component, region, layer, doping type, or part discussed below may be referred to as the second element, component, region, layer, or part.

[0085] As used herein, the singular forms "a", "an", and "the" may also include the plural forms unless the context clearly dictates otherwise. It should also be understood that when the terms "comprise" and / or "include" are used in this specification, the presence of the stated features, integers, steps, operations, elements, and / or components can be determined, but one or more other features, integers, steps, operations, elements, components, and / or groups may not be excluded. At the same time, as used herein, the term "and / or" includes any and all combinations of the related listed items.

[0086] Embodiments of the invention are described herein with reference to cross-sectional views that are schematic illustrations of ideal embodiments (and intermediate structures) of the present disclosure, and such variations in the illustrated shapes due to, for example, manufacturing techniques and / or tolerances can be expected. Embodiments of the present disclosure should not be limited to the specific shapes of the regions shown herein, but include shape deviations due to, for example, manufacturing techniques. Thus, the regions shown in the figures are substantially schematic, and their shapes do not represent the actual shapes of the regions of the device and do not limit the scope of the present disclosure.

[0087] In three-dimensional memories, the staircase structure based on the metal-oxide stack structure has received extensive attention. The staircase structure can be formed by alternately stacking multiple insulating layers and multiple conductive layers, so as to lead out the signal lines connecting the memory cells of the corresponding layer using any conductive layer, and solve the problem that it is difficult to lead out the signal lines after the memory cells are stacked three-dimensionally.

[0088] In the current manufacturing method, it is necessary to manufacture the step partitions through multiple cycles of trimming-etching, and multiple replication-etching processes to form the staircase structure. However, as the number of stacked layers of memory cells in the three-dimensional memory increases, this manufacturing method of the staircase structure that requires repeated etching also becomes more complicated. Therefore, a more efficient manufacturing method of the staircase structure needs to be developed urgently.

[0089] Based on this, some embodiments of the present disclosure provide a manufacturing method of a semiconductor structure, which is beneficial to reducing the complexity of the process steps and realizing the efficient manufacturing of the staircase structure.

[0090] In a first aspect, please refer to Figures 1 - 6 , some embodiments of the present disclosure provide a manufacturing method of a semiconductor structure, including the following steps S100 to S500.

[0091] S100, please refer to Figure 1 and Figure 2 , provide a substrate 1, and form a stack structure 2 on one side of the substrate 1; the stack structure 2 includes: a plurality of target material layers 21 stacked along a direction perpendicular to the substrate 1, and a transfer material layer 22 located between any two adjacent target material layers 21.

[0092] In some embodiments, please refer to Figure 2 , the surface of the substrate 1 has an isolation layer 6, and the isolation layer 6 is disposed between the substrate 1 and the stack structure 2 for protecting the substrate 1 from being etched.

[0093] In some examples, the stack structure 2 starts to be stacked with the target material layer 21. The isolation layer 6 and the target material layer 21 are formed of different materials.

[0094] Exemplarily, the isolation layer 6 can be an insulating material such as nitride, oxide or oxynitride. The isolation layer 6 is, for example, a silicon nitride layer or a silicon oxide layer.

[0095] Exemplarily, the substrate 1 can be composed of a semiconductor material, an insulating material, a conductive material, or any combination of their material types. The substrate 1 can be a single-layer structure or a multi-layer structure. For example, the substrate 1 can be a substrate such as a silicon (Si) substrate, a silicon germanium (SiGe) substrate, a silicon germanium carbon (SiGeC) substrate, a silicon carbide (SiC) substrate, a gallium arsenide (GaAs) substrate, an indium arsenide (InAs) substrate, an indium phosphide (InP) substrate, or other III / V semiconductor substrates or II / VI semiconductor substrates. Or, for another example, the substrate 1 can be a layered substrate including a stack such as Si and SiGe, a stack of Si and SiC, silicon on insulator (SOI), or silicon germanium on insulator, etc.

[0096] In some embodiments, the thicknesses of the plurality of target material layers 21 can be the same or different, and the thicknesses of the plurality of transfer material layers 22 can be the same or different. The thicknesses of the target material layer 21 and the transfer material layer 22 can be set according to specific process requirements. In addition, the stacked structure 2 can include multiple pairs of target material layers 21 and transfer material layers 22 that are alternately stacked. For example, the stacked structure 2 can include 32 pairs, 64 pairs, 128 pairs, or more than 128 pairs of target material layers 21 and transfer material layers 22. It should be noted that although specific numbers of pairs of the target material layer 21 and the transfer material layer 22 are exemplified here, in other embodiments, other numbers of pairs of the target material layer 21 and the transfer material layer 22 can also be used, and the present disclosure does not limit this.

[0097] S200, please refer to Figure 1 and Figure 2 , etch the stacked structure 2 along the direction perpendicular to the substrate 1 to form an etch trench G extending in the first direction (e.g., the Y direction).

[0098] In some embodiments, please refer to Figure 2 , the etch trench G can penetrate the stacked structure 2 and extend to the substrate 1, or can only penetrate several pairs of the target material layer 21 and the transfer material layer 22 in the stacked structure 2. It should be noted that in the embodiments of the present disclosure, the number of steps in the finally formed stepped structure is less than or equal to the number of pairs of the target material layer 21 and the transfer material layer 22 penetrated by the etch trench G.

[0099] Exemplarily, the etch trench G can be formed by dry etching based on a photomask.

[0100] S300, please refer to Figure 1 and Figure 3 , form a sacrificial material layer 3 in the etch trench G.

[0101] Exemplarily, the sacrificial material layer 3 is formed by a deposition process, including but not limited to physical vapor deposition process, chemical vapor deposition process, epitaxial deposition process, or atomic layer deposition process, etc.

[0102] Exemplarily, after forming the sacrificial material layer 3 in the etching trench G, the manufacturing method of the semiconductor structure further includes: using a grinding process to make the surface of the sacrificial material layer 3 facing away from the substrate 1 flush with the surface of the stacked structure 2 facing away from the substrate 1, and the grinding process includes but is not limited to a Chemical Mechanical Polishing (CMP) process.

[0103] S400, please refer to Figure 1 and Figure 4 , using an isotropic etching process to etch the sacrificial material layer 3, and synchronously etching the sidewalls of the target material layers 21 exposed in the etching trench G in sequence from top to bottom along the direction parallel to the substrate 1, so that the remaining portions of the target material layers 21 correspondingly form first steps 41, and the plurality of first steps 41 are arranged in a second direction (e.g., the X direction) to form an initial stepped structure; wherein, the second direction (e.g., the X direction) intersects with the first direction (e.g., the Y direction).

[0104] In this step, it should be noted that there is a high etching selectivity between the target material layer 21 and the transfer material layer 22, so as to achieve etching only the sacrificial material layer 3 and the target material layer 21 without etching the transfer material layer 22.

[0105] Exemplarily, the isotropic etching process can be wet etching, or can be isotropic dry remote plasma source (RPS) etching or vapor etching.

[0106] It should be noted that in the isotropic etching process, when etching the same material, the etching rates in all directions are the same.

[0107] In the embodiment of the present disclosure, when using the isotropic etching process for etching, it can be understood that since the etching is performed from top to bottom at the opening of the etching trench G facing away from the substrate 1, the sidewalls of the corresponding target material layers 21 exposed in the etching trench G can also be etched layer by layer from top to bottom, resulting in different etching times for each layer of the target material layers 21 in the spatial dimension, that is, the upper layer has a longer etching time and the lower layer has a shorter etching time, and the etching rate is the same in all directions. Thus, please refer to Figure 4 , it can be made that the remaining portions of the target material layers 21 correspondingly form first steps 41, and the plurality of first steps 41 are arranged in a second direction (e.g., the X direction) to form an initial stepped structure.

[0108] In the embodiments of the present disclosure, when forming the first step 41, the side walls of each target material layer 21 exposed in the etching trench G are etched in sequence based on the etching depth of the sacrificial material layer 3 in the etching trench G, so that each target material layer 21 is only etched in the second direction (for example, the X direction), which can effectively avoid the side etching problem of the photoresist in the prior art, strengthen the controllability of the formation of the stepped structure 4 and break through the layer number limit, and realize the manufacture of the infinite stepped structure 4.

[0109] S500, please refer to Figure 1 、 Figure 5 and Figure 6 , and use each first step 41 as a mask to etch the adjacent transfer material layers 22 respectively, so that the remaining parts of each transfer material layer 22 correspondingly form the second step 42, and the stepped structure 4 is obtained.

[0110] Exemplarily, please refer to Figure 5 , before performing step S500, the manufacturing method of the semiconductor structure further includes: forming a first filling layer 71 in the etching trench G and the removal area of each target material layer 21; wherein, the material of the first filling layer 71 can be the same as the material of the transfer material layer 22.

[0111] Exemplarily, the material of the first filling layer 71 can be W, or can also be Cu, Al, Ti, Mo, Nb, V, Hf, Ta, Cr, Zr, Fe, Ru, Os, Co, Rh, Ir, Ni, Pa, Pt, Ag, Au, and Co-based alloys, Fe-based alloys, Ni-based alloys, FeNi-based alloys, CoNi-based alloys, FeCo-based alloys, Al-based alloys, Cu-based alloys, Mg-based alloys, Ti-based alloys, low-carbon steel, stainless steel, or conductive metal nitrides (such as titanium nitride TiN), conductive metal silicides, conductive metal carbides, conductive doped semiconductors (such as doped polysilicon), conductive metal oxide semiconductors (such as indium tin oxide) and other conductive materials, and can also be semiconductor or dielectric materials such as SiNx, doped polysilicon, amorphous silicon, doped polysilicon germanium, AsGa, AlAsGa, InP, etc.

[0112] Exemplarily, please refer to Figure 6 , the etching process of the first step 41 adjacent to the transfer material layer 22 includes dry etching (Dryetch).

[0113] It should be noted that, please continue to refer to Figure 6 , using each first step 41 as a mask to self-align and etch the adjacent transfer material layers 22 located below it can realize the transfer of the corresponding step pattern of any first step 41 between adjacent film layers. It can be understood that each first step 41 and the corresponding second step 42 located below it have the same projection on the substrate 1 and constitute the same step.

[0114] In the embodiments of the present disclosure, based on the isotropic etching process, the efficient manufacturing of the stepped structure 4 is realized; moreover, by utilizing the high etching selectivity between the target material layer 21 and the transfer material layer 22, the transfer of the stepped structure between the film layers can be achieved. Compared with the prior art, the embodiments of the present disclosure do not need to manufacture step partitions, only need to perform one mask pattern definition (i.e., form the etching trench G), and realize the manufacturing of the multi-layer stepped structure 4 based on the isotropic etching process and the self-aligned etching process, thereby reducing the complexity of the process procedures and realizing the efficient manufacturing of the stepped structure 4.

[0115] In some embodiments, the target material layer 21 is an insulating material layer and the transfer material layer 22 is a conductive material layer; or, the target material layer 21 is a conductive material layer and the transfer material layer 22 is an insulating material layer.

[0116] In some possible implementation manners, the target material layer 21 is an insulating material layer and the transfer material layer 22 is a conductive material layer.

[0117] Exemplarily, the target material layer 21 may be a SiO2 material, or may also be SiN x 、AlO x 、HfO x 、TiO x 、SiO x N y 、SiO x C z N y or other insulating materials;

[0118] Exemplarily, the transfer material layer 22 may be W, or may also be Cu, Al, Ti, Mo, Nb, V, Hf, Ta, Cr, Zr, Fe, Ru, Os, Co, Rh, Ir, Ni, Pa, Pt, Ag, Au, and Co-based alloys, Fe-based alloys, Ni-based alloys, FeNi-based alloys, CoNi-based alloys, FeCo-based alloys, Al-based alloys, Cu-based alloys, Mg-based alloys, Ti-based alloys, low-carbon steel, stainless steel, or conductive metal nitrides (such as titanium nitride TiN), conductive metal silicides, conductive metal carbides, conductive doped semiconductors (such as doped polysilicon), conductive metal oxide semiconductors (such as indium tin oxide) and other conductive materials, or may also be SiN x 、doped polysilicon, amorphous silicon, doped polysilicon germanium, AsGa, AlAsGa, InP and other semiconductors or dielectric materials.

[0119] Exemplarily, both the target material layer 21 and the sacrificial material layer 3 are insulating material layers, and the materials used for the target material layer 21 and the sacrificial material layer 3 may be the same or different.

[0120] Exemplarily, the sacrificial material layer 3 can be made of SiO2 material with different growth conditions or doping types from the target material layer 21, and can also be SiN x , AlO x , HfO x , TiO x , SiO x N y , SiO x C z N y or other insulating materials.

[0121] In some other possible embodiments, the target material layer 21 is a conductive material layer and the transfer material layer 22 is an insulating material layer.

[0122] Exemplarily, the target material layer 21 can be W, and can also be Cu, Al, Ti, Mo, Nb, V, Hf, Ta, Cr, Zr, Fe, Ru, Os, Co, Rh, Ir, Ni, Pa, Pt, Ag, Au, and Co-based alloys, Fe-based alloys, Ni-based alloys, FeNi-based alloys, CoNi-based alloys, FeCo-based alloys, Al-based alloys, Cu-based alloys, Mg-based alloys, Ti-based alloys, low-carbon steel, stainless steel, or conductive materials such as conductive metal nitrides (such as titanium nitride TiN), conductive metal silicides, conductive metal carbides, conductive doped semiconductors (such as doped polysilicon), conductive metal oxide semiconductors (such as indium tin oxide), etc. It can also be SiN x , doped polysilicon, amorphous silicon, doped polysilicon germanium, AsGa, AlAsGa, InP and other semiconductors or dielectric materials.

[0123] Exemplarily, the transfer material layer 22 can be made of SiO2 material, and can also be SiN x , AlO x , HfO x , TiO x , SiO x N y , SiO x C z N y or other insulating materials.

[0124] Exemplarily, both the target material layer 21 and the sacrificial material layer 3 are conductive material layers, and the materials used for the target material layer 21 and the sacrificial material layer 3 can be the same or different.

[0125] Exemplarily, the sacrificial material layer 3 can be TiN, W, or can also be Cu, Al, Ti, Mo, Nb, V, Hf, Ta, Cr, Zr, Fe, Ru, Os, Co, Rh, Ir, Ni, Pa, Pt, Ag, Au, as well as Co-based alloys, Fe-based alloys, Ni-based alloys, FeNi-based alloys, CoNi-based alloys, FeCo-based alloys, Al-based alloys, Cu-based alloys, Mg-based alloys, Ti-based alloys, low-carbon steel, stainless steel, or conductive materials such as conductive metal nitrides (such as titanium nitride TiN), conductive metal silicides, conductive metal carbides, conductive doped semiconductors (such as doped polysilicon), and conductive metal oxide semiconductors (such as indium tin oxide).

[0126] It is worth mentioning that in the embodiments of the present disclosure, the width of each step in the stepped structure 4 can be controlled by one or more of the following methods: adjusting the etching selectivity of each target material layer 21 relative to the sacrificial material layer 3, adjusting the thickness of the transfer material layer 22, or adjusting the width of the etching trench G.

[0127] In some embodiments, the etching rate of the sacrificial material layer 3 is less than or equal to the etching rate of the target material layer 21. In this way, as the etching depth of the sacrificial material layer 3 changes, it is beneficial to ensure that the target material layer 21 can have an etching amount that meets the requirements to form a step with a target step width.

[0128] In some embodiments, the etching selectivity between the target material layers 21 of different layers and the sacrificial material layer 3 is different. For example, the etching selectivity between each target material layer 21 and the sacrificial material layer 3 can be made different by respectively using different doping types, doping concentrations, or different growth conditions for the target material layers 21 of different layers. Or, in some other examples, the etching selectivity between the sacrificial material layer 3 and each layer of the target material layer 21 can be made different by respectively using different doping types, doping concentrations, or different growth conditions to form different regions in the sacrificial material layer 3 corresponding to each layer of the target material layer 21.

[0129] In the embodiments of the present disclosure, it should be explained that when the sacrificial material layer 3 is etched from top to bottom, the etching of each layer of the target material layer 21 is also carried out synchronously. In this way, by controlling the etching selectivity between the sacrificial material layer 3 and each layer of the target material layer 21, the etching rate difference between each layer of the target material layer 21 and the sacrificial material layer 3 can be controlled, thereby realizing the regulation of the step width and strengthening the controllability of the formation of the stepped structure 4.

[0130] Exemplarily, the higher the etching selectivity of the target material layer 21 relative to the sacrificial material layer 3, the larger the width of the first step 41 that can be formed by the lower target material layer 21.

[0131] In some embodiments, the thickness of the transfer material layer 22 is positively correlated with the width of the second step 42 formed by the adjacent transfer material layer 22 below it.

[0132] Here, please refer to Figure 3 and Figure 4 for understanding. The greater the thickness of the transfer material layer 22, the longer the etching removal time required for the sacrificial material layer 3 in the corresponding thickness region, which can make the etching time of the target material layer 21 above the transfer material layer 22 relatively long, while the etching time of the target material layer 21 below the transfer material layer 22 is relatively short. Thus, it is beneficial to form a first step 41 with a larger width below the transfer material layer 22. Correspondingly, the adjacent transfer material layer 22 below can be etched using the first step 41 as a mask to form a second step 42 with a larger width. Conversely, the smaller the thickness of the transfer material layer 22, the shorter the etching removal time required for the sacrificial material layer 3 in the corresponding thickness region, which can make the etching time of the target material layer 21 above the transfer material layer 22 relatively short, while the etching time of the target material layer 21 below the transfer material layer 22 is relatively long. Thus, it is beneficial to form a first step 41 with a smaller width below the transfer material layer 22. Correspondingly, the adjacent transfer material layer 22 below can be etched using the first step 41 as a mask to form a second step 42 with a smaller width.

[0133] In the embodiments of the present disclosure, by controlling the thickness of the transfer material layer 22, the regulation of the step width is realized, strengthening the controllability of the formation of the stepped structure 4.

[0134] In some embodiments, the size of the etching trench G in the second direction (e.g., the X direction) is negatively correlated with the step width difference between any two adjacent first steps 41.

[0135] It should be explained that the size of the etching trench G in the second direction (e.g., the X direction) is its width. The smaller the width of the etching trench G, due to the etch loading effect, the slower the downward etching rate of the sacrificial material layer 3 in the etching trench G, then the etching time of the upper target material layer 21 can be relatively increased, and the etching time of the lower target material layer 21 can be relatively decreased, which is beneficial to increasing the step width difference between adjacent first steps 41. Conversely, the larger the width of the etching trench G, due to the etch loading effect, the faster the downward etching rate of the sacrificial material layer 3 in the etching trench G, then the etching time of the upper target material layer 21 can be relatively decreased, and the etching time of the lower target material layer 21 can be relatively increased, which is beneficial to decreasing the step width difference between adjacent first steps 41.

[0136] In the embodiments of the present disclosure, by controlling the width of the etching trench G (i.e., the dimension in the second direction), the regulation of the step width difference between adjacent first steps 41 (and adjacent second steps 42) is realized, and the controllability of the formation of the stepped structure 4 is enhanced.

[0137] In some embodiments, please refer to Figure 3 and Figure 4 Understand that in step S400, an isotropic etching process is used to etch the sacrificial material layer 3, and simultaneously, the side walls of each target material layer 21 exposed in the etching trench G are etched in sequence from top to bottom along the direction parallel to the substrate 1, including: symmetrically etching the side walls of each target material layer 21 exposed in the etching trench G on the opposite sides of the etching trench G in the second direction (e.g., the X direction) to form an initial stepped structure symmetrically arranged with the etching trench G as the center.

[0138] In the embodiments of the present disclosure, based on the same etching trench G, an initial stepped structure symmetrically arranged with the etching trench G as the center can be formed by synchronous etching on the opposite sides of the etching trench G in the second direction (e.g., the X direction), for example Figure 4 as shown in, which is beneficial to improving production efficiency and reducing production costs.

[0139] Exemplarily, to symmetrically etch the side walls of each target material layer 21 exposed in the etching trench G on the opposite sides of the etching trench G in the second direction, a hydrogen fluoride vapor etching process (HF vapor etch) can be used.

[0140] In some embodiments, please refer to Figure 7 , after performing step S500, the method for manufacturing the semiconductor structure further includes: after obtaining the stepped structure 4, forming a second filling layer 72 covering the stepped structure 4 and filling the etching trench G.

[0141] Exemplarily, the second filling layer 72 is an insulating material layer. In some examples, when the target material layer 21 is an insulating material layer, the material of the second filling layer 72 is the same as that of any target material layer 21. In other examples, when the target material layer 21 is a conductive material layer, the material of the second filling layer 72 is the same as that of the transfer material layer 22.

[0142] Exemplarily, the material of the second filling layer 72 can be SiO 2 material, and can also be SiNx, AlOx, HfOx, TiOx, SiOxNy, SiOxCzNy or other insulating materials.

[0143] It should be added that, in some embodiments, the material of the sacrificial material layer 3 can be an oxide; wherein, by selecting the type of oxide of the sacrificial material layer 3, it can be ensured that the etching rates of the target material layer 21 and the sacrificial material layer 3 are different, so as to realize the regulation of the width of the first step 41.

[0144] In some other embodiments, please refer to Figure 8 , the sacrificial material layer 3 includes a plurality of sub-selection regions 31 that are spaced apart along the direction perpendicular to the substrate 1 and correspond to the target material layer 21 one by one; wherein, the etching selectivity ratios between the target material layer 21 and the sacrificial material layer 3 of different sub-selection regions 31 are different.

[0145] Exemplarily, the material of the sacrificial material layer 3 includes silicon oxide, and different doping types, different doping concentrations or different growth conditions can be adopted in different sub-selection regions 31 to achieve different etching selectivity ratios between each sub-selection region 31 and the sacrificial material layer 3.

[0146] In some embodiments, please refer to Figure 9 and Figure 10 , before forming the stacked structure 2 on one side of the substrate 1, the manufacturing method further includes: forming an isolation barrier 5 on one side of the substrate 1; wherein, the stacked structure 2 is formed on one side of the isolation barrier 5, and the etching trench G exposes the side wall of the isolation barrier 5 facing the stacked structure 2.

[0147] Exemplarily, step S100 can be specifically embodied as step S110 as shown in Figure 9 .

[0148] In some examples, the isolation barrier 5 and the isolation layer 6 can be made of the same material or different materials.

[0149] Exemplarily, the isolation barrier 5 and the isolation layer 6 are made of the same material. The isolation barrier 5 and the isolation layer 6 can be patterned after forming the isolation material layer. For example, a stacked structure accommodation groove is formed in the isolation material layer by using a dry etching process, so as to facilitate the subsequent formation of the stacked structure 2 in the stacked structure accommodation groove.

[0150] In some examples, the material of the isolation barrier 5 is different from that of the target material layer 21.

[0151] Exemplarily, the isolation barrier 5 can adopt insulating materials such as nitrides, oxides or oxynitrides. The isolation barrier 5 is, for example, silicon nitride or silicon oxide.

[0152] Thus, in some embodiments in which the isolation barrier 5 is formed, please refer to Figure 10The stacked structure 2 is formed on one side of the isolation retaining wall 5. After etching to form the etched groove G, the etched groove G exposes the sidewall of the isolation retaining wall 5 facing the stacked structure 2. Here, the etched groove G can be formed at the interface between the stacked structure 2 and the isolation retaining wall 5.

[0153] See also Figure 11 , a sacrificial material layer 3 is formed in the etched groove G.

[0154] See also Figure 12 , the sidewalls of each target material layer 21 exposed in the etching groove G are etched on the side of the etching groove G opposite to the isolation retaining wall 5 in the second direction to form an initial step structure distributed on the side of the etching groove G away from the isolation retaining wall 5 in the second direction (for example, the X direction).

[0155] See also Figure 13 A first filling layer 71 is formed in the etching groove G and the removal area of ​​each target material layer 21 . The material of the first filling layer 71 can be the same as that of the transferred material layer 22 .

[0156] See also Figure 14 , using each first step 41 as a mask, the adjacent transfer material layer 22 and the first filling layer 71 are etched respectively to form each second step 42 , thereby obtaining a stepped structure 4 .

[0157] See also Figure 15 , a second filling layer 72 covering the stepped structure 4 and filling the etched trench G is formed.

[0158] In some embodiments, see Figures 16 - 21 , the number of stacked layers of the target material layer 21 is greater than the first threshold. In step S400, the sacrificial material layer 3 is etched using an isotropic etching process, and the sidewalls of each target material layer 21 exposed in the etching groove G are etched sequentially from top to bottom in a direction parallel to the substrate 1. The process can also be implemented as follows.

[0159] See also Figure 16 , a target material layer 21 with a target number of layers and a corresponding transferred material layer 22 are used as an etching unit U; the target number of layers is less than or equal to a second threshold, and the second threshold is less than or equal to half of the first threshold.

[0160] For example, the target number of layers corresponding to different etching units U is the same. However, it is understandable that the target number of layers corresponding to different etching units U is different, which is also allowed.

[0161] Here, when the number of stacked layers of the target material layer 21 in the stacked structure 2 is greater than the first threshold, the process conditions for the target layer matching corresponding to the etching unit U can be selected and set, which can eliminate the influence that the lateral etching rate of the target material layer 21 slows down as the etching depth of the sacrificial material layer 3 increases, so as to facilitate the manufacture of the stepped structure 4 to break through the layer number limit, thereby realizing the efficient manufacture of the stepped structure 4 with unlimited layer numbers.

[0162] Please refer to Figures 17 - 21 , etch the sacrificial material layer 3 corresponding to the etching unit U layer by layer from top to bottom, and after forming the initial first step 41A on the target material layer 21 in the etching unit U and forming the initial second step 42A on the transfer material layer 22 in the etching unit U, etch the sacrificial material layer 3 corresponding to the next etching unit U.

[0163] Here, the etching unit U includes the target material layer 21 and the transfer material layer 22 of the target layer pair. The initial first step 41A and the initial second step 42A refer to: when etching the sacrificial material layer 3 corresponding to the next etching unit U, the intermediate structure between the first step 41 and the second step 42 formed in the previous etching unit U. And, the initial first step 41A and the initial second step 42A (i.e., the intermediate structure between the first step 41 and the second step 42) are continuously etched during the etching process of each subsequent etching unit U until the final stepped structure 4 is obtained (i.e., the etching for forming the steps ends).

[0164] The following takes etching two etching units U to obtain the stepped structure 4 as an example for illustration. However, it can be understood that in some examples, the stepped structure 4 can also be obtained after etching away all the sacrificial material layers 3.

[0165] Please refer to Figure 17 , etch the sacrificial material layer 3 corresponding to the first etching unit U along the direction close to the substrate 1 to form an etching groove G on one side of the sidewall of the first etching unit U, and etch the target material layer 21 of the target layer number based on the etching groove G to form the initial first step 41A.

[0166] Please refer to Figure 18 , use the initial first step 41A as a mask to self-align and etch each transfer material layer 22 in the first etching unit U to form the initial second step 42A.

[0167] It can be understood that in some embodiments, please combine Figure 18 and Figure 19It is understood that after etching to form the initial second step 42A, if the top initial first step 41A is an insulating step and the top target material layer 21 in the second etching unit U is an insulating material layer, the top insulating step and the exposed portion of the top insulating material layer in the second etching unit U can be etched away first, or after forming a first filling layer 71 that fills the etched groove G and covers the resulting structure, the first filling layer 71 and the corresponding transfer material layers 22 can be simultaneously etched to form the initial second step 42A, and the material of the first filling layer 71 can be the same as that of the transfer material layer 22.

[0168] See also Figure 20 , the sacrificial material layer 3 corresponding to the second etching unit U is etched so that the etching groove G extends to one side of the side wall of the second etching unit U along the direction close to the substrate 1, and each target material layer 21 in the first etching unit U and the second etching unit U is etched based on the etching groove G to form a first step 41.

[0169] See also Figure 21 , using the first step 41 as a mask, self-aligningly etches each transfer material layer 22 in the first etching unit U and the second etching unit U to form a second step 42 .

[0170] From the above, in the embodiment of the present disclosure, the sacrificial material layer 3 corresponding to different etching units U can be etched in stages based on the same photomask to form etching grooves G in stages and to perform side etching in sequence on the corresponding target material layer 21. Moreover, it can be understood that after the sacrificial material layer 3 is etched or the etching of the sacrificial material layer 3 is finished, the steps obtained correspond to the first step 41 and the second step 42.

[0171] In some embodiments, see Figure 21 , the target material layer 21 is an insulating material layer, and the transfer material layer 22 is a conductive material layer. The etching units U located on opposite sides of the etching groove G in the second direction (for example, the X direction) can form a stepped structure 4 with double-sided steps symmetrically arranged around the etching groove G after performing the corresponding etching process.

[0172] In other embodiments, see Figures 22 - 27 The target material layer 21 is an insulating material layer, and the transfer material layer 22 is a conductive material layer. Each etching unit U located on the side of the etching groove G away from the isolation barrier 5 in the second direction (eg, X direction) can form a stepped structure 4 with a single side step after performing a corresponding etching process.

[0173] The following is an example of etching two etching units U to obtain a stepped structure 4 with a single step. However, it can be understood that in some examples, the stepped structure 4 can also be obtained after etching away all the sacrificial material layers 3.

[0174] Please refer to Figure 22 and Figure 23 , along the direction close to the substrate 1, etch the sacrificial material layer 3 corresponding to the first etching unit U, so as to form an etching groove G on one side of the side wall of the first etching unit U, and expose one side wall of the isolation barrier 5 through the etching groove G; etch the target material layer 21 with the target number of layers based on the etching groove G to form an initial first step 41A.

[0175] Please refer to Figure 24 , using each initial first step 41A as a mask to self-align and etch each transfer material layer 22 in the first etching unit U to form an initial second step 42A.

[0176] It can be understood that in some embodiments, please combine Figure 24 and Figure 25 to understand that after etching to form the initial second step 42A, if the top-layer initial first step 41A is an insulating step and the top-layer target material layer 21 in the second etching unit U is an insulating material layer, the exposed part of the top-layer insulating step and the top-layer insulating material layer in the second etching unit U can be etched and removed first, or after forming the first filling layer 71 that fills the etching groove G and covers the obtained structure, the first filling layer 71 and the corresponding transfer material layers 22 can be etched synchronously to form the initial second step 42A. The material of the first filling layer 71 can be the same as that of the transfer material layer 22.

[0177] Please refer to Figure 26 , etch the sacrificial material layer 3 corresponding to the second etching unit U, so that the etching groove G extends along the direction close to the substrate to one side of the side wall of the second etching unit U, and etch each target material layer 21 in the first etching unit U and the second etching unit U based on the etching groove G to form a first step 41.

[0178] Please refer to Figure 27 , using the first step 41 as a mask to self-align and etch each transfer material layer 22 in the first etching unit U and the second etching unit U to form a second step 42.

[0179] In still other embodiments, please refer to Figures 28 - 34 , the target material layer 21 is a conductive material layer and the transfer material layer 22 is an insulating material layer. Each etching unit U located on opposite sides of the etching groove G in the second direction (e.g., the X direction) can form a stepped structure 4 with bilateral steps symmetrically arranged with the etching groove G as the center after performing the corresponding etching process.

[0180] Here, the etching steps of each etching unit U can refer to the manufacturing process of the stepped structure 4 with bilateral steps in the foregoing some embodiments, and will not be elaborated here.

[0181] In some other embodiments, see Figures 35 - 41 The target material layer 21 is a conductive material layer, and the transfer material layer 22 is an insulating material layer. Each etching unit U located on the side of the etching groove G away from the isolation barrier 5 in the second direction (eg, X direction) can form a stepped structure with a single side step after performing a corresponding etching process.

[0182] Here, the etching steps of each etching unit U may be performed with reference to the manufacturing process of the stepped structure 4 with a single-side step in some of the aforementioned embodiments, which will not be described in detail here.

[0183] In the second aspect, the present disclosure also provides a semiconductor structure according to some embodiments. It should be noted that the technical advantages of the manufacturing method of the aforementioned semiconductor structure are also possessed by the structure, and the same or corresponding technical features as the aforementioned embodiments can be referred to the corresponding description of the corresponding technical features in the aforementioned embodiments, and will not be described in detail below.

[0184] In some embodiments, see Figure 3 , Figure 8 , Figure 11 , Figure 16 , Figure 22 and Figure 28 , the semiconductor structure includes: a substrate 1, a stacked structure 2 and a sacrificial material layer 3. The stacked structure 2 is located on one side of the substrate 1, and includes: a plurality of target material layers 21 stacked in a direction perpendicular to the substrate 1, and a transfer material layer 22 located between any two adjacent target material layers 21; the stacked structure 2 has an etching groove G. The sacrificial material layer 3 is filled in the etching groove G. Among them, the target material layer 21 is configured to form a plurality of first steps 41 arranged along the second direction after etching. The transfer material layer 22 is configured to form a second step 42 after etching using the adjacent first step 41 as a mask, so that each first step 41 and each second step 42 constitute a step structure 4.

[0185] In some embodiments, the target material layer 21 is an insulating material layer, and the transfer material layer 22 is a conductive material layer.

[0186] In other embodiments, the target material layer 21 is a conductive material layer, and the transfer material layer 22 is an insulating material layer.

[0187] In some embodiments, see Figure 3 and Figure 8 The semiconductor structure further includes: an isolation layer 6 arranged between the substrate 1 and the stacked structure 2 .

[0188] In some embodiments, see Figure 11 , Figure 22 and Figure 35, the semiconductor structure further includes: an isolation barrier 5 located on one side of the stacked structure 2 along a direction parallel to the substrate 1; wherein, the sacrificial material layer 3 is located between the isolation barrier 5 and the stacked structure 2.

[0189] In some embodiments, the etch selectivity between different layer target material layers 21 and the sacrificial material layer 3 is different.

[0190] In some examples, the sacrificial material layer 3 includes a plurality of sub-selection regions 31 that are spaced apart along a direction perpendicular to the substrate 1 and correspond one-to-one with the target material layers 21; wherein, the etch selectivity between the target material layer 21 and the sacrificial material layer 3 of different sub-selection regions 31 is different.

[0191] In some embodiments, the thickness of the transfer material layer 22 (i.e., the dimension in the direction perpendicular to the substrate 1) is positively correlated with the width of the second step to be formed by the adjacent transfer material layer below it.

[0192] In some embodiments, the dimension of the etch trench G in the second direction (e.g., the X direction) is negatively correlated with the step width difference between any two adjacent first steps to be formed.

[0193] In a third aspect, the present disclosure also provides a memory according to some embodiments. It should be noted that the memory also has all the technical advantages of the aforementioned semiconductor structure and its manufacturing method. For the same or corresponding parts as those in the above embodiments, reference can be made to the corresponding descriptions in the foregoing embodiments, and details will not be elaborated below.

[0194] In some embodiments, the memory includes: at least one stepped structure 4; wherein, the stepped structure 4 can be obtained by etching the semiconductor structure as described in the second aspect of the embodiments of the present disclosure. The stepped structure 4 includes: a plurality of first steps 41 stacked along a direction perpendicular to the substrate 1, and a second step 42 located between any two adjacent first steps 41.

[0195] Here, it can be understood that the manufacturing method of etching the aforementioned semiconductor structure to form the stepped structure 4 can refer to the relevant etching steps in the manufacturing method of the semiconductor structure described in the first aspect of the embodiments of the present disclosure.

[0196] In addition, the distribution position, distribution quantity, and the number of stacked steps therein of the stepped structure 4 in the memory in the embodiments of the present disclosure can all be set according to requirements. The embodiments of the present disclosure do not limit this.

[0197] Figure 42 An exemplary top view structure of a memory is provided. Please refer to Figure 42, the memory includes an array region and a peripheral region. The stepped structure 4 can be disposed in the peripheral region. The memory further includes a plurality of memory cells arrayed in the array region. The memory cells include, for example: a transistor T and a capacitor C. The transistor T includes a gate 81, a gate dielectric layer 82 and a semiconductor layer 83 surrounding the sidewalls of the gate 81; wherein, the gate 81 is electrically connected to the word line WL; the semiconductor layer 83 can serve as the channel region and source / drain of the transistor T, and the outer walls on the opposite sides of the semiconductor layer 83 in the X direction are electrically connected to the bit line BL and the first electrode of the capacitor C respectively. The capacitor C further includes a dielectric layer covering the first electrode and a second electrode covering the dielectric layer. The word line WL can extend in a direction perpendicular to the substrate 1. The bit line BL can extend in the Y direction. And, the plurality of memory cells can be arranged at intervals in the Y direction to form columns.

[0198] Exemplarily, a column of memory cells shares the same bit line BL.

[0199] Exemplarily, two adjacent columns of memory cells are respectively located on both sides of the bit line BL and share the same bit line BL.

[0200] Exemplarily, please continue to refer to Figure 42 , the memory further includes: a common bit line CBL disposed on the same layer as the bit line BL; wherein, each bit line BL can be electrically connected to the common bit line CBL on the same layer through a corresponding selection transistor ( Figure 42 not shown in the figure). Here, being disposed on the same layer means that: the heights of the two from the surface of the substrate 1 are substantially the same.

[0201] It should be added that, in some of the above embodiments, each conductive step in the stepped structure 4 can be respectively an external connection end of the corresponding common bit line CBL and is led out through a lead CT.

[0202] In some embodiments, please refer to Figure 43 and Figure 44 , the target material layer 21 and the transfer material layer 22 for forming each step in the stepped structure 4 can be formed by etching using a patterning process after alternately laminating a plurality of initial target material layers 210 and a plurality of initial transfer material layers 220 in a direction perpendicular to the substrate 1.

[0203] Exemplarily, as shown in Figure 43 , a plurality of initial target material layers 210 and a plurality of initial transfer material layers 220 are alternately laminated in a direction perpendicular to the substrate 1, for example, starting with the initial target material layer 210 and ending with the initial transfer material layer 220. Then, an etching protection layer 91 can be formed on the upper surface of the topmost initial transfer material layer 220, and a photoresist pattern 9 can be formed on the surface of the etching protection layer 91. Thus, each initial target material layer 210 and each initial transfer material layer 220 can be etched based on the photoresist pattern 9 to obtain as shown in Figure 44The stacked structure shown in [description], the stacked structure includes each target material layer 21 and transfer material layer 22 mentioned in some of the foregoing embodiments, and can simultaneously form the required insulating pattern and conductive pattern in the array region.

[0204] Exemplarily, the etching protection layer 91 can be a hard mask layer, such as a silicon nitride layer; or, the etching protection layer 91 can be an anti-reflection layer.

[0205] Fourthly, according to some embodiments, the present disclosure further provides an electronic device, including: a memory as described in the third aspect of the embodiments of the present application. It should be noted that the technical advantages of the foregoing semiconductor structure, its manufacturing method, and the memory are also possessed by this electronic device. For the same or corresponding parts as those in the above embodiments, reference may be made to the corresponding descriptions in the foregoing embodiments, which will not be elaborated in detail below.

[0206] The technical features of the above embodiments can be combined arbitrarily. For the sake of brevity of description, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, it should be considered as the scope recorded in this specification.

[0207] The above-described embodiments only represent several implementation manners of the present disclosure, and their descriptions are relatively specific and detailed, but they should not be construed as limiting the scope of the invention patent. It should be pointed out that for those of ordinary skill in the art, without departing from the concept of the present disclosure, several modifications and improvements can still be made, and these all belong to the protection scope of the present disclosure.

Claims

1. A manufacturing method of a semiconductor structure, characterized in that, comprising: providing a substrate, and forming a stacked structure on one side of the substrate; the stacked structure includes: a plurality of target material layers stacked along a direction perpendicular to the substrate, and transfer material layers located between any two adjacent target material layers; etching the stacked structure along a direction perpendicular to the substrate to form an etching trench extending in a first direction; forming a sacrificial material layer in the etching trench; etching the sacrificial material layer by using an isotropic etching process, and simultaneously etching the sidewalls of the target material layers exposed in the etching trench in sequence from top to bottom along a direction parallel to the substrate, so that the remaining portions of the target material layers respectively form first steps, and the plurality of first steps are arranged in a second direction to form an initial stepped structure; wherein, the second direction intersects with the first direction; etching the adjacent transfer material layers respectively by using the first steps as masks, so that the remaining portions of the transfer material layers respectively form second steps, and a stepped structure is obtained.

2. The manufacturing method of the semiconductor structure according to claim 1, characterized in that, the etching selectivity ratios between the target material layers of different layers and the sacrificial material layer are different.

3. The manufacturing method of the semiconductor structure according to claim 2, characterized in that, the thickness of the transfer material layer is positively correlated with the width of the second step formed by the adjacent transfer material layer below it.

4. The manufacturing method of the semiconductor structure according to claim 2, characterized in that, the dimension of the etching trench in the second direction is negatively correlated with the step width difference between any two adjacent first steps.

5. The manufacturing method of the semiconductor structure according to claim 1, characterized in that, the etching the sacrificial material layer by using an isotropic etching process, and simultaneously etching the sidewalls of the target material layers exposed in the etching trench in sequence from top to bottom along a direction parallel to the substrate includes: etching the sidewalls of the target material layers exposed in the etching trench symmetrically on two opposite sides of the etching trench in the second direction, so as to form the initial stepped structure symmetrically arranged with the etching trench as the center.

6. The manufacturing method of the semiconductor structure according to claim 1, characterized in that, the sacrificial material layer includes a plurality of sub-selection regions distributed at intervals along a direction perpendicular to the substrate and corresponding to the target material layers one by one; wherein, the etching selectivity ratios between the target material layer and the sacrificial material layers of different sub-selection regions are different.

7. The manufacturing method of the semiconductor structure according to claim 1, characterized in that, before forming the stacked structure on one side of the substrate, the manufacturing method further includes: forming an isolation barrier on one side of the substrate; wherein, the stacked structure is formed on one side of the isolation barrier, and the etching trench exposes the sidewall of the isolation barrier facing the stacked structure.

8. The manufacturing method of the semiconductor structure according to claim 1, characterized in that, The number of stacked layers of the target material layer is greater than a first threshold; etching the sacrificial material layer using an isotropic etching process, and synchronously etching the sidewalls of the target material layers exposed in the etching trench from top to bottom in sequence along a direction parallel to the substrate, further comprising: Using the target material layer of the target number of layers and the corresponding transfer material layer as an etching unit; the target number of layers is less than or equal to a second threshold, and the second threshold is less than or equal to one-half of the first threshold; Etching the sacrificial material layer corresponding to the etching unit from top to bottom one by one, and after forming an initial first step on the target material layer in the etching unit and forming an initial second step on the transfer material layer in the etching unit, etching the sacrificial material layer corresponding to the next etching unit.

9. The manufacturing method of a semiconductor structure according to any one of claims 1 to 8, characterized in that, The target material layer is an insulating material layer, and the transfer material layer is a conductive material layer; Or, the target material layer is a conductive material layer, and the transfer material layer is an insulating material layer.

10. The manufacturing method of a semiconductor structure according to claim 9, characterized in that, The target material layer is an insulating material layer, and the transfer material layer is a conductive material layer; before etching the adjacent transfer material layers with each of the first steps as a mask so that the remaining portions of the transfer material layers respectively form second steps to obtain a stepped structure, the manufacturing method further comprises: Forming a first filling layer in the etching trench and the removal regions of the target material layers, and the material of the first filling layer is the same as that of the transfer material layer; Wherein, etching the adjacent transfer material layers with each of the first steps as a mask further comprises etching the first filling layer.

11. The manufacturing method of a semiconductor structure according to claim 9, characterized in that, further comprising: After obtaining the stepped structure, forming a second filling layer covering the stepped structure and filling the etching trench.

12. A semiconductor structure, characterized in that, comprising: A substrate; A stacked structure located on one side of the substrate, comprising: a plurality of target material layers stacked along a direction perpendicular to the substrate, and a transfer material layer located between any two adjacent target material layers; the stacked structure has an etching trench; A sacrificial material layer filled in the etching trench; Wherein, the target material layer is configured to form a plurality of first steps arranged in a second direction after etching; the transfer material layer is configured to use the adjacent first steps as a mask to form second steps after etching so that each of the first steps and each of the second steps constitute a stepped structure.

13. The semiconductor structure according to claim 12, characterized in that, further comprising: An isolation barrier located on one side of the stacked structure along a direction parallel to the substrate; Wherein, the sacrificial material layer is located between the isolation barrier and the stacked structure.

14. A memory, characterized in that, comprising: At least one stepped structure; wherein, The stepped structure is obtained by etching the semiconductor structure as described in claim 12 or 13; The stepped structure includes: a plurality of the first steps stacked in a direction perpendicular to the substrate, and the second steps located between any two adjacent ones of the first steps.

15. An electronic device, characterized in that, it includes: a memory as described in claim 14.

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