Method of manufacturing a capacitor array
By doping P-type or N-type impurities in the hard mask layer during semiconductor manufacturing, the source leakage problem caused by the height difference structure is solved, the process yield is improved and the high consistency of the hard mask layer is maintained.
Patent Information
- Application Number
- CN202410340008.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Priority Date
- 2023-12-12
- Filing Date
- 2024-03-25
- Publication Date
- 2025-06-13
AI Technical Summary
In the semiconductor manufacturing process, as the structural size decreases, components in the semiconductor structure are prone to leakage due to too close spacing, resulting in a decrease in process yield.
By doping P-type or N-type impurities into the hard mask layer, the doped hard mask layer is formed, and the etch resistance or etching rate of the hard mask layer is improved, thereby reducing the source drain caused by the height difference structure.
The source leakage of the storage element caused by the height difference structure is effectively reduced, the process yield of the semiconductor structure is improved, and the height of the hard mask layer is basically consistent.
Smart Images
Figure CN120152277A_ABST
Abstract
Description
Technical Field
[0001] The present disclosure relates to a method for manufacturing a capacitor array. More specifically, the present disclosure relates to a method for manufacturing a capacitor array by doping impurities. Background Art
[0002] As electronic devices become lighter and thinner, semiconductor devices such as dynamic random access memories (DRAMs) become more highly integrated. In addition, the performance of DRAMs is improved by shortening the pitch between semiconductor structures in the DRAMs. Due to the reduction in the size of semiconductor structures, in addition to increasing the difficulty of the process, components in the semiconductor structures are also prone to leakage due to the too-close pitch.
[0003] Therefore, in the semiconductor manufacturing process, how to reduce leakage to improve the process yield of semiconductor structures has become an important issue. Summary of the Invention
[0004] Embodiments of the present disclosure provide a method for manufacturing a capacitor array, including the following steps. Provide a substrate, and the substrate includes a first capping layer located above the substrate, a second capping layer located on the first capping layer, and a first hard mask layer located on the second capping layer, and the substrate defines an array region and a peripheral region. Form a photoresist layer on the first hard mask layer in the peripheral region, and the photoresist layer exposes the first hard mask layer in the array region. Dope P-type impurities in the first hard mask layer exposed through the photoresist layer to form a second hard mask layer in the array region. Form a pattern layer on the first hard mask layer and the second hard mask layer to expose multiple exposed portions on the surface of the second hard mask layer. Etch the exposed portions of the second hard mask layer, the second capping layer, and the first capping layer to form multiple trenches. Form capacitors in the trenches.
[0005] In some embodiments, the concentration of the P-type impurities is between 2×10 14 and 2×10 18 ions / cm 2 ².
[0006] In some embodiments, the P-type impurities are boron.
[0007] In some embodiments, the trenches are formed by a dry etching process using a halogen-based gas.
[0008] In some embodiments, the first capping layer has a first thickness, the second capping layer has a second thickness, the first hard mask layer has a third thickness, and the photoresist layer has a fourth thickness.
[0009] In some embodiments, after forming the trench, the thickness of the second hard mask layer is less than the third thickness of the first hard mask layer, and there is a thickness difference between the thickness and the third thickness.
[0010] In some embodiments, the thickness difference is 10 nanometers.
[0011] In some embodiments, the substrate includes a plurality of active regions and a contact layer. The active regions are disposed on the upper portion of the substrate in the array region. The contact layer is disposed on the active regions and the peripheral region in the array region, and includes a plurality of contact plugs.
[0012] In some embodiments, the trench exposes the surface of the contact layer, and the position of the trench corresponds to the contact plug.
[0013] In some embodiments, forming a capacitor in the trench includes the following steps. Depositing a first conductive layer on the inner surface of the trench, and the first conductive layer directly contacts the contact plug. Depositing an insulating layer on the first conductive layer. Depositing a second conductive layer on the insulating layer.
[0014] Embodiments of the present disclosure provide a method for manufacturing a capacitor array, including the following steps. Providing a substrate, and the substrate includes a first cover layer above the substrate, a second cover layer on the first cover layer, and a first hard mask layer on the second cover layer, and the substrate defines an array region and a peripheral region. Forming a photoresist layer on the first hard mask layer in the array region, and the photoresist layer exposes the first hard mask layer in the peripheral region. Doping an N-type impurity in the first hard mask layer exposed through the photoresist layer to form a second hard mask layer in the peripheral region. Forming a pattern layer on the first hard mask layer and the second hard mask layer to expose a plurality of exposed portions on the surface of the second hard mask layer. Etching the exposed portions of the second hard mask layer, the second cover layer, and the first cover layer to form a plurality of trenches. Forming a capacitor in the trench.
[0015] In some embodiments, the concentration of the N-type impurity is between 2×10 14 and 2×10 18 ions / cm 2 .
[0016] In some embodiments, the N-type impurity is arsenic.
[0017] In some embodiments, the trench is formed by a dry etching process using a halogen-based gas.
[0018] In some embodiments, the first cover layer has a first thickness, the second cover layer has a second thickness, the first hard mask layer has a third thickness, and the photoresist layer has a fourth thickness.
[0019] In some embodiments, after forming the trench, the thickness of the second hard mask layer is less than the third thickness of the first hard mask layer, and there is a thickness difference between the thickness and the third thickness.
[0020] In some embodiments, the thickness difference is 10 nanometers.
[0021] In some embodiments, the substrate includes a plurality of active regions and a contact layer. The active regions are disposed on an upper portion of the substrate in the array region. The contact layer is disposed on the active regions and the peripheral region in the array region, and includes a plurality of contact plugs.
[0022] In some embodiments, the trench exposes the surface of the contact layer, and the position of the trench corresponds to the contact plug.
[0023] In some embodiments, forming a capacitor in the trench includes the following steps. Depositing a first conductive layer on an inner surface of the trench, and the first conductive layer directly contacts the contact plug. Depositing an insulating layer on the first conductive layer. Depositing a second conductive layer on the insulating layer. Description of the Drawings
[0024] Read the following embodiments in conjunction with the accompanying drawings to clearly understand the viewpoints of the present disclosure. It should be noted that, according to the standard practice in the industry, various features are not drawn to scale. In fact, for the purpose of clear discussion, the dimensions of various features may be arbitrarily enlarged or reduced.
[0025] Figures 1 to 6 are cross-sectional views of a method for manufacturing a capacitor array of a semiconductor structure according to a first embodiment of the present disclosure at different stages; and
[0026] Figures 7 to 9 are cross-sectional views of a method for manufacturing a capacitor array of a semiconductor structure according to a second embodiment of the present disclosure at different stages. Detailed Description of the Embodiments
[0027] Now, embodiments of the present disclosure will be described in detail. Examples of the embodiments of the present disclosure are shown in the accompanying drawings. Wherever possible, the same reference numerals are used in the drawings and the description to refer to the same or similar parts.
[0028] In addition, for convenience of description, spatial relative terms such as "above", "upper", "below", "between", etc. may be used in the present disclosure to describe the relationship between one element or feature and another element as shown in the accompanying drawings) or function. Except for the orientation depicted in the accompanying drawings, spatial relative terms are intended to cover different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90 degrees or in other directions), and the spatial relative descriptors used in the present disclosure may be correspondingly interpreted.
[0029] The terms "comprising", "having", "including", etc. used in the present disclosure are open-ended terms, meaning including but not limited to.
[0030] In the prior art, after etching a storage structure through a height aspect ratio contact (HARC), a height difference (e.g., 350 nanometers (nm)) is generated between the hard mask layer (e.g., polysilicon mask) in the array region and the hard mask layer in the peripheral region. Due to the lower height of the hard mask layer in the array region, after a subsequent etch-back process configured to form capacitor trenches, an etch difference (e.g., 20 nm) will also be generated between the capping layer (e.g., nitride layer) in the array region and the capping layer in the peripheral region. Accordingly, a high-step structure is caused. Further, the bowed critical dimension (bowed CD) of the holes in each trench that is etched will be enlarged. In this way, the lower-height capping layer and the enlarged CD will cause source leakage of a storage element (SSLK). Accordingly, embodiments of the present disclosure provide a method for manufacturing a capacitor array of a semiconductor structure, in which impurities are implanted into the hard mask layer before forming the capacitor trenches to solve the above problems.
[0031] Please refer to Figures 1 to 6 , Figures 1 to 6 is a cross-sectional view of a method for manufacturing a capacitor array of a semiconductor structure according to a first embodiment of the present disclosure at different stages.
[0032] First, in Figure 1 , a substrate 102 is provided, and the substrate 102 defines an array region 110 and a peripheral region 120. The substrate 102 includes a plurality of active regions 104 having a plurality of source / drain (S / D) regions (not shown) located in the array region 110, and a contact layer 130 having a plurality of contact plugs 132 located in the array region 110 and the peripheral region 120. In addition, the contact plugs 132 in the array region 110 are formed above the active regions 104.
[0033] In some embodiments, the substrate 102 may include silicon, such as single-crystalline silicon, polysilicon, or amorphous silicon. The substrate 102 may include an elemental semiconductor, such as germanium. In some embodiments, the substrate 102 may include an alloy semiconductor, such as silicon germanium, silicon germanium carbide, indium gallium phosphide, or other suitable materials. In some embodiments, the substrate 102 may include a compound semiconductor, such as silicon carbide (SiC), gallium arsenide (GaAs), indium phosphide (InP), indium arsenide (InAs), or other suitable materials. In addition, in some embodiments, the substrate 102 optionally has a semiconductor-on-insulator (SOI) structure.
[0034] Further, in Figure 1 a first cover layer 140 is deposited on the contact layer 130, and the first cover layer 140 has a first thickness TH1. In some embodiments, the first cover layer 140 includes an oxide. In some embodiments, the first thickness TH1 of the first cover layer 140 is 1.8 micrometers (μm). Subsequently, a second cover layer 150 is deposited on the first cover layer 140, and the second cover layer 150 has a second thickness TH2. In some embodiments, the second cover layer 150 includes a nitride. In some embodiments, the second thickness TH2 of the second cover layer 150 is 0.1 μm. Then, a hard mask layer 160 is formed on the second cover layer 150, and the hard mask layer 160 has a third thickness TH3. In some embodiments, the hard mask layer 160 includes polysilicon. In some embodiments, the third thickness TH3 of the hard mask layer 160 is 0.5 μm to 0.6 μm.
[0035] Next, in Figure 2 a photoresist layer 170 is formed on the hard mask layer 160 in the peripheral region 120 to expose the exposed portion of the hard mask layer 160 in the array region 110. In some embodiments, the hard mask layer 160 has a fourth thickness TH4. In some embodiments, the fourth thickness TH4 is 0.2 μm. Subsequently, the exposed portion of the hard mask layer 160 is doped with P-type impurities to form a doped hard mask layer 160DP. Additionally, the doping depth of the P-type impurities is the same as the third thickness TH3 of the hard mask layer 160. In some embodiments, the concentration of the P-type impurities is between 2×10 14 and 2×10 18 ions / cm 2 . In some embodiments, the P-type impurity is boron. Further, after doping the P-type impurities, the photoresist layer 170 is removed by a lift-off process.
[0036] Further, in Figure 3 a pattern layer 180 is formed on the hard mask layer 160 and the doped hard mask layer 160DP. The pattern layer 180 exposes a plurality of first portions PR1 on the surface of the doped hard mask layer 160DP and covers a plurality of second portions PR2 on the surface of the doped hard mask layer 160DP and the surface of the hard mask layer 160. When forming the pattern layer 180, a photolithography process is performed on the hard mask layer 160 and the doped hard mask layer 160DP. Specifically, a photolithography process is performed on the first portion PR1 of the exposed surface of the pattern layer 180 and the doped hard mask layer 160DP.
[0037] Subsequently, in Figure 4 a first portion (e.g., Figure 3Etch the doped hard mask layer 160DP, the second capping layer 150, and the first capping layer 140 of the first portion PR1 until the upper surface of the contact layer 130 is exposed to form a plurality of trenches TR1. In addition, after forming the first trench TR1, remove the pattern layer (e.g., Figure 3 pattern layer 180). Also, after the etching process, the thickness of the doped hard mask layer 160DP becomes the fifth thickness TH5. In some embodiments, the thickness difference D1 between the third thickness TH3 and the fifth thickness TH5 is 10 nanometers (nm). In some embodiments, the positions of the first trenches TR1 respectively correspond to the contact plugs 132 in the array region 110. In some embodiments, the etching process is a dry etching process using a gas. In some embodiments, the gas is a halogen-based gas. In some embodiments, the halogen-based gas is Cl 2(g) .
[0038] In addition, the P-type impurities in the doped hard mask layer 160DP of the array region 110 increase the etching resistance of the doped hard mask layer 160DP to the etching gas (e.g., halogen-based gas). Specifically, during the dry etching process, non-volatile by-products, such as chlorine oxides (e.g., BOClx) of P-impurities, are generated, thus reducing the etching rate. In this way, through the embodiments of the present disclosure, the source-side leakage current (SSLK) of the storage element caused by the height difference structure can be reduced. And the heights of the hard mask layer 160 and the doped hard mask layer 160DP can be made substantially the same.
[0039] Furthermore, in Figure 5 , after forming the first trench TR1, remove the doped hard mask layer (e.g., Figure 4 doped hard mask layer 160DP) and the hard mask layer (e.g., Figure 4 hard mask layer 160). Subsequently, deposit a first conductive layer 192 on the inner surface of the first trench TR1. And the first conductive layer 192 contacts the surface of the contact layer 130 exposed through the first trench TR1. More specifically, a plurality of first conductive layers 192 respectively contact a plurality of contact plugs 132 in the array region 110. In some embodiments, the material of the first conductive layer 192 includes metal and polysilicon. In some embodiments, the first conductive layer 192 is formed by chemical vapor deposition (CVD) process, physical vapor deposition (PVD) process, atomic layer deposition (ALD) process, or any suitable deposition process.
[0040] Next, in Figure 6In [the structure], an insulating layer 194 is formed on a first conductive layer 192, and a second conductive layer 196 is formed on the insulating layer 194. In some embodiments, the insulating layer 194 and the second conductive layer 196 are deposited by, for example, a CVD process, a PVD process, an ALD process, or any suitable deposition process. In some embodiments, the insulating layer 194 includes an oxide. In some embodiments, the second conductive layer 196 includes metal and polysilicon. It is worth mentioning that the capacitor 190 including the first conductive layer 192, the insulating layer 194, and the second conductive layer 196 is formed in a trench (e.g., Figure 4 the trench TR1). Similarly, multiple capacitors 190 in the array region 110 form a capacitor array of the semiconductor structure 100.
[0041] Furthermore, an embodiment of the present invention also provides a method for manufacturing a capacitor of another semiconductor structure. Please refer to Figures 7 to 9 , Figures 7 to 9 which is a cross-sectional view of a method for manufacturing a capacitor array of a semiconductor structure according to a second embodiment of the present disclosure at different stages.
[0042] The main difference between the first embodiment and the second embodiment is that an N-type impurity is doped in the hard mask layer in the peripheral region 120 in the second embodiment. The detailed description is as follows.
[0043] In Figure 7 , a substrate 102 having an active region 104 and a contact layer 130 having contact plugs 132 is provided. In addition, a first capping layer 140, a second capping layer 150, and a hard mask layer 160 are sequentially formed on the contact layer 130. Moreover, the technical features of the substrate 102, the active region 104, the contact layer 130, the contact plugs 132, the first capping layer 140, the second capping layer 150, and the hard mask layer 160 are as described above and will not be elaborated herein.
[0044] Next, a photoresist layer 270 is formed on the hard mask layer 160 in the array region 110 to expose an exposed portion of the hard mask layer 160 in the peripheral region 120. Subsequently, the exposed portion of the hard mask layer 160 is exposed, and an N-type impurity is doped in the exposed portion of the hard mask layer 160 to form a doped hard mask layer 160DN. In addition, the doping depth of the N-type impurity is the same as the third thickness TH3 of the hard mask layer 160. In some embodiments, the concentration of the N-type impurity is between 2×10 14 and 2×10 18 ions / cm 2 . In some embodiments, the N-type impurity is arsenic. In addition, after doping the N-type impurity, the photoresist layer 270 is removed by a stripping process.
[0045] Subsequently, in Figure 8In [the structure], a pattern layer 180 is formed on the hard mask layer 160 and the doped hard mask layer 160DN to expose a plurality of third portions PR3 of the surface of the hard mask layer 160 and cover a plurality of fourth portions PR4 of the surface of the hard mask layer 160 and the surface of the doped hard mask layer 160DN. Subsequently, a photolithography process is performed on the pattern layer 180 and the third portions PR3 of the exposed surface of the hard mask layer 160.
[0046] In addition, in Figure 9 [the structure], an etching process is performed on the hard mask layer 160, the second capping layer 150, and the first capping layer 140 of the third portions (e.g., the third portions PR3 of Figure 8 [the structure]) until the surface of the contact layer 130 is exposed to form a plurality of second trenches TR2. In addition, after the second trenches TR2 are formed, the pattern layer (e.g., the pattern layer 180 of Figure 8 [the structure]) is removed. And, after the etching process, the thickness of the doped hard mask layer 160DN becomes a sixth thickness TH6. In some embodiments, the thickness difference D2 between the third thickness TH3 and the sixth thickness TH6 is 10 nm. In some embodiments, the etching process is a dry etching process using a gas. In some embodiments, the gas is a halogen-based gas. In some embodiments, the halogen-based gas is Cl 2(g) .
[0047] In addition, due to the N-type impurities (such as arsenic) in the doped hard mask layer 160DN in the peripheral region 120, the etching rate of the doped hard mask layer 160DN for the etching gas (such as a halogen-based gas) is [affected]. Accordingly, by doping only N-type impurities in the doped hard mask layer 160DN in the peripheral region 120, the etching rate of the doped hard mask layer 160DN in the peripheral region 120 can be increased. In this way, the occurrence of the height difference structure can be reduced. In this way, the heights of the hard mask layer 160 and the doped hard mask layer 160DN can be made substantially the same, and further, the source leakage (SSLK) of the memory element caused by the height difference structure can be reduced.
[0048] In addition, in the second embodiment, after the second trenches TR2 are formed, the hard mask layer 160 and the doped hard mask layer 160DN are removed. Subsequently, a first conductive layer is formed on the inner surface of the second trenches TR2. Similar to the foregoing, an insulating layer is formed on the first conductive layer, and a second conductive layer is formed on the insulating layer, and then a capacitor is formed in the second trenches TR2, and the capacitor structure is similar to the structure shown in Figure 5 [the structure]. Therefore, similar descriptions are not repeated herein.
[0049] In summary, in the embodiment of doping P-type impurities, the source leakage (SSLK) of the storage element due to the height difference structure can be reduced by improving the etching resistance of the hard mask. Additionally, in the embodiment of doping N-type impurities, the source leakage (SSLK) of the storage element due to the height difference structure can be reduced by increasing the etching rate of the hard mask in the peripheral region.
[0050] Although some embodiments of the present disclosure have been described in considerable detail, other embodiments are possible. Therefore, the spirit and scope of the claims should not be limited to the embodiments described herein.
[0051] The features of multiple embodiments in the present disclosure are outlined above to make it easier for those skilled in the art to understand the present disclosure. Any person skilled in the art should understand that the present disclosure can easily be used as a basis for changing or designing other structures or processes to achieve the same purpose and / or obtain the same advantages as the embodiments of the present disclosure. Any person skilled in the art can also understand that the equivalent structures described above do not depart from the spirit and scope of the present disclosure, and changes, substitutions, and modifications can be made without departing from the spirit and scope of the present disclosure.
[0052]
Symbol Description
[0053] 100: Semiconductor structure
[0054] 102: Substrate
[0055] 104: Active region
[0056] 110: Array region
[0057] 120: Peripheral region
[0058] 130: Contact layer
[0059] 132: Contact plug
[0060] 140: First capping layer
[0061] 150: Second capping layer
[0062] 160: Hard mask layer
[0063] 160DP, 160DN: Doped hard mask layer
[0064] 170, 270: Photoresist layer
[0065] 180: Pattern layer
[0066] 190: Capacitor
[0067] 192: First conductive layer
[0068] 194: Insulating layer
[0069] 196: The second conductive layer
[0070] D1, D2: Thickness difference
[0071] PR1: The first part
[0072] PR2: The second part
[0073] PR3: The third part
[0074] PR4: The fourth part
[0075] TH1: The first thickness
[0076] TH2: The second thickness
[0077] TH3: The third thickness
[0078] TH4: The fourth thickness
[0079] TH5: The fifth thickness
[0080] TH6: The sixth thickness
[0081] TR1, TR2: Trenches
Claims
1. A method for manufacturing a capacitor array, characterized in that: include: Providing a substrate, wherein the substrate comprises a first covering layer located above the substrate, a second covering layer located on the first covering layer, and a first hard mask layer located on the second covering layer, and the substrate defines an array region and a peripheral region; forming a photoresist layer on the first hard mask layer in the peripheral region, wherein the photoresist layer exposes the first hard mask layer in the array region; doping P-type impurities in the first hard mask layer exposed by the photoresist layer to form a second hard mask layer in the array region; forming a pattern layer on the first hard mask layer and the second hard mask layer to expose a plurality of exposed portions of a surface of the second hard mask layer; etching the second hard mask layer, the second capping layer, and the first capping layer of the plurality of exposed portions to form a plurality of trenches; as well as A capacitor is formed in each of the trenches.
2. The method according to claim 1, characterized in that The concentration of the P-type impurities is between 2×10 14 Up to 2×10 18 Ions / cm 2 between.
3. The method according to claim 1, characterized in that The P-type impurity is boron.
4. The method according to claim 1, characterized in that: The plurality of trenches are formed by a dry etching process using a halogen-based gas.
5. The method according to claim 1, characterized in that The first covering layer has a first thickness, the second covering layer has a second thickness, the first hard mask layer has a third thickness, and the photoresist layer has a fourth thickness.
6. The method according to claim 5, characterized in that After the plurality of grooves are formed, the thickness of the second hard mask layer is less than the third thickness of the first hard mask layer, and there is a thickness difference between the second hard mask layer and the third thickness.
7. The method according to claim 6, characterized in that The thickness difference is 10 nanometers.
8. The method according to claim 1, characterized in that The substrate comprises: A plurality of active regions are disposed on an upper portion of the substrate in the array region; and The contact layer is disposed on the plurality of active regions and the peripheral region of the array region of the substrate and includes a plurality of contact plugs.
9. The method according to claim 8, characterized in that The plurality of trenches expose the upper surface of the contact layer, and the position of each trench corresponds to each contact plug.
10. The method according to claim 9, characterized in that The capacitor formed in each of the trenches includes: Depositing a first conductive layer on the inner surface of each of the trenches, wherein the first conductive layer directly contacts each of the contact plugs; depositing an insulating layer on the first conductive layer; and A second conductive layer is deposited on the insulating layer.
11. A method for manufacturing a capacitor array, characterized in that: include: Providing a substrate, wherein the substrate comprises a first covering layer located above the substrate, a second covering layer located on the first covering layer, and a first hard mask layer located on the second covering layer, and the substrate defines an array region and a peripheral region; forming a photoresist layer on the first hard mask layer in the array region, wherein the photoresist layer exposes the first hard mask layer in the peripheral region; doping N-type impurities in the first hard mask layer exposed through the photoresist layer to form a second hard mask layer in the peripheral area; forming a pattern layer on the first hard mask layer and the second hard mask layer to expose a plurality of exposed portions of a surface of the second hard mask layer; etching the second hard mask layer, the second capping layer, and the first capping layer of the plurality of exposed portions to form a plurality of trenches; as well as A capacitor is formed in each of the trenches.
12. The method according to claim 11, characterized in that The concentration of the N-type impurities is between 2×10 14 Up to 2×10 18 Ions / cm 2 between.
13. The method according to claim 11, characterized in that The N-type impurity is arsenic.
14. The method according to claim 11, characterized in that The plurality of trenches are formed by a dry etching process using a halogen-based gas.
15. The method according to claim 11, characterized in that The first covering layer has a first thickness, the second covering layer has a second thickness, the first hard mask layer has a third thickness, and the photoresist layer has a fourth thickness.
16. The method according to claim 15, characterized in that After the plurality of grooves are formed, the thickness of the second hard mask layer is less than the third thickness of the first hard mask layer, and there is a thickness difference between the second hard mask layer and the third thickness.
17. The method according to claim 16, characterized in that The thickness difference is 10 nanometers.
18. The method according to claim 11, characterized in that The substrate comprises: A plurality of active regions are disposed on an upper portion of the substrate in the array region; and The contact layer is disposed on the plurality of active regions and the peripheral region of the array region of the substrate and includes a plurality of contact plugs.
19. The method according to claim 18, characterized in that The plurality of trenches expose the upper surface of the contact layer, and the position of each trench corresponds to each contact plug.
20. The method according to claim 19, characterized in that The capacitor formed in each of the trenches includes: Depositing a first conductive layer on the inner surface of each of the trenches, wherein the first conductive layer directly contacts each of the contact plugs; depositing an insulating layer on the first conductive layer; and A second conductive layer is deposited on the insulating layer.